Semiconductor structure

Abstract

A semiconductor structure includes a gate contact structure on a gate structure of a transistor. The gate contact structure includes a metal via passing through a dielectric layer and contacting a gate electrode of the gate structure. The metal via includes a metal, such as ruthenium, having a low product of resistivity and average free path. An interface between the metal via and the gate electrode is oxygen free. Therefore, the metal through hole of the gate contact structure has better conduction performance.

Description

Technical Field

[0001] This utility model relates to semiconductor structures and methods for forming semiconductor structures. Background Technology

[0002] With the advancement of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is increasing. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAAFETs). This shrinkage has increased the complexity of semiconductor manufacturing processes. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor structure is provided, comprising: a substrate; a fin structure on the substrate; a source / drain region on the fin structure; a source / drain contact structure on the source / drain region; a gate structure on the fin structure and adjacent to the source / drain region; a dielectric layer on the gate structure; and a gate contact structure in the dielectric layer and on the gate structure, wherein the gate contact structure comprises: a conductive layer in contact with the gate structure; and a self-assembled monolayer surrounding the conductive layer.

[0004] According to some embodiments of the present disclosure, a semiconductor structure is provided, comprising: a transistor on a substrate, wherein the transistor includes: a channel region; and a gate structure surrounding the channel region; a dielectric layer on the transistor; and a gate contact structure in the dielectric layer and on the gate structure, wherein: the gate contact structure is ruthenium; and there is no oxide layer at the interface between the gate structure and the gate contact structure. Attached Figure Description

[0005] The nature of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with general industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration and discussion.

[0006] Figure 1 This is an isometric view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0007] Figure 2 This is a cross-sectional view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0008] Figure 3This is a cross-sectional view of an enlarged region of a semiconductor transistor including a gate contact structure according to some embodiments.

[0009] Figure 4 This is a flowchart of a method for forming a gate contact structure of a semiconductor transistor according to some embodiments.

[0010] Figure 5 and Figure 6 This is an isometric view of an intermediate structure during the fabrication of a gate contact structure of a semiconductor transistor, according to some embodiments.

[0011] Figures 7 to 18 and Figures 20 to 23 This is a cross-sectional view of an intermediate structure during the fabrication of a semiconductor transistor according to some embodiments.

[0012] Figure 19 This is a diagram of a mass load during an atomic layer cleaning procedure used to clean an opening in a semiconductor structure, according to some embodiments.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally refer to the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided objectives. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. As used herein, the formation of a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition itself does not specify a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of explanation, this document may use spatial relative terms such as "under," "below," "below," "above," "on top," and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value, as interpreted by those skilled in the art based on the teachings herein.

[0017] It should be noted that the embodiments described by references to "an embodiment," "an exemplary embodiment," "exemplary," etc., in this specification may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly stated or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0018] It should be understood that the wording or terminology used herein is for illustrative rather than restrictive purposes, and that the wording or terminology used herein should be interpreted by one of skill in the art in light of the teachings herein.

[0019] As an example, and not a limitation, a nanostructure transistor with nanosheet (NS) or nanowire (NW) channel regions, such as a GAA nanosheet (NS) or nanowire (NW) FET (collectively referred to as "GAAFET"), can be formed as follows: A fin structure having alternating silicon-germanium (SiGe) and silicon (Si) NS or NW layers is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed on a middle portion of the fin structure to cover the top and sidewall surfaces of the fin structure, such that the edge portions of the fin structure are not covered by the sacrificial gate structure. The edge portions of the fin structure not covered by the sacrificial gate structure are removed. Subsequently, the edge portions of the SiGe NS or NW layers are recessed relative to the edge portions of the SiGe NS or NW layers, and an inner spacer structure is formed by depositing a dielectric material to fill the space formed by the etched portions of the SiGe NS or NW layers. Next, a source / drain (S / D) epitaxial structure is formed to abut (or contact) the edge portion of the fin-like structure, such that the S / D epitaxial structure contacts the Si NS or NW layer and is isolated (or separated) from the SiGe NS or NW layer by an inner spacer structure. The source / drain may refer to a source or a drain individually or jointly, depending on the context. In a subsequent operation, the sacrificial gate structure is removed to expose the top and sidewall surfaces of the fin-like structure. The SiGe NS or NW layer is selectively removed from the fin-like structure. During the selective removal process, the Si NS or NW layer and the inner spacer structure are not removed. Subsequently, a metal gate structure is formed to surround the Si NS or NW layer. Similar to the SiGe NS or NW layer, the metal gate structure is isolated (or separated) from the S / D epitaxial structure by an inner spacer structure before their selective removal.

[0020] The structure of a GAAFET can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual-patterning or multi-patterning procedures. Dual-patterning or multi-patterning procedures combine lithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be built compared to those obtained using a single direct lithography process in other ways. For example, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0021] As semiconductor devices continue to shrink, the critical dimensions of GAAFETs (such as the length / width of the Si NS or NW layer as a channel and the metal gate structure) become smaller in exemplary GAAFETs formed by the procedures described above. Accordingly, forming a gate contact via through a dielectric layer on the metal gate structure becomes more challenging because a higher aspect ratio (depth to width ratio) of the gate contact via is necessary for effective electrical coupling with the metal gate structure, which has a smaller critical dimension. For example, once the width of the gate contact via shrinks to approximately 10 nm or less, the conductivity of the gate contact via becomes significantly affected by the resistivity of the metal used for the gate via and the mean free path of electrons in the metal. Other materials with lower resistivity and mean free path of electrons, such as tungsten (W), yield better conductivity characteristics compared to other materials for gate vias. Furthermore, a smaller metal gate structure provides a smaller contact interface between the gate contact via and the metal gate structure, and the quality of their contact interface becomes more critical in influencing conductivity characteristics. During the formation of a gate contact via, an oxide layer can be formed on the top surface of the metal gate structure while an upper dielectric layer is etched to form a narrow opening for the gate contact via. The presence of this oxide layer at the contact interface can become a bottleneck for conductivity. Furthermore, forming a high-quality gate via within a narrow opening through the dielectric layer can be difficult because the metal deposited on the dielectric side surface of the opening can form overhangs and / or premature junctions during deposition, introducing defects, voids, and / or discontinuities into the gate via and impairing its conductivity.

[0022] The embodiments described herein relate to overcoming the challenges mentioned above. In some embodiments, a structure of a semiconductor device may include a dielectric layer on a field-effect transistor. The structure may further include a gate contact structure that extends through the dielectric layer and contacts a gate structure of the field-effect transistor. The gate contact structure may include a metal via that contacts a gate electrode of the gate structure. The metal via may include a metal, such as ruthenium, having a low product of resistivity and electron mean free path. An interface between the metal via and the gate electrode may be oxygen-free. The gate contact structure may further include a passivation layer between the metal via and the dielectric layer. In some embodiments, a method of forming the structure may include: forming an opening through the dielectric layer to expose a top surface of the gate electrode; and cleaning the top surface of the gate electrode to remove an oxide layer at the top surface of the gate electrode. The method may further include: forming a small molecule inhibitor (SMI) layer at the top surface of the gate electrode; forming the passivation layer on the dielectric side surface of the opening; removing the SMI layer; and depositing the metal via in the opening. The passivation layer prevents metal deposition on the dielectric side surface of the opening to avoid the formation of defects, voids, and / or discontinuities.

[0023] Regarding the selection of metals for gate contact vias, the table below lists the resistivity (ρ) and mean free path (λ) of several metal materials. Although their ρ values ​​are relatively low, metals such as copper (Cu), molybdenum (Mo), and tungsten (W) may be less suitable for gate contact vias with small critical dimensions and high aspect ratios due to their relatively large λ values. A comparison of the ρ·λ product of metal materials shows that ruthenium (Ru), cobalt (Co), or iridium (Ir) are better candidates.

[0024]

[0025] According to some embodiments, a semiconductor device 100 having a plurality of transistors 105 formed on a substrate 102 is referenced. Figure 1 and 2 To illustrate. The semiconductor device 100 may be included in a microprocessor, a memory cell, or other integrated circuit (IC). Figure 1 An isometric view of a semiconductor device 100 is shown. Figure 2 Examples along Figure 1 The line BB is a cross-sectional view of the semiconductor device 100 (e.g., along the xz plane).

[0026] See Figure 1The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 may include: (i) a basic semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium arsenide phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Furthermore, the substrate 102 may be doped depending on design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, a crystal orientation of the substrate 102 may be (100), (110), or (111).

[0027] Although Figure 1 and Figure 2 The diagram shows a fin structure 110 housing two transistors 105, but any number of transistors 105 may be arranged along the fin structure 110. In some embodiments, the transistors 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in the x-direction) and a gate structure 115 traversing the plurality of fin structures 110 along a second horizontal direction (e.g., in the y-direction). In some embodiments, a crystal orientation of the fin structure 110 may be the same as the crystal orientation of the substrate 102.

[0028] See Figure 1 and Figure 2One or more nanosheet (NS) layers 120 may be disposed on the fin structure 110. Each NS layer 120 may be covered by a gate structure 115 to serve as a channel for a transistor 105. For example, the top, side, and bottom surfaces of each NS layer 120 may be surrounded by and in contact with the gate structure 115. The fin structure 110 and the NS layer 120 may be made of a material similar to (e.g., with a lattice mismatch of about 5%) the substrate 102. In some embodiments, a crystal orientation of the NS layer 120 may be the same as the crystal orientation of the fin structure 110. In some embodiments, each of the fin structure 110 and the NS layer 120 may be made of Si or SiGe. Each of the fin structure 110 and the NS layer 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and the NS layer 120 may be doped together with a p-type dopant or with an n-type dopant. Although Figure 1 Each transistor 105 is shown to include four NS layers 120, and Figure 2 Each transistor 105 is shown to include three NS layers 120, but any number of NS layers 120 may be included in each transistor 105. For example, each transistor 105 may include one, two, five, or six NS layers 120.

[0029] See Figure 1 and Figure 2 The gate structure 115 may be a multilayer structure that surrounds each NS layer 120 to modulate the transistor 105. The gate structure 115 may have a length Lc, representing the channel length of the transistor 105. The length Lc may have any suitable horizontal (e.g., in the x-direction) dimension, such as about 3 nm to about 200 nm. In some embodiments, the height of the gate structure 115 on the fin structure 110 along a straight direction (e.g., in the z-direction) may be between about 12 nm and about 14 nm. In some embodiments, the height of the gate structure 115 on the fin structure 110 may be greater than about 14 nm. By way of example and not limitation, each gate structure 115 may include a dielectric stack formed of an interface dielectric layer 115a and a gate dielectric layer 115b. Furthermore, each gate structure 115 includes a gate electrode 115c having a capping layer, one or more work function metal layers, and a metal filler, etc., which are not shown separately for simplicity. Figure 1The gate dielectric layer 115b may comprise any suitable dielectric material having any suitable thickness to provide channel modulation for the transistor 105. In some embodiments, the gate dielectric layer 115b may be made of silicon oxide or a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). In some embodiments, the gate dielectric layer 115b may have a thickness ranging from about 1 nm to about 5 nm. Other materials and thicknesses of the gate dielectric layer 115b are within the scope and spirit of this disclosure. The gate electrode 115c may serve as a gate terminal of the transistor 105. The gate electrode 115c may comprise any suitable conductive material providing a suitable work function to modulate the transistor 105. In some embodiments, the gate electrode 115c may be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Other materials of the gate electrode 115c are within the scope and spirit of this disclosure.

[0030] See Figure 1 and Figure 2 The S / D epitaxial structure 125 may be disposed on opposite sides (e.g., along the x-direction) of each NS layer 120 to serve as the source and drain terminals of the transistor 105. The S / D epitaxial structure 125 may be disposed on the fin structure 110. In some embodiments, the S / D epitaxial structure 125 may be disposed on the fin structure 110 such that the S / D epitaxial structure 125 and the fin structure 110 are electrically isolated. The S / D epitaxial structure 125 may be made of an epitaxially grown semiconductor material similar to (e.g., with a lattice mismatch within about 5%) the NS layer 120. In some embodiments, the S / D epitaxial structure 125 may be made of Si, Ge, SiGe, InGaAs, or GaAs. The S / D epitaxial structure 125 may be doped with a p-type dopant, an n-type dopant, or an intrinsic dopant. In some embodiments, the S / D epitaxial structure 125 may have a different doping type than the NS layer 120. In some embodiments, the n-type dopant in the S / D epitaxial structure 125 may include P, As, Sb, or a combination thereof. In some embodiments, a crystal orientation of the S / D epitaxial structure 125 may be the same as the crystal orientation of the NS layer 120.

[0031] See Figure 1 and Figure 2The semiconductor device 100 may include an inner spacer structure 130 that abuts (or contacts) a side surface of the gate structure 115. The inner spacer structure 130 may separate the gate structure 115 from the S / D epitaxial structure 125. For example, the inner spacer structure 130 may be formed on opposite sides of the gate structure 115 along the channel direction of the transistor 105 (e.g., along the x-direction) to separate the gate structure 115 from the S / D epitaxial structure 125. In some embodiments, the inner spacer structure 130 may be formed between two orthogonally (e.g., in the z-direction) adjacent NS layers 120. In some embodiments, the inner spacer structure 130 may be formed between the fin structure 110 and the NS layer 120. In some embodiments, the inner spacer structure 130 may include a silicon-based dielectric, such as silicon nitride (SiN), silicon oxy-carbon-nitride (SiOCN), silicon carbon-nitride (SiCN), or silicon oxy-nitride (SiON). In some embodiments, the inner spacer structure 130 may include a low-k material, such as a porous material, and a carbon-rich silicon oxide-based dielectric.

[0032] See Figure 1 and Figure 2 The semiconductor device 100 may further include a gate spacer 135, which is formed between the gate structure 115 and the S / D epitaxial structure 125, and which can provide structural support during the formation of the gate structure 115. Additionally, the gate spacer 135 can be used to form the S / D junction (not shown). Figure 1 During this period, the gate spacer 135 provides electrical isolation and protection for the gate structure 115. The gate spacer 135 may be made of any suitable dielectric material. In some embodiments, the gate spacer 135 may be made of silicon oxide, silicon nitride, or a low-k material having a dielectric constant of less than about 3.9. In some embodiments, the gate spacer 135 may have any suitable thickness, such as from about 5 nm to about 15 nm. Other materials and thicknesses of the gate spacer 135 are within the scope and spirit of this disclosure, based on the present disclosure.

[0033] See Figure 1The semiconductor device 100 may further include shallow trench isolation (STI) regions 138, which are configured to provide electrical isolation between fin structures 110. STI regions 138 may also provide electrical isolation between transistor 105 and adjacent active and passive components integrated or deposited on substrate 102. STI regions 138 may include one or more dielectric material layers, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. Other dielectric materials for STI regions 138 are within the scope and spirit of this disclosure.

[0034] See Figure 1 and Figure 2 The semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation for structural elements it surrounds or covers, such as the gate structure 115 and the S / D epitaxial structure 125. In some embodiments, a gate spacer 135 may be formed between the gate structure 115 and the ILD layer 165. The ILD layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon carbide, silicon oxynitride, silicon oxycarbon nitride, and silicon carbonitride. The ILD layer 165 may have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Other insulating materials and thicknesses of the ILD layer 165 are within the scope and spirit of this disclosure.

[0035] See Figure 1 and Figure 2 The semiconductor device 100 may further include dielectric layers 152, 154, and 156 on the transistor 105. In some embodiments, dielectric layers 152, 154, and 156 may include silicon oxide and / or silicon nitride. For example, dielectric layers 152 and 156 may be silicon oxide layers, and dielectric layer 154 may be a silicon nitride layer. In some embodiments, dielectric layers 152, 154, and 156 may be etch stop layers.

[0036] See Figure 1 and Figure 2The semiconductor device 100 may further include an S / D contact 163 that is in contact with the S / D epitaxial structure 125. The S / D contact 163 may be disposed on the S / D epitaxial structure 125 and surrounded by an ILD layer 165. In some embodiments, the S / D contact 163 may be disposed through one or more of dielectric layers 152, 154, and 156. In some embodiments, a silicide layer 164 may be disposed between the S / D contact 163 and the S / D epitaxial structure 125. In some embodiments, a height of the S / D contact 163 may be between about 10 nm and about 50 nm. The S / D contact 163 may include any suitable conductive material that provides low contact resistance with the S / D epitaxial structure 125. In some embodiments, the S / D contact 163 may be made of polysilicon, titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, nickel, or a combination thereof. Based on the disclosure herein, other materials concerning S / D contact 163 are within the scope and spirit of this disclosure.

[0037] See Figure 1 and Figure 2The semiconductor device 100 may further include one or more gate contact vias 167 that contact the gate electrode 115c. The gate contact vias 167 may be disposed on the gate structure 115 and pass through one or more of the dielectric layers 152, 154, and 156. In some embodiments, an interface between the gate contact via 167 and the gate electrode 115c may be substantially flat. In some embodiments, the interface between the gate contact via 167 and the gate electrode 115c may be curved. In some embodiments, a horizontal cross-section of the gate contact via 167 may have a rectangular shape or a cylindrical shape. In some embodiments, the gate contact via 167 may have a tapered shape, wherein the width of a top surface is greater than the width of a bottom surface. In some embodiments, the gate contact via 167 may have a uniform width from its top surface to its bottom surface. In some embodiments, the width of the top surface of the gate contact via 167 may be between about 2 nm and about 40 nm. In some embodiments, the width of the bottom surface of the gate contact via 167 may be between about 1 nm and about 40 nm. In some embodiments, the ratio of the width of the top surface of the gate contact via 167 to the width of the bottom surface of the gate contact via 167 may be between about 1 and about 3. In some embodiments, if the ratio is greater than about 3, the width of the bottom surface of the gate contact via 167 may be too small, resulting in a high contact resistance between the gate contact via 167 and the gate electrode 115c. In some embodiments, the height of the gate contact via 167 may be between about 10 nm and about 50 nm. In some embodiments, the aspect ratio of the gate contact via 167 may be between about 5:1 and about 20:1. In some embodiments, if the aspect ratio of the gate contact via 167 is less than about 5:1, the width of the gate contact via 167 may exceed the width of the gate electrode 115c and interfere with surrounding contact structures, such as the S / D contact 163. In some embodiments, if the aspect ratio of the gate contact via 167 is greater than about 20:1, the gate contact via 167 may be too narrow, resulting in a higher resistivity.

[0038] Figure 3 Example Figure 2 The cross-sectional view shows an enlarged portion 300 surrounding the area of ​​the gate contact via 167. Unless otherwise noted, the same annotation applies. Figure 1 and Figure 2 The discussion of the components in the text also applies to... Figure 3 .

[0039] See Figure 3 In some embodiments, the gate contact via 167 may be a conductive layer comprising a metallic material having a resistivity product of less than about 400 μΩ·µm. 2For example, the metallic material may include Ru. In some embodiments, the metallic material may include Ru, Ir, Co, or a combination thereof. In some embodiments, the metallic material may include Ru, Ir, Co, W, Cu, Mo, or a combination thereof. In some embodiments, an interface 167b between the gate contact via 167 and the gate electrode 115c may be oxygen-free. For example, the atomic percentage of oxygen at interface 167b may be less than about 3.5%. In some embodiments, if the atomic percentage of oxygen at interface 167b is greater than about 3.5%, the conductive properties of the gate contact via 167 may be affected by a high contact resistance between the gate contact via 167 and the gate electrode 115c.

[0040] In some embodiments, a self-assembled monolayer (SAM) 369 may be disposed between the gate contact via 167 and dielectric layers 152, 154, and 156. SAM 369 is a passivation layer that inhibits the deposition of metal material on dielectric layers 152, 154, and 156. In some embodiments, SAM 369 may include aminosilane functional groups. For example, SAM 369 may include dimethylamino-trimethylsilane (TMSDMA), hexamethyldisilazane (HMDS), or a combination thereof. During a deposition process of the gate contact via 167, as discussed below, the presence of SAM 369 effectively prevents dangling and premature bridging of metal material on dielectric layers 152, 154, and 156, avoids the formation of defects, voids, and / or discontinuities in the gate contact via 167, and improves its conductivity characteristics. In some embodiments, SAM 369 may cover an integral side surface of dielectric layers 152, 154, and 156, and a bottom end 369b of SAM 369 may contact one end of an interface 152b between dielectric layer 152 and gate electrode 115c. In some embodiments, gate contact via 167 may protrude into gate electrode 115c such that a portion of gate contact via 167 may lie directly below the bottom end 369b of SAM 369. In some embodiments, SAM 369 may cover a top surface of dielectric layer 156. In some embodiments, a top surface of gate contact via 167 and a top surface of SAM 369 may be coplanar.

[0041] Although Figure 1 and Figure 2 The transistor 105 is illustrated as an embodiment of a GAAFET, but it should be understood that, Figure 3 The gate contact via 167 described can be applied to other types of transistors, such as MOSFETs, FinFETs, complementary fin field-effect transistors (CFETs), or vertical fin field-effect transistors (VFETs).

[0042] According to some embodiments, Figure 4 Examples used to form Figures 1-3 The diagram shows a process 400 for manufacturing transistor 105. This disclosure is not limited to this description of operations, and additional operations may be performed. Other manufacturing operations may be performed between various operations of method 400 and are omitted only for clarity. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in different ways. Figure 4 The illustrated method is performed in a specific order. In some embodiments, one or more other operations may be performed to supplement or replace the operations currently described. For illustrative purposes, method 400 is referred to... Figure 5-18 The structure shown in Figures 20-23 will be used for illustration. Unless otherwise noted, the same annotations apply. Figure 1-3 The discussion of the components in the text also applies to... Figure 5-18 And 20-23.

[0043] See Figure 4 Method 400 begins with operation 405 and procedure of forming a fin structure on a substrate (e.g., substrate 102). In some embodiments, forming the fin structure may include forming a stack of alternating first NS layers and second NS layers on the substrate. Figure 5 This is an isometric view of a substrate 102 and a stack 520 forming alternating first NS layers 520a and second NS layers 520b. In some embodiments, the first NS layer 520a and the second NS layer 520b are formed on an exposed top surface of the substrate 102. In some embodiments, the first NS layer 520a is a sacrificial NS layer that undergoes subsequent removal, and the second NS layer 520b corresponds to... Figure 1 The NS layer 120 is shown. In some embodiments, the material of the first NS layer 520a in the stack 520 is selected such that the first NS layer 520a can be selectively removed from the stack 520 by etching without removing the second NS layer 520b. For example, the first NS layer 520a may be a SiGe NS layer and the second NS layer 520b may be a Si NS layer.

[0044] The first NS layer 520a and the second NS layer 520b can be grown using any suitable method. For example, the first NS layer 520a and the second NS layer 520b can be grown using a chemical vapor deposition (CVD) process with a precursor gas, such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germanane (GeH4), digermanane (Ge2H6), other suitable gases, or combinations thereof. In some embodiments, the first NS layer 520a may include Ge at a concentration between about 20% and about 30%, while the second NS layer 520b is substantially free of germanium—for example, having a Ge concentration of less than about 1%. In some embodiments, the second NS layer 520b, which corresponds to... Figure 1 The NS layer 120 forms the channel region of transistor 105 and can be lightly doped or intrinsic (e.g., undoped). If lightly doped, the doping level of the second NS layer 520b is less than about 10. 13 atoms / cm 3 The first NS layer 520a and the second NS layer 520b can be deposited sequentially without vacuum interruption (e.g., in situ) to avoid the formation of any interposer layer. In some embodiments, in a subsequent etching operation, the first NS layer 520a may be doped to increase its etch selectivity compared to the second NS layer 520b.

[0045] In some embodiments, the thickness of the first NS layer 520a controls the spacing between each interval of the second NS layers 520b in the stack 520. The thicknesses of the first NS layer 520a and the second NS layer 520b can range, for example, from about 3 nm to about 15 nm. Since the first NS layer 520a and the second NS layer 520b are grown separately, the thickness of each NS layer can be adjusted independently, for example, based on the deposition time. In some embodiments, additional or fewer numbers of first NS layers 520a and second NS layers 520b can be formed in the stack 520. In some embodiments, the total number of NS layers can be 2n, where n is the number of first NS layers 520a or the number of second NS layers 520b in the stack 520. In some embodiments, n can be 1, 2, 3, 4, 5, 6, or any integer greater than 6.

[0046] See Figure 4 Operation 405 may further include a process of patterning the stack 520 to form a fin structure. In some embodiments, the stack 520 is patterned to form a fin structure having a width along the y-direction and a length along the x-direction. The fin structure can be formed by patterning using any suitable method. For example, the fin structure can be patterned using one or more lithography processes including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine lithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be built compared to those obtained using a single direct lithography process in other ways. In some embodiments, a sacrificial layer is formed on the stack 520 and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask structure to pattern the fin structure.

[0047] As an example, not a limitation. Figure 6This is an isometric view of the fin structure 620 formed from the stack 520 using the aforementioned patterning process. In some embodiments, the fin structure 620 may be formed by etching a first NS layer 520a and a second NS layer 520b into the first NS layer 620a and the second NS layer 620b. In some embodiments, the aforementioned patterning process does not terminate on the top surface of the substrate 102, but continues to etch a top portion of the substrate 102 to form a fin structure 110 from the substrate 102 under the fin structure 620. Since the fin structure 620 and the fin structure 110 are formed using the same patterning process, the fin structure 620 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 620 in the xz plane and the yz plane are substantially aligned with the corresponding sidewall surfaces of the fin structure 110, such as... Figure 6 As shown.

[0048] Additional fin structures, such as fin structure 620, may be formed on substrate 102 in the same or different regions of substrate 102. For simplicity, these additional fin structures are not shown on... Figure 6 As shown in the figure. As an example and not a limitation, each fin structure 620 has a width along the y-direction between approximately 15 nm and approximately 150 nm.

[0049] In some embodiments, the first NS layer 620a and the second NS layer 620b are referred to as "nanosheets" when their width along the y-direction is substantially different from their height along the z-direction—for example, when their width is greater than / narrower than their height. In some embodiments, the first NS layer 620a and the second NS layer 620b may also be referred to as "nanowires" when their width along the y-direction is substantially equal to their height along the z-direction. In some embodiments, the first NS layer 620a and the second NS layer 620b are deposited as nanosheets and subsequently patterned to form nanowires with substantially equal height and width. By way of example and not limitation, the first NS layer 620a and the second NS layer 620b will be illustrated in the context of nanosheet (NS) layers. For the purposes of this disclosure, nanowires (NW) are within the spirit and scope of this disclosure. Furthermore, for illustrative purposes and without limiting the scope of this disclosure, the first NS layer 620a and the second NS layer 620b in method 400 will be illustrated in the context of SiGe and Si NS layers, respectively.

[0050] In some embodiments, after the fin structure 620 is formed, an STI region 138 may be formed on an etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the STI region 138 may electrically isolate the fin structure 110 and include one or more silicon oxide-based dielectrics. By way of example and not limitation, the STI region 138 may be formed as follows: An isolation structure material (e.g., a silicon oxide-based dielectric) is blanket-deposited on the fin structure 620 and the substrate 102. The deposited isolation structure material is planarized (e.g., using a chemical mechanical polishing (CMP) process) such that the top surface of the isolation structure material is substantially coplanar with the top surface of the fin structure 620. The planarized isolation structure material is then etched back so that the resulting STI region 138 has a height substantially similar to that of the fin structure 110, such as Figure 6 As shown. In some embodiments, the fin structure 620 protrudes from the STI region 138, such that the STI region 138 does not cover the sidewall portion of the fin structure 620, as... Figure 6 As shown.

[0051] Method 400 continues with operation 410 and procedures for forming an S / D epitaxial structure and a gate structure on the fin structure. Operation 410 may begin by removing a portion of the fin structure to form an opening in the fin structure, including (i) forming a sacrificial gate structure 700, as referred to Figure 7 As described above, and (ii) removing portions of the fin structure 620 exposed by the sacrificial gate structure 700, as referenced. Figure 8 As explained.

[0052] In some embodiments, the length of the sacrificial gate structure 700 is formed along the y-direction—for example, perpendicular to the y-direction. Figure 6 The fin structure 620 and the sacrificial gate structure 700 shown in the isometric view are formed along the x-direction. This is an example, not a limitation. Figure 7 For the sample taken along the cutting line AB Figure 6 A cross-sectional view. Figure 7 The sacrificial gate structure 700 is shown formed on a portion of the fin structure 620. Because Figure 7 This is a cross-sectional view, not an isometric view, therefore the portion of the sacrificial gate structure 700 covering the sidewall portion of the fin structure 620 is not shown. Additionally, in Figure 7 In the cross-sectional view, only Figure 6 One of the fin structures 620. In some embodiments, portions of the sacrificial gate structure 700 are formed between and within the fin structures 620. Figure 6 The STI region 138 is shown.

[0053] In some embodiments, the sacrificial gate structure 700 may cover the top and sidewall portions of the fin structure 620. During a subsequent gate replacement procedure, the sacrificial gate structure 700 is then replaced with... Figure 1 The gate structure 115 is shown. The sacrificial gate structure 700 may include a sacrificial gate electrode 700a formed in a sacrificial gate dielectric (not shown for simplicity). Figure 7 (Middle) Above. The sacrificial gate structure 700 may also include a capping layer 705, which is formed on the top surface of the sacrificial gate structure 700. In some embodiments, the capping layer 705 may protect the sacrificial gate electrode 700a from subsequent etching operations. During this manufacturing stage, gate spacers 135 may be formed on the side surfaces of the sacrificial gate structure 700. As discussed above, the gate spacers 135 are not removed during the gate replacement procedure; rather, the gate spacers 135 facilitate the following: Figure 1 The formation of the gate structure 115 shown.

[0054] By way of example and not limitation, the sacrificial gate structure 700 may be formed by depositing and patterning a sacrificial gate electrode 700a on the fin structure 620. In some embodiments, the sacrificial gate structure 700 is formed on a plurality of fin structures 620. Figure 7 As shown, a portion of the fin structure 620 is not covered by the sacrificial gate structure 700. This is because the width of the sacrificial gate structure 700 is narrower than the length of the fin structure 620 along the x-direction. In some embodiments, the sacrificial gate structure 700 is used as a mask structure in subsequent etching operations to define... Figure 1 The channel region of transistor 105 is shown. For this reason, the lateral dimensions (e.g., width and length) of the sacrificial gate structure 700 and the gate structure 115 are substantially similar.

[0055] See Figure 8The removal process can remove portions of the fin structure 620 not covered by the sacrificial gate structure 700. In some embodiments, the removal process involves a dry etching process, a wet etching process, or a combination thereof. The removal process is selective for the first NS layer 620a and the second NS layer 620b, shaping them into a first NS layer 820a and an NS layer 120, respectively. The removal process can further remove portions of the fin structure 110. In some embodiments, the dry etching process includes: an etchant having an oxygen-containing gas, a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); an iodine-containing gas; other suitable etching gases and / or plasma; or combinations thereof. Wet etching chemistry may include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH); or combinations thereof.

[0056] In some embodiments, the etchant used in the aforementioned etching process does not substantially etch the sacrificial gate structure 700—which is protected by the capping layer 705 and the gate spacer 135—and Figure 6 The STI region 138 is shown. This is because the capping layer 705, the gate spacer 135, and the STI region 138 comprise a material with low etch selectivity, such as a silicon nitride-based material (e.g., silicon nitride, silicon carbon nitride, and silicon carbon oxy-nitride), or a silicon oxide-based material. In some embodiments, Figure 6 The STI region 138 shown is used as an etch stop layer in the above etch process.

[0057] After removing the portion of the fin structure 620 not covered by the sacrificial gate structure 700, an opening 840 is formed in each fin structure 620, such as Figure 8 As shown, opening 840 divides each fin structure 620 into separate portions, each of which is covered by a sacrificial gate structure 700.

[0058] See Figure 4 After forming the opening 840, operation 410 can continue the process of forming the inner spacer. The process of forming the inner spacer may include (i) selectively etching the edge portion of the first NS layer 820a to form the recess structure 945, as shown in the reference. Figure 9 As explained, and (ii) the formation of an inner spacer structure 130 in the recessed structure 945, as shown in reference Figure 10 As described. According to some embodiments, Figure 9 The exposed edge of the first NS layer 820a is shown after being laterally etched (e.g., recessed) along the x-direction and becoming the first NS layer 920a. Figure 8 The structure. According to some embodiments, the exposed edge of the first NS layer 820a is along, as shown in the figure. Figure 9 The amount of recessed (e.g., partially etched) in the x-direction is approximately 3 nm to approximately 10 nm to form the recessed structure 945.

[0059] In some embodiments, selective etching of the first NS layer 820a can be achieved using a dry etching process selective for SiGe. For example, halogen-based chemicals exhibit high etch selectivity for Ge and low etch selectivity for Si. Therefore, halogen gases etch Ge-containing layers, such as the first NS layer 820a, at a higher etch rate than substantially Ge-free layers (such as NS layer 120). In some embodiments, halogen-based chemicals include fluorine-based and / or chlorine-based gases. Alternatively, a wet etching chemical with high selectivity for SiGe can be used. By way of example and not limitation, a wet etching chemical may include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonium hydroxide and H2O2 and water (APM). The aforementioned etching process is timed to remove the desired amount of SiGe.

[0060] In some embodiments, the first NS layer 820a with a higher Ge atom concentration has a higher etch rate than the NS layer 120 with a lower or zero Ge atom concentration. Therefore, the etch rate of the aforementioned etching process can be adjusted by regulating the Ge atom concentration (e.g., Ge content) in the first NS layer 820a. As discussed above, the Ge content in the first NS layer 820a can be in the range of about 20% to about 30%. A SiGe nanosheet layer with about 20% Ge can be etched more slowly than a SiGe nanosheet layer with about 30% Ge. Therefore, the Ge concentration can be adjusted accordingly to achieve the desired etch rate and selectivity between the first NS layer 820a and the NS layer 120.

[0061] See Figure 9 and Figure 10 Once the concave structure 945 is formed, a dielectric layer can be deposited in a blanket-like manner. Figure 9 The dielectric layer portion outside the recessed structure 945 can be removed from the entire structure, leaving the inner spacer structure 130 filling the recessed structure 945, as shown in the reference. Figure 10 As explained.

[0062] See Figure 4After forming the inner spacer structure 130, operation 410 can continue the process of forming the S / D epitaxial structure in the opening 840. For example, as shown in reference... Figure 11 As explained, the S / D epitaxial structure 125 can be formed by epitaxially growing a semiconductor material in the opening 840.

[0063] In some embodiments, such as reference Figure 11 As explained, the S / D epitaxial structure 125 can be epitaxially grown using a CVD process, which is similar to the process used in operation 405 to form the first NS layer 520a and the second NS layer 520b, as shown in the reference. Figure 5 As described above. In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the side surface of the second NS layer 120 in a horizontal direction (e.g., along the x-axis). In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the top surface of the fin structure 110 in a vertical direction (e.g., along the z-axis). In some embodiments, the S / D epitaxial structure 125 may be grown using a plasma-enhanced CVD (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3, or a combination thereof) may be used to grow a semiconductor material (e.g., Si) having the same or similar crystal structure as the NS layer 120. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) may be used to selectively remove the semiconductor material having an amorphous structure formed on the dielectric surface (e.g., the side surfaces of the inner spacer structure 130 and the gate spacer 135). Removing the semiconductor material with an amorphous structure ensures that the crystal structure of the S / D epitaxial structure 125 is crystalline. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsine (AsH3), antimonyane (SbH3), or a combination thereof, can be used in a CVD or PECVD process to dope the S / D epitaxial structure 125.

[0064] See Figure 4 Operation 410 can continue a process of forming a gate structure. The process of forming a metal gate structure may include (i) removing the sacrificial gate structure 700 and the first NS layer 920a, as shown in reference... Figure 12 As described above, and (ii) forming a metal gate structure 115 to surround the NS layer 120, as referenced Figure 13 As explained.

[0065] In some embodiments, removing the sacrificial gate structure 700 may include removing the capping layer 705 to expose the sacrificial gate electrode 700a, and subsequently removing the sacrificial gate electrode 700a to expose the fin structure 620 between the S / D epitaxial structures 125. In some embodiments, removing the first NS layer 920a may include selectively etching the first NS layer 920a without removing the NS layer 120, as referenced. Figure 12 As explained.

[0066] In some embodiments, forming the metal gate structure 115 may include (i) forming an interface dielectric layer 115a on the exposed surface of the second NS layer 120, (ii) forming a gate dielectric layer 115b on the interface dielectric layer 115a, and (iii) forming a gate electrode 115c on the gate dielectric layer 115b, as shown in the reference. Figure 13 As described above, the metal gate structure 115 is electrically isolated from the S / D epitaxial structure 125 by the inner spacer structure 130 and the gate spacer 135. In some embodiments, after forming the metal gate structure 115, an ILD layer 165 may be formed to fill the space above the S / D epitaxial structure 125. In some embodiments, one or more of the dielectric layers 152, 154, and 156 may be formed on the metal gate structure 115 and the ILD layer 165 by sequentially depositing dielectric layers such as silicon oxide and silicon nitride.

[0067] See Figure 4 Operation 410 can continue to form a procedure for S / D contact 163, as shown in the following example. Figure 14 As described above. In some embodiments, forming the S / D contact 163 may include (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 and through the ILD layer 165 to expose the S / D epitaxial structure 125, (ii) forming a silicide layer 164 on the S / D epitaxial structure 125, and (iii) depositing a metal material (e.g., W, Cu and / or Mo) in the opening.

[0068] See Figure 4 Method 400 continues to operation 415, wherein a contact opening is formed on the gate structure. For example, as referenced... Figure 15 As described, a contact opening 1640 is formed through one or more of the dielectric layers 152, 154, and 156 to expose the gate electrode 115c. In some embodiments, the contact opening 1640 may be formed to protrude into the gate electrode 115c. In some embodiments, the formation of the contact opening 1640 may include a dry etching process with one or more etchants and may include the following sequence of operations: (i) etching portions of the dielectric layers 152, 154, or 156, and (ii) etching portions of the gate electrode 115c, as referenced. Figure 15As described above, the contact opening 1640 may expose a top surface of the gate electrode 115c and a side surface of the dielectric layers 152, 154, or 156. In some embodiments, the vertical cross-sectional profile of the contact opening 1640 may have a vertical or inclined side surface. In some embodiments, the horizontal cross-sectional profile of the contact opening 1640 may have a rectangular shape or a circular shape.

[0069] In some embodiments, during the formation of the contact opening 1640, the top surface of the gate electrode 115c may be oxidized due to the reaction between the etchant and the metal material (e.g., TiN) of the gate electrode 115c. Figure 16 Example Figure 15 An enlarged region 1600 surrounds the contact opening 1640. For example... Figure 16 As shown, an oxide layer 1682 may be formed on the gate electrode 115c. In some embodiments, the oxide layer 1682 may be formed due to a reaction between oxygen and a metallic material at the top surface of the gate electrode 115c. In some embodiments, a thickness d1 of the oxide layer 1682 may be between about 0.5 nm and about 5 nm. In some embodiments, the oxide layer 1682 may include titanium oxynitride (TiO2). x N y ).

[0070] Since the presence of oxide layer 1682 increases the contact resistance between gate electrode 115c and a subsequently formed gate contact via, oxide layer 1682 can be removed in a subsequent operation 420 before forming the gate contact via.

[0071] See Figure 4 Method 400 continues with operation 420, in which a cleaning procedure is performed in the contact opening. For example, see reference... Figure 17-20 As described, a cleaning process is performed in contact opening 1640 to remove oxide layer 1682. In some embodiments, the cleaning process may include using a non-plasma-based cleaning process, such as an atomic layer etching (ALE) process comprising one or more cycles. In some embodiments, the cleaning process may include removing about one atomic layer (e.g., about 0.1 nm) of oxide layer 1682 in each cycle of an ALE process. In some embodiments, each cycle of an ALE process may include the following sequence of operations: (i) exposing oxide layer 1682 to a fluorine-based etching gas 1790 (e.g., tungsten hexafluoride (WF6) or hydrogen fluoride (HF)), which reacts with about one atomic layer of oxide layer 1682 to form a first byproduct layer 1784 having a thickness df on oxide layer 1682 with reduced thickness d2, and a first byproduct gas 1795, such as Figure 17As shown, and (ii) exposing the byproduct layer 1784 to a reactant gas 1890 (e.g., boron trichloride (BCl3)) to remove the first byproduct layer 1784, and forming a second byproduct layer 1886 having a thickness db on the oxide layer 1682, and a second byproduct gas 1895, as... Figure 18 As shown. In a subsequent cycle of the ALE process, the second byproduct layer 1886 can be further removed upon exposure to a fluorine-based etching gas 1790, which further reduces the thickness of the oxide layer 1682, similar to the reference. Figure 17 The steps (i) described.

[0072] In some embodiments, the first byproduct layer 1784 may include tungsten oxynitride fluoride (WONF) and / or titanium oxynitride fluoride (TiONF). In some embodiments, the second byproduct layer 1886 may include boron oxynitride (BON). x N y In some embodiments, the first byproduct gas 1795 may include boron trifluoride (BF3). In some embodiments, the second byproduct gas 1895 may include tungsten tetrachloride (WOCl4), titanium tetrachloride (TiCl4), boron trifluoride (BF3), and nitrogen chloride (NCl). x ).

[0073] The cleaning process may include any number of cycles of the ALE process, and the number of cycles may depend on the thickness of the oxide layer 1682. For example, Figure 19 A graph showing a mass load 1900 of oxide layer 1682 during the cleaning process is displayed. At the beginning of each cycle (at times t1, t2, t3, and t4), when oxide layer 1682 is exposed to fluorine-based etching gas 1790, the mass load 1900 increases, corresponding to the formation of the first byproduct layer 1784. Within each cycle, when reactant gas 1890 is introduced into contact opening 1640 (at times t1', t2', t3', and t4'), the mass load 1900 decreases, corresponding to the removal or reduction of the first byproduct layer 1784 to the second byproduct layer 1886. Between adjacent cycles, a mass difference Δm corresponds to a reduction in the thickness d2-d1 of oxide layer 1682, which can be between about 0.2 nm and about 1 nm. In some embodiments, the mass load 1900 can be monitored in real time, and the cleaning process can continue until oxide layer 1682 is completely removed, as... Figure 20 As shown, this corresponds to the negligible mass difference between adjacent loops in the ALE program within mass load 1900.

[0074] In some embodiments, the flow rates of the fluorine-based etching gas 1790 and reactant gas 1890 may be between about 10 sccm and about 100 sccm. In some embodiments, the ALE process may be performed at a temperature between about 150°C and about 300°C and at a pressure between about 1 torr and about 10 torr.

[0075] See Figure 4 Method 400 continues with operation 425, wherein an inhibitor layer is formed on a bottom surface of the contact opening. For example, see reference... Figure 21 As described, an inhibitor layer 2167 is deposited on the bottom surface of the contact opening 1640, which is also the exposed top surface of the gate electrode 115c. In some embodiments, forming the inhibitor layer 2167 may include depositing a monomolecular inhibitor layer having molecules, including nitrogen and aromatic rings, such as pyridine, aniline, pyrrole, or a combination thereof. In some embodiments, the inhibitor layer 2167 may be formed at a temperature between about 150°C and about 300°C and at a pressure between about 1 torr and about 10 torr. In some embodiments, due to the chemical structure of the molecules and appropriate deposition conditions, the inhibitor layer 2167 may be selectively formed only on conductive surfaces (e.g., the exposed top surface of the gate electrode 115c) and not on non-conductive surfaces (e.g., the dielectric side surfaces or top surfaces of dielectric layers 152, 154, or 156). In some embodiments, the inhibitor layer 2167 may include portions of the side surfaces of the gate electrode 115c covered in the contact opening 1640, such as... Figure 21 As shown. In some embodiments, a top end 2167t of the inhibitor layer 2167 may contact one end of the interface 152b between the gate electrode 115c and the dielectric layer 152.

[0076] See Figure 4 Method 400 continues with operation 430, wherein a passivation layer is formed on the side surface of the contact opening. For example, see reference... Figure 22As described, SAM 369, as a passivation layer, may be formed on the side surface of the contact opening 1640. In some embodiments, SAM 369 may be formed to cover all dielectric surfaces exposed in the contact opening 1640, such that subsequent metal deposition in the contact opening 1640 does not form overhangs or premature structures on the dielectric surfaces of the contact opening 1640. In some embodiments, SAM 369 may also be formed on the top surface of the dielectric layer 156. In some embodiments, forming SAM 369 may include depositing a material having aminosilane functional groups, such as TMSDMA, HMDS, or a combination thereof. In some embodiments, the presence of the inhibitor layer 2167 prevents SAM 369 from forming on an exposed surface of the inhibitor layer 2167 because the inhibitor layer 2167 repels aminosilane functional groups.

[0077] See Figure 4 Method 400 continues to operation 435, wherein a gate contact structure is formed in the contact opening. In some embodiments, forming the gate contact structure may include (i) making such a gate contact structure as Figure 22 The structure shown was annealed in a hydrogen (H2) environment at a temperature between approximately 350°C and 450°C to release the inhibitor layer 2167 and expose the top surface of the gate electrode 115c in the contact opening 1640, as... Figure 23 As shown, and (ii) a metal material layer is formed on the gate electrode 115c in the contact opening 1640 to form a gate contact via 167, as... Figure 3 As shown. In some embodiments, forming the metallic material layer may include performing a CVD process using ruthenium dodecylcarbonyltriruthenium (Ru3(CO)). 12 DCR (Dielectric-Co-Cr) is used as a precursor to deposit Ru on the exposed surface of the gate electrode 115c. In some embodiments, other precursors may be used to deposit other metals (e.g., Ir, Co, W, Cu, and / or Mo) into the contact opening 1640. In some embodiments, the presence of SAM 369 on the side surface of the contact opening 1640 prevents metal material from being deposited on the dielectric side surface of the contact opening 1640 covered by SAM 369. In some embodiments, metal material deposition may stop once a top surface of the gate contact via 167 is coplanar with the top surface of the SAM 369.

[0078] The embodiments described herein pertain to a structure of a semiconductor device and a method of forming the structure. The structure may include a dielectric layer on a field-effect transistor. The structure may further include a gate contact structure that extends through the dielectric layer and contacts a gate structure of the field-effect transistor. The gate contact structure may include a metal via that contacts a gate electrode of the gate structure. The metal via may include a metal, such as ruthenium, having a low product of resistivity and mean free path. An interface between the metal via and the gate electrode may be oxygen-free. The gate contact structure may further include a passivation layer between the metal via and the dielectric layer. A method of forming the structure may include: forming an opening through the dielectric layer to expose a top surface of the gate electrode; and cleaning the top surface of the gate electrode to remove an oxide layer at the top surface of the gate electrode. The method may further include: forming a small molecule inhibitor (SMI) layer on the top surface of the gate electrode exposed in the opening; forming the passivation layer on the side surface of the opening; removing the SMI layer; and depositing the metal via in the opening.

[0079] In some embodiments, a structure includes: a substrate; a fin structure on the substrate; an S / D region on the fin structure; an S / D contact structure on the S / D region; a gate structure on the fin structure and adjacent to the S / D region; and a dielectric layer on the gate structure. The structure further includes a gate contact structure in the dielectric layer and on the gate structure. The gate contact structure includes a conductive layer in contact with the gate structure and a self-assembled monolayer (SAM) surrounding the conductive layer.

[0080] In some embodiments, the SAM separates the conductive layer from the dielectric layer.

[0081] In some embodiments, the conductive layer comprises ruthenium.

[0082] In some embodiments, the ratio of the width of a top surface of the conductive layer to the width of a bottom surface of the conductive layer is between about 1 and about 3.

[0083] In some embodiments, the atomic percentage of oxygen at an interface between the conductive layer and the gate structure is less than about 3.5%.

[0084] In some embodiments, the SAM comprises dimethylamino-trimethylsilane (TMSDMA) or hexamethyldisilazane (HMDS).

[0085] In some embodiments, the product of the resistivity of the conductive layer and the mean free path length of electrons in the conductive layer is less than about 400 μΩ·μm. 2 .

[0086] In some embodiments, a structure includes a transistor on a substrate. The transistor includes a channel region and a gate structure surrounding the channel region. The structure further includes: a dielectric layer on the transistor; and a gate contact structure in the dielectric layer and on the gate structure. The gate contact structure includes ruthenium. An interface between the gate structure and the gate contact structure is oxygen-free.

[0087] In some embodiments, the gate contact structure includes a metal via and a self-assembled monolayer (SAM) between the metal via and the dielectric layer.

[0088] In some embodiments, the aspect ratio of the gate contact structure is between about 5:1 and about 20:1.

[0089] In some embodiments, the width of the gate contact structure is between about 2 nm and about 40 nm.

[0090] In some embodiments, the gate structure comprises titanium nitride.

[0091] In some embodiments, the transistor further includes a source / drain (S / D) region, wherein the structure further includes an S / D contact structure that passes through the dielectric layer and contacts the S / D region, and wherein the S / D contact structure includes tungsten.

[0092] In some embodiments, a method includes: forming a fin structure on a substrate; forming a gate structure on the fin structure; depositing a dielectric layer on the gate structure; and forming an opening through the dielectric layer to expose a top surface of the gate structure. The method may further include: removing an oxide layer from the top surface of the gate structure; forming an inhibitor layer on the top surface of the gate structure; forming a passivation layer on a side surface of the opening; and depositing a conductive layer in the opening.

[0093] In some embodiments, removing the oxide layer comprises performing an atomic layer etching process.

[0094] In some embodiments, forming the inhibitor layer involves depositing a pyridine layer on the top surface of the gate structure without covering the side surface of the opening with the pyridine layer.

[0095] In some embodiments, forming the passivation layer comprises depositing a dimethylamino-trimethylsilane (TMSDMA) layer to cover the side surface of the opening, without covering the inhibitor layer with the TMSDMA.

[0096] In some embodiments, depositing the conductive layer includes: removing the inhibitor layer; and after removing the inhibitor layer, depositing a ruthenium layer in the opening.

[0097] In some embodiments, depositing the ruthenium layer comprises performing a chemical vapor deposition process using dodecyltriruthenium as a precursor.

[0098] In some embodiments, depositing the conductive layer includes forming an oxygen-free interface between the conductive layer and the gate structure.

[0099] It will be understood that the detailed description section, rather than the abstract section, is intended to interpret the claims. The abstract section of this disclosure may set forth one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and is therefore not intended to limit the appended claims in any way.

[0100] The foregoing disclosure outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other programs and structures to perform the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a fin structure on the substrate; a source / drain region on the fin structure; a source / drain contact structure on the source / drain region; a gate structure on the fin structure and adjacent to the source / drain region; a dielectric layer on the gate structure; and a gate contact structure in the dielectric layer and on the gate structure, wherein the gate contact structure comprises: a conductive layer in contact with the gate structure; and a self-assembled monolayer surrounding the conductive layer. The self-assembled monolayer separates the conductive layer from the dielectric layer.

2. The semiconductor structure of claim 1, wherein, The conductive layer is ruthenium.

3. The semiconductor structure of claim 1, wherein, A ratio of a width of a top surface of the conductive layer to a width of a bottom surface of the conductive layer is between 1 and 3.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure comprises:

5. The semiconductor structure of claim 1, wherein, The product of the resistivity of the conductive layer and the average free path of electrons in the conductive layer is less than 400 μΩ·μm 2 .

6. A semiconductor structure, characterized by a transistor on a substrate, wherein the transistor comprises: a channel region; and a gate structure surrounding the channel region; a dielectric layer on the transistor; and a gate contact structure in the dielectric layer and on the gate structure, wherein: the gate contact structure is ruthenium; and there is no oxide layer at an interface between the gate structure and the gate contact structure. The gate contact structure comprises a metal via and a self-assembled monolayer between the metal via and the dielectric layer. An aspect ratio of the gate contact structure is between 5:1 and 20:

1. The transistor further comprises a source / drain region, the semiconductor structure further comprises a source / drain contact structure, the source / drain contact structure passing through the dielectric layer and contacting the source / drain region.

7. The semiconductor structure of claim 6, wherein, A width of the gate contact structure is between 2 nm and 40 nm.

8. The semiconductor structure of claim 6, wherein, ​ 9. The semiconductor structure of claim 6, wherein, ​ 10. The semiconductor structure of claim 6, wherein, ​

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