BGA chip packaging structure capable of reducing production cost

Abstract

The utility model discloses a BGA (Ball Grid Array) chip packaging structure capable of reducing production cost in the field of circuit board design, which comprises a chip packaging area arranged on a circuit board and corresponding to a BGA chip, the chip packaging area is positioned below the BGA chip, and a plurality of chip bonding pads are arranged in the chip packaging area; the plurality of chip bonding pads are divided into non-empty bonding pads and empty bonding pads, a plurality of pins are arranged at the bottom of the BGA chip, and the plurality of pins are connected with the corresponding non-empty bonding pads; the non-empty bonding pad is connected with the corresponding wire, at least one part of the wire extends into the chip packaging area, and at least one wire is connected with the corresponding through hole through the empty bonding pad, so that same-layer wire outgoing of the BGA chip is realized. According to the utility model, the problem that the production cost is increased due to the fact that the BGA chip with the pitch of 0.5 mm and below adopts the HDI design is solved, the HDI design can be avoided, and the production cost is reduced.

Description

Technical Field

[0001] This utility model relates to the field of circuit board design technology, specifically to a BGA chip packaging structure that reduces production costs. Background Technology

[0002] As electronic devices evolve towards miniaturization and higher performance, Ball Grid Array (BGA) packaging technology has been widely adopted in integrated circuit packaging due to its high density and high reliability. However, for BGA chips with a solder ball pitch of 0.5mm or less, their close-pitch characteristics present technical challenges to packaging design. Specifically, due to the extremely small pad spacing, traditional through-hole vias (ThHVs) are difficult to place directly within the package area beneath the BGA chip. This is because the mechanical drilling size of the through-hole and the safety spacing requirements between the pads conflict with the dense solder ball layout, leading to insufficient signal trace space or an increased risk of electrical short circuits.

[0003] To address these issues, existing technologies typically employ High Density Interconnect (HDI) designs, utilizing laser-guided microvias and blind / buried vias to achieve fine routing across multiple layers. However, HDI processes require additional laser drilling, multiple lamination processes, and precise alignment steps, increasing production costs and process complexity.

[0004] The above-mentioned defects urgently need to be addressed. Utility Model Content

[0005] To address the issue of increased production costs associated with HDI design for BGA chips with a pitch of 0.5mm or less, this invention provides a BGA chip packaging structure that reduces production costs.

[0006] The technical solution of this utility model is as follows:

[0007] A BGA chip packaging structure for reducing production costs includes a chip packaging area on a circuit board corresponding to the BGA chip, the chip packaging area being located below the BGA chip, and the chip packaging area having multiple chip pads.

[0008] The chip pads are divided into non-empty pads and empty pads. The BGA chip has multiple pins on its bottom, and the multiple pins are connected to the corresponding non-empty pads.

[0009] The non-empty pads are connected to the corresponding traces, at least a portion of which extends into the chip package area, and at least one of the traces passes through the empty pads and is connected to the corresponding vias to achieve same-layer routing of the BGA chip.

[0010] According to the present invention based on the above scheme, the chip packaging area is divided into an inner layer area and an outer layer area. The non-empty pads located in the inner layer area are connected to the corresponding vias through the corresponding traces, and at least one trace located in the outer layer area is connected to the corresponding via through the empty pads.

[0011] According to the above-described scheme of this utility model, the chip pads located in the outer layer region are arranged in a matrix.

[0012] According to the present invention based on the above scheme, the chip pads located in the inner layer region are arranged in a rectangular pattern.

[0013] According to the above-described scheme of this utility model, the width of the trace is greater than 4mil.

[0014] According to the above-described scheme of this utility model, the diameter of the through hole is 8mil to 10mil.

[0015] According to the above-described scheme of this utility model, the diameter of the chip pad is 0.25mm to 0.30mm.

[0016] The advantages of this utility model based on the above solution are as follows:

[0017] In the aforementioned BGA chip packaging structure that reduces production costs, by removing unused pins from the BGA chip, the area corresponding to the empty pads becomes available wiring space, allowing traces to pass directly through this area. This reduces the difficulty of circuit board routing and improves the utilization of space beneath the BGA chip. Simultaneously, at least one trace connects directly to a via after passing through the empty pad, allowing the via to be placed within the chip package area, solving the problem of not being able to embed vias in close-pitch designs. Furthermore, the traces extend within the chip package area, utilizing the lateral space freed up by the empty pads to achieve same-layer routing. This means signal lines can be connected without switching to other layers, reducing the need for stacked blind / buried vias or microvias, avoiding HDI designs, and lowering production costs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of this utility model;

[0020] Figure 2 This is a schematic diagram of the circuit board structure;

[0021] Figure 3 for Figure 2 Enlarged view of section A;

[0022] Figure 4 This is a schematic diagram showing the distribution of chip pads on a circuit board.

[0023] Figure 5 This is a schematic diagram of the chip pad structure.

[0024] In the diagram, 1 is the circuit board; 11 is the chip packaging area; 111 is the inner layer area; 112 is the outer layer area; 12 is the chip pad; 121 is the non-empty pad; 122 is the empty pad; 13 is the trace; 14 is the through hole; and 2 is the BGA chip. Detailed Implementation

[0025] To make the technical problem to be solved, the technical solution, and the beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0026] With the trend towards miniaturization and high performance in electronic devices, Ball Grid Array (BGA) packaging technology has been widely used in the field of integrated circuit packaging due to its high density and high reliability. However, when it comes to BGA chips with a solder ball pitch of 0.5mm or less, the close spacing of the solder pads presents many technical challenges to the packaging design. One such challenge is that traditional through-hole vias (HDI) are difficult to place directly in the packaging area beneath the BGA chip due to the extremely small pad spacing. This is mainly because the drilling size of HDI and the necessary safety spacing between the pads conflict with the extremely dense solder ball layout, ultimately limiting signal trace space or significantly increasing the risk of electrical short circuits. To address these issues, existing technologies generally employ High Density Interconnect (HDI) designs, utilizing laser-guided microvias and blind / buried via (B / Buried Via) technologies to achieve fine routing across multiple layers of circuitry. However, the HDI process has obvious drawbacks. It requires additional laser drilling, multiple pressing processes, and precise alignment, which undoubtedly increases production costs and the complexity of the process.

[0027] like Figures 1 to 5 As shown, to solve the above-mentioned technical problems, this utility model provides a BGA chip packaging structure that reduces production costs. It includes a chip packaging area 11 on a circuit board 1 corresponding to a BGA chip 2. The chip packaging area 11 is located below the BGA chip 2, and multiple chip pads 12 are provided within the chip packaging area 11. These multiple chip pads 12 are divided into non-empty pads 121 and empty pads 122. The bottom of the BGA chip 2 has multiple pins, and these pins are soldered to the corresponding non-empty pads 121. This utility model removes the pins corresponding to the empty pads 122 on the BGA chip 2. By removing the unused pins on the BGA chip 2, the area originally corresponding to the empty pads 122 becomes a wiring space, allowing traces 13 to pass directly through this area. This reduces the wiring difficulty of the circuit board 1 and improves the utilization rate of the space below the BGA chip 2.

[0028] like Figures 2 to 5 As shown, in this embodiment, the non-empty pad 121 is connected to the corresponding trace 13. At least a portion of the trace 13 extends into the chip package area 11, and at least one trace 13 passes through the empty pad 122 and connects to the corresponding via 14. That is, the via 14 can be arranged within the chip package area 11, solving the problem that via 14 cannot be embedded in close-pitch chips. In addition, the trace 13 extends within the chip package area 11, utilizing the lateral space released by the empty pad 122 to achieve same-layer routing. That is, the signal line can be connected without switching to other layers, reducing the need for stacked blind / buried vias or microvias, avoiding the use of HDI design, and reducing production costs. It should be noted that since the BGA chip 2 has removed unused pins, the trace 13 will not cause a short circuit when passing through the empty pad 122.

[0029] like Figure 4 , Figure 5 As shown, in this embodiment, the chip packaging area 11 is divided into an inner layer area 111 and an outer layer area 112. Non-empty pads 121 located in the inner layer area 111 are connected to corresponding vias 14 via corresponding traces 13. Because the inner layer area 111 has a large internal space and a large distance between it and the outer layer area 112, the non-empty pads 121 located in the inner layer area 111 do not need to pass through empty pads 122 and can be directly connected to the corresponding vias 14 via corresponding traces 13, reducing wiring length and signal transmission delay. Furthermore, at least one trace 13 located in the outer layer area 112 is connected to the corresponding via 14 via an empty pad 122. Because the spacing between the chip pads 12 in the outer layer area 112 is small, the traces 13 of the non-empty pads 121 located in the outer layer area 112 can be connected to the corresponding vias 14 via empty pads 122, improving the space utilization of the entire chip packaging area 11 and contributing to the overall layout rationality of the circuit board 1.

[0030] In this embodiment, the outermost non-empty pad 121 in the outermost region 112 is not connected to the corresponding via 14 through the non-empty pad 121. The second outermost non-empty pad 121 in the outermost region 112 is connected to the corresponding via 14 through one or two non-empty pads 121. The non-empty pad 121 in the outermost region 112 near the inner region 111 is connected to the corresponding via 14 through two or three non-empty pads 121. In actual design, the number of non-empty pads 121 in the outermost region 112 can be designed according to the actual situation.

[0031] In this embodiment, the via 14 corresponding to the trace 13 located in the inner layer region 111 is located within the chip package region 11. This allows for more efficient planning of the trace 13 layout around the via 14 location within the inner layer region 111 during the wiring design. The via 14 corresponding to the trace 13 located in the outer layer region 112 can be located either within or outside the chip package region 11, providing more possibilities for various complex circuit designs. In actual design, the location of the via 14 corresponding to the trace 13 located in the outer layer region 112 can be designed according to actual needs.

[0032] like Figure 4 , Figure 5 As shown, in this embodiment, the chip pads 12 located in the outer layer region 112 are arranged in a matrix, making the routing 13 planning more regular. For example, in the horizontal and vertical directions, the routing 13 can be arranged in an orderly manner along the rows and columns of the pads. When connecting using empty pads 122, it is easier to calculate and plan the path of the routing 13, reducing routing difficulty and improving routing efficiency. In addition, the chip pads 12 located in the inner layer region 111 are arranged in a rectangular pattern, which is adapted to the larger internal space of the inner layer. The rectangular arrangement can make full use of the shape characteristics of the inner layer space, making the direct connection between the non-empty pads 121 and the vias 14 smoother. Compared with other irregular arrangements, the rectangular arrangement can reduce the bending and detour of the routing, further shorten the routing length, and optimize signal transmission.

[0033] In this embodiment, the width of trace 13 is greater than 4mil. The width of trace 13 can be designed to be any value in the range of 4.2mil, 4.4mil, 4.6mil, 4.8mil, 5mil, 5.2mil, 5.4mil, 5.6mil, 5.8mil, 6mil, 6.2mil, 6.4mil, 6.6mil, 6.8mil, 7mil, etc. In actual design, the width of trace 13 can be designed according to the impedance requirements.

[0034] In this embodiment, the diameter of the through hole 14 is 8mil to 10mil. The diameter of the through hole 14 can be designed to be any value in the range of 8mil, 8.2mil, 8.4mil, 8.6mil, 8.8mil, 9mil, 9.2mil, 9.4mil, 9.6mil, 9.8mil, and 10mil. In actual design, the diameter of the through hole 14 can be designed according to the actual situation.

[0035] In this embodiment, the diameter of the chip pad 12 is 0.25mm to 0.30mm. The diameter of the chip pad 12 can be designed to be any value in the range of 0.25mm, 0.26mm, 0.27mm, 0.28mm, 0.29mm, 0.30mm, etc. In actual design, the diameter of the chip pad 12 can be designed according to the actual situation.

[0036] It should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product is usually placed in during use, or the orientation or positional relationship that is commonly understood by those skilled in the art, or the orientation or positional relationship that the product is usually placed in during use. It is only for the purpose of facilitating the description of this application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this application.

[0037] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0038] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.

Claims

1. A BGA chip package structure with reduced production cost, characterized in that, The chip packaging area corresponding to the BGA chip is arranged on the circuit board, and the chip packaging area is located below the BGA chip. The plurality of chip pads are divided into non-empty pads and empty pads, the bottom of the BGA chip is provided with a plurality of pins, and the plurality of pins are connected with the corresponding non-empty pads. The non-empty pads are connected with corresponding wires, at least a part of the wires extends into the chip packaging area, and at least one wire is connected with a corresponding via through the empty pad, so as to realize the same layer wire-out of the BGA chip.

2. The BGA chip package structure with reduced production cost according to claim 1, wherein, The chip packaging area is divided into an inner area and an outer area, the non-empty pads in the inner area are connected with corresponding vias through corresponding wires, and at least one wire in the outer area is connected with a corresponding via through the empty pad.

3. The BGA chip package structure with reduced production cost according to claim 2, wherein, The chip pads in the outer area are arranged in a matrix.

4. The BGA chip package structure with reduced production cost according to claim 2, wherein, The chip pads in the inner area are arranged in a rectangle.

5. The BGA chip package structure with reduced production cost according to claim 1, wherein, The width of the wire is greater than 4 mil.

6. The BGA chip package structure with reduced production cost according to claim 1, wherein, The diameter of the via is 8 mil-10 mil.

7. The BGA chip package structure with reduced production cost according to claim 1, wherein, The diameter of the chip pad is 0.25 mm-0.30 mm.

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