Semiconductor structure
By setting conductive bumps and current control bumps of different densities in the active and idle areas of the semiconductor substrate, the problems of inconsistent conductive bump height and silicon interposer cracking were solved, and the flatness and structural stability of the conductive bumps were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2026-03-13
AI Technical Summary
In the existing large-size packaged silicon interposers, uneven current distribution during the conductive bump fabrication process leads to inconsistent conductive bump heights and silicon interposer cracking.
Conductive bumps and current control bumps of different densities are set in the active and idle areas of the semiconductor substrate. By forming a current control pattern in the idle area, the electroplating current is dispersed, thus avoiding uneven current distribution.
This effectively avoids the problems of inconsistent conductive bump height and silicon interposer cracking, ensuring the flatness and structural stability of the conductive bumps.
Smart Images
Figure CN223993895U_ABST
Abstract
Description
Technical Field
[0001] This application relates to a semiconductor device, and more particularly to a wafer-type semiconductor structure. Background Technology
[0002] With the development of industrial applications, the functions required for electronic components used in high-speed computing, AI artificial intelligence and other fields have become more and more diversified and the performance has become higher and higher. Therefore, it is necessary to integrate and package multiple heterogeneous chips and develop towards large-size packages with high stack-up, high density, high I / O number and high pin number.
[0003] Existing large-size electronic packages, such as CoWoS (Chip on Wafer on Substrate) type electronic packages, include a through silicon interposer (TSI) disposed on the flip-chip side of a package substrate, and at least one semiconductor wafer disposed on the TSI, wherein the TSI has a plurality of conductive bumps for bonding the semiconductor wafer or the package substrate.
[0004] However, the aforementioned silicon interposer is made from silicon wafers. In the process of fabricating the multiple conductive bumps, the distribution area and density of the multiple conductive bumps are uncertain due to actual application requirements. Therefore, when the multiple conductive bumps are electroplated, the uneven current distribution (the current is too concentrated or dispersed) often causes the height of the multiple conductive bumps to be inconsistent, and may even lead to the silicon interposer chipping problem due to uneven stress distribution during the process.
[0005] Therefore, how to overcome the various shortcomings of existing technologies is a technical problem that all sectors urgently need to solve. Utility Model Content
[0006] In view of the deficiencies in the prior art, this application provides a semiconductor structure, including: a semiconductor substrate defining adjacent active regions and idle regions, wherein the active region is provided with a plurality of semiconductor substrate units, and each semiconductor substrate unit defines an electrical contact dense region and an electrical contact sparse region; a plurality of conductive bumps formed on each of the semiconductor substrate units in the active region; and a plurality of current control bumps formed in the idle regions, wherein the density of the plurality of conductive bumps in the electrical contact dense region is greater than the density of the plurality of current control bumps in the idle region, and the density of the plurality of current control bumps in the idle region is greater than the density of the plurality of conductive bumps in the electrical contact sparse region.
[0007] This application also provides a method for manufacturing a semiconductor structure, comprising: providing a semiconductor substrate, defining adjacent active regions and idle regions, wherein the active regions are provided with a plurality of semiconductor substrate units, and each semiconductor substrate unit defines an electrical contact dense region and an electrical contact sparse region; forming a plurality of conductive bumps on each of the semiconductor substrate units in the active regions; and forming a plurality of current control bumps in the idle regions, wherein the density of the plurality of conductive bumps in the electrical contact dense region is greater than the density of the plurality of current control bumps in the idle region, and the density of the plurality of current control bumps in the idle region is greater than the density of the plurality of conductive bumps in the electrical contact sparse region.
[0008] In the aforementioned semiconductor structure and its manufacturing method, each semiconductor substrate unit in the functional region is provided with a plurality of electrical connection pads.
[0009] In the aforementioned semiconductor structure and its manufacturing method, an insulating layer is provided on the semiconductor substrate, and the insulating layer has multiple openings that expose the multiple electrical connection pads.
[0010] The aforementioned semiconductor structure and its manufacturing method further include forming a conductive layer on the insulating layer and the plurality of electrical connection pads.
[0011] In the aforementioned semiconductor structure and its fabrication method, the conductive layer is a bump-under metal layer.
[0012] The aforementioned semiconductor structure and its manufacturing method further include forming a resist layer on the conductive layer, wherein the resist layer has a plurality of first openings in the active area to expose the conductive layer corresponding to the plurality of electrical connection pads, and the resist layer has a plurality of second openings in the idle area to form a current control pattern, and exposes the conductive layer corresponding to a portion of the insulating layer.
[0013] The aforementioned semiconductor structure and its manufacturing method further include forming the plurality of conductive bumps in the plurality of first openings and forming the plurality of current control bumps in the plurality of second openings.
[0014] The aforementioned semiconductor structure and its fabrication method also include removing the resist layer and the conductive layer it covers.
[0015] In the aforementioned semiconductor structure and its fabrication method, the density of the multiple conductive bumps in the dense electrical contact region is greater than twice the density of the multiple conductive bumps in the sparse electrical contact region.
[0016] As can be seen from the above, the semiconductor structure of this application mainly utilizes multiple first openings of the resist layer in the active area of the semiconductor substrate. When multiple conductive bumps are to be formed by electroplating, multiple second openings of the resist layer are simultaneously set in the idle area of the semiconductor substrate (forming a current control pattern), thereby electroplating to form multiple current control bumps, so as to disperse the electroplating current and avoid the problem of uneven distribution of electroplating current causing inconsistent height and flatness of multiple conductive bumps. Attached Figure Description
[0017] Figures 1 to 6 This is a cross-sectional and planar schematic diagram of the semiconductor structure and its fabrication method according to this application.
[0018] Explanation of reference numerals in the attached figures
[0019] 1. Semiconductor Structure
[0020] 10 Semiconductor substrate
[0021] 10a Scope
[0022] 10b Unused Area
[0023] 100 Semiconductor Substrate Units
[0024] 100A Dense Area of Electrical Contacts
[0025] 100b Electrical contact sparse region
[0026] 11 Electrical connection pads
[0027] 12 Insulation layer
[0028] 120 opening
[0029] 13 Conductive layer
[0030] 14. Barrier layer
[0031] 141 First Opening
[0032] 142 Second opening
[0033] 142p Current Control Pattern
[0034] 15 Conductive bumps
[0035] 16 Current-controlled bumps. Detailed Implementation
[0036] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.
[0037] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.
[0038] Please see Figures 1 to 6 The figures shown are cross-sectional and planar schematic diagrams of the semiconductor structure and its fabrication method according to this application. The semiconductor structure of this application is a monolithic architecture, such as a wafer form.
[0039] like Figure 1 As shown, a semiconductor substrate 10 (e.g., a wafer, a silicon substrate, or a glass substrate) is provided, which defines adjacent active regions 10a and idle regions 10b. The active regions 10a are provided with a plurality of semiconductor substrate units 100 (e.g., wafers), while the semiconductor substrate 10 in the idle regions 10b does not have any complete semiconductor substrate unit 100.
[0040] Please refer to the following at the same time. Figure 2 ,for Figure 1 A partial cross-sectional view of the semiconductor substrate 10 shows that a plurality of electrical connection pads 11 are provided on one surface of each semiconductor substrate unit 100 corresponding to the active region 10a. These electrical connection pads 11 may be provided only in the active region 10a and not in the idle region 10b, or they may be provided in both the active region 10a and the idle region 10b. An insulating layer 12 is provided on the entire semiconductor substrate 10, and the insulating layer 12 has a plurality of openings 120 forming the openings through which the plurality of electrical connection pads 11 are exposed. In one embodiment, the material forming the electrical connection pads 11 may be aluminum, and the material forming the insulating layer 12 may be polyimide (PI), benezocyclobutene (BCB), or polybenzoxazole (PBO).
[0041] In addition, each of the semiconductor substrate units 100 also defines an electrical contact dense region 100a and an electrical contact sparse region 100b, wherein the density of the plurality of electrical connection pads 11 in the electrical contact dense region 100a is greater than twice the density of the plurality of electrical connection pads 11 in the electrical contact sparse region 100b.
[0042] Next, a conductive layer 13 is formed on the insulating layer 12 and on the plurality of electrical connection pads 11 that expose the openings 120 of the insulating layer 12. The conductive layer 13 can serve as an under bump metal layer (UBM). In this embodiment, the material forming the conductive layer 13 can be titanium / copper (Ti / Cu) or titanium / tungsten / copper (Ti / W / Cu).
[0043] like Figure 3 and Figure 4 As shown, where, Figure 4 for Figure 3 A partial top view is shown. Then, a patterned resist layer 14 is formed on the conductive layer 13. The resist layer 14 has multiple first openings 141 in the active area 10a, exposing the conductive layer 13 corresponding to the multiple electrical connection pads 11. The resist layer 14 has multiple second openings 142 in the idle area 10b, exposing the conductive layer 13 corresponding to the portion of the insulating layer 12. The multiple second openings 142 formed by the resist layer 14 in the idle area 10b constitute a current control pattern 142p. The size or shape of each second opening 142 can be the same or different, depending on the actual needs.
[0044] like Figure 5 As shown, a plurality of conductive bumps 15 are formed on the conductive layer 13 exposing the plurality of first openings 141 through an electroplating process, and a plurality of current control bumps 16 are formed on the conductive layer 13 exposing the plurality of second openings 142 (current control pattern 142p).
[0045] Accordingly, compared to existing applications where the density of multiple electrical connection pads 11 in the dense electrical contact region 100a is greater than twice the density of multiple electrical connection pads 11 in the sparse electrical contact region 100b, which may lead to uneven electroplating current, this application addresses this by additionally forming multiple second openings 142 in the resist layer 14 in the idle region 10b (non-complete wafer region) to create a current control pattern 142p. This disperses the electroplating current, and the resist layer 14 in the dense electrical contact region 100a... The density of the multiple first openings 141 in the idle area 10b is greater than the density of the multiple second openings 142 (current control pattern 142p) in the resistive layer 14 in the idle area 10b, and the density of the multiple second openings 142 (current control pattern 142p) in the resistive layer 14 in the idle area 10b is greater than the density of the multiple first openings 141 in the resistive layer 14 in the electrical contact sparse area 100b. This can prevent current from concentrating in the electrical contact sparse area 100b, thus avoiding flatness problems of the conductive bumps 15.
[0046] like Figure 6As shown, the resist layer 14 and the conductive layer 13 it covers are then removed to obtain the semiconductor structure 1 of this application.
[0047] Through the aforementioned manufacturing method, this application provides a semiconductor structure 1, which is a monolithic architecture and includes a semiconductor substrate 10, which defines adjacent active regions 10a and idle regions 10b. The active region 10a is provided with a plurality of semiconductor substrate units 100, and each semiconductor substrate unit 100 defines an electrical contact dense region 100a and an electrical contact sparse region 100b. A plurality of conductive bumps 15 are formed on each of the semiconductor substrate units 100 in the active region 10a. A plurality of current control bumps 16 are formed in the idle region 10b. The density of the plurality of conductive bumps 15 in the electrical contact dense region 100a is greater than the density of the plurality of current control bumps 16 in the idle region 10b, and the density of the plurality of current control bumps 16 in the idle region 10b is greater than the density of the plurality of conductive bumps 15 in the electrical contact sparse region 100b. For example, the density of multiple conductive bumps 15 in the dense electrical contact region 100a is greater than twice the density of multiple conductive bumps 15 in the sparse electrical contact region 100b.
[0048] The semiconductor structure 1 also includes a plurality of electrical connection pads 11, which are provided only on each of the semiconductor substrate units in the active region 10a, and not in the idle region 10b.
[0049] The semiconductor structure 1 also includes an insulating layer 12 disposed on the semiconductor substrate 10, and has multiple openings 120 that expose the multiple electrical connection pads 11.
[0050] The semiconductor structure 1 further includes a conductive layer 13 disposed on a portion of the insulating layer 12 and the electrical connection pad 11. The conductive layer 13 is a bump-under metal layer. The plurality of conductive bumps 15 are disposed on the conductive layer 13 corresponding to the plurality of electrical connection pads 11, and the current control bump 16 is disposed on the conductive layer 13 corresponding to the portion of the insulating layer 12.
[0051] In summary, the semiconductor structure of this application mainly utilizes multiple first openings of the resist layer in the active area of the semiconductor substrate. When electroplating to form multiple conductive bumps, multiple second openings of the resist layer are also set in the idle area of the semiconductor substrate (forming a current control pattern), thereby electroplating to form multiple current control bumps to disperse the electroplating current and avoid uneven distribution of electroplating current causing inconsistent height and flatness of multiple conductive bumps.
[0052] The above embodiments are used to illustrate the principles and effects of this application, and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.
Claims
1. A semiconductor structure, characterized by, Comprising: a semiconductor substrate, defining an active region and a spare region, wherein the active region is provided with a plurality of semiconductor substrate units, and each of the semiconductor substrate units defines an electrically connecting dense region and an electrically connecting sparse region; a plurality of conductive bumps formed on each of the semiconductor substrate units of the active region; and a plurality of current control bumps formed on the spare region, wherein the density of the plurality of conductive bumps of the electrically connecting dense region is greater than the density of the plurality of current control bumps of the spare region, and the density of the plurality of current control bumps of the spare region is greater than the density of the plurality of conductive bumps of the electrically connecting sparse region.
2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a plurality of electrically connecting pads provided only on each of the semiconductor substrate units of the active region.
3. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises an insulating layer provided on the semiconductor substrate, and the insulating layer is formed with a plurality of openings to expose the plurality of electrically connecting pads.
4. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises a conductive layer provided on part of the insulating layer and the plurality of electrically connecting pads.
5. The semiconductor structure of claim 4, wherein, The conductive layer is a bump under metal layer.
6. The semiconductor structure of claim 4, wherein, The plurality of conductive bumps are provided on the conductive layer corresponding to the plurality of electrically connecting pads.
7. The semiconductor structure of claim 4, wherein, The plurality of current control bumps are provided on the conductive layer corresponding to the part of the insulating layer.
8. The semiconductor structure of claim 1, wherein, The density of the plurality of conductive bumps of the electrically connecting dense region is greater than 2 times the density of the plurality of conductive bumps of the electrically connecting sparse region.