Semiconductor device

Abstract

A semiconductor device includes a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate, a plurality of second nanostructure channels arranged in the first direction and adjacent to the first nanostructure channels in a second direction, the first nanostructure channel and the second nanostructure channel extend in a third direction perpendicular to the second direction. The semiconductor device further includes a first gate structure surrounding the first nanostructure channel, a first gate dielectric layer between the first gate structure and the first nanostructure channel, a second gate structure surrounding the second nanostructure channel, and a second gate dielectric layer between the second gate structure and the second nanostructure channel, wherein in the third direction, an angle between the first gate dielectric layer on a sidewall of a nanostructure channel in the first nanostructure channels and the first gate dielectric layer on a top surface of the nanostructure channel is greater than or equal to 100 degrees.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] As semiconductor device manufacturing advances and technology nodes shrink in size, the short-channel effect (SCE) can impact transistors, causing effects such as hot carrier degradation, barrier reduction, quantum confinement, and others. Furthermore, as the gate length of transistors used in smaller technology nodes decreases, source / drain (S / D) electron tunneling increases, thus increasing the transistor's off-state current (the current flowing through the transistor channel when the transistor is in an off configuration). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, and gate-all-around (GAA) devices, are options that may overcome the short-channel effect at smaller technology nodes. Compared to other transistor types, nanostructure transistors are high-efficiency structures that can reduce the short-channel effect and enhance carrier mobility. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor device includes a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate of the semiconductor device, and a plurality of second nanostructure channels arranged in a second direction adjacent to the first nanostructure channels and perpendicular to the first nanostructure channels, wherein the first and second nanostructure channels extend in a third direction perpendicular to the second direction. The semiconductor device includes a first gate structure surrounding the first nanostructure channels and including a first type work function metal layer, and a first gate dielectric layer located between the first gate structure and the first nanostructure channels, wherein in a third direction, the angle between a first portion of the first gate dielectric layer located on the sidewall of a nanostructure channel in the first nanostructure channel and a second portion of the first gate dielectric layer located on the top surface of the nanostructure channel is greater than or equal to 100 degrees. The semiconductor device includes a second gate structure surrounding each of the second nanostructure channels and including a second type work function metal layer different from the first type work function metal layer, and a second gate dielectric layer located between the second gate structure and the second nanostructure channels.

[0004] According to some embodiments of this disclosure, a semiconductor device includes a first transistor. The first transistor includes a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate, a first gate structure surrounding the first nanostructure channels and including a metal layer of a first type of work function, and a first high-dielectric-constant gate dielectric layer located between the first gate structure and the first nanostructure channels, wherein the first high-dielectric-constant gate dielectric layer includes a plurality of corner rounded corners located at a plurality of corners of the first nanostructure channels.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate, a plurality of adjacent interlayer dielectric regions adjacent to a plurality of sides of the first nanostructure channels, a first type work function metal layer surrounding each of the first nanostructure channels and located on a plurality of sidewalls of the adjacent interlayer dielectric regions, and a first gate dielectric layer located between the first type work function metal layer and the first nanostructure channels, wherein gaps between the adjacent interlayer dielectric regions physically separate a plurality of portions of the first type work function metal layer on the sidewalls of the adjacent interlayer dielectric regions. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1C An example implementation of the fin definition process described herein is illustrated;

[0008] Figure 2 Illustrated the example virtual gate structure fabrication process described in this article;

[0009] Figure 3 An example implementation of the source / drain trench formation process described herein is illustrated;

[0010] Figure 4A and Figure 4B An example embodiment of the inner spacer formation process described herein is illustrated;

[0011] Figure 5 An example implementation of the source / drain region formation process described herein is illustrated;

[0012] Figure 6 An example implementation of the interlayer dielectric formation process described herein is illustrated;

[0013] Figures 7A to 7P Illustrated example implementations of the alternative gate process described herein;

[0014] Figure 8 An example of corner rounding in the nanostructure channel of the semiconductor device described in this article is illustrated;

[0015] Figure 9 and Figure 10 This document presents an example process flow diagram related to the formation of semiconductor devices.

[0016] [Symbol Explanation]

[0017] 100: Implementation Method

[0018] 105: Semiconductor Devices

[0019] 110: Semiconductor substrate

[0020] 115: Layer stacking

[0021] 120: Sacrificial Nanostructure Layer

[0022] 125: Nanostructured Channel Layer

[0023] 130: Hard mask layer

[0024] 135: Covering layer

[0025] 140: Oxide layer

[0026] 145: Nitride layer

[0027] 150, 150a, 150b: Fin structure

[0028] 155: Part

[0029] 160: Fin section

[0030] 165: Lining

[0031] 170: Shallow trench isolation area

[0032] 200: Implementation Method

[0033] 205: Virtual gate structure

[0034] 210: Gate electrode layer

[0035] 215: Hard mask layer

[0036] 220: Spacer layer

[0037] 225: Gate dielectric layer

[0038] 300: Implementation Method

[0039] 305: Source / Drain Groove

[0040] 310, 310a, 310b: Platform Area

[0041] 315, 315a, 315b: Nanostructured channels

[0042] 400: Implementation Method

[0043] 405: Void

[0044] 410: Inner spacer

[0045] 500: Implementation Method

[0046] 505: Buffer Area

[0047] 510: Source / Drain Region

[0048] 600: Implementation Method

[0049] 605: Dielectric layer

[0050] 610: Contact Etching Stop Layer

[0051] 615: Covering layer

[0052] 700: Implementation Method

[0053] 705: Opening

[0054] 710a: n-type gate structure

[0055] 710b: p-type gate structure

[0056] 715: Gate dielectric layer

[0057] 720: Sacrifice Interval Layer

[0058] 725: Gap

[0059] 730: Masking layer

[0060] 735: Sacrificial Spacer

[0061] 740: Positive ion

[0062] 745: Positive surface charge

[0063] 750: p-type work function metal layer

[0064] 755: p-type work function metal layer

[0065] 760: Mask layer

[0066] 765: n-type work function metal layer

[0067] 770: n-type work function metal layer

[0068] 775: Gate electrode layer

[0069] 800, 802, 804, 806: Examples

[0070] 900: Process

[0071] 910, 920, 930, 940: Squares

[0072] 1000: Process

[0073] 1010, 1020, 1030, 1040, 1050, 1060, 1070: Blocks AA, BB, CC, DD: Cross-sections

[0074] D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11: Dimensions X, Y, Z: Orientation Detailed Implementation

[0075] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0076] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0077] Nanostructured transistors can include gate structures surrounding multiple nanostructured channels. Gate structures surrounding nanostructured channels increase control over the gate structure above the conductive channels in the nanostructured channels, increase the drive current of the nanostructured transistor, and / or reduce the short-channel effect (SCE) of the nanostructured transistor. In some examples, semiconductor devices can include p-type metal-oxide-semiconductor (PMOS) nanostructured transistors and n-type metal-oxide-semiconductor (NMOS) nanostructured transistors. Integrating PMOS and NMOS nanostructured transistors into the same semiconductor device can realize complementary metal-oxide-semiconductor (CMOS) integrated circuits within the semiconductor device. CMOS integrated circuits have various applications in the semiconductor industry, including microprocessors (e.g., central processing units (CPUs)), graphics processing units (GPUs), memory devices, digital logic circuits, image sensors (e.g., CMOS image sensors), and / or radio frequency (RF) circuits.

[0078] The threshold voltage (Vt) of a nanostructured transistor is the gate voltage required to turn it on or off. If the threshold voltage is too low (meaning the gate voltage required to turn it on is too low), the transistor may experience significant leakage current when turned off. Conversely, if the threshold voltage is too high, the higher gate voltage required to operate the transistor may degrade its power efficiency. For both PMOS and NMOS nanostructured transistors, the type of metal used in the gate structure can directly affect the threshold voltage. The work function of the gate structure... Adjusting the metal to achieve optimal performance for PMOS nanostructure transistors can result in a large band gap between the work function of the gate structure and the conduction band (EC) of NMOS nanostructure transistors, leading to high threshold voltage (and low energy efficiency) in NMOS nanostructure transistors. Similarly, adjusting the metal to optimize the work function of the gate structure can result in a large band gap between the work function of the gate structure and the valence band (EV) of PMOS nanostructure transistors, leading to high threshold voltage (and low energy efficiency) in PMOS nanostructure transistors.

[0079] In some examples, the work function metal layers of PMOS and NMOS nanostructure transistors can be formed sequentially. For instance, the work function metal layer of the PMOS nanostructure transistor can be formed first, followed by the work function metal layer of the NMOS nanostructure transistor. The work function metal layer of the PMOS nanostructure transistor can be formed around the nanostructure channels of both the PMOS and NMOS nanostructure transistors, and subsequently, before forming the work function metal layer of the NMOS nanostructure transistor, the work function metal layer of the PMOS nanostructure transistor can be removed from the nanostructure channels of the NMOS nanostructure transistor. However, residual material from the work function metal layer of the PMOS nanostructure transistor may remain on the nanostructure channels of the NMOS nanostructure transistor, for example, between vertically adjacent nanostructure channels. Such residual material may alter the threshold voltage of the NMOS nanostructure transistor, thus potentially causing the NMOS nanostructure transistor to perform suboptimally.

[0080] In some embodiments described herein, sacrificial spacers are formed between vertically adjacent nanostructure channels of the first nanostructure transistor to avoid or reduce the likelihood of material deposition of the work function metal layer of the second nanostructure transistor between the vertically adjacent nanostructure channels. In this manner, the sacrificial spacers increase the likelihood of completely removing material of the work function metal layer of the second nanostructure transistor from the first nanostructure transistor before the work function metal layer of the second nanostructure transistor is formed.

[0081] Forming sacrificial spacers can be achieved by depositing a conformal sacrificial spacer layer around the nanostructure channels of the first nanostructure channel, followed by etching the sacrificial spacer layer such that it remains as a sacrificial spacer only between the vertically adjacent nanostructure channels of the first nanostructure transistor. In some examples, a seam may be formed within the sacrificial spacer layer between the vertically adjacent nanostructure channels. The anisotropic wet etching technique described herein can be used to etch the sacrificial spacer layer such that the etching does not enlarge (or minimally enlarges) the seam, which would otherwise increase the likelihood that the work function metal layer material of the second nanostructure transistor is deposited in the seam between the vertically adjacent nanostructure channels. Therefore, the anisotropic wet etching technique described herein can increase the likelihood of completely removing the work function metal layer material of the second nanostructure transistor from the first nanostructure transistor before forming the work function metal layer of the second nanostructure transistor.

[0082] Figures 1A to 1C An example embodiment 100 of the fin definition process described herein is illustrated. Example embodiment 100 includes examples of forming a fin structure and associated shallow trench isolation (STI) regions for a semiconductor device 105 described herein. The fabricated semiconductor device 105 may include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. Example embodiment 100 includes examples of forming a fin structure and associated shallow trench isolation regions for the transistors of the semiconductor device 105.

[0083] Figures 1A to 1C Each of the illustrations shows a perspective view of the semiconductor device 105 and a cross-sectional view along section AA in the perspective view. For example... Figure 1A As shown, the semiconductor processing apparatus 105 is related to the semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates.

[0084] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be a superlattice. The layer stack 115 comprises multiple alternating layers arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the Z direction). For example, the layer stack 115 includes vertically alternating sacrificial nanostructure layers 120 and nanostructure channel layers 125 above the semiconductor substrate 110. (Illustrated) Figure 1A The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 is an example, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are also within the scope of this disclosure.

[0085] The sacrificial nanostructure layer 120 can define the vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 125, and the sacrificial nanostructure layer 120 can serve as a berthing layer for the gate structure surrounding the nanostructure channels of the transistor subsequently formed in the semiconductor device 105. The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. As an example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). Thus, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 can be selectively etched depending on the type of etchant used (e.g., the sacrificial nanostructure layer 120 may be etched without etching the nanostructure channel layer 125, or the nanostructure channel layer 125 may be etched without etching the sacrificial nanostructure layer 120).

[0086] One or more types of deposition tools can be used to deposit and / or grow alternating layers of layer stack 115, such that layer stack 115 includes nanostructures (e.g., nanosheets) on semiconductor substrate 110. For example, deposition tools can be used to epitaxially grow sacrificial nanostructure layer 120 and / or nanostructure channel layer 125, and epitaxial techniques can include, for example, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or other suitable epitaxial techniques. Additionally and / or alternatively, deposition of sacrificial nanostructure layer 120 and / or nanostructure channel layer 125 can be achieved through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques.

[0087] One or more masking layers may be formed (e.g., using one or more deposition tools) on the layer stack 115. The masking layers may include a hard mask (HM) layer 130, a capping layer 135, an oxide layer 140, and / or a nitride layer 145. The masking layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0088] like Figure 1B As shown, an etch layer stack 115 and a semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This forms a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend in the Y direction within the semiconductor device 105 and may be arranged in the X direction within the semiconductor device 105. The fin structure 150 includes a portion 155 of the layer stack 115 above and / or over a fin portion 160 on the semiconductor substrate 110. The fin structure 150 can be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on the pattern in the one or more masking layers. The patterning of the one or more masking layers can be done using photolithography techniques, including dual-patterning or multi-patterning techniques. Etching tools can be used to etch the semiconductor substrate 110 according to the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0089] like Figure 1BAs further shown, some of the formed fin structures 150 can have different widths for different types of nanostructure transistors. As an example, the fin structure 150a forming the first subgroup can be used for p-type nanostructure transistors (e.g., p-type metal-oxide-semiconductor nanostructure transistors), and the fin structure 150b forming the second subgroup can be used for n-type nanostructure transistors (e.g., n-type metal-oxide-semiconductor nanostructure transistors). As another example, the fin structure 150a forming the first subgroup can be used for nanostructure transistors configured to operate at low voltages, and the fin structure 150b forming the second subgroup can be used for nanostructure transistors configured to operate at high voltages.

[0090] like Figure 1C As shown, a liner 165 and a shallow trench isolation region 170 are formed between adjacent fin portions 160 of the fin structure 150. The liner 165 and the shallow trench isolation region 170 may each comprise a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low dielectric constant dielectric materials and / or other suitable insulating materials.

[0091] A deposition tool can be used to conformally deposit the liner 165 (e.g., using atomic layer deposition or other conformal deposition techniques) and can deposit a dielectric layer (e.g., using chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other suitable deposition techniques) on the liner 165, such that the dielectric layer completely fills the voids between the fin structures 150 and extends above the top of the fin structures 150. Next, a planarization tool can be used to perform a planarization or polishing operation (e.g., chemical mechanical planarization (CMP) operation) to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the nitride layer 145. The nitride layer 145 serves as the top layer for CMP planarization in the planarization operation. Next, an etching tool can be used to etch the dielectric layer to form shallow trench isolation regions 170, such that the top surface of the shallow trench isolation regions 170 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0092] As mentioned above, Figures 1A to 1C As an example. Other examples may differ. Figures 1A to 1C As stated above.

[0093] Figure 2An example embodiment 200 of the virtual gate formation process described herein is illustrated. Example embodiment 200 includes an example of forming a virtual gate structure 205 for a nanostructure transistor in a semiconductor device 105. In some embodiments, in Figures 1A to 1C The operation described in Example Implementation 200 is performed after the process described above.

[0094] Figure 2 A perspective view of a semiconductor device 105 having a dummy gate structure 205 formed thereon is illustrated. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed over a portion of the fin structure 150 and a portion of the shallow trench isolation region 170. The dummy gate structure 205 extends in the X direction and is aligned in the Y direction such that the dummy gate structure 205 is substantially perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in subsequent process stages of the semiconductor device 105. The dummy gate structure 205 can also be used to define source / drain (S / D) trenches to form the source / drain regions of nanostructured transistors within the fin structure 150.

[0095] The virtual gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 above and / or on the gate electrode layer 210, a spacer layer 220 located on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (polysilicon or PO) or other materials. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or other materials) and a nitride layer formed above the oxide layer (e.g., a pad nitride layer that may include silicon nitride (e.g., Si3N4) or other materials). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiO2, for example, SiO2). x ), silicon nitride (e.g., Si3N4, for example, Si x N y ), high-k dielectric materials (e.g., dielectric materials with a dielectric constant greater than about 3.9) and / or other suitable materials.

[0096] The layer forming the virtual gate structure 205 can be formed using a variety of semiconductor process technologies, such as depositing the layer of the virtual gate structure 205, patterning the layer of the virtual gate structure 205 to define the virtual gate structure 205, and / or other semiconductor process technologies.

[0097] Figure 2Further reference sections are illustrated in the figures used in the following description. Section AA spans the fin structure 150 in the source / drain region of semiconductor device 105 in the XZ plane (considered a Y-section). Section BB is perpendicular to section AA in the YZ plane (considered an X-section) and spans the dummy gate structure 205 and along the underlying fin structure 150. Section CC is parallel to section AA and perpendicular to section BB in the XZ plane and along the dummy gate structure 205. Section DD is perpendicular to section AA in the YZ plane (considered an X-section) and spans the dummy gate structure 205 and along the shallow trench isolation region 170 between adjacent underlying fin structures 150. For clarity, the following figures refer to these reference sections. In some figures, some reference numbers illustrating components or features may be omitted to avoid obscuring other components or features in order to depict these figures.

[0098] As mentioned above, Figure 2 As an example. Other examples may differ. Figure 2 As stated above.

[0099] Figure 3 An example embodiment 300 of the source / drain trench formation process described herein is illustrated. Example embodiment 300 includes an example of forming a source / drain trench 305 for the source / drain region of a nanostructured transistor in semiconductor device 105. Figure 3 Draw Figure 2 Multiple perspectives, including Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The perspective of section CC in the middle. In some implementations, in Figures 1A to 2 Following the aforementioned process, the operations described with respect to Example Implementation 300 are performed.

[0100] like Figure 3 As shown in sections AA and BB, a source / drain recess 305 is formed through a portion 155 of the fin structure 150 during the etching operation. The source / drain recess 305 is formed on opposite sides of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes using plasma etching, wet chemical etching, and / or other types of etching techniques.

[0101] The source / drain recesses 305 also extend into the fin portion 160 of the fin structure 150. This forms a plateau region 310 in the fin structure 150. The sidewalls of the portions of the respective source / drain recesses 305 below portion 155 correspond to the sidewalls of the plateau region 310. The plateau region 310 (also referred to as the pedestal) represents the region of the fin portion 160 of the fin structure 150, in which the nanostructured channels defined by the nanostructured channel layer 125 are located. The nanostructured channels 315 extend between adjacent source / drain recesses 305 and are located beneath the virtual gate structure 205 between adjacent source / drain recesses 305.

[0102] The nanostructure channel 315 includes silicon-based nanostructures (e.g., nanosheets or nanowires) and serves as a semiconducting channel for the nanostructure transistors of the semiconductor device 105. In some embodiments, the nanostructure channel 315 may include silicon germanium (SiGe) or other silicon-based materials. The nanostructure channels 315 are arranged in a direction generally perpendicular to the semiconductor substrate 110 (e.g., the Z direction). In other words, the nanostructure channels 315 are vertically aligned or stacked above the semiconductor substrate 110.

[0103] As mentioned above, Figure 3 As an example. Other examples may differ. Figure 3 As stated above.

[0104] Figure 4A and Figure 4B An example embodiment 400 of the internal spacer formation process described herein is illustrated. Example embodiment 400 includes an example of forming internal spacers between the ends of a nanostructured channel 315 and exposed in a source / drain groove 305. Figure 4A and Figure 4B Each drawing Figure 2 Multiple perspectives, including Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The perspective of section CC in the middle. In some implementations, in Figures 1A to 3 Following the aforementioned process, the operations described with respect to Example Implementation 400 are performed.

[0105] like Figure 4AAs shown in section BB, during the etching operation, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain trench 305 are laterally etched (e.g., in the X direction generally parallel to the length of the sacrificial nanostructure layer 120), thereby forming voids 405 between the ends of the nanostructure channels 315 exposed in the source / drain trench 305. Specifically, the etching tool can be used to laterally etch the ends of the sacrificial nanostructure layer 120 beneath the dummy gate structure 205 through the source / drain trench 305 to form voids 405 between the ends of the nanostructure channels 315. The voids 405 can be formed into generally curved shapes, generally concave shapes, generally triangular shapes, generally square shapes, or other shapes.

[0106] like Figure 4B As shown in cross sections AA and BB, an inner spacer (InSP) 410 is formed in the void 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The structure includes the inner spacer 410 to reduce parasitic capacitance in the nanostructure transistor and to protect the source / drain regions (subsequently formed in the source / drain recess 305) from etching during the nanosheet release operation of removing the sacrificial nanostructure layer 120 between the nanostructure channels 315. The inner spacer 410 comprises silicon nitride (Si). x N y ), silicon dioxide (SiO) x ), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN) and / or other dielectric materials.

[0107] To form the inner spacer 410, a deposition tool can be used to deposit a layer of dielectric material in the cavity 405 and along the sidewalls and bottom surface of the source / drain recess. Chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other deposition techniques can be used to deposit the dielectric material layer. An etching tool is used to subsequently remove excess material from the source / drain recess, such that the remaining portion corresponds to the inner spacer 410 in the cavity 405. In some embodiments, the etching operation can cause the surface of the inner spacer 410 facing the source / drain recess 305 to bend or recess. In some embodiments, the surface of the inner spacer 410 facing the source / drain recess 305 is generally flat, such that the surface of the inner spacer 410 and the surface of the end of the nanostructure channel 315 are generally smooth and flush.

[0108] As mentioned above, Figure 4A and Figure 4B As an example. Other examples may differ. Figure 4A and Figure 4B As stated above.

[0109] Figure 5 An example implementation 500 of the source / drain region formation process described herein is illustrated. Example implementation 500 includes an example of forming source / drain regions for a nanostructure transistor of semiconductor device 105. Figure 5 Draw Figure 2 Multiple perspectives, including Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The perspective of section CC in the middle. In some implementations, in Figures 1A to 4B Following the aforementioned process, the operations described with respect to Example Implementation 500 are performed.

[0110] like Figure 5 As shown in cross sections AA and BB, one or more layers are used to fill the source / drain recess 305 to form source / drain regions within the source / drain recess 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain recess 305, and the deposition tool can deposit source / drain regions 510 on the buffer regions 505 within the source / drain recess 305. In some embodiments, the deposition tool is used to deposit a capping layer on the source / drain regions 510 within the source / drain recess 305.

[0111] Buffer region 505 may include silicon (Si), boron-doped silicon (SiB), other dopants, and / or other materials. A buffer region 505 may be included between the source / drain region 510 and the adjacent plateau region 310 to reduce, minimize, and / or prevent dopant migration and / or leakage current from the source / drain region 510 to the adjacent plateau region 310, which could otherwise lead to short-channel effects in the semiconductor device 105. Therefore, buffer region 505 can improve the performance of the semiconductor device 105 and / or increase the yield of the semiconductor device 105.

[0112] Depending on the context, source / drain regions 510 may independently represent a source or drain, or a set may represent both a source and a drain. Source / drain regions 510 may be included on opposite sides of the dummy gate structure 205, such that a nanostructure channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain regions 510. Each source / drain region 510 includes silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), n-type materials (e.g., phosphorus (P) or arsenide (As), etc.), and / or other types of dopants. Therefore, semiconductor device 105 may include p-type metal-oxide-semiconductor nanostructure transistors with p-type source / drain regions 510, n-type metal-oxide-semiconductor nanostructure transistors with n-type source / drain regions 510, and / or other types of nanostructure transistors.

[0113] One or more layers forming the source / drain region 510 can be epitaxially grown, deposited (e.g., using chemical vapor deposition, physical vapor deposition, atomic layer deposition), and / or using one or more other deposition techniques. For example, a deposition tool can epitaxially grow a first layer (referred to as L1) of the source / drain region 510 over an associated buffer region 505 (which may be referred to as L0), and a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 510 can be epitaxially grown over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or other dopants) and may be included in the structure as a masking layer to reduce short-channel effects in the semiconductor device 105 and reduce dopant squeezing or migration into the nanostructure channel 315. The second layer may include highly doped silicon or highly doped silicon-germanium. The structure may include a second layer to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0114] As mentioned above, Figure 5 As an example. Other examples may differ. Figure 5 As stated above.

[0115] Figure 6 An example implementation 600 of the interlayer dielectric (ILD) formation process described herein is illustrated. Figure 6 Draw Figure 2 Multiple perspectives, including Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The perspective of section DD in the middle. In some implementations, in Figures 1A to 5Following the aforementioned process, the operations described with respect to Example Implementation 600 are performed.

[0116] like Figure 6 As shown in cross-sections AA and BB, a dielectric layer 605 is formed over the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce and / or avoid the possibility of damage to the source / drain region 510 during an alternative gate process that replaces the dummy gate structures 205. The dielectric layer 605 may be referred to as an ILD zero layer (ILD0) or other ILD layers.

[0117] like Figure 6 As shown in sections AA, BB, and DD, a contact etch stop layer (CESL) 610 is conformally deposited (e.g., by a deposition tool) over the source / drain region 510 before the formation of dielectric layer 605. The contact etch stop layer 610 provides a mechanism to stop the etch process when forming contacts or vias in the source / drain region 510. The contact etch stop layer 610 may be formed of a dielectric material with a different etch selectivity than adjacent layers or components. The contact etch stop layer 610 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the contact etch stop layer 610 may include or may be silicon nitride (Si). x N y Silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxynitride (SiCO), or combinations thereof. The deposited contact etch stop layer 610 can be deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, or other deposition techniques. In some embodiments, a capping layer 615 is formed on the dielectric layer 605.

[0118] As mentioned above, Figure 6 As an example. Other examples may differ. Figure 6 As stated above.

[0119] Figures 7A to 7P An example implementation 700 of the replacement gate (RPG) process described herein is illustrated. Example implementation 700 includes an example of a replacement gate process in which a high-dielectric-constant / metal gate structure (e.g., an replacement gate structure) is used to replace the dummy gate structure 205 for the nanostructured transistor of semiconductor device 105. Figures 7A to 7P Each drawing Figure 2 Multiple perspectives, including Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle, Figure 2The angle of section CC and / or Figure 2 The perspective of section DD in the middle. In some implementations, in Figures 1A to 6 Following the aforementioned process, the operations described with respect to Example Implementation 700 are performed.

[0120] like Figure 7A As shown in sections BB and CC, the alternative gate process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removing the dummy gate structure 205 leaves an opening (or groove) between the dielectric layers 605 and provides a path to the underlying sacrificial nanostructure layer 120. Removing the dummy gate structure 205 can be one or more etching operations. Such etching operations can include plasma etching, wet chemical etching, and / or other types of etching techniques.

[0121] Removing the dummy gate structure 205 exposes the platform region 310a in the semiconductor device 105 and the stack of nanostructure channels 315a arranged in the Z direction above the platform region 310a. Removing the dummy gate structure 205 also exposes the platform region 310b in the semiconductor device 105 and the stack of nanostructure channels 315b arranged in the Z direction above the platform region 310b. The nanostructure channels 315a and 315b in the semiconductor device 105 extend in the Y direction. The nanostructure channels 315a and 315b in the semiconductor device 105 can be arranged in the X direction such that the nanostructure channels 315a and 315b are side-by-side or laterally adjacent.

[0122] In preparing the n-type gate structure around the nanostructure channel 315a of the NMOS nanostructure transistor forming the semiconductor device 105, the platform region 310a and the nanostructure channel 315a can be exposed. In preparing the p-type gate structure around the nanostructure channel 315b of the PMOS nanostructure transistor forming the semiconductor device 105, the platform region 310b and the nanostructure channel 315b can be exposed.

[0123] like Figure 7AAs further shown, the alternative gate process includes a nanostructure release operation (e.g., a SiGe release operation). The nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This creates openings 705 between nanostructure channels 315a (e.g., the region around nanostructure channels 315a) and between nanostructure channels 315b (e.g., the region around nanostructure channels 315b). The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on the etch selectivity differences between the materials of the sacrificial nanostructure layer 120 and the materials of the nanostructure channels 315a / 315b, and the etch selectivity differences between the materials of the sacrificial nanostructure layer 120 and the materials of the inner spacer 410. The inner spacer 410 may serve as an etch stop layer in the etching operation to protect the source / drain regions 510 from etching.

[0124] like Figures 7B to 7P As shown in cross-sections CC and / or DD, the alternative gate operation continues, and for the nanostructure transistor of semiconductor device 105, a gate structure (e.g., an alternative gate structure) is formed in the openings 705 between the nanostructure channels 315. Specifically, for the NMOS nanostructure transistor of semiconductor device 105, an n-type gate structure 710a is formed in the region between and around the nanostructure channels 315a. The n-type gate structure 710a occupies the region previously occupied by the sacrificial nanostructure layer 120, such that the n-type gate structure 710a surrounds the nanostructure channel 315a and encircles at least three sides of the nanostructure channel 315a. In some embodiments, the n-type gate structure 710a completely surrounds the nanostructure channel 315a and encircles all four sides of the nanostructure channel 315a.

[0125] For a PMOS nanostructure transistor in semiconductor device 105, a p-type gate structure 710b is formed in the region between and around the nanostructure channels 315b. The p-type gate structure 710b occupies the region previously occupied by the sacrificial nanostructure layer 120, such that the p-type gate structure 710b surrounds the nanostructure channel 315b and encircles at least three sides of the nanostructure channel 315b. In some embodiments, the p-type gate structure 710b completely surrounds the nanostructure channel 315b and encircles all four sides of the nanostructure channel 315b.

[0126] like Figure 7BAs shown, the gate dielectric layer 715 can be formed around the nanostructure channels 315a and 315b and on the platform regions 310a and 310b. Deposition tools can be used to deposit the gate dielectric layer 715, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. In some embodiments, the gate dielectric layer 715 is a high-dielectric-constant gate dielectric layer comprising one or more high-dielectric-constant materials (e.g., dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2, dielectric constant approximately 3.9)). Examples include lanthanum oxide (La). x O y For example, La2O3), hafnium oxide (HfO) x For example, HfO2), zirconium oxide (ZrO2) x For example, ZrO2) and / or aluminum oxide (Al) x O y Materials such as Al2O3 can be used. Alternatively, silicon dioxide (SiO2) and / or other dielectric materials can be used instead of high-dielectric-constant dielectric materials. In some embodiments, the gate dielectric layer 715 may have a thickness ranging from about 0.5 nanometers to about 3 nanometers. However, other numerical ranges are also within the scope of this disclosure.

[0127] like Figure 7B As further shown, a sacrificial spacer layer 720 is formed on the gate dielectric layer 715, such that the sacrificial spacer layer 720 surrounds the nanostructured channels 315a and 315b. The sacrificial spacer layer 720 is also formed on the plateau regions 310a and 310b. Deposition tools can be used to deposit the gate dielectric layer 715, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The sacrificial spacer layer 720 includes one or more materials that can be selectively etched relative to the gate dielectric layer 715, so that the sacrificial spacer layer 720 can subsequently be removed with minimal or no etching of the gate dielectric layer 715. Example materials for the sacrificial spacer layer 720 include alumina (Al₂O₃). x O y Examples include Al2O3, titanium nitride (TiN), and / or tungsten carbonitride (WCN).

[0128] The sacrificial spacer layer 720 can be formed to a certain thickness such that it is at least partially incorporated between vertically adjacent nanostructure channels 315a (e.g., adjacent in the Z direction) and between vertically adjacent nanostructure channels 315b. In some embodiments, the sacrificial spacer layer 720 is formed to a thickness in the range of about 30 angstroms to about 35 angstroms. However, other thickness values ​​and / or ranges of the sacrificial spacer layer 720 are also within the scope of this disclosure. A gap (or void) 725 is formed in the sacrificial spacer layer 720 between vertically adjacent nanostructure channels 315a and / or between vertically adjacent nanostructure channels 315b. The gap 725 may have a width in the Z direction (…). Figure 7B The size indicated by the label (D1) is less than approximately 1 nanometer.

[0129] like Figure 7C As shown, the sacrificial spacer layer 720 can be conformally deposited on a region of the dielectric layer 605. The sacrificial spacer layer 720 can conform to the cross-sectional profile of the region of the dielectric layer 605.

[0130] like Figure 7D and Figure 7E As shown, an etch-back operation can be performed to thin the sacrificial spacer layer 720 (e.g., reduce the thickness of the sacrificial spacer layer 720). For example, the thickness of the sacrificial spacer layer 720 before the etch-back operation can be in the range of approximately 30 angstroms to approximately 35 angstroms, and the thickness of the sacrificial spacer layer 720 after the etch-back operation can be in the range of approximately 15 angstroms to approximately 20 angstroms. However, other thickness values ​​and / or ranges of the sacrificial spacer layer 720 are also within the scope of this disclosure.

[0131] Etching tools can be used to etch the sacrificial spacer layer 720 during an etch-back operation. Dry etching techniques (e.g., plasma-based etching techniques, gas-based etching techniques), wet etching techniques (e.g., wet chemical etching techniques), and / or other suitable etching techniques can be used to etch the sacrificial spacer layer 720 to reduce the thickness of the sacrificial spacer layer 720.

[0132] like Figure 7F and Figure 7G As shown, the masking layer 730 can be used to remove the sacrificial spacer layer 720 from the nanostructure channel 315b and the platform region 310b. The masking layer 730 protects the sacrificial spacer layer 720 on the nanostructure channel 315a and the platform region 310a, such that the sacrificial spacer layer 720 remains on the nanostructure channel 315a and the platform region 310a.

[0133] A deposition tool can be used to deposit a mask layer 730 on nanostructure channels 315a, nanostructure channels 315b, plateau regions 310a and 310b. Subsequently, portions of the mask layer 730 can be removed from the nanostructure channels 315b and plateau regions 310b, thereby patterning the mask layer 730. An etching tool can be used to etch the mask layer 730 to pattern it.

[0134] Next, an etching tool can be used to remove the sacrificial spacer layer 720 from the nanostructure channel 315b and the plateau region 310b, while the masking layer 730 protects the nanostructure channel 315a and the plateau region 310a. In some embodiments, a wet etching technique is used to remove the sacrificial spacer layer 720 from the nanostructure channel 315b and the plateau region 310b. For example, a basic (or alkaline) wet etchant, such as ammonium hydroxide (NH4OH) (e.g., a wet etchant having a pH greater than 7), can be used to isotropically etch the sacrificial spacer layer 720 to remove the sacrificial spacer layer 720 from the nanostructure channel 315b and the plateau region 310b with minimal or no etching of the gate dielectric layer 715 on the nanostructure channel 315b and the plateau region 310b. The ammonium hydroxide wet etchant includes negatively charged ions (e.g., OH-) that can isotropically etch the sacrificial spacer layer 720. - The material of the sacrificial spacer layer 720 (e.g., aluminum oxide (Al2O3) etc.) can have a positive surface charge that attracts negatively charged ions from the ammonium hydroxide wet etchant.

[0135] Subsequently, the masking layer 730 can be removed from the nanostructure channel 315a and the platform region 310a using plasma ashing techniques (e.g., using nitrogen (N2) plasma and hydrogen (H2) reaction gas) and / or other types of masking layer removal techniques.

[0136] like Figures 7H to 7J As shown, another etch-back operation can be performed to trim the sacrificial spacer layer 720 on the nanostructure channel 315a and the platform region 310a. The sacrificial spacer layer 720 is also removed from the sidewalls of the region of dielectric layer 605 and from the top surface of dielectric layer 605 and shallow trench isolation region 170.

[0137] like Figure 7IAs shown, portions of the sacrificial spacer layer 720 on the sidewalls of the nanostructure channel 315a and the platform region 310a can be anisotropically etched to remove portions of the sacrificial spacer layer 720 on the sidewalls of the nanostructure channel 315a and the platform region 310a. Therefore, portions of the sacrificial spacer layer 720 between vertically adjacent nanostructure channels 315a are retained as sacrificial spacers 735. The etch-back operation also removes portions of the sacrificial spacer layer 720 on the shallow trench isolation region 170 and on the top surface of the topmost nanostructure channel 315a.

[0138] Anisotropic etching of the sacrificial spacer layer 720 can be achieved using an acidic wet etchant comprising positive ions 740 (e.g., a wet etchant having a pH value below 7). Therefore, a wet etchant different from the one used to remove the sacrificial spacer layer 720 from the nanostructure channel 315b and the plateau region 310b can be used to trim the sacrificial spacer layer 720 on the nanostructure channel 315a and the plateau region 310a. For example, a wet etchant comprising hydrogen ions (H+) can be used. + A wet etchant can be used to trim the sacrificial spacer layer 720 on the nanostructure channels 315a and the platform region 310a. Using an amphoteric material such as alumina for the sacrificial spacer layer 720 allows for etching with either an alkaline or acidic wet etchant. Examples of acidic wet etchants include hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrobromic acid (HBr), and / or carbon dioxide (CO2) dissolved in water (H2O). In some embodiments, the wet etchant is diluted in water to have a concentration from approximately 0.1 parts per million (ppm) to approximately 1 × 10⁻⁶. 7 Concentrations in the range of ppm. However, other values ​​and / or ranges are also within the scope of this disclosure. Example reactions between the wet etchant and the material of the sacrificial spacer layer 720 may include:

[0139] Al₂O₃ + 6H₂O + →2Al 3+ +H +

[0140] Hydrogen ions decompose alumina into aluminum cations and byproducts such as water (H2O). Hydrogen ions can protonate the oxygen atoms in alumina, causing solid alumina to decompose into soluble aluminum cations and water molecules.

[0141] The material of the sacrificial spacer layer 720 can have a positive surface charge 745. The positive surface charge 745 of the sacrificial spacer layer 720 repels positive ions 740 in the wet etchant. The charge repulsion between the positive surface charge 745 of the sacrificial spacer layer 720 and the positive ions 740 of the wet etchant promotes vertical etching of the sacrificial spacer layer 720 (e.g., Z-direction etching) and inhibits or prevents lateral etching of the sacrificial spacer layer 720 (e.g., X-direction etching, Y-direction etching). Specifically, the positive surface charge 745 of the sacrificial spacer layer 720 repels positive ions 740 in the wet etchant from entering the gaps 725 in the sacrificial spacer layer 720 between vertically adjacent nanostructure channels 315a. This avoids or minimizes etching of the sacrificial spacer layer 720 between vertically adjacent nanostructure channels 315a, and thus minimizes or prevents the expansion of the gaps 725 between the sacrificial spacers 735. Therefore, the Z-direction width of the gap 725 after the etch-back operation ( Figure 7I The size indicated by the symbol (D2) can also be less than about 1 nanometer.

[0142] like Figure 7I As further shown, the wet etchant used to trim the sacrificial spacer layer 720 to form the sacrificial spacer 735 can also etch the gate dielectric layer 715 on the nanostructure channels 315a and / or 315b. This may cause some corner rounding of the gate dielectric layer 715 to be located in the X direction at the corners of the nanostructure channels 315a and / or 315b. Therefore, in Figures 7H to 7J After the etch-back operation, the angle in the X direction between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315a and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315a can be greater than the angle between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315a and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315a before the etch-back operation. Additionally and / or alternatively, in Figures 7H to 7J After the etch-back operation, the angle in the X direction between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315b and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315b can be greater than the angle between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315b and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315b before the etch-back operation. For example, in Figures 7H to 7J Prior to the etching-back operation, the angle in the X direction between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315a (or nanostructure channel 315b) and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315a (or nanostructure channel 315b) can be less than approximately 100 degrees, and in Figures 7H to 7J After the etching-back operation, the angle in the X direction between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315a (or nanostructure channel 315b) and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315a (or nanostructure channel 315b) can be greater than or approximately equal to 100 degrees. However, other numerical ranges are also within the scope of this disclosure.

[0143] like Figure 7J As shown, the sacrificial spacer layer 720 is removed (e.g., completely removed) from the sidewall of the region of dielectric layer 605, resulting in minimal to no residual material of the sacrificial spacer layer 720 remaining on the sidewall of the region of dielectric layer 605.

[0144] like Figure 7K and Figure 7L As shown, a p-type work function metal layer 750 is formed on the gate dielectric layer 715, such that the p-type work function metal layer 750 surrounds the nanostructure channels 315a and 315b. The p-type work function metal layer 750 may also be formed on the plateau regions 310a and 310b. In some embodiments, the p-type work function metal layer 750 surrounding the nanostructure channels 315b is incorporated between the nanostructure channels 315b. In some embodiments, the p-type work function metal layer 750 surrounding the nanostructure channels 315b is not incorporated between the nanostructure channels 315b.

[0145] Since the p-type gate structure 710b is a metal gate structure, it may include a p-type work function metal layer 750 to adjust the work function of the p-type gate structure 710b. The p-type work function metal layer 750 may include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or other metals with a work function greater than approximately 4.7 eV. The structure may include a p-type work function metal layer 750 to adjust the work function of the PMOS nanostructure transistor, such that the work function is adjusted to be close to the valence band of the material of the nanostructure channel 315b. This allows for a relatively low threshold voltage and a relatively low leakage current in the PMOS nanostructure transistor.

[0146] Deposition tools can be used to deposit p-type work function metal layers 750, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, etc. Figures 1A to 1COther deposition techniques and / or other suitable deposition techniques may be described. The deposition of the p-type work function metal layer 750 may be performed in one or more deposition operations. In some embodiments, the p-type work function metal layer 750 is formed to a thickness ranging from about 0.5 nanometers to about 20 nanometers. However, other numerical ranges may also be within the scope of this disclosure.

[0147] Because no masking layer was used on the nanostructure channel 315a and the plateau region 310a when forming the p-type work function metal layer 750, the p-type work function metal layer 750 was also formed on the nanostructure channel 315a and the sidewalls of the plateau region 310a. For example... Figure 7K As shown, the sacrificial spacer 735 avoids or minimizes the material of the deposited p-type work function metal layer 750 between vertically adjacent nanostructure channels 315a and between the bottommost nanostructure channel 315a and the platform region 310a. Specifically, the above regarding Figures 7H to 7J Anisotropic etching of the intermediate sacrificial spacer layer 720 to form sacrificial spacers 735 inhibits the widening of the gaps 725 between the sacrificial spacers 735. Therefore, the gaps 725 are too small to allow material of the p-type work function metal layer 750 to be deposited within them.

[0148] like Figure 7L As shown, a p-type work function metal layer 750 may also be formed on the sidewalls of the region of dielectric layer 605. In some embodiments, an additional p-type work function metal layer 755 may also be formed on the p-type work function metal layer 750. The p-type work function metal layer 755 may include tantalum nitride (TaN) and / or other types of p-type work function metals.

[0149] The above regarding Figures 7H to 7J Anisotropic etching that trims the sacrificial spacer layer 720 to form the sacrificial spacer 735 can completely remove the sacrificial spacer layer 720 from the sidewalls of the region of the dielectric layer 605, while minimizing residual material to the point where no sacrificial spacer layer 720 remains on the sidewalls of the region of the dielectric layer 605. Therefore, as Figure 7L As shown, the p-type work function metal layer 750 formed on the sidewalls of the adjacent region of dielectric layer 605 is not merged between the adjacent regions of dielectric layer 605 in the Y direction. Instead, the p-type work function metal layer 750 formed on the sidewalls of the adjacent region of dielectric layer 605 is spaced apart in the Y direction by a certain distance ( Figure 7LThe mask layer (indicated by size D3) is physically separated from the adjacent regions of dielectric layer 605. This avoids, minimizes, and / or reduces the possibility of the mask layer becoming trapped between the adjacent regions of dielectric layer 605, where the mask layer is used to remove the p-type work function metal layer 750 from the n-type gate structure 710a. Otherwise, a trapped mask layer could cause under-etching of the mask layer and residual material of the mask layer remaining between the adjacent regions of dielectric layer 605.

[0150] like Figure 7M As shown, the p-type work function metal layer 750 can be removed from the nanostructure channel 315a and the plateau region 310a. If the p-type work function metal layer 750 remains around the nanostructure channel 315a and on the plateau region 310a, the p-type work function metal layer 750 may cause the work function of the n-type gate structure 710a to be too far from the conduction band of the material of the nanostructure channel 315a. Therefore, a masking layer 760 can be formed on the nanostructure channel 315b and the plateau region 310b, and the masking layer 760 can be used to remove the p-type work function metal layer 750 from the nanostructure channel 315a and the plateau region 310a, so that the p-type work function metal layer 750 remains on the nanostructure channel 315b and the plateau region 310b.

[0151] A deposition tool can be used to deposit a masking layer 760 on nanostructure channels 315a, 315b, plateau regions 310a and 310b. Then, a portion of the masking layer 760 can be removed from the nanostructure channels 315a and plateau regions 310a to pattern the masking layer 760. An etching tool can be used to etch the masking layer 760 to pattern the masking layer 760. Then, the etching tool can be used to remove the p-type work function metal layer 750 from the nanostructure channels 315a and plateau regions 310a, while the masking layer 760 protects the nanostructure channels 315b and plateau regions 310b.

[0152] like Figure 7M As further shown, the sacrificial spacer 735 is also removed from the nanostructure channel 315a and the plateau region 310a. In some embodiments, the sacrificial spacer 735 can be removed after the p-type work function metal layer 750 is removed from the nanostructure channel 315a and the plateau region 310a. For example, a first etching operation can be performed to remove the p-type work function metal layer 750, followed by a second etching operation to remove the sacrificial spacer 735. In some embodiments, the sacrificial spacer 735 and the p-type work function metal layer 750 are removed together from the nanostructure channel 315a and the plateau region 310a in the same etching operation.

[0153] In some embodiments, wet etching is used to remove the sacrificial spacer 735 from the nanostructured channel 315a and the plateau region 310a. For example, a base (or alkaline) wet etchant, such as ammonium hydroxide (NH4OH) (e.g., a wet etchant having a pH greater than 7), can be used to isotropically etch the sacrificial spacer 735 to remove it from the nanostructured channel 315a and the plateau region 310a with minimal etching of the gate dielectric layer 715 on the nanostructured channel 315a and the plateau region 310a. Because the material of the sacrificial spacer 735 (e.g., alumina (Al2O3) etc.) can have a positive surface charge that attracts negatively charged ions in the ammonium hydroxide wet etchant, including negatively charged ions (e.g., OH-). - Ammonium hydroxide wet etchant (with ions) can isotropically etch sacrificial spacers 735.

[0154] Subsequently, plasma ashing techniques (e.g., using nitrogen (N2) plasma and hydrogen (H2) reaction gases) and / or other types of masking layer removal techniques can be used to remove the masking layer 760 from the nanostructure channel 315b and the platform region 310b.

[0155] like Figure 7N As shown, the masking layer 760 is completely removed from the adjacent region of the dielectric layer 605 separating the nanostructure channel 315a. Figures 7H to 7J To minimize residual material of the sacrificial spacer layer 720 remaining on the sidewalls of the region of the dielectric layer 605, removing (e.g., completely removing) the sacrificial spacer layer 720 from the sidewalls of the region of the dielectric layer 605 avoids or minimizes the possibility of the p-type work function metal layer 750 merging between adjacent regions of the dielectric layer 605 of the nanostructure channel 315a spacer. Otherwise, the merging of the p-type work function metal layer 750 between adjacent regions of the dielectric layer 605 of the nanostructure channel 315a spacer could increase the possibility of material of the masking layer 760 becoming trapped between adjacent regions of the dielectric layer 605 of the nanostructure channel 315a spacer. Figures 7H to 7J The removal (e.g., complete removal) of the sacrificial spacer 720 from the sidewalls of the region of the dielectric layer 605, in order to minimize the possibility of material of the masking layer 760 getting trapped between adjacent regions of the dielectric layer 605 and the partition of the nanostructure channel 315a, is described above.

[0156] like Figure 7OAs shown, one or more n-type work function metal layers are formed on the gate dielectric layer 715 of the n-type gate structure 710a. After removing the p-type work function metal layer 750 and the sacrificial spacer 735 from the nanostructure channel 315a and the plateau region 310a, one or more n-type work function metal layers may be formed around the nanostructure channel 315a and on the plateau region 310. The one or more n-type work function metal layers may include n-type work function metal layer 765 and / or n-type work function metal layer 770. The n-type work function metal layer 770 and the n-type work function metal layer 765 may include different materials or different combinations of materials. Alternatively, the n-type work function metal layer 770 and the n-type work function metal layer 765 may include the same material and / or the same combination of materials. Each of the n-type work function metal layer 770 and the n-type work function metal layer 765 includes one or more metallic materials to modulate or adjust the work function of the n-type gate structure 710a to approximate the conduction band of the material of the nanostructure channel 315a. In some embodiments, the n-type work function metal layer 765 comprises titanium aluminum (TiAl). In some embodiments, the n-type work function metal layer 765 comprises titanium aluminum carbon (TiAlC). In some embodiments, the n-type work function metal layer 770 comprises another aluminum-containing metal. In some embodiments, the n-type work function metal layer 770 comprises other n-type work function metal materials.

[0157] An n-type work function metal layer 765 and / or an n-type work function metal layer 770 are formed such that the n-type work function metal layer 765 and / or the n-type work function metal layer 770 surrounds each nanostructure channel 315a. The n-type work function metal layer 765 and / or the n-type work function metal layer 770 can also be formed on the exposed portion of the platform region 310a below the nanostructure channel 315a. Deposition tools can be used to deposit the n-type work function metal layer 765 and / or the n-type work function metal layer 770, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques.

[0158] In some embodiments, the n-type work function metal layer 765 is formed such that the n-type work function metal layer 765 is incorporated between vertically adjacent nanostructure channels 315a. In some embodiments, the n-type work function metal layer 765 is formed such that the n-type work function metal layer 765 is not incorporated between vertically adjacent nanostructure channels 315a.

[0159] like Figure 7PAs shown, a gate electrode layer 775 is formed for an n-type gate structure 710a, and a gate electrode layer 775 is formed for a p-type gate structure 710b. In some embodiments, the n-type gate structure 710a and the p-type gate structure 710b both form the same gate electrode layer 775. In some embodiments, separate and electrically isolated gate electrode layers 775 are formed for each n-type gate structure 710a and the p-type gate structure 710b. The gate electrode layer 775 may be formed on the n-type work function metal layer 770 and the n-type work function metal layer 765 above the nanostructure channel 315a of the n-type gate structure 710a. The gate electrode layer 775 may be formed on the p-type work function metal layer 750 above the nanostructure channel 315b of the p-type gate structure 710b.

[0160] The gate electrode layer 775 comprises one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). Deposition tools can be used to deposit the gate electrode layer 775, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. The gate electrode layer 775 can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the gate electrode layer 775 is deposited on the seed layer. In some embodiments, after depositing the gate electrode layer 775, a planarization tool can be used to planarize the gate electrode layer 775.

[0161] As mentioned above, Figures 7A to 7P As an example. Other examples may differ. Figures 7A to 7P As stated above.

[0162] Figure 8 An example of rounded corners in the nanostructure channels of the semiconductor device described in this article is illustrated. (See also: Regarding...) Figure 7I The wet etchant used to trim the sacrificial spacer layer 720 to form the sacrificial spacer 735 can also etch the gate dielectric layer 715 on the nanostructure channels 315a and / or 315b. This may cause some corner rounded corners of the gate dielectric layer 715 to be located in the X direction at the corners of the nanostructure channels 315a and / or 315b. Figure 8 Examples 800, 802, 804, and 806 are illustrated for corner rounding in gate dielectric layer 715 for multiple example sizes of nanostructure channel 315.

[0163] In Example 800, the nanostructured channel 315 can have a width in the X direction (in Figure 8 The dimension (D4) is in the range of approximately 10 nanometers to approximately 12 nanometers. In Example 802, the nanostructured channel 315 may have a width in the X direction (in... Figure 8The dimension (D5) is in the range of approximately 17 nanometers to approximately 20 nanometers. In Example 804, the nanostructured channel 315 may have a width in the X direction (in... Figure 8 The dimension (D6) is in the range of approximately 25 nanometers to approximately 30 nanometers. In Example 806, the nanostructured channel 315 may have a width in the X direction (in... Figure 8 The size indicated by the Chinese label (D7) is in the range of approximately 55 nanometers to approximately 60 nanometers.

[0164] The angle between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315 and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315 (dimension D8 in Example 800, dimension D9 in Example 802, dimension D10 in Example 804, and dimension D11 in Example 806) can be greater than or approximately equal to 100 degrees. For example, because the corners of the gate dielectric layer 715 are rounded due to the use of a wet etchant to trim the sacrificial spacer layer 720 to form the sacrificial spacer 735, the angle between the gate dielectric layer 715 on the sidewall of the nanostructure channel 315 and the gate dielectric layer 715 on the top or bottom surface of the nanostructure channel 315 can be in the range of approximately 100 degrees to approximately 160 degrees. However, other values ​​and ranges may also be within the scope of this disclosure.

[0165] As mentioned above, Figure 8 As an example. Other examples may differ. Figure 8 As stated above.

[0166] Figure 9 This is a flowchart of an example process 900 related to the semiconductor device described herein. In some embodiments, one or more semiconductor process tools are used for execution. Figure 9 One or more process blocks, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor process tools.

[0167] like Figure 9 As shown, process 900 may include forming a plurality of nanostructured channels arranged in a direction generally perpendicular to the semiconductor substrate of the semiconductor device (block 910). For example, one or more semiconductor process tools may be used to form a plurality of nanostructured channels (e.g., nanostructured channels 315, nanostructured channels 315a) arranged in a direction generally perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105) (e.g., the Z direction), as described herein.

[0168] like Figure 9As further shown, process 900 may include forming a sacrificial spacer layer around the plurality of nanostructure channels (block 920). For example, one or more semiconductor process tools may be used to form a sacrificial spacer layer (e.g., sacrificial spacer layer 720) around the plurality of nanostructure channels, as described herein.

[0169] like Figure 9 As further shown, process 900 may include etching the sacrificial spacer layer using a wet etchant to remove a first portion of the sacrificial spacer layer from the sides of the plurality of nanostructure channels (block 930). For example, one or more semiconductor process tools may be used to etch the sacrificial spacer layer using a wet etchant to remove a first portion of the sacrificial spacer layer from the sides of the plurality of nanostructure channels, as described herein. In some embodiments, a second portion of the sacrificial spacer layer is retained between vertically adjacent nanostructure channels of the plurality of nanostructure channels as a sacrificial spacer (e.g., sacrificial spacer 735). In some embodiments, hydrogen ions (H+) in the wet etchant... + (e.g., positive ion 740) suppresses the etching of sacrificial spacers between vertically adjacent nanostructure channels of multiple nanostructure channels.

[0170] like Figure 9 As further shown, process 900 may include forming a power function metal layer on multiple nanostructure channels (block 940). For example, one or more semiconductor process tools may be used to form a power function metal layer (e.g., a p-type work function metal layer 750) on multiple nanostructure channels, as described herein. In some embodiments, sacrificial spacers suppress the formation of a power function metal layer between vertically adjacent nanostructure channels of the multiple nanostructure channels.

[0171] Process 900 may include additional implementations, such as any single implementation or any combination of implementations described below and / or one or more other processes described elsewhere herein.

[0172] In a first embodiment, the sacrificial spacer layer comprises a material having a positive surface charge (e.g., a positive surface charge 745).

[0173] In the second embodiment, the wet etchant, alone or in combination with the first embodiment, includes a hydrogen-containing acid.

[0174] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 900 includes etching the sacrificial spacer layer to reduce the thickness of the sacrificial spacer layer, wherein the step of etching the sacrificial spacer layer to remove a first portion of the sacrificial spacer layer includes etching the sacrificial spacer layer to remove the first portion of the sacrificial spacer layer after etching the sacrificial spacer layer to reduce the thickness of the sacrificial spacer layer.

[0175] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 900 includes forming a gate dielectric layer (e.g., gate dielectric layer 715) around a plurality of nanostructure channels, wherein the step of forming a sacrificial spacer layer includes forming a sacrificial spacer layer on the gate dielectric layer and etching the sacrificial spacer layer to cause etching of the corners of the gate dielectric layer.

[0176] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 900 includes etching the sacrificial spacer layer with a wet etchant to remove a third portion of the sacrificial spacer layer from the sidewalls of adjacent interlayer dielectric regions (e.g., adjacent regions of dielectric layer 605) adjacent to the sides of the plurality of nanostructure channels.

[0177] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 900 includes removing the work function metal layer and sacrificial spacers from the plurality of nanostructure channels, and forming another work function metal layer (e.g., n-type work function metal layer 765, n-type work function metal layer 770) around the plurality of nanostructure channels after removing the work function metal layer and sacrificial spacers.

[0178] In the seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, the work function metal layer is a p-type work function metal layer, and the other work function metal layer is an n-type work function metal layer.

[0179] Although Figure 9 Example blocks of process 900 in some implementations are shown, but process 900 can be relative to... Figure 9 The illustrations include additional blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more blocks of process 900 can be executed in parallel.

[0180] Figure 10 This is a flowchart of an example process 1000 relating to the formation of the semiconductor device described herein. In some embodiments, one or more semiconductor process tools are used for execution. Figure 10 One or more process blocks, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor process tools.

[0181] like Figure 10As shown, process 1000 may include forming a plurality of first nanostructure channels arranged in a direction (Z direction) generally perpendicular to the semiconductor substrate of the semiconductor device (block 1010). For example, one or more semiconductor process tools may be used to form a plurality of first nanostructure channels (e.g., nanostructure channel 315a) arranged in a direction (e.g., Z direction) generally perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105), as described herein.

[0182] like Figure 10 As further shown, process 1000 may include forming a plurality of second nanostructure channels arranged in a direction generally perpendicular to the semiconductor substrate (block 1020). For example, one or more semiconductor process tools may be used to form a plurality of second nanostructure channels (e.g., nanostructure channel 315b) arranged in a direction generally perpendicular to the semiconductor substrate, as described herein.

[0183] like Figure 10 As further shown, process 1000 may include forming a sacrificial spacer layer around a plurality of first nanostructure channels and around a plurality of second nanostructure channels (block 1030). For example, one or more semiconductor process tools may be used to form a sacrificial spacer layer (e.g., sacrificial spacer layer 720) around a plurality of first nanostructure channels and around a plurality of second nanostructure channels, as described herein.

[0184] like Figure 10 As further shown, process 1000 may include performing a first etch operation using a first wet etchant to remove a sacrificial spacer layer from a plurality of second nanostructure channels (block 1040). For example, one or more semiconductor process tools may be used to perform the first etch operation using the first wet etchant to remove a sacrificial spacer layer from a plurality of second nanostructure channels, as described herein.

[0185] like Figure 10As further shown, process 1000 may include performing a second etching operation using a second wet etchant different from the first wet etchant to remove a first portion of the sacrificial spacer layer from the sides of the plurality of first nanostructure channels (block 1050). For example, one or more semiconductor process tools may be used to perform the second etching operation using a second wet etchant different from the first wet etchant to remove a first portion of the sacrificial spacer layer from the sides of the plurality of first nanostructure channels, as described herein. In some embodiments, a second portion of the sacrificial spacer layer remains between vertically adjacent nanostructure channels of the plurality of first nanostructure channels as a sacrificial spacer (e.g., sacrificial spacer 735). In some embodiments, a gap (e.g., gap 725) is located between vertically adjacent sacrificial spacers between vertically adjacent nanostructure channels. In some embodiments, hydrogen ions (H+) in the second wet etchant... + The combination of materials (e.g., positive ion 740) and sacrificial spacers suppresses the increase in vertical width of the slit (e.g., size D1, size D2) during the second etching operation.

[0186] like Figure 10 As further shown, process 1000 may include forming a power function metal layer on and around a plurality of first nanostructure channels and a plurality of second nanostructure channels after performing a second etching operation (block 1060). For example, one or more semiconductor process tools may be used to form a power function metal layer (e.g., a p-type work function metal layer 750) on and around a plurality of first nanostructure channels and a plurality of second nanostructure channels after performing a second etching operation, as described herein. In some embodiments, sacrificial spacers suppress the formation of a power function metal layer between vertically adjacent nanostructure channels of the plurality of first nanostructure channels.

[0187] like Figure 10 As further shown, process 1000 may include removing a work function metal layer from a plurality of first nanostructure channels (block 1070). For example, one or more semiconductor process tools may be used to remove the work function metal layer from the plurality of first nanostructure channels, as described herein.

[0188] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations described below and / or one or more other processes described elsewhere herein.

[0189] In a first embodiment, the first wet etchant comprises an alkaline wet etchant, and the second wet etchant comprises an acidic wet etchant.

[0190] In the second embodiment, alone or in combination with the first embodiment, the second wet etchant includes at least one of cyanofluorine (HF), hydrochloric acid (HCl), sulfuric acid (H2SO4), hydrobromic acid (HBr), and / or carbon dioxide (CO2) dissolved in water (H2O).

[0191] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 1000 includes forming a high-k dielectric gate dielectric layer (e.g., gate dielectric layer 715) around a plurality of first nanostructure channels, wherein the step of forming a sacrificial spacer layer includes forming a sacrificial spacer layer on the high-k dielectric gate dielectric layer, and a second etching operation causing corner rounding of the high-k dielectric gate dielectric layer.

[0192] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the work function metal layer is a first type of work function metal layer, and process 1000 includes forming a second type of work function metal layer (e.g., n-type work function metal layer 765, n-type work function metal layer 770) around the plurality of first nanostructure channels after removing the work function metal layer from the plurality of first nanostructure channels.

[0193] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 1000 includes removing sacrificial spacers from the plurality of first nanostructure channels after removing the work function metal layer from the plurality of first nanostructure channels, wherein forming a second type of work function metal layer includes removing the second type of work function metal layer after removing the sacrificial spacers.

[0194] In the sixth embodiment, the step of performing the second etching operation, alone or in combination with one or more of the first to fifth embodiments, includes performing the second etching operation using a second wet etchant to remove a third portion of the sacrificial spacer layer from the sidewall of the adjacent interlayer dielectric region (e.g., the adjacent region of dielectric layer 605) adjacent to the sides of the plurality of first nanostructure channels.

[0195] In the seventh embodiment, the step of forming a work function metal layer, alone or in combination with one or more of the first to sixth embodiments, includes forming a work function metal layer on the sidewalls of adjacent interlayer dielectric regions, wherein a portion of the work function metal layer on the sidewalls of adjacent interlayer dielectric regions is physically separated by a gap (e.g., size D3) between adjacent interlayer dielectric regions.

[0196] Although Figure 10 Example blocks of process 1000 in some implementations are shown, but process 1000 can be relative to... Figure 10The illustrations include additional blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more blocks of process 1000 can be executed in parallel.

[0197] In this manner, sacrificial spacers are formed between the vertically adjacent nanostructure channels of the first nanostructure transistor to avoid or reduce the likelihood of material deposition of the work function metal layer of the second nanostructure transistor between the vertically adjacent nanostructure channels of the first nanostructure transistor. The sacrificial spacers can be formed by depositing a conformal sacrificial spacer layer around the nanostructure channels of the first nanostructure channel, and then etching the sacrificial spacer layer so that it remains as a sacrificial spacer only between the vertically adjacent nanostructure channels of the first nanostructure transistor. In some examples, gaps can be formed within the sacrificial spacer layer between the vertically adjacent nanostructure channels. The anisotropic wet etching technique described herein can be used to etch the sacrificial spacer layer such that the etching does not enlarge (or minimally enlarges) the gaps, which would otherwise increase the likelihood of material deposition of the work function metal layer of the second nanostructure transistor between the vertically adjacent nanostructure channels of the first nanostructure transistor. Therefore, the anisotropic wet etching technique described herein can increase the likelihood of completely removing material of the work function metal layer of the second nanostructure transistor from the first nanostructure transistor before the formation of the work function metal layer of the second nanostructure transistor.

[0198] As described in further detail herein, some embodiments described herein include a method of forming a semiconductor device. The method includes forming a plurality of nanostructured channels arranged in a direction generally perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming a sacrificial spacer layer around the plurality of nanostructured channels. The method includes etching the sacrificial spacer layer using a wet etchant to remove a first portion of the sacrificial spacer layer from the sides of the plurality of nanostructured channels. A second portion of the sacrificial spacer layer remains between vertically adjacent nanostructured channels in the plurality of nanostructured channels as a sacrificial spacer. Hydrogen ions (H+) in the wet etchant... + A method to suppress the etching of sacrificial spacers between vertically adjacent nanostructure channels in multiple nanostructure channels. The method involves forming a power-functional metal layer on the multiple nanostructure channels. The sacrificial spacers suppress the formation of the power-functional metal layer between vertically adjacent nanostructure channels in the multiple nanostructure channels.

[0199] In some embodiments, the sacrificial spacer layer comprises a material having a positive surface charge. In some embodiments, the wet etchant comprises a hydroacid. In some embodiments, the method further comprises etching the sacrificial spacer layer to reduce the thickness of the sacrificial spacer layer, wherein etching the sacrificial spacer layer to remove a first portion of the sacrificial spacer layer comprises etching the sacrificial spacer layer to remove a first portion of the sacrificial spacer layer after etching the sacrificial spacer layer to reduce the thickness of the sacrificial spacer layer. In some embodiments, the method further comprises forming a gate dielectric layer around the nanostructure channel, wherein forming the sacrificial spacer layer comprises forming the sacrificial spacer layer on the gate dielectric layer, and wherein etching the sacrificial spacer layer causes etching of multiple corners of the gate dielectric layer. In some embodiments, the method further comprises etching the sacrificial spacer layer using a wet etchant to remove multiple third portions of the sacrificial spacer layer from multiple sidewalls of multiple adjacent interlayer dielectric regions, wherein the adjacent interlayer dielectric regions are adjacent to the sidewalls of the nanostructure channel. In some embodiments, the method further comprises removing the work function metal layer and the sacrificial spacer from the nanostructure channel, and after removing the work function metal layer and the sacrificial spacer, forming an additional work function metal layer around the nanostructure channel. In some embodiments, the work function metal layer is a p-type work function metal layer, and the additional work function metal layer is an n-type work function metal layer.

[0200] As described in further detail herein, some embodiments described herein include a method of forming a semiconductor device. The method includes forming a plurality of first nanostructure channels arranged in a direction generally perpendicular to a semiconductor substrate of the semiconductor device. The method includes forming a plurality of second nanostructure channels arranged in a direction generally perpendicular to the semiconductor substrate. The method includes forming a sacrificial spacer layer around the plurality of first nanostructure channels and around the plurality of second nanostructure channels. The method includes performing a first etching operation using a first wet etchant and a second etching operation using a second wet etchant to remove the sacrificial spacer layer from the plurality of second nanostructure channels and to remove a first portion of the sacrificial spacer layer from the sides of the plurality of first nanostructure channels. A second portion of the sacrificial spacer layer remains between vertically adjacent nanostructure channels in the plurality of first nanostructure channels as a sacrificial spacer. Gap is located between vertically adjacent sacrificial spacers between vertically adjacent nanostructure channels. Hydrogen ions (H+) in the second wet etchant... + The combination of materials, including sacrificial spacers, suppresses the increase in vertical width of the gap during the second etching operation. The method includes forming a work function metal layer on and around a plurality of first nanostructure channels and a plurality of second nanostructure channels after performing the second etching operation. Sacrificial spacers suppress the formation of the work function metal layer between vertically adjacent nanostructure channels of the plurality of first nanostructure channels. The method includes removing the work function metal layer from the plurality of first nanostructure channels.

[0201] In some embodiments, the first wet etchant includes an alkaline wet etchant, and the second wet etchant includes an acidic wet etchant selected from at least one of cyanofluoride, hydrochloric acid, sulfuric acid, hydrobromic acid, or carbon dioxide dissolved in water. In some embodiments, the method further includes forming a high-dielectric-constant gate dielectric layer around the first nanostructure channel, wherein forming a sacrificial spacer layer includes forming a sacrificial spacer layer on the high-dielectric-constant gate dielectric layer, and a second etch operation causes corner rounding of the high-dielectric-constant gate dielectric layer. In some embodiments, the work function metal layer is a first type of work function metal layer, wherein the method further includes forming a second type of work function metal layer around the first nanostructure channel after removing the work function metal layer from the first nanostructure channel. In some embodiments, the method further includes removing the sacrificial spacer from the first nanostructure channel after removing the work function metal layer from the first nanostructure channel, wherein forming the second type of work function metal layer includes removing the second type of work function metal layer after removing the sacrificial spacer. In some embodiments, performing the second etching operation includes performing the second etching operation using a second wet etchant to remove a plurality of third portions of the sacrificial spacer layer from a plurality of sidewalls of a plurality of adjacent interlayer dielectric regions, wherein the adjacent interlayer dielectric regions are adjacent to the sides of the first nanostructure channel. In some embodiments, forming a work function metal layer includes forming a work function metal layer on the sidewalls of the adjacent interlayer dielectric regions, wherein a plurality of portions of the work function metal layer on the sidewalls of the adjacent interlayer dielectric regions are physically separated by gaps between the adjacent interlayer dielectric regions. In some embodiments, removing the sacrificial spacer layer from the second nanostructure channel includes performing a first etching operation using a first wet etchant to remove the sacrificial spacer layer from the second nanostructure channel, and removing a first portion of the sacrificial spacer layer from the side of the nanostructure channel includes performing a second etching operation using a second wet etchant different from the first wet etchant to remove the first portion of the sacrificial spacer layer from the side of the nanostructure channel.

[0202] As described in further detail herein, some embodiments described herein include a semiconductor device. The semiconductor device includes a plurality of first nanostructure channels arranged in a first direction substantially perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a plurality of second nanostructure channels arranged in a first direction substantially perpendicular to the semiconductor substrate and adjacent to the plurality of first nanostructure channels in a second direction. The plurality of first nanostructure channels and the plurality of second nanostructure channels extend in a third direction substantially perpendicular to the second direction. The semiconductor device includes a first gate structure surrounding the plurality of first nanostructure channels, wherein the first gate structure includes a first type work function metal layer. The semiconductor device includes a first gate dielectric layer between the first gate structure and the plurality of first nanostructure channels. In the third direction, the angle between a first portion of the first gate dielectric layer on the sidewall of one of the nanostructure channels and a second portion of the first gate dielectric layer on the top surface of the nanostructure channel is greater than or approximately equal to 100 degrees. The semiconductor device includes a second gate structure surrounding each of the plurality of second nanostructure channels, wherein the second gate structure includes a second type work function metal layer. The semiconductor device includes a second gate dielectric layer between the second gate structure and the plurality of second nanostructure channels.

[0203] In some embodiments, the angle between a first portion of the first gate dielectric layer and a second portion of the first gate dielectric layer is in the range of approximately 100 degrees to approximately 160 degrees. In some embodiments, in the third-party upward direction, an additional angle between the first portion of the second gate dielectric layer located on the sidewall of an additional nanostructure channel in the second nanostructure channel and the second portion of the second gate dielectric layer located on the top surface of the nanostructure channel is greater than or approximately equal to 100 degrees. In some embodiments, the additional angle between the first portion of the second gate dielectric layer and the second portion of the second gate dielectric layer is in the range of approximately 100 degrees to approximately 160 degrees.

[0204] As described in further detail herein, some embodiments of the present invention include a semiconductor device comprising a first transistor. The first transistor includes a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate, a first gate structure surrounding the first nanostructure channels and including a first type of work function metal layer, and a first high-dielectric-constant gate dielectric layer located between the first gate structure and the first nanostructure channels, wherein the first high-dielectric-constant gate dielectric layer includes a plurality of corner rounded corners located at a plurality of corners of the first nanostructure channels. In some embodiments, the semiconductor device further includes a second transistor adjacent to the first transistor in a second direction different from the first direction. The second transistor includes a plurality of second nanostructure channels arranged in the first direction, a second gate structure surrounding the first nanostructure channels and including a second type of work function metal layer different from the first type of work function metal layer, and a second high-dielectric-constant gate dielectric layer located between the second gate structure and the second nanostructure channels, wherein the second high-dielectric-constant gate dielectric layer includes a plurality of corner rounded corners located at a plurality of corners of the second nanostructure channels. In some embodiments, the corner rounded corners of the first high-dielectric-constant gate dielectric layer and the corner rounded corners of the second high-dielectric-constant gate dielectric layer are greater than or equal to 100 degrees.

[0205] As described in further detail herein, some embodiments described herein include a semiconductor device. The semiconductor device includes a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate, a plurality of adjacent interlayer dielectric regions adjacent to a plurality of sides of the first nanostructure channels, a first type work function metal layer surrounding each of the first nanostructure channels and located on a plurality of sidewalls of the adjacent interlayer dielectric regions, and a first gate dielectric layer located between the first type work function metal layer and the first nanostructure channels, wherein gaps between the adjacent interlayer dielectric regions physically separate multiple portions of the first type work function metal layer on the sidewalls of the adjacent interlayer dielectric regions. In some embodiments, the semiconductor device further includes a plurality of platform regions located below the first nanostructure channels, wherein the first gate dielectric layer and the first type work function metal layer are located on the platform regions. In some embodiments, the semiconductor device further includes a plurality of second nanostructure channels arranged in a first direction and adjacent to the first nanostructure channel in a second direction different from the first direction, a second type of work function metal layer surrounding each of the second nanostructure channels, a second gate dielectric layer located between the second type of work function metal layer and the second nanostructure channel, and a gate electrode layer located on the first type of work function metal layer and the second type of work function metal layer.

[0206] The terms “approximately” and “substantially” can refer to numerical values ​​that vary within 5% of a given value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely illustrative and not intended to be limiting. It should be understood that the terms “approximately” and “substantially” can, in light of this disclosure, represent numerical values ​​of a given value.

[0207] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate of the semiconductor device; a plurality of second nanostructure channels arranged in the first direction perpendicular to the semiconductor substrate and adjacent to the plurality of first nanostructure channels in a second direction, wherein the plurality of first nanostructure channels and the plurality of second nanostructure channels extend in a third direction perpendicular to the second direction; a first gate structure surrounding the plurality of first nanostructure channels and comprising a first type work function metal layer; a first gate dielectric layer between the first gate structure and the plurality of first nanostructure channels, wherein an angle between a first portion of the first gate dielectric layer on a sidewall of a nanostructure channel of the plurality of first nanostructure channels and a second portion of the first gate dielectric layer on a top surface of the nanostructure channel is greater than or equal to 100 degrees in the third direction; a second gate structure surrounding each of the plurality of second nanostructure channels and comprising a second type work function metal layer different from the first type work function metal layer; and a second gate dielectric layer between the second gate structure and the plurality of second nanostructure channels. wherein the angle between the first portion of the first gate dielectric layer and the second portion of the first gate dielectric layer is in a range of 100 degrees to 160 degrees.

2. The semiconductor device according to claim 1, wherein wherein an additional angle between a first portion of the second gate dielectric layer on a sidewall of an additional nanostructure channel of the plurality of second nanostructure channels and a second portion of the second gate dielectric layer on a top surface of the nanostructure channel is greater than or equal to 100 degrees in the third direction.

3. The semiconductor device according to claim 1, wherein wherein the additional angle between the first portion of the second gate dielectric layer and the second portion of the second gate dielectric layer is in a range of 100 degrees to 160 degrees.

4. The semiconductor device according to claim 3, wherein Comprising:

5. A semiconductor device, characterized by comprising: a first transistor comprising: a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate; a first gate structure surrounding the plurality of first nanostructure channels and comprising a first type work function metal layer; and a first high-k gate dielectric layer between the first gate structure and the plurality of first nanostructure channels, wherein the first high-k gate dielectric layer comprises corner rounding at corners of the plurality of first nanostructure channels. further comprising:

6. The semiconductor device according to claim 5, wherein a second transistor adjacent to the first transistor in a second direction different from the first direction, wherein the second transistor comprises: a plurality of second nanostructure channels arranged in the first direction; a second gate structure surrounding the plurality of first nanostructure channels and comprising a second type work function metal layer different from the first type work function metal layer; and ​ a second high-k gate dielectric layer between the second gate structure and the plurality of second nanostructure channels, wherein the second high-k gate dielectric layer includes corner rounding at corners of the plurality of second nanostructure channels.

7. The semiconductor device according to claim 6, wherein wherein the corner rounding of the first high-k gate dielectric layer and the corner rounding of the second high-k gate dielectric layer are greater than or equal to 100 degrees.

8. A semiconductor device, characterized by comprising: comprising: a plurality of first nanostructure channels arranged in a first direction perpendicular to a semiconductor substrate; a plurality of adjacent ILD regions adjacent to sides of the plurality of first nanostructure channels; a first work function metal layer surrounding each of the plurality of first nanostructure channels and on sidewalls of the plurality of adjacent ILD regions, wherein a gap between the plurality of adjacent ILD regions physically separates portions of the first work function metal layer on the sidewalls of the plurality of adjacent ILD regions; and a first gate dielectric layer between the first work function metal layer and the plurality of first nanostructure channels.

9. The semiconductor device according to claim 8, wherein further comprising: a plurality of platform regions under the plurality of first nanostructure channels, wherein the first gate dielectric layer and the first work function metal layer are on the plurality of platform regions.

10. The semiconductor device according to claim 8, wherein further comprising: a plurality of second nanostructure channels arranged in the first direction and adjacent to the plurality of first nanostructure channels in a second direction different from the first direction; a second work function metal layer surrounding each of the plurality of second nanostructure channels; a second gate dielectric layer between the second work function metal layer and the plurality of second nanostructure channels; and a gate electrode layer on the first work function metal layer and the second work function metal layer.

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