Semiconductor device

Abstract

A semiconductor device includes a plurality of nanostructure channels, a plurality of inner spacers, a gate structure, and a source / drain region. The nanostructure channel is located on the substrate and arranged in the direction perpendicular to the substrate, and comprises a first nanostructure channel and a second nanostructure channel located above the first nanostructure channel. The source / drain region adjoins the nanostructured channel. A gate structure surrounds each of the nanostructure channels, a first portion of the gate structure under the first nanostructure channel having a first width at about a center of the first portion, and a second portion of the gate structure between the first and second nanostructure channels having a second width at about a center of the second portion, a difference between the second width and a third width at the top of the second portion is less than a difference between the first width and the second width. The inner spacers are located between the source / drain region and the gate structure, and one of the inner spacers is located between the first and second nanostructure channels.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] As semiconductor device manufacturing technologies advance and process node sizes shrink, transistors may suffer from short-channel effects (SCEs), such as hot carrier degradation, barrier reduction, and quantum confinement. Furthermore, as transistor gate lengths shrink with smaller process nodes, source / drain (S / D) pad tunneling increases, leading to an increase in the transistor's turn-off current (the current flowing through the transistor's channels when it is off). Silicon (Si) / silicon-germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, and gate-all-around (GAA) devices, are potential candidates for overcoming short-channel effects at smaller process nodes. Nanotransistors are more likely to exhibit reduced SCEs and enhanced carrier mobility compared to other types of transistors. Utility Model Content

[0003] According to one embodiment of this disclosure, a semiconductor device includes a plurality of nanostructured channels, a plurality of internal spacers, a gate structure, and source / drain regions. The nanostructured channels are located on a substrate, wherein the nanostructured channels are disposed in a direction perpendicular to the substrate, and wherein the nanostructured channels include a first nanostructured channel and a second nanostructured channel located above the first nanostructured channel. The source / drain regions are adjacent to the nanostructured channels. A gate structure surrounds each of the nanostructured channels, wherein a first portion of the gate structure under the first nanostructured channel has a first width at approximately the center of the first portion, wherein a second portion of the gate structure between the first and second nanostructured channels has a second width at approximately the center of the second portion, and wherein the difference between the second width and a third width at the top of the second portion is less than the difference between the first width and the second width. Internal spacers are located between the source / drain regions and the gate structure, wherein one of the internal spacers is located between the first and second nanostructured channels.

[0004] According to one embodiment of this disclosure, a semiconductor device includes a plurality of nanostructured channels, a plurality of internal spacers, a gate structure, and source / drain regions. The nanostructured channels are located on a substrate, wherein each nanostructured channel includes a first nanostructured channel and a second nanostructured channel located above the first nanostructured channel. The source / drain regions are adjacent to the nanostructured channels. A gate structure surrounds each nanostructured channel, wherein a first portion of the gate structure below the first nanostructured channel has a first width at approximately the center of the first portion, wherein a second portion of the gate structure between the first and second nanostructured channels has a second width at approximately the center of the second portion, and wherein the difference between the second width and a third width at the top of the second portion is less than the difference between the first and second widths. The difference between the second and third widths is less than the thickness of the second nanostructured channel. Internal spacers are located between the source / drain regions and the gate structure, wherein one of the internal spacers is located between the first and second nanostructured channels.

[0005] According to one embodiment of this disclosure, a semiconductor device includes a plurality of nanostructured channels, a plurality of internal spacers, a gate structure, and source / drain regions. The nanostructured channels are located on a substrate, wherein the nanostructured channels are disposed in a direction perpendicular to the substrate, and wherein the nanostructured channels include a first nanostructured channel and a second nanostructured channel located above the first nanostructured channel. The source / drain regions are adjacent to the nanostructured channels. A gate structure surrounds each of the nanostructured channels, wherein a first portion of the gate structure under the first nanostructured channel has a first width at approximately the center of the first portion, wherein a second portion of the gate structure between the first and second nanostructured channels has a second width at approximately the center of the second portion, and wherein the difference between the second width and a third width at the top of the second portion is less than the thickness of the second nanostructured channel. Internal spacers are located between the source / drain regions and the gate structure, wherein one of the internal spacers is located between the first and second nanostructured channels. Attached Figure Description

[0006] The nature of this disclosure can be best understood by reading it in conjunction with the accompanying drawings and the embodiments described below. Note that, according to standard practice in this industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figures 1A to 1C This is a schematic diagram of one embodiment of the fin definition process described herein;

[0008] Figure 2 This is a schematic diagram of an embodiment of the dummy gate structure formation process described herein;

[0009] Figure 3This is a schematic diagram of an embodiment of the source / drain recess formation process described herein;

[0010] Figures 4A to 4D This is a schematic diagram of an embodiment of the internal spacer formation process described herein;

[0011] Figure 5 This is a schematic diagram of an embodiment of the source / drain region formation process described herein;

[0012] Figure 6 This is a schematic diagram of an embodiment of the interlayer dielectric formation process described herein;

[0013] Figure 7A and Figure 7B This is a schematic diagram of one embodiment of the alternative gate formation process described herein;

[0014] Figure 8 This is a schematic diagram of an example of the semiconductor device described herein;

[0015] Figure 9 and Figure 10 This is a schematic diagram of an example process for forming a semiconductor device as described herein.

[0016] [Symbol Explanation]

[0017] 100, 200, 300, 400, 500, 600, 700: Examples

[0018] 105: Semiconductor Devices

[0019] 110: Semiconductor substrate

[0020] 115: Layer stacking

[0021] 120: Sacrificial Nanostructure Layer

[0022] 125: Nanostructured Channel Layer

[0023] 130: Silicon-Germanium Region

[0024] 135: Silicon Valley

[0025] 140: Rigid Coverage Layer

[0026] 145: Covering layer

[0027] 150: Oxide layer

[0028] 155: Nitride layer

[0029] 160: Fin-like structure

[0030] 160a: First Subset

[0031] 160b: Second Subset

[0032] 165: Part

[0033] 170: Fin section

[0034] 175: Padding

[0035] 180: STI area

[0036] 205: Dummy gate structure

[0037] 210: Gate electrode layer

[0038] 215: Rigid Coverage Layer

[0039] 220: Spacer layer

[0040] 225: Gate dielectric layer

[0041] 305: Source / Drain Recess

[0042] 310:convex area

[0043] 315: Nanostructured Channels

[0044] 405: Cavity

[0045] 410, 425, 440, 445, 455, 805: Details

[0046] 415: Inner surface

[0047] 420: Base

[0048] 430: Midpoint

[0049] 435: Endpoint

[0050] 450: Internal spacer

[0051] 505: Buffer

[0052] 510: Source / Drain Region

[0053] 515: Covering layer

[0054] 605: Dielectric layer

[0055] 705: Opening

[0056] 710: Gate Structure

[0057] 715: Metal gate electrode

[0058] 720: High-k dielectric layer

[0059] 800: Example

[0060] 900, 1000: Process

[0061] 910, 920, 930, 940, 950: Steps

[0062] 1010, 1020, 1030, 1040, 1050, 1060: Steps

[0063] AA, BB, CC: Cross-section

[0064] D1~D32: Dimensions Detailed Implementation

[0065] The following disclosure provides numerous different embodiments or examples for implementing various features of the described subject matter. Specific examples of elements and configurations are described below to simplify this specification. Of course, these are merely examples and not limiting. For instance, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or reference letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0066] Spatial relative terms such as “below,” “under,” “bottom,” “above,” and “top” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the apparatus in use or operation other than those shown in the accompanying drawings. The apparatus may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein shall be interpreted accordingly.

[0067] Some nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors) include an inner spacer between the source / drain regions and the gate structure. This inner spacer provides various process and performance advantages, such as electrical isolation between the source / drain regions and the gate structure, and / or protection of the source / drain regions from etching during replacement gate operations where the gate structure replaces the sacrificial nanostructure layer.

[0068] However, forming internal spacers can be difficult and may introduce defects, reducing their ability to provide electrical isolation and / or protect the source / drain regions from etching. For example, rounded corners may occur when forming cavities for internal spacers in nanostructures, potentially reducing the lateral thickness of the spacers at the top or bottom of the spacers. This reduction in lateral thickness may result in less etch buffering or etch termination during gate replacement operations, potentially causing etching through the spacers into the source / drain regions, damaging them, and / or creating electrical short circuits between the source / drain regions and the gate structure. This can lead to the failure of nanostructured transistors and reduce the yield of nanostructured transistors on semiconductor devices.

[0069] In some embodiments described herein, the inner spacer is formed in the nanostructured transistor of a semiconductor device in a manner that reduces the likelihood of etching through the inner spacer into adjacent source / drain regions. Specifically, the multi-etch process described herein is performed to form cavities in which the inner spacer is formed. The multi-etch process includes one or more first etch processes to form the cavity and one or more second etch processes to refine the corners of the cavity to reduce the roundness of the cavity corners. The corners of the cavity have sharper sidewalls and more pronounced transitions (e.g., increased perpendicularity) due to the one or more second etch processes. This results in lower error and increased consistency of the inner spacer. The increased consistency of the lateral thickness of the inner spacer reduces the likelihood of etching through any particular portion of the inner spacer during a gate replacement operation where the gate structure of the nanostructured transistor replaces the sacrificial nanostructure layer. Thus, the techniques described herein can reduce the likelihood of nanostructured transistor failure and / or increase the yield of nanostructured transistors formed on semiconductor devices.

[0070] Figures 1A to 1C This is a schematic diagram of an embodiment 100 of the fin-defining process described herein. Embodiment 100 includes forming a fin structure and associated shallow trench isolation (STI) region for a semiconductor device 105 described herein. The semiconductor device 105 may be fabricated to include one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. Embodiment 100 includes forming a fin structure and associated shallow trench isolation (STI) region for a semiconductor device 105 described herein.

[0071] Figures 1A to 1C A perspective view of the semiconductor device 105 and a cross-sectional view along line segment AA in the perspective view are shown respectively. Figure 1AAs shown, the semiconductor processing device 105 is associated with the semiconductor substrate 110. The semiconductor substrate 110 includes a silicon substrate, a substrate formed of a silicon-containing material, a group III-V composite substrate, such as a gallium arsenide substrate, a silicon-on-insulator substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or other types of semiconductor substrates.

[0072] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 comprises multiple alternating layers along a direction generally perpendicular to the semiconductor substrate (e.g., the Z direction). For example, the layer stack 115 comprises vertically alternating sacrificial nanostructure layers 120 and nanostructure channel layers 125 above the semiconductor substrate 110. Figure 1A The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown in the illustration are merely examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are also within the scope of this disclosure.

[0073] The sacrificial nanostructure layer 120 defines the vertical distance between adjacent nanostructure channels formed by the nanostructure channel layer 125, and serves as a reserved location for the gate structure of the transistor in the subsequently formed semiconductor device 105. The sacrificial nanostructure layer 120 comprises a first material composition, and the nanostructure channel layer 125 comprises a second material composition. In some embodiments, the first and second material compositions are the same. In some embodiments, the first and second material compositions are different. For example, the sacrificial nanostructure layer 120 may comprise silicon-germanium, and the nanostructure channel layer 125 may comprise silicon. This allows the sacrificial nanostructure 120 and / or the nanostructure channel layer 125 to be selectively etched depending on the type of etchant used (e.g., such that the sacrificial nanostructure layer 120 is etched while the nanostructure channel layer 125 is not etched, or such that the nanostructure channel layer 125 is etched while the sacrificial nanostructure layer 120 is not etched).

[0074] One or more deposition tools may be used to deposit and / or grow alternating layers of layer stack 115 to include nanostructures (e.g., nanosheets) on semiconductor substrate 110. For example, the deposition tools may be used to epitaxially grow sacrificial nanostructure layers 120 and / or nanostructure channel layers 125, including techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial techniques. Additionally and / or alternatively, the deposition of sacrificial nanostructure layers 120 and / or nanostructure channel layers 125 may be performed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable deposition techniques.

[0075] like Figure 1AA detailed enlarged view of a portion of the layer stack 115 shows that hybridization may occur between two or more nanostructure layers within the layer stack 115. For example, hybridization may occur between the sacrificial nanostructure layer 120 and a vertically adjacent nanostructure channel layer 125. Hybridization may cause diffusion of silicon and / or germanium between the sacrificial nanostructure layer 120 and the nanostructure channel layer 125. Therefore, a silicon-germanium region 130 may be included between the sacrificial nanostructure layer 120 and the nanostructure channel layer 125. The silicon-germanium region 130 may comprise a region of silicon-germanium having a greater silicon concentration than that of the sacrificial nanostructure layer 120 (e.g., due to silicon diffusion from the nanostructure channel layer 125 to the sacrificial nanostructure layer 120). In some embodiments, the silicon-germanium region 130 is a region within the sacrificial nanostructure layer 120.

[0076] Silicon region 135 may be contained between silicon-germanium region 130 and nanostructured channel layer 125. Silicon region 135 may contain a region of silicon with a germanium concentration greater than that of nanostructured channel layer 125 (e.g., due to germanium diffusion from sacrificial nanostructured layer 120 to nanostructured channel layer 125). The germanium concentration in silicon region 135 may be less than the germanium concentration in silicon-germanium region 130 and less than the germanium concentration in sacrificial nanostructured layer 120. Therefore, the germanium concentration may increase from nanostructured channel layer 125 through silicon region 135 and silicon-germanium region 130 to sacrificial nanostructured layer 120. In some embodiments, silicon region 135 is a region within nanostructured channel layer 125.

[0077] One or more masking layers may be formed (e.g., using one or more deposition tools) on the layer stack 115. The masking layers may include a hard mask (HM) layer 140, a capping layer 145, an oxide layer 150, and / or a nitride layer 155. The masking layers may be used for fin patterning operations to form fin-like structures in the semiconductor substrate 110.

[0078] like Figure 1B As shown, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This allows a fin structure 160 to be formed extending above the semiconductor substrate 110. The fin structure 160 may extend along the Y direction in the semiconductor device 105 and may be disposed along the X direction. The fin structure 160 includes a portion 165 of the layer stack 115 located on a fin portion 170 above the semiconductor substrate 110. The fin structure 160 may be patterned with one or more mask layers and the semiconductor substrate 110 may be etched according to the pattern formed by the one or more mask layers. The one or more mask layers may be patterned using photolithography techniques, including dual patterning or multiple patterning techniques. The etching tool may utilize dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof to etch the semiconductor substrate 110 according to the pattern formed by the one or more mask layers.

[0079] like Figure 1BAs further shown, some fin structures 160 can be formed with different widths for different types of nanostructure transistors. For example, a first subset 160a of the fin structures can be formed as a P-type nanostructure transistor (e.g., a P-type metal-oxide-semiconductor (PMOS) nanostructure transistor), and a second subset 160b of the fin structures can be formed as an N-type nanostructure transistor (e.g., an N-type metal-oxide-semiconductor (NMOS) nanostructure transistor). In another example, the first subset 160a of the fin structures can be formed as a nanostructure transistor configured to operate at a lower voltage, and the second subset 160b of the fin structures can be formed as a nanostructure transistor configured to operate at a higher voltage.

[0080] like Figure 1C As shown, pad 175 and STI region 180 may be formed between the fin portions 170 of adjacent fin structures 160. Pad 175 and STI region 180 may respectively contain dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low-k dielectric materials and / or other suitable insulating materials.

[0081] A deposition tool can be used to conformally deposit the pad 175 (e.g., using ALD or other conformal deposition techniques) and deposit a dielectric layer (e.g., using CVD, PVD, ALD, and / or other suitable deposition techniques) on the pad 175 such that the dielectric layer completely fills the space between the fin structures 160 and extends to the top of the fin structures 160. A planarization tool can be used to perform planarization or polishing operations (e.g., chemical mechanical polishing (CMP)) to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top surface of the nitride layer 155. The nitride layer 155 serves as a CMP termination layer in the planarization operation. An etching tool can be used to subsequently etch the dielectric layer to form the STI region 180 such that the top surface of the STI region 180 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0082] As mentioned above, Figures 1A to 1C Provided as an example. Other examples are available. Figures 1A to 1C The content described differs from the descriptions in the related articles.

[0083] Figure 2 This is a schematic diagram of an embodiment 200 of the dummy gate structure formation process described herein. Embodiment 200 includes an example of a dummy gate structure 205 forming a nanostructure transistor of a semiconductor device 105. In some embodiments, the operation described in embodiment 200 is performed in conjunction with... Figures 1A to 1C The process described is carried out afterward.

[0084] Figure 2A perspective view of a semiconductor device 105 and a dummy gate structure 205 formed thereon is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed on a portion of the fin structure 160 and a portion of the STI region 180. The dummy gate structure 205 extends in the x-direction and is arranged in the y-direction such that the dummy gate structure 205 is substantially perpendicular to the fin structure 160. The dummy gate structure 205 is a sacrificial structure to be replaced by a gate structure or gate stack in subsequent process stages of the semiconductor device 105. The dummy gate structure 205 can be used to define source / drain (S / D) recesses, where the source / drain regions of the nanostructure transistor are formed in the source / drain (S / D) recesses within the fin structure 160.

[0085] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 on the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 under the gate electrode layer 210. The gate electrode layer 210 comprises polysilicon (PO) or other materials. The hard mask layer 215 comprises one or more layers, such as an oxide layer (e.g., a pad oxide layer comprising silicon dioxide or other materials) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer comprising silicon nitride such as Si3N4 or other materials). The spacer layer 220 comprises silicon oxide, nitrogen-free silicon oxide, or other suitable materials. The gate dielectric layer 225 may comprise silicon oxide (e.g., silicon dioxide), silicon nitride (e.g., Si3N4), a high dielectric constant (high k) material (e.g., a dielectric material having a dielectric constant greater than about 3.9), and / or other suitable materials.

[0086] The layer of the dummy gate structure 205 can be formed by a variety of semiconductor process technologies, such as depositing the layer of the dummy gate structure 205, patterning the layer of the dummy gate structure 205 to define the dummy gate structure 205, and / or other semiconductor process technologies.

[0087] Figure 2 Further cross-sections for use in the figures described below are illustrated. Cross-section AA is in the xz plane (referred to as the y-section) passing through the fin structure 160 in the semiconductor device 105. Cross-section BB is in the yz plane perpendicular to cross-section AA (referred to as the x-section) and passing through the dummy gate structure 205 and along the fin structure 160 below. Cross-section CC is in the xz plane parallel to cross-section AA and perpendicular to cross-section BB and along the dummy gate structure 205. The following figures refer to these cross-sections for clarity. In some figures, for ease of illustration, reference numerals for some elements or features may be omitted to avoid obscuring other elements or features.

[0088] As mentioned above, Figure 2 Provided as an example. Other examples are available. Figure 2The content described differs from the descriptions in the related articles.

[0089] Figure 3 This is a schematic diagram of an embodiment 300 of the source / drain recess formation process described herein. Embodiment 300 includes an example of a source / drain recess 305 forming the source / drain region of a nanostructure transistor of a semiconductor device 105. Figure 3 From Figure 2 The multiple viewpoints depicted in the illustration include Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The viewpoint of section CC in the diagram. In some embodiments, the operation described in embodiment 300 is performed in conjunction with... Figures 1A to 2 The process described is carried out afterward.

[0090] like Figure 3 As shown in cross-sectional planes AA and BB, the source / drain recess 305 is formed through a portion 165 of the fin structure 160 during an etching operation. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and may be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes the use of plasma etching, wet chemical etching, and / or other etching techniques.

[0091] The source / drain recesses 305 also extend into a portion of the fin structure 160 during the etching operation. This results in the formation of convex regions 310 in the fin structure 160. The sidewalls of each portion of the source / drain recess 305 beneath the layer stack 115 correspond to the sidewalls of the convex regions 310. The convex regions 310 (also referred to as bases) refer to the regions on the fin portions 170 of the fin structure 160 that define nanochannels from the nanostructure channel layer 125. The nanostructure channels 315 extend between adjacent source / drain recesses 305 and lie beneath the dummy gate structure 205 between adjacent source / drain recesses 305.

[0092] The nanostructure channel 315 comprises a silicon-based nanostructure (e.g., nanosheets or nanowires, etc.) that serves as a semiconductor channel for a nanostructured transistor in the semiconductor device 105. In some embodiments, the nanostructure channel 315 may comprise silicon germanium (SiGe) or other silicon-based materials. The nanostructure channel 315 is disposed in a direction approximately perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructure channel 315 is disposed or stacked vertically above the semiconductor substrate 110.

[0093] As mentioned above, Figure 3 Provided as an example. Other examples are available. Figure 3 The content described differs from the descriptions in the related articles.

[0094] Figures 4A to 4D This is a schematic diagram of an embodiment 400 of the internal spacer formation process described herein. Embodiment 400 includes an example of forming internal spacers between the ends of nanostructured channels 315 exposed between source / drain recesses 305. Figures 4A to 4C They are from Figure 2 The multiple viewpoints depicted in the illustration include Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The viewpoint of section CC in the diagram. In some embodiments, the operation described in embodiment 300 is performed in conjunction with... Figures 1A to 3 The process described is carried out afterward.

[0095] like Figure 4A As shown in the cross-sectional plane BB, the ends of the sacrificial nanostructure layer 120 are exposed within the source / drain recesses 305 and are etched laterally (e.g., approximately in the x-direction parallel to the length of the sacrificial nanostructure layer 120) in one or more etch operations, thus forming cavities 405 exposed within the source / drain recesses 305 between the ends of the sacrificial nanostructure layer 120. Specifically, an etching tool can be used to laterally etch the ends of the sacrificial nanostructure layer 120 under the dummy gate structure 205 through the source / drain recesses 305 to form cavities 405 between the ends of the nanostructure channels 315.

[0096] In embodiments where the sacrificial nanostructure layer 120 is silicon-germanium and the nanostructure channel 315 is silicon, the sacrificial nanostructure layer 120 is etched in one or more etch operations using a wet etchant. The wet etchant, for example, comprises a mixed solution of hydrogen peroxide (H₂O₂), acetic acid (CH₃COOH), and / or hydrogen fluoride (HF), followed by rinsing with water. The mixed solution and water can be provided to penetrate the source / drain recess 305 to etch the sacrificial nanostructure layer 120 within the source / drain recess 305. In some embodiments, etching with the mixed solution and rinsing with water are repeated multiple times to form the cavity 405.

[0097] like Figure 4A As shown in detail 410, the cavity 405 may have a curved or arched inner surface 415. Specifically, the inner surface 415 may be concave such that the midpoint of the inner surface 415 extends inwardly into the cavity 405 from the base 420 corresponding to the top and bottom ends of the inner surface 415. The base 420 corresponds to the arc base of the inner surface 415. After one or more first etching operations, the cavity has a first distance dimension D1 between approximately the midpoint of the arc corresponding to the inner surface 415 and approximately the midpoint of the arc base 420. After one or more first etching operations, the inner surface 415 has a first radius of curvature R. The first radius of curvature R corresponds to the reciprocal of the curvature (κ) of the inner surface 415 (e.g., R = 1 / κ).

[0098] The upper and lower corners of cavity 405 correspond to the junctions of inner surface 415 and sidewalls of cavity 405, wherein the sidewalls of cavity 405 are the upper and lower surfaces of cavity 405. After one or more first etching operations, the cavity has a dimension D2 corresponding to a first angle (e.g., a first angle between inner surface 415 and the z-direction plane in semiconductor device 105) at a corner of cavity 405. In some embodiments, dimension D2 is contained in the range of about 40 degrees to about 45 degrees. However, other ranges of values ​​are also within the scope of this disclosure.

[0099] like Figure 4A As shown in another detail 425, after one or more first etch operations, the distance between approximately the midpoint 430 of the cavity 405 formed on the opposite side of the sacrificial nanostructure layer 120 is ( Figure 4A The dimension D3 is less than the distance between the endpoints 435 at the bottom of the cavity 405 after one or more first etching operations. Figure 4A (denoted as dimension D4), and less than the distance between the endpoints 435 at the top of the cavity 405 after one or more first etching operations. Figure 4A (This is denoted as dimension D5). The fillet radius of the inner surface 415 corresponds to half the average of the difference between dimension D5 and dimension D3 and the difference between dimension D4 and dimension D3 (e.g., fillet radius = AVG[(D5-D3) & (D4-D3)] / 2).

[0100] like Figure 4B As shown in the cross-sectional plane BB, one or more etching operations (e.g., using an etching tool) are performed to modify the cross-sectional profile of the inner surface 415 of the cavity 405. Specifically, one or more second etching operations can be used to laterally etch the cavity 405 to refine the corners of the cavity 405, thereby reducing the fillet radius of the cavity 405. In other words, one or more second etching operations are performed to flatten the inner surface 415 of the cavity 405 (e.g., to flatten the cross-sectional curvature of the inner surface).

[0101] like Figure 4BAs shown in detail 440, one or more second etching operations may include trimming (e.g., removing portions) the silicon-germanium regions 130 at the top and bottom of the cavity 405, and trimming (e.g., removing portions) the silicon regions 135 at the top and bottom of the cavity 405 to increase the orthogonality of the upper and lower corners of the cavity 405. An etching technique selectively etches the silicon-germanium regions 130 and silicon regions 135 in the cavity 405, while minimizing or omitting etching of the sacrificial nanostructure layer 120 at the ends of the nanostructure channel 315 in the cavity 405. For example, one or more second etching operations may include performing an etching operation using a gas-based etchant, wherein the gas-based etchant comprises a combination of fluorine (F2) and ammonia (NH4). The combination of fluorine and ammonia can be used to form a protective layer on the inner surface of cavity 405 (corresponding to the end of the sacrificial nanostructure layer 120 exposed in cavity 405) to block the etching of the portion corresponding to the inner surface 415 of the sacrificial nanostructure layer 120. At the same time, the combination of fluorine and ammonia is used to etch the exposed surfaces of silicon-germanium region 130 and silicon region 135 in cavity 405.

[0102] The combination of fluorine and ammonia can selectively form a protective layer on the sacrificial nanostructure layer 120 due to the high germanium content of the sacrificial nanostructure layer 120. The wafer can selectively etch the silicon-germanium regions 130 and silicon regions 135 due to their high silicon content. The protective layer is formed on the sacrificial nanostructure layer 120 in cavity 405 due to the reaction of germanium in the sacrificial nanostructure layer 120 with fluorine and ammonia in the gas-based etchant. Such a reaction may include:

[0103] SiGe+4F2+NH3→SiF4+GeF4+NH3→GeF4+2HF+2NH3→(NH4)2GeF6

[0104] Fluorine and ammonia react with germanium to form ammonium fluorinated germanate on the exposed surface of the sacrificial nanostructure layer 120 in cavity 405. Ammonium fluorinated germanate (AFG) protects the sacrificial nanostructure layer 120 from etching (or reduces the etching rate) in one or more second etching operations.

[0105] In some embodiments, fluorine and ammonia may be premixed in the gas supply system of an etching tool used to perform one or more second etching operations. The fluorine and ammonia mixture may then be provided to the processing chamber of the etching tool, wherein a semiconductor device is configured to perform one or more second etching operations. In some embodiments, fluorine and ammonia are provided to the processing chamber in separate gas streams. The fluorine and ammonia mix and react in the processing chamber to perform one or more etching operations. For example, a fluorine gas stream may be provided first to the processing chamber, fluorine-related treatment may be performed, the fluorine gas stream may be stopped, and then an ammonia gas stream may be provided. In some embodiments, premixing fluorine and ammonia may result in a faster etching rate and some etching of the sacrificial nanostructure layer 120 in the silicon-germanium region 130 and silicon region 135, while providing separate fluorine and ammonia gas streams may result in a slower and more controlled etching rate in the silicon-germanium region 130 and silicon region 135.

[0106] In some embodiments, the fluorine gas flow rate may be in the range of approximately 10 standard cubic centimeters per second (SCCM) to approximately 100 SCCM. A flow rate less than 10 SCCM may result in insufficient planarization of the inner surface 415 of cavity 405, while a flow rate greater than 100 SCCM may result in over-etching of the silicon-germanium region 130 and the silicon region 135. Providing a flow rate in the range of approximately 10 SCCM to approximately 100 SCCM results in planarization of the inner surface 415 of cavity 405 and minimal over-etching of the silicon-germanium region 130 and the silicon region 135. However, other fluorine flow rate values ​​and ranges are also within the scope of this disclosure.

[0107] In some embodiments, the duration of the fluorine gas flow may range from approximately 30 seconds to approximately 360 seconds. Less than 30 seconds may result in insufficient planarization of the inner surface 415 of cavity 405, while more than 360 seconds may result in over-etching of the silicon-germanium region 130 and the silicon region 135. A fluorine gas flow duration in the range of approximately 30 seconds to approximately 360 seconds results in planarization of the inner surface 415 of cavity 405 and minimal over-etching of the silicon-germanium region 130 and the silicon region 135. However, other values ​​and ranges for the duration of the fluorine gas flow are also within the scope of this disclosure.

[0108] In some embodiments, the ammonia flow rate may be in the range of approximately 50 SCCM to approximately 500 SCCM. A flow rate less than 50 SCCM may result in insufficient planarization of the inner surface 415 of cavity 405, while a flow rate greater than 500 SCCM may result in over-etching of the silicon-germanium region 130 and the silicon region 135. Providing a flow rate in the range of approximately 50 SCCM to approximately 500 SCCM results in planarization of the inner surface 415 of cavity 405 and minimal over-etching of the silicon-germanium region 130 and the silicon region 135. However, other ammonia flow rate values ​​and ranges are also within the scope of this disclosure.

[0109] In some embodiments, the duration of the ammonia gas flow may range from approximately 30 seconds to approximately 360 seconds. Less than 30 seconds may result in insufficient planarization of the inner surface 415 of cavity 405, while more than 360 seconds may result in over-etching of the silicon-germanium region 130 and the silicon region 135. A duration of ammonia gas flow ranging from approximately 30 seconds to approximately 360 seconds results in planarization of the inner surface 415 of cavity 405 and minimal over-etching of the silicon-germanium region 130 and the silicon region 135. However, other values ​​and ranges for the duration of the ammonia gas flow are also within the scope of this disclosure.

[0110] In some embodiments, a cyclic etching technique is used to perform one or more second etch operations, wherein multiple etch cycles are performed to etch the silicon-germanium region 130 and the silicon region 135 in the cavity 405. Each etch cycle may include etching the silicon-germanium region 130 and the silicon region 135 using a gas-based etchant, followed by removal of etching byproducts (e.g., from the processing chamber) resulting from etching the silicon-germanium region 130 and the silicon region 135. In some embodiments, the number of etch cycles includes approximately 2 to approximately 10 etch cycles. Fewer than 2 etch cycles may result in insufficient planarization of the inner surface 415 of the cavity 405, while more than 10 etch cycles may result in over-etching of the silicon-germanium region 130 and the silicon region 135. Performing 2 to 10 etch cycles results in planarization of the inner surface 415 of the cavity 405 and minimal over-etching of the silicon-germanium region 130 and the silicon region 135. However, other numbers of etch cycles are also within the scope of this disclosure.

[0111] Even though the examples of one or more second etching operations described herein involve the use of gas-based etchants containing fluorine and ammonia, other gas-based etchants and other types of etchants may also be used to perform one or more second etching operations.

[0112] like Figure 4B As shown in detail 440, after one or more second etching operations, the cavity 405 has a second distance dimension D6 between approximately the midpoint of the arc corresponding to the inner surface 415 and approximately the midpoint of the base 420 of the arc. Due to the reduction in the cross-sectional curvature of the inner surface 415 caused by the one or more second etching operations, the second distance after the one or more second etching operations is smaller than the first distance (dimension D1) after the one or more first etching operations. After the one or more second etching operations, the inner surface 415 has a second radius of curvature. Due to the reduction in the cross-sectional curvature (κ) of the inner surface 415 caused by the one or more second etching operations, the second radius of curvature R is greater than the first radius of curvature of the inner surface 415 after the one or more first etching operations.

[0113] like Figure 4BAs further shown in detail 440, after one or more second etching operations, the cavity 405 has a dimension D7 corresponding to a second angle (e.g., a second angle at the intersection of the inner surface 415 and the z-direction plane in the semiconductor device 105) at a corner of the cavity 405. After one or more second etching operations, the cross-sectional curvature of the inner surface 415 is reduced due to the one or more second etching operations, and the second angle at the corner of the cavity 405 is smaller than the first angle (dimension D2) at the corner of the cavity 405 after one or more first etching operations. In some embodiments, dimension D7 is less than approximately 10 degrees. However, other values ​​of dimension D7 are also within the scope of this disclosure.

[0114] like Figure 4B Another detail shown in section 445 is the distance between approximately the midpoint 430 of the cavities on the opposite side of the sacrificial nanostructure layer 120 after one or more second etch operations. Figure 4B The distance between the endpoints 435 at the bottom of the cavity 405 (denoted as dimension D9) is less than the distance between the endpoints 435 after one or more second etching operations. Figure 4B The dimension is denoted as D10, and is less than the distance between the endpoints 435 at the top of the cavity 405 after one or more second etching operations. Figure 4B (This is denoted as dimension D11). Furthermore, the differences between dimensions D10 and D9, and between dimensions D11 and D9, are smaller than the differences between dimensions D4 and D3, and between dimensions D5 and D3. Therefore, after one or more second etching operations, the roundness of the inner surface 415 of the cavity 405 is less than the roundness of the inner surface 415 of the cavity 405 before one or more second etching operations.

[0115] like Figure 4C As shown in cross-sectional planes AA and BB, inner spacers 450 are formed between cavities 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recesses 305. The inner spacers 450 are included to reduce the parasitic capacitance of the nanostructure transistors and to protect the source / drain regions (subsequently formed within the source / drain recesses 305) from etching during the removal of the sacrificial nanostructure layer 120 between the nanostructure channels 315. As shown above, this achieves a mating... Figures 4A to 4C The described technique for forming a cavity 405 in which an inner spacer 450 is formed, resulting in a high uniformity in the lateral thickness of the inner spacer 450, reduces the likelihood of etching through the inner spacer 450 into the source / drain region compared to other cavity forming techniques. The inner spacer 450 comprises silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, silicon oxycarbide nitride, and / or other dielectric materials.

[0116] To form the inner spacer 450, a dielectric material is deposited in the cavity 405 and along the sidewalls and bottom surface of the source / drain recess using a deposition tool. CVD, PVD, ALD, and / or other deposition techniques can be used to deposit this dielectric material. An etching tool is then used to remove excess material from the source / drain recess. In some embodiments, the etching operation may cause the surface of the inner spacer 450 facing the source / drain recess 305 to bend or recess. In some embodiments, the surface of the inner spacer 450 facing the source / drain recess 305 is approximately flat such that the surface of the inner spacer 450 and the surface of the end of the nanostructure channel 315 are approximately average and flush.

[0117] like Figure 4D The detailed portion 455 in the cross-sectional plane BB is shown because of the fit Figure 4A and Figure 4B The described multi-etch process for forming cavities 405 in which inner spacers 450 are formed may have one or more dimensions for the sacrificial nanostructure layer 120 and / or the inner spacers 450. The sacrificial nanostructure layer 120 between the uppermost nanostructure channel 315 and the intermediate nanostructure channel 315 below the uppermost nanostructure channel 315 may have a cross-sectional width in the y-direction corresponding to dimension D12 (approximately at the center of a portion of the sacrificial nanostructure layer 120 between adjacent inner spacers 450). In some embodiments, dimension D12 is included in the range of approximately 12 nanometers to approximately 18 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. The inner spacers 450 adjacent to the sacrificial nanostructure layer 120 may have a cross-sectional width in the y-direction corresponding to dimension D13 at approximately the center of the inner spacer 450, dimension D14 at the bottom of the inner spacer 450, and dimension D15 at the top of the inner spacer 450. In some embodiments, the difference between dimensions D13 and D14, and the difference between dimensions D13 and D15, may each be within the range of approximately 0.5 nanometers to approximately 1.5 nanometers, allowing the inner spacer 450 to achieve high lateral thickness uniformity. This reduces the likelihood of etching through the inner spacer 450 (e.g., at the top or bottom of the inner spacer 450). However, other ranges of values ​​are also within the scope of this disclosure.

[0118] The sacrificial nanostructure layer 120 between the intermediate nanostructure channel 315 and the lowermost nanostructure channel 315 below the intermediate nanostructure channel 315 may have a cross-sectional width in the y-direction corresponding to dimension D16 (approximately at the center of the portion of the sacrificial nanostructure layer 120 between adjacent inner spacers 450). In some embodiments, dimension D16 is included in the range of approximately 12 nanometers to approximately 18 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. The inner spacers 450 adjacent to the sacrificial nanostructure layer 120 may have a cross-sectional width in the y-direction corresponding to dimension D17 at approximately the center of the inner spacer 450, dimension D18 at the bottom of the inner spacer 450, and dimension D19 at the top of the inner spacer 450. In some embodiments, the difference between dimension D17 and dimension D18 and the difference between dimension D17 and dimension D19 may each be included in the range of approximately 0.5 nanometers to approximately 1.5 nanometers, such that the inner spacers 450 can achieve high lateral thickness uniformity. This reduces the likelihood of etching through the inner spacer 450 (e.g., at the top or bottom of the inner spacer 450). However, other ranges of values ​​are also within the scope of this disclosure.

[0119] In some embodiments, the difference between dimension D17 and dimension D13 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. In some embodiments, the difference between dimension D18 and dimension D14 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. In some embodiments, the difference between dimension D19 and dimension D15 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure.

[0120] The sacrificial nanostructure layer 120 between the lowermost nanostructure channel 315 and the protrusion region 310 below the lowermost nanostructure channel 315 may have a cross-sectional width in the y-direction corresponding to dimension D20 (approximately at the center of the portion of the sacrificial nanostructure layer 120 between adjacent inner spacers 450). In some embodiments, dimension D20 is included in the range of approximately 12 nanometers to approximately 18 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. The inner spacers 450 adjacent to the sacrificial nanostructure layer 120 may have a cross-sectional width in the y-direction corresponding to dimension D21 at approximately the center of the inner spacer 450, dimension D22 at the bottom of the inner spacer 450, and dimension D23 at the top of the inner spacer 450. In some embodiments, the difference between dimension D21 and dimension D22 and the difference between dimension D21 and dimension D23 may each be included in the range of approximately 0.5 nanometers to approximately 1.5 nanometers, such that the inner spacers 450 can achieve high lateral thickness uniformity. This reduces the likelihood of etching through the inner spacer 450 (e.g., at the top or bottom of the inner spacer 450). However, other ranges of values ​​are also within the scope of this disclosure.

[0121] In some embodiments, the difference between dimension D21 and dimension D13 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. In some embodiments, the difference between dimension D22 and dimension D14 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. In some embodiments, the difference between dimension D23 and dimension D15 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure.

[0122] In some embodiments, the difference between dimension D21 and dimension D17 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. In some embodiments, the difference between dimension D22 and dimension D18 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure. In some embodiments, the difference between dimension D23 and dimension D19 is less than about 6 nanometers. However, other ranges of values ​​are also within the scope of this disclosure.

[0123] As mentioned above, Figures 4A to 4D Provided as an example. Other examples are available. Figures 4A to 4D The content described differs from the descriptions in the related articles.

[0124] Figure 5 This is a schematic diagram of an embodiment 500 of the source / drain region formation process described herein. Embodiment 500 includes an example of forming the source / drain regions of a nanostructured transistor of semiconductor device 105. Figure 5 From Figure 2 The multiple viewpoints depicted in the illustration include Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The viewpoint of section CC in the diagram. In some embodiments, the operation described in embodiment 500 is performed in conjunction with... Figures 1A to 4D The process described is carried out afterward.

[0125] like Figure 5 As shown in cross-sections AA and BB, the source / drain recess 305 is filled with one or more layers, forming a source / drain region within the source / drain recess 305. For example, a deposition tool can be used to deposit a buffer zone 505 at the bottom of the source / drain recess 305, and the deposition tool can be used to deposit a source / drain region 510 on the buffer zone 505 within the source / drain recess 305. In some embodiments, the deposition tool can be used to deposit a capping layer 515 on the source / drain region 510 within the source / drain recess 305.

[0126] Buffer 505 may contain silicon, boron-doped or other doped silicon, and / or other materials. Buffer 505 may be included between the source / drain region 510 and the adjacent bump region 310 to reduce, minimize, and / or prevent dopant migration and / or leakage current from the source / drain region 510 to the adjacent bump region 310. Accordingly, buffer 505 may improve the performance of semiconductor device 105 and / or increase the yield of semiconductor device 105.

[0127] The term "source / drain region" can be used separately or collectively as the source or drain, depending on the context. The source / drain region 510 may be included on the opposite side of the dummy gate structure 205 such that the nanostructure channel 315 under the dummy gate structure 205 extends between and is electrically coupled to the source / drain region 510. Each source / drain region 510 comprises silicon and one or more dopants, such as P-type materials (boron or germanium, etc.), N-type dopants (phosphorus or arsenic, etc.), and / or other dopants. Accordingly, the semiconductor device 105 may include a P-type metal-oxide-semiconductor (PMOS) nanostructure transistor including a P-type source / drain region 510, an N-type metal-oxide-semiconductor (NMOS) nanostructure transistor including an N-type source / drain region 510, and / or other types of nanostructure transistors.

[0128] One or more layers of the source / drain region 510 may be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 510 on an associated buffer 505 (referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, or L2-2) of the source / drain region 510 on the first layer. The first layer may comprise lightly doped silicon (e.g., doped with boron, phosphorus, and / or other dopants) and may be included as a barrier layer to reduce short-channel effects in the semiconductor device 105 and to reduce dopant extrusion or migration into the nanostructure channel 315. The second layer may comprise heavily doped silicon or heavily doped silicon-germanium. The second layer may be included to provide compressive stress to prevent boron loss.

[0129] The capping layer 515 may comprise silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or other materials. The capping layer may be included to reduce dopant diffusion and protect the underlying source / drain regions 510 prior to contact formation. Furthermore, the capping layer 515 may facilitate the formation of metal-semiconductor alloys (e.g., silicides).

[0130] As mentioned above, Figure 5 Provided as an example. Other examples are available. Figure 5 The content described differs from the descriptions in the related articles.

[0131] Figure 6This is a schematic diagram of an embodiment 600 of the interlayer dielectric formation process described herein. Figure 6 From Figure 2 The multiple viewpoints depicted in the illustration include Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2 The viewpoint of section CC in the diagram. In some embodiments, the operation described in embodiment 600 is performed in conjunction with... Figures 1A to 5 The process described is carried out afterward.

[0132] like Figure 6 As shown in cross-sections AA and BB, a dielectric layer 605 is formed on the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the area between the dummy gate structures 205. The dielectric layer 605 is formed to prevent or reduce the likelihood of damage to the source / drain region 510 during the gate replacement process. The dielectric layer 605 may be referred to as the ILD zero layer (ILD0 layer) or another ILD layer.

[0133] In one embodiment, a contact etch-stop layer (CESL) is conformally deposited (e.g., using a deposition tool) on the source / drain region 510 prior to the formation of the dielectric layer 605. Alternatively, a capping layer 515 may serve as the CESL. The dielectric layer 605 is thus formed on the CESL. The CESL provides a mechanism to terminate the etching process when forming conductive contacts or conductive vias in the source / drain region 510. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers. The CESL may comprise or be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may comprise or be silicon nitride, silicon carbide, carbon nitride, silicon oxynitride, silicon carbide, or a combination thereof, etc. The CESL may be deposited using deposition processes such as ALD, CVD, or other deposition techniques.

[0134] As mentioned above, Figure 6 Provided as an example. Other examples are available. Figure 5 The content described differs from the descriptions in the related articles.

[0135] Figure 7A and Figure 7B This is a schematic diagram of an embodiment 700 of the substitution gate (RPG) formation process described herein. Embodiment 700 includes an example of a substitution gate formation process in which a dummy gate structure 205 of a nanostructured transistor of semiconductor device 105 is replaced with a high-k / metal gate structure (e.g., a substitution gate structure). Figure 7A and Figure 7B From Figure 2 The multiple viewpoints depicted in the illustration include Figure 2 The viewpoint of section AA in the middle, Figure 2 The viewpoint of section BB in the middle and Figure 2The viewpoint of section CC in the diagram. In some embodiments, the operation described in embodiment 700 is performed in conjunction with... Figures 1A to 6 The process described is carried out afterward.

[0136] like Figure 7A As shown in cross-sections BB and CC, the gate replacement process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removing the dummy gate structure 205 leaves an opening (or recess) between the dielectric layers 605 and provides contact means for the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 may be removed in one or more etching operations. Such etching operations may include plasma etching, wet chemical etching, and / or another etching technique.

[0137] like Figure 7A As further shown, the gate replacement process includes a nanostructure release operation (e.g., a silicon-germanium release operation). A nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., the silicon-germanium layer). This creates openings 705 between the nanostructure channels 315 (e.g., the area around the nanostructure channels 315). The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation may include using an etching tool to perform an etching operation to remove the sacrificial nanostructure layer 120 based on the difference in etch selectivity between the material of the sacrificial nanostructure layer 120 and the material of the nanostructure channels 315, and between the material of the sacrificial nanostructure layer 120 and the material of the inner spacer 450.

[0138] The inner spacer 450 can act as an etch stop layer during the etching operation to protect the source / drain region 510 from etching. As shown above, this achieves a mating effect. Figures 4A to 4C The technique described in the description of forming a cavity 405 in which an inner spacer 450 is formed, thereby giving the inner spacer 450 a highly uniform lateral thickness, reduces the possibility of etching through the inner spacer 450 into the source / drain region 510 compared to other cavity forming techniques.

[0139] like Figure 7BAs shown in cross-sections BB and CC, the gate replacement process includes forming a gate structure 710 (e.g., a gate replacement structure) in the openings 705 between the source / drain regions 510 and the inner spacers 450. Specifically, the gate structure 710 fills the area between and around the nanostructure channels 315, vacating the area previously occupied by the sacrificed nanostructure layer 120, so that the gate structure completely surrounds and encloses the nanostructure channels 315. This improves control over the nanostructure channels 315, increases the drive current of the nanostructure transistors in the semiconductor device 105, and / or reduces the short-channel effect of the nanostructure transistors in the semiconductor device 105, etc. The gate structure 710 can also fill the space previously occupied by the dummy gate structure 205. Portions of the gate structure 710 are formed in a vertically alternating arrangement between pairs of nanostructure channels 315. In other words, as... Figure 7B As shown, the semiconductor device 105 includes one or more nanostructured channels 315 and gate structures 710 partially and vertically stacked.

[0140] The gate structure 710 may individually include a metal gate electrode 715. The metal gate electrode 715 may include one or more metallic materials, such as tungsten, cobalt, ruthenium, and / or titanium, etc. Additionally and / or alternatively, the gate structure 710 may individually include one or more work function metal layers to tune the work function of the metal gate electrode 715.

[0141] Before forming the metal gate electrode 715, a conformal high-k dielectric layer 720 of the gate structure 710 can be deposited on the sidewalls of the nanostructure channel 315 and the inner spacer 450. The gate structure 710 may individually include additional layers, such as interface layers, adhesive layers, and / or capping layers, etc. The high-k dielectric layer 720 may individually include one or more high-k dielectric materials, such as silicon nitride, hafnium oxide, lanthanum oxide, and / or other suitable high-k dielectric materials.

[0142] Some source / drain regions 510 and gate structures 710 may be shared by two or more nanostructure transistors in a semiconductor device. In these embodiments, such as Figure 7B In the example, one or more source / drain regions 510 and gate structure 710 may be connected or coupled to multiple nanostructure channels 315. This allows multiple nanostructure channels 315 to be controlled by a gate structure 710 and a pair of source / drain regions 510.

[0143] As mentioned above, Figure 7A and Figure 7B Provided as an example. Other examples are available. Figure 7A and Figure 7B The content described differs from the descriptions in the related articles.

[0144] Figure 8This is a schematic diagram of an example 800 of the semiconductor device 105 described herein. The semiconductor device 105 can be configured as described above. Figures 1A to 7B The described technological formation. For example... Figure 8 As shown, the semiconductor device 105 includes a plurality of nanostructured channels 315 on a semiconductor substrate 110. The nanostructured channels 315 are disposed along a z-direction perpendicular to the semiconductor substrate 110. The semiconductor device 105 includes source / drain regions 510 adjacent to the nanostructured channels 315. The semiconductor device includes a gate structure 710 surrounding each nanostructured channel 315. Inner spacers 450 are included between the source / drain regions 510 and the gate structure. The inner spacers 450 are disposed between the ends of vertically adjacent nanostructured channels 315. The lowermost inner spacer 450 may be disposed between the convex region 310 and the lowermost nanostructured channel 315 on the convex region 310.

[0145] In the semiconductor device 105, some interlayer mixing may occur in the layers or structures that are continuously formed in the semiconductor device 105, such as mixing between the sacrificial nanostructure layer 120 and the nanostructure channel layer 125. Therefore, a silicon region 135 with a larger germanium content than the nanostructure channel 315 may be located between the nanostructure channel 315 and the portion of the gate structure 710 surrounding the nanostructure channel 315. Furthermore, the silicon region 135 may be included between the nanostructure channel 315 and the inner spacer 450 located at the end of the gate structure 710. Due to one or more second etch operations in the multiple etch process forming the cavity 405, the inner spacer 450 may extend into a portion of the silicon region 135. Therefore, the thickness of the silicon region 135 contacting the gate structure 710 may be greater than the thickness of the silicon region 135 contacting the inner spacer 450.

[0146] One or more dimensions of the semiconductor device 105 are shown in Figure 8In detail portion 805, the portion of the gate structure 710 between the uppermost nanostructure channel 315 and the middle nanostructure channel 315 below the uppermost nanostructure channel 315 may have a cross-sectional width in the y-direction corresponding to dimension D24 (approximately the center of the portion of the gate structure 710 between adjacent inner spacers 450), dimension D25 (the bottom of the portion of the gate structure 710 between adjacent inner spacers 450), and dimension D26 (the top of the portion of the gate structure 710 between adjacent inner spacers 450). In some embodiments, due to the multiple etching process of the inner surface 415 of the cavity 405 of the inner spacers 450 as described herein, the difference between dimensions D24 and D25 and the difference between dimensions D24 and D26 may be less than approximately 3 nanometers to approximately 0 nanometers. For example, the difference between dimensions D24 and D26 and / or the difference between dimensions D24 and D25 may be in the range of approximately 0.5 nanometers to approximately 1.5 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. The difference between size D24 and size D26 and / or the difference between size D24 and size D25 may be less than the z-direction thickness of the nanostructure channel 315, while the z-direction thickness of the nanostructure channel 315 may be contained in the range of approximately 3 nanometers to approximately 10 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the ratio of size D24 to size D25 and / or the ratio of size D24 to size D26 may be contained in the range of approximately 1.03:1 to approximately 1.12:1. However, other values ​​and ranges are also within the scope of this disclosure.

[0147] The gate structure 710 may have a cross-sectional width in the y-direction corresponding to dimensions D27 (approximately the center of the portion of the gate structure 710 between adjacent inner spacers 450), D28 (the bottom of the portion of the gate structure 710 between adjacent inner spacers 450), and D29 (the top of the portion of the gate structure 710 between adjacent inner spacers 450). The range of these dimensions and the associated differences and ratios may be similar to dimensions D24, D25, and D26. The difference between dimension D27 and dimension D24 may be approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. The difference between dimension D28 and dimension D25 may be approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. The difference between dimension D29 and dimension D26 may be approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0148] The gate structure 710 may have a cross-sectional width in the y-direction corresponding to dimensions D30 (approximately the center of the portion of the gate structure 710 between adjacent inner spacers 450), D31 (the bottom of the portion of the gate structure 710 between adjacent inner spacers 450), and D32 (the top of the portion of the gate structure 710 between adjacent inner spacers 450). The range of these dimensions and the associated differences and ratios may be similar to dimensions D24, D25, and D26. The difference between dimension D30 and dimension D24 may be approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and other ranges are also within the scope of this disclosure. The difference between dimension D31 and dimension D25 may be approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and other ranges are also within the scope of this disclosure. The difference between dimension D32 and dimension D26 may be approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and other ranges are also within the scope of this disclosure. The difference between size D30 and size D27 can be from approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. The difference between size D31 and size D28 can be from approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. The difference between size D32 and size D29 can be from approximately 0 nanometers to approximately 6 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0149] As mentioned above, Figure 8 Provided as an example. Other examples are available. Figure 8 The content described differs from the descriptions in the related articles.

[0150] Figure 9 This is a schematic diagram of an example process 900 for forming a semiconductor device as described herein. In some embodiments, Figure 9 One or more steps are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, imaging tools, etching tools, planarization tools, and / or ion implantation tools, etc.

[0151] like Figure 9 As shown, process 900 includes forming a layer stack (step 910) over a substrate of a semiconductor device, comprising a plurality of first nanostructure layers and a plurality of second nanostructure layers overlapping the first nanostructure layers in a direction approximately perpendicular to the substrate. For example, one or more semiconductor processing tools may be used to form a layer stack 115 over a substrate (e.g., semiconductor substrate 110) of semiconductor device 105, comprising a plurality of first nanostructure layers (e.g., sacrificial nanostructure layer 120) and a plurality of second nanostructure layers overlapping the first nanostructure layers (e.g., nanostructure channel layer 125) in a direction approximately perpendicular to the substrate (e.g., the z-direction).

[0152] like Figure 9As further shown, process 900 includes forming recesses through the layer stack to form a plurality of nanostructure channels from a plurality of second nanostructure layers (step 920). For example, one or more semiconductor processing tools may be used to form recesses (e.g., source / drain recesses 305) through the layer stack 115 to form a plurality of nanostructure channels 315 from a plurality of second nanostructure layers (e.g., nanostructure channel layer 125). In some embodiments, the ends of the plurality of first nanostructure layers (e.g., sacrificial nanostructure layer 120) and the ends of the plurality of nanostructure channels 315 are exposed from the recesses.

[0153] like Figure 9 As further shown, process 900 includes performing a first etching operation to laterally etch one end of one of a plurality of first nanostructure layers through a recess, thereby forming a cavity between a first nanostructure channel and a second nanostructure channel in a plurality of nanostructure channels (step 930). For example, one or more semiconductor processing tools may be used to perform the first etching operation to laterally etch one end of one of a plurality of first nanostructure layers (e.g., sacrificial nanostructure layer 120) through a recess (e.g., source / drain recess 305), thereby forming a cavity 405 between a first nanostructure channel 315 and a second nanostructure channel 315 in a plurality of nanostructure channels.

[0154] like Figure 9 As further shown, process 900 includes performing a second etching operation after the first etching operation to change the profile of the inner surface of the cavity (step 940). For example, one or more semiconductor processing tools can be used to perform the second etching operation after the first etching operation to change the profile of the inner surface 415 of the cavity 405.

[0155] like Figure 9 As further shown, process 900 includes forming an inner spacer in the cavity after the second etching operation (step 950). For example, one or more semiconductor processing tools may be used to form the inner spacer 450 in the cavity 405 after the second etching operation.

[0156] Process 900 may include additional embodiments, such as any single embodiment described below or any combination of embodiments described below and / or in conjunction with one or more processes described elsewhere herein.

[0157] In the first embodiment, the interface between the nanostructure layer (e.g., the sacrificial nanostructure layer 120) and the first nanostructure channel 315 includes a silicon-germanium region 130 having a silicon concentration greater than that of the nanostructure layer (e.g., the sacrificial nanostructure layer 120) and a silicon region 135 having a germanium concentration greater than that of the first nanostructure channel, and the second etching operation includes trimming the silicon-germanium region 130 and the silicon region 135.

[0158] In the second embodiment, alone or in combination with the first embodiment, the inner surface 415 of the cavity 405, after the first etching operation, has a first distance (dimension D1) between approximately the midpoint of the arc of the inner surface 415 and approximately the midpoint of the base 420 of the arc, and the inner surface 415 of the cavity 405, after the second etching operation, has a second distance (dimension D6) between approximately the midpoint of the arc of the inner surface 415 and approximately the midpoint of the base 420 of the arc, wherein the second distance is smaller than the first distance.

[0159] In the third embodiment, the second etching operation is performed alone or in combination with one or more of the first and second embodiments to flatten the cross-sectional curvature of the inner surface of the cavity.

[0160] In the fourth embodiment, performing the second etching operation alone or in combination with one or more of the first to third embodiments includes performing the second etching operation using a gas-based etchant containing a combination of fluorine and ammonia.

[0161] In the fifth embodiment, the second etching operation, performed alone or in combination with one or more of the first to fourth embodiments, includes providing a first gas flow of fluorine into a processing chamber in which the semiconductor device is located, and after the first gas flow stops, providing a second gas flow of ammonia into the processing chamber.

[0162] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the difference between the width of the nanostructure layer at approximately the midpoint (D3, D9) and the width of the nanostructure layer at the bottom (D4, D10) is smaller after the second etching operation than before the second etching operation.

[0163] In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, the inner surface 415 of the cavity 405, after the first etching operation, has a first angle (e.g., dimension D2) between approximately the midpoint 430 of the arc of the inner surface 415 and the end point of the arc, and the inner surface 415 of the cavity 405, after the second etching operation, has a second angle (e.g., dimension D7) between approximately the midpoint 430 of the arc of the inner surface 415 and the end point 435 of the arc, wherein the second angle is smaller than the first angle.

[0164] even though Figure 9 The illustration depicts example steps of process 900, which in some embodiments are compared to... Figure 9 As shown, steps may include additional steps, fewer steps, different steps, or steps in a different order. Alternatively, two or more steps of process 900 may be performed in parallel.

[0165] Figure 10 This is a schematic diagram of an example process 1000 for forming a semiconductor device as described herein. In some embodiments, Figure 10One or more steps are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, imaging tools, etching tools, planarization tools, and / or ion implantation tools, etc.

[0166] like Figure 10 As shown, process 1000 includes forming a layer stack (step 1010) over a substrate of a semiconductor device, comprising a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layers overlapping the sacrificial nanostructure layers in a direction approximately perpendicular to the substrate. For example, one or more semiconductor processing tools may be used to form a layer stack 115 over a substrate (e.g., semiconductor substrate 110) of semiconductor device 105, comprising a plurality of sacrificial nanostructure layers 120 and a plurality of nanostructure channel layers 125 overlapping the sacrificial nanostructure layers 120 in a direction approximately perpendicular to the substrate (e.g., the z-direction).

[0167] like Figure 10 As further shown, process 1000 includes forming source / drain recesses through a layer stack to form a plurality of nanostructured channels from a plurality of nanostructured channel layers (step 1020). For example, one or more semiconductor processing tools can be used to form source / drain recesses 305 through a layer stack 115 to form a plurality of nanostructured channels 315 from a plurality of nanostructured channel layers 125. In some embodiments, the ends of the plurality of sacrificial nanostructured layers 120 and the ends of the plurality of nanostructured channels 315 are exposed in the source / drain recesses 305.

[0168] like Figure 10 As further shown, process 1000 includes performing a first etching operation to laterally etch one end of one of a plurality of sacrificial nanostructure layers through a source / drain recess, thereby forming a cavity between a first nanostructure channel and a second nanostructure channel among a plurality of nanostructure channels (step 1030). For example, one or more semiconductor processing tools may be used to perform the first etching operation to laterally etch one end of one of a plurality of sacrificial nanostructure layers 120 through a source / drain recess 305, thereby forming a cavity 405 between a first nanostructure channel 315 and a second nanostructure channel 315 among a plurality of nanostructure channels 315. In some embodiments, after the first etching operation, the inner surface 415 of the cavity 405 has a first radius of curvature.

[0169] like Figure 10As further shown, process 1000 includes performing a second etching operation after the first etching operation to laterally etch the top and bottom ends of the inner surface of the cavity (step 1040). For example, one or more semiconductor processing tools can be used to perform the second etching operation after the first etching operation to laterally etch the top and bottom ends of the inner surface 415 of the cavity 405. In some embodiments, after the second etching operation, the inner surface 415 of the cavity 405 has a second radius of curvature greater than the first radius of curvature.

[0170] like Figure 10 As further shown, process 1000 includes forming an inner spacer in the cavity after performing the first etching operation (step 1050). For example, one or more semiconductor processing tools may be used to form the inner spacer 450 in the cavity 405 after performing the first etching operation.

[0171] like Figure 10 As further shown, process 1000 includes forming a source / drain region in the source / drain recess such that the source / drain region is adjacent to an inner spacer (step 1060). For example, one or more semiconductor processing tools may be used to form a source / drain region 510 in the source / drain recess 305 such that the source / drain region 510 is adjacent to an inner spacer 450.

[0172] Process 1000 may include additional embodiments, such as any single embodiment described below or any combination of embodiments described below and / or in conjunction with one or more processes described elsewhere herein.

[0173] In the first embodiment, the interface between the sacrificial nanostructure layer 120 and the first nanostructure channel 315 includes a silicon-germanium region 130 having a silicon concentration greater than that of the sacrificial nanostructure layer 120 and a silicon region 135 having a germanium concentration greater than that of the first nanostructure channel 315, and the second etching operation includes performing multiple etching cycles to etch the silicon-germanium region 130 and the silicon region 135.

[0174] In the second embodiment, either alone or in combination with the first embodiment, one of the etching cycles includes etching the silicon-germanium region 130 and the silicon region 135 using a gas-based etchant containing a combination of fluorine and ammonia.

[0175] In the third embodiment, alone or in combination with one or more of the first and second embodiments, the etching cycle includes removing etching byproducts resulting from etching the silicon-germanium region 130 and the silicon region 135 from the processing chamber in which the semiconductor device 105 is located.

[0176] In the fourth embodiment, fluorine and ammonia react with silicon in the silicon-germanium region 130 alone or in combination with one or more of the first to third embodiments to form ammonium fluorosilicate ((NH4)2SiF6), wherein the ammonium fluorosilicate protects the sacrificial nanostructure layer 120 from etching during the second etching operation.

[0177] In the fifth embodiment, fluorine and ammonia react with germanium in the sacrificial nanostructure layer 120, alone or in combination with one or more of the first to fourth embodiments, to form ammonium fluorosilicate ((NH4)2SiF6), wherein the ammonium fluorosilicate protects the sacrificial nanostructure layer 120 from etching during the second etching operation.

[0178] even though Figure 10 The illustration depicts example steps of process 1000. In some embodiments, process 1000 is compared to... Figure 10 As shown, steps may include additional steps, fewer steps, different steps, or steps in a different order. Alternatively, two or more steps of process 1000 may be performed in parallel.

[0179] In this way, internal spacers are formed in nanostructured transistors of semiconductor devices in a manner that reduces the likelihood of etching through the internal spacers into adjacent source / drain regions. Specifically, the multi-etch process described herein is performed to form cavities in which the internal spacers are formed. The multi-etch process includes one or more first etch processes to form the cavity, and one or more second etch processes to refine the corners of the cavity to reduce the roundness of the cavity. Because of the second etch operation, the corners of the cavity have sharper sidewalls that intersect with the inner surface (e.g., increased orthogonality). This results in smaller tolerances and improved uniformity of lateral thickness in the subsequently formed internal spacers. The improved uniformity of lateral thickness reduces the likelihood of etching through any portion of the internal spacers during gate replacement operations. Thus, the technique described herein can reduce the likelihood of nanostructured transistor failure and / or improve the yield of nanostructured transistors formed on semiconductor devices.

[0180] As detailed above, a method of manufacturing a semiconductor includes forming a stack of layers comprising a plurality of first nanostructure layers and a plurality of second nanostructure layers overlapping the first nanostructure layers in a direction approximately perpendicular to the substrate over a substrate of a semiconductor device; forming recesses through the stack to form a plurality of nanostructure channels from the second nanostructure layers, wherein a plurality of ends of the first nanostructure layers and a plurality of ends of the nanostructure channels are exposed from the recesses; performing a first etching operation to laterally etch one end of one of the first nanostructure layers through the recesses to form a cavity between the first nanostructure channels and the second nanostructure channels in the plurality of nanostructure channels; performing a second etching operation after the first etching operation to change the contour of the inner surface of the cavity; and forming an inner spacer in the cavity after the first etching operation.

[0181] In one embodiment, the interface between the nanostructure layer and the first nanostructure channel includes a silicon-germanium region having a silicon concentration greater than that of the nanostructure layer and a silicon region having a germanium concentration greater than that of the first nanostructure channel, and the second etching operation includes trimming the silicon-germanium region and the silicon region. In one embodiment, after the first etching operation, the inner surface of the cavity has a first distance between approximately the midpoint of an arc on the inner surface and approximately the midpoint of the base of the arc, and after the second etching operation, the inner surface of the cavity has a second distance between approximately the midpoint of an arc on the inner surface and approximately the midpoint of the base of the arc, wherein the second distance is smaller than the first distance. In one embodiment, the second etching operation flattens the cross-sectional curvature of the inner surface of the cavity. In one embodiment, the second etching operation includes performing the second etching operation using a gas-based etchant comprising a combination of fluorine and ammonia. In one embodiment, the second etching operation includes providing a first gas flow of fluorine into a processing chamber in which the semiconductor device is located, and after the first gas flow stops, providing a second gas flow of ammonia into the processing chamber. In one embodiment, the difference between the width of the nanostructure layer at approximately the midpoint and the width of the nanostructure layer at the bottom is smaller after the second etching operation than before the second etching operation. In one embodiment, after the first etching operation, the inner surface of the cavity has a first angle between approximately the midpoint and the end of the arc of the inner surface, and after the second etching operation, the inner surface of the cavity has a second angle between approximately the midpoint and the end of the arc of the inner surface, wherein the second angle is smaller than the first angle.

[0182] As detailed above, a method for manufacturing a semiconductor device includes forming a stack of layers over a substrate of the semiconductor device, comprising a plurality of sacrificial nanostructure layers and a plurality of nanostructure channel layers overlapping the sacrificial nanostructure layers in a direction approximately perpendicular to the substrate; forming source / drain recesses through the stacked layers to form a plurality of nanostructure channels from the nanostructure channel layers, wherein a plurality of ends of the sacrificial nanostructure layers and a plurality of ends of the nanostructure channels are exposed from the source / drain recesses; performing a first etching operation to laterally etch one end of one of the sacrificial nanostructure layers through the source / drain recesses to form a cavity between a first nanostructure channel and a second nanostructure channel in the nanostructure channels; wherein after the first etching operation, the inner surface of the cavity has a first radius of curvature; after the first etching operation, performing a second etching operation to laterally etch the top and bottom ends of the inner surface of the cavity; wherein after the second etching operation, the inner surface of the cavity has a second radius of curvature greater than the first radius of curvature; and after the second etching operation, forming an inner spacer in the cavity and forming a source / drain region in the source / drain recess, such that the source / drain region is adjacent to the inner spacer.

[0183] In one embodiment, the interface between the sacrificial nanostructure layer and the first nanostructure channel includes a silicon-germanium region having a silicon concentration greater than that of the sacrificial nanostructure layer and a silicon region having a germanium concentration greater than that of the first nanostructure channel, and the second etching operation includes performing multiple etching cycles to etch the silicon-germanium region and the silicon region. In one embodiment, one of the etching cycles includes etching the silicon-germanium region and the silicon region using a gas-based etchant comprising a combination of fluorine and ammonia. In one embodiment, the etching cycle includes removing etching byproducts resulting from etching the silicon-germanium region and the silicon region from a processing chamber in which the semiconductor device is located. In one embodiment, fluorine and ammonia react with silicon in the silicon-germanium region to form ammonium fluorosilicate ((NH4)2SiF6), and wherein the ammonium fluorosilicate protects the sacrificial nanostructure layer from etching in the second etching operation. In one embodiment, fluorine and ammonia react with germanium in the sacrificial nanostructure layer to form ammonium fluorosilicate ((NH4)2SiF6), and wherein the ammonium fluorosilicate protects the sacrificial nanostructure layer from etching in the second etching operation.

[0184] As detailed above, a semiconductor device includes a plurality of nanostructured channels, a plurality of internal spacers, a gate structure, and source / drain regions. The nanostructured channels are located on a substrate, wherein the nanostructured channels are disposed in a direction perpendicular to the substrate, and wherein the nanostructured channels include a first nanostructured channel and a second nanostructured channel located above the first nanostructured channel. Source / drain regions are adjacent to the nanostructured channels. A gate structure surrounds each nanostructured channel, wherein a first portion of the gate structure below the first nanostructured channel has a first width at approximately the center of the first portion, wherein a second portion of the gate structure between the first and second nanostructured channels has a second width at approximately the center of the second portion, and wherein the difference between the second width and a third width at the top of the second portion is less than the difference between the first width and the second width. Internal spacers are located between the source / drain regions and the gate structure, wherein one of the internal spacers is located between the first and second nanostructured channels. According to an embodiment of this disclosure, a semiconductor device includes a plurality of nanostructured channels, a plurality of internal spacers, a gate structure, and source / drain regions. A nanostructured channel is located on a substrate, wherein the nanostructured channel includes a first nanostructured channel and a second nanostructured channel located above the first nanostructured channel. Source / drain regions are adjacent to the nanostructured channels. A gate structure surrounds each nanostructured channel, wherein a first portion of the gate structure below the first nanostructured channel has a first width at approximately the center of the first portion, wherein a second portion of the gate structure between the first and second nanostructured channels has a second width at approximately the center of the second portion, and wherein the difference between the second width and a third width at the top of the second portion is less than the difference between the first and second widths. The difference between the second and third widths is less than the thickness of the second nanostructured channel. Inner spacers are located between the source / drain regions and the gate structure, wherein one of the inner spacers is located between the first and second nanostructured channels. According to an embodiment of this disclosure, a semiconductor device includes a plurality of nanostructured channels, a plurality of inner spacers, a gate structure, and source / drain regions. The nanostructured channels are located on a substrate, wherein the nanostructured channels are disposed in a direction perpendicular to the substrate, and wherein the nanostructured channels include a first nanostructured channel and a second nanostructured channel located above the first nanostructured channel. The source / drain regions are adjacent to the nanostructure channels. A gate structure surrounds each of the nanostructure channels, wherein a first portion of the gate structure under the first nanostructure channel has a first width at approximately the center of the first portion, wherein a second portion of the gate structure between the first and second nanostructure channels has a second width at approximately the center of the second portion, and wherein the difference between the second width and a third width at the top of the second portion is less than the thickness of the second nanostructure channel. An inner spacer is located between the source / drain regions and the gate structure, wherein one of the inner spacers is located between the first and second nanostructure channels.

[0185] In one embodiment, the difference between the second width and the third width is less than about 3 nanometers. In one embodiment, the difference between the first width and the second width is less than about 6 nanometers. In one embodiment, the difference between the second width and the third width is less than the thickness of the second nanostructure channel. In one embodiment, the difference between the fourth width located approximately at the center of the inner spacer and the fifth width located at the top of the inner spacer is in the range of about 0.5 nanometers to about 1.5 nanometers. In one embodiment, a semiconductor device further includes a silicon region located between the first nanostructure channel and the inner spacer, wherein the inner spacer extends into a portion of the silicon region.

[0186] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other methods and structures for achieving the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a plurality of nanostructure channels on a substrate, wherein the plurality of nanostructure channels are disposed along a direction perpendicular to the substrate, and wherein the plurality of nanostructure channels comprise a first nanostructure channel and a second nanostructure channel over the first nanostructure channel; a source / drain region adjacent to the plurality of nanostructure channels; a gate structure surrounding each of the plurality of nanostructure channels, wherein a first portion of the gate structure under the first nanostructure channel has a first width at about a center of the first portion, wherein a second portion of the gate structure between the first nanostructure channel and the second nanostructure channel has a second width at about a center of the second portion, and wherein a difference between the second width and a third width at a top of the second portion is less than a difference between the first width and the second width, and wherein a difference between the second width and a third width at a top of the second portion is less than a thickness of the second nanostructure channel; and a plurality of inner spacers between the source / drain region and the gate structure, 2. The semiconductor device according to claim 1, wherein wherein one of the plurality of inner spacers is between the first nanostructure channel and the second nanostructure channel.

3. The semiconductor device according to claim 2, wherein The difference between the second width and the third width is less than 3 nanometers.

4. The semiconductor device according to claim 1, wherein The difference between the first width and the second width is less than 6 nanometers.

5. The semiconductor device according to claim 1, wherein The difference between the second width and the third width is less than a thickness of the second nanostructure channel.

6. The semiconductor device according to claim 1, wherein A difference between a fourth width at about a center of the inner spacer and a fifth width at a top of the inner spacer is included in a range from 0.5 nanometers to 1.5 nanometers. Further comprising: a silicon region between the first nanostructure channel and the inner spacer, 7. A semiconductor device, characterized by comprising: wherein the inner spacer extends into a portion of the silicon region. Comprising: a plurality of nanostructure channels on a substrate, wherein the plurality of nanostructure channels comprise a first nanostructure channel and a second nanostructure channel over the first nanostructure channel; a source / drain region adjacent to the plurality of nanostructure channels; a gate structure surrounding each of the plurality of nanostructure channels, wherein a first portion of the gate structure under the first nanostructure channel has a first width at about a center of the first portion, wherein a second portion of the gate structure between the first nanostructure channel and the second nanostructure channel has a second width at about a center of the second portion, and wherein a difference between the second width and a third width at a top of the second portion is less than a difference between the first width and the second width, and a difference between the second width and the third width is less than a thickness of the second nanostructure channel; and a plurality of inner spacers between the source / drain region and the gate structure, 8. The semiconductor device according to claim 7, wherein wherein one of the plurality of inner spacers is between the first nanostructure channel and the second nanostructure channel.

9. A semiconductor device, characterized by comprising: A difference between a fourth width at about a center of the inner spacer and a fifth width at a top of the inner spacer is included in a range from 0.5 nanometers to 1.5 nanometers. Comprising: a plurality of nanostructure channels on a substrate, wherein the plurality of nanostructure channels are disposed along a direction perpendicular to the substrate, and wherein the plurality of nanostructure channels comprise a first nanostructure channel and a second nanostructure channel over the first nanostructure channel; wherein the plurality of nanostructure channels includes a first nanostructure channel and a second nanostructure channel positioned above the first nanostructure channel; a source / drain region adjacent to the plurality of nanostructure channels; a gate structure surrounding each of the plurality of nanostructure channels, wherein a first portion of the gate structure under the first nanostructure channel has a first width at about a center of the first portion, wherein a second portion of the gate structure between the first nanostructure channel and the second nanostructure channel has a second width at about a center of the second portion, and wherein a difference between the second width and a third width at a top of the second portion is less than a thickness of the second nanostructure channel; and a plurality of inner spacers between the source / drain region and the gate structure, wherein one of the plurality of inner spacers is between the first nanostructure channel and the second nanostructure channel.

10. The semiconductor device according to claim 9, wherein further comprising: a silicon region between the first nanostructure channel and the inner spacer, wherein the inner spacer extends into a portion of the silicon region.

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