Semiconductor device including vertical channel

Abstract

The utility model provides a semiconductor assembly which comprises a memory unit structure. The memory unit structure comprises a transistor structure and a storage structure. The gate of the transistor structure extends in a direction substantially perpendicular to the substrate surface of the semiconductor component, which enables the gate length to increase without increasing or minimizing the horizontal or lateral dimensions of the memory cell structure. The channel layer may be a U-shaped layer in that the channel layer is included on at least two of a sidewall and a bottom surface of the gate. This design increases the channel area of the transistor structure, enabling low current leakage of the memory cell structure, and enabling high lateral density of the memory cell structure in the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device including a vertical channel. BACKGROUND

[0002] Non-volatile memory cells are a type of memory cell that can include a transistor connected in series with a memory element, such as a capacitor, a phase change material layer, a resistive layer, and / or a magnetic layer. This can be referred to as a transistor-one memory element (1T-1X) cell. The memory element in a 1T-1X cell selectively stores data (e.g., a logic value of "1" or a logic value of "0") based on charge, resistivity, capacitance, and / or magnetic field. The state of the memory element can be selectively modified and / or read by using the transistor to charge or discharge the memory element. SUMMARY

[0003] One embodiment of the present application provides a semiconductor device. The semiconductor component includes a plurality of backside dielectric layers. The semiconductor component includes a memory cell structure located in the plurality of backside dielectric layers. The memory cell structure includes a storage structure and a transistor structure located above the storage structure. The transistor structure includes a first source / drain region, a second source / drain region located above the first source / drain region, a gate, and a channel layer. The gate extends between the first source / drain region and the second source / drain region. The channel layer extends between the first source / drain region and the second source / drain region. The channel layer is located on at least two sides of the gate and below a bottom surface of the gate.

[0004] Another embodiment of the present application provides a semiconductor device. The semiconductor component includes a plurality of backside dielectric layers. The semiconductor component includes a memory cell structure located in the plurality of backside dielectric layers, and the memory cell structure includes a storage structure. The memory cell structure includes a first source / drain region. The memory cell structure includes a second source / drain region located above the first source / drain region. The memory cell structure includes a gate having an extended shape in a direction substantially perpendicular to the plurality of backside dielectric layers. The first source / drain region is located below a bottom surface of the gate. The second source / drain region is located adjacent to opposing sidewalls of the gate. The memory cell structure includes a channel layer located on at least two sides of the gate and below a bottom surface of the gate. The first source / drain region contacts a bottom section of the channel layer located between the bottom surface of the gate and the first source / drain region. The second source / drain region contacts a sidewall section of the channel layer located between the sidewalls of the gate and the second source / drain region. BRIEF DESCRIPTION OF DRAWINGS

[0005] The aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the components are not drawn to scale. In practice, the dimensions of the various components can be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 This is a diagram of an example environment that implements the systems and / or methods described in this disclosure.

[0007] Figures 2A to 2C This is a diagram of an exemplary semiconductor component described in this disclosure.

[0008] Figures 3A to 3D This is a diagram of an example embodiment of the memory cell structure disclosed herein.

[0009] Figures 4A to 4X This is a diagram of an example embodiment forming the memory cell structure described in this disclosure.

[0010] Figure 5A and Figure 5B This is a diagram of an example embodiment of the memory cell structure disclosed herein.

[0011] Figures 6A to 6F This is a diagram of an example embodiment forming the memory cell structure described in this disclosure.

[0012] Figure 7A and Figure 7B This is a diagram of an example embodiment of the memory cell structure described in this disclosure.

[0013] Figures 8A to 8D This is a diagram of an example embodiment forming the memory cell structure described in this disclosure.

[0014] Figure 9A and Figure 9B This is a diagram of an example embodiment of the memory cell structure described in this disclosure.

[0015] Figures 10A to 10D This is a diagram of an example embodiment forming the memory cell structure described in this disclosure.

[0016] Figure 11 This is a diagram of an example component or component of the component described in this disclosure.

[0017] Figure 12 This is a flowchart of an exemplary process related to forming the memory cell structure described in this disclosure.

[0018] [Icon Symbol Explanation]

[0019] 100: Example Environment

[0020] 102: Sedimentation Tools

[0021] 104: exposure tool

[0022] 106: development tool

[0023] 108: etch tool

[0024] 110: planarization tool

[0025] 112: plating tool

[0026] 114: wafer / die transport tool

[0027] 200: semiconductor assembly

[0028] 202: memory cell structure

[0029] 204: storage structure

[0030] 206, 208, 210: source / drain regions

[0031] 212: channel layer

[0032] 212a, 212b: sidewall segments

[0033] 212c: bottom segment

[0034] 214: gate

[0035] 216: gate dielectric layer

[0036] 216a, 216b, 216c: portions

[0037] 218, 224, 226: source / drain interconnects

[0038] 220: word line conductive structure

[0039] 222: bit line conductive structure

[0040] 228, 232, 236, 240, 244, 246: dielectric layers

[0041] 230, 234, 238, 242: etch stop layers

[0042] 248, 250, 254, 256, 258, 260, 262, 406: liner layers

[0043] 252: transistor structure

[0044] 300, 400, 500, 600, 700, 800, 900, 1000: example embodiments

[0045] 402, 408, 602, 802, 1002: recesses

[0046] 404, 412: electrically conductive layer

[0047] 410: sacrificial layer

[0048] 702, 704: diffusion barrier layer

[0049] 1100: assembly

[0050] 1110: bus

[0051] 1120: processor

[0052] 1130: memory

[0053] 1140: input member

[0054] 1150: output member

[0055] 1160: communication member

[0056] 1200: process

[0057] 1210, 1220, 1230, 1240, 1250, 1260, 1270, 1280: block

[0058] A-A, B-B: section line

[0059] D1, D2, D3, D4, D5: dimension DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments, or examples, for implementing different features of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first member formed above or over a second member can include embodiments in which the first and second members are formed in direct contact with each other, and can also include embodiments in which an additional member can be formed between the first and second members such that the first and second members can not be in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0061] In addition, for ease of description, spatially relative terms, such as "beneath", "below", "lower", "over", "upper" and the like, can be used herein for the purpose of illustrating one (some) component or feature's relationship to another component(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0062] In the event that power is not applied for a long period of time, a memory component of a memory cell structure (e.g., a 1T-1X memory cell structure) can be configured to store data. Current leakage through a transistor of the memory cell structure can have a negative impact on the ability of the memory component over a long period of time. For example, if the memory component is implemented by a capacitor, current leakage through the transistor can cause the charge stored in the capacitor to dissipate, resulting in loss of data. Thus, the memory component can need to be periodically "refreshed" (e.g., the charge stored in the memory component can need to be replenished) to prevent loss of data. This increases power consumption of the memory cell structure, thereby reducing the power efficiency of the memory cell structure. Increasing the gate length of the transistor can reduce current leakage through the transistor, but at the cost of reducing the memory cell density in a semiconductor component in which the memory cell structure is included.

[0063] In some examples described herein, a semiconductor component includes a memory cell structure (e.g., a 1T-1X memory cell structure) and the memory cell structure includes a storage structure corresponding to a memory component of the memory cell structure and a transistor structure. The gate of the transistor structure extends in a vertical direction in the semiconductor component (e.g., a z-direction that is substantially perpendicular to a surface of a substrate of the semiconductor component), which enables increasing the size of the gate length with minimal or no increase in the horizontal or lateral size (e.g., x-y direction) of the memory cell structure. The channel layer can be a U-shaped channel layer, in which the channel layer is included on at least two sidewalls of the gate to be on the bottom surface of the gate. This increases the channel area of the transistor structure, enabling low current leakage of the memory cell structure and enabling high horizontal or lateral density of the memory cell structure in a semiconductor device. The low current leakage of the memory cell structure enables longer retention time between refreshes of data stored in the storage structure of the memory cell structure, which reduces power consumption of the memory cell structure and improves the power efficiency of the memory cell structure.

[0064] Figure 1 FIG. 1 is a diagram of an example environment in which systems and / or methods described herein can be implemented. Figure 1As shown, the example environment 100 can include a plurality of semiconductor processing tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102-112 can include a deposition tool 102, an exposure tool 104, a development tool 106, an etch tool 108, a planarization tool 110, a plating tool 112, and / or another type of semiconductor processing tool. In other examples, the tools included in the example environment 100 can be included in a semiconductor cleanroom, a semiconductor foundry, a semiconductor processing facility, and / or a semiconductor manufacturing facility.

[0065] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more components capable of depositing various types of materials on a substrate. In some examples, the deposition tool 102 includes a spin-on tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some examples, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some examples, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some examples, the deposition tool 102 includes an epitaxy tool configured to form layers and / or regions in a component through epitaxial growth. In some examples, the example environment 100 includes multiple types of deposition tools 102.

[0066] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer with a radiation source, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray light source, an e-beam light source, and / or the like. The exposure tool 104 can use the radiation source to expose the photoresist layer to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor component layer patterns for forming one or more semiconductor components, can include a pattern for forming one or more structures of a semiconductor component, can include a pattern for etching various portions of a semiconductor component, and / or the like. In some examples, the exposure tool 104 includes a scanner, a stepper, or another type of exposure tool.

[0067] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed by a radiation source such that the pattern transferred from the exposure tool 104 to the photoresist layer is developed. In some examples, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some examples, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some examples, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0068] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some examples, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a particular duration to remove a particular amount of one or more portions of the substrate. In some examples, the etching tool 108 can use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which can involve using ionized gas to isotropically or directionally etch the one or more portions.

[0069] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 can include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool capable of polishing or planarizing a layer or surface in a deposited material or plated material. The planarization tool 110 can employ a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize a surface of a semiconductor component. The planarization tool 110 can use a polishing pad and a retaining ring (e.g., typically larger in diameter than the semiconductor component) with a polishing and corrosive chemical slurry. The polishing pad and semiconductor component can be pressed together by a dynamic polishing head, and secured in position by the retaining ring. The dynamic polishing head can be rotated on different axes of rotation to remove material and level any irregularities of the semiconductor component, thereby leveling or planarizing the semiconductor component.

[0070] The plating tool 112 is a semiconductor processing tool capable of electroplating one or more metals on a substrate (e.g., a wafer, a semiconductor component, and / or the like) or a portion of a substrate. For example, the plating tool 112 can include a copper plating assembly, an aluminum plating assembly, a nickel plating assembly, a tin plating assembly, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating assembly, and / or a plating assembly for one or more other types of conductive materials, metals, and / or the like.

[0071] The wafer / die transport tools 114 include mobile robots, robot arms, trams or rail cars, overhead hoist transport (OHT) systems, automated materially handling systems (AMHS), and / or other types of components configured to transport substrates and / or semiconductor components between the semiconductor processing tools 102-112, between processing chambers of the same semiconductor processing tool, and / or to and from other locations such as wafer racks, storage rooms, and / or the like. In some examples, the wafer / die transport tools 114 can be programmed components configured to travel a particular path, and / or can be semi-autonomously or autonomously operated components. In some examples, the example environment 100 includes multiple wafer / die transport tools 114.

[0072] For example, in other examples, the wafer / die transport tools 114 can be included in a cluster tool or other type of tool that includes multiple processing chambers, and the wafer / die transport tools 114 can be configured to transport substrates and / or semiconductor components between the multiple processing chambers, between a processing chamber and a buffer area, between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)). In some examples, the wafer / die transport tools 114 can be included in a multi-chamber (or multi-cluster) deposition tool 102, which can include a pre-clean processing chamber (e.g., to clean or remove oxides, oxidation, and / or other types of contamination or byproducts from substrates and / or semiconductor components) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these examples, the wafer / die transport tools 114 are configured to transport substrates and / or semiconductor components between the processing chambers of the deposition tool 102 without breaking or removing a vacuum (or at least a partial vacuum) between the processing chambers and / or between processing operations in the deposition tool 102, as described herein.

[0073] In some instances, one or more of semiconductor processing tools 102-112 and / or wafer / die transport tool 114 may be used to perform one or more semiconductor processing operations as described in this disclosure. For example, in other instances, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may be used to form a first source / drain region of a memory cell structure in a semiconductor assembly; form a plurality of dielectric layers on the first source / drain region; form a first source / drain interconnect and a second source / drain interconnect in the plurality of dielectric layers; form a conductive layer on the plurality of dielectric layers and on the first source / drain interconnect and the second source / drain interconnect; form a recess between the first source / drain interconnect and the second source / drain interconnect in the plurality of dielectric layers and through the conductive layer, wherein forming the recess through the conductive layer results in the formation of a second source / drain region above the first source / drain interconnect and a third source / drain region above the second source / drain interconnect; form a channel layer on the sidewalls and bottom surface of the recess; form a gate dielectric layer on the channel layer in the recess; and / or form a gate on the gate dielectric layer. In some instances, one or more of semiconductor processing tools 102-112 and / or wafer / die transport tool 114 may be used to perform the following: Figures 4A to 4X , Figures 6A to 6F , Figures 8A to 8D , Figures 10A to 10D and / or Figure 12 One or more semiconductor processing operations described herein.

[0074] Figure 1 The number and arrangement of components shown are provided only as one or more examples. In reality, with... Figure 1 Compared to the components shown, there may be additional components, fewer components, different components, or components arranged differently. Furthermore, Figure 1 The two or more components shown can be implemented in a single component, or Figure 1 The single component shown can be implemented as multiple and distributed components. Alternatively, a set of components (e.g., one or more components) of example environment 100 may perform one or more functions performed by another set of components of example environment 100.

[0075] Figures 2A to 2C This is a diagram of an exemplary semiconductor component 200 described in this disclosure. The semiconductor component 200 may include a semiconductor memory component or another type of semiconductor component including one or more memory cell structures 202. In some instances, the semiconductor component 200 includes a plurality of memory cell structures 202 arranged in a grid-like array of memory cells. Each memory cell structure 202 may correspond to a 1T-1X memory cell in the memory cell array.

[0076] Figure 2A A perspective view of a memory cell structure 202 is illustrated. The memory cell structure 202 includes a storage structure 204 coupled with a transistor structure. The storage structure 204 includes a capacitor structure (e.g., a deep trench capacitor (DTC) structure, a thin film capacitor structure), a ferroelectric storage structure, a resistive storage structure, a phase change material storage structure, and / or another type of storage structure that can be configured to correspond to two or more states of two or more logical values.

[0077] The storage structure 204 is electrically coupled with a source / drain region 206 of the memory cell structure 202. Depending on the context, a “source / drain region” can refer to a source or a drain, alone or collectively. The source / drain region 206 is located above the storage structure 204, such that the storage structure and the source / drain region 206 are vertically aligned along a z-direction in the semiconductor assembly 200. The z-direction can be substantially perpendicular to a substrate and / or one or more backend dielectric layers of the semiconductor assembly 200.

[0078] The memory cell structure 202 also includes one or more source / drain regions 208 and / or 210 located above the source / drain region 206 in the z-direction. A channel layer 212 of the memory cell structure 202 is located between the gate 214 and the source / drain regions 208 and / or 210. The source / drain regions 208 and 210 are located at sidewalls of the gate 214, while the sidewalls are located at opposite sides of the gate 214, and the source / drain region 206 is located below a bottom surface of the gate 214.

[0079] The gate 214 includes an elongated structure in the z-direction. The gate 214 extends in the z-direction between the source / drain region 206 and the source / drain region 208 (and / or between the source / drain region 206 and the source / drain region 210), and thus can be referred to as a vertical gate. The channel layer 212 can be a U-shaped layer, such that the channel layer 212 is located on two or more sidewalls of the gate 214 and on a bottom surface of the gate 214. The U-shaped channel layer 212 forms a U-shaped channel through which current flows between the source / drain region 206 and the source / drain region 208 and between the source / drain region 206 and the source / drain region 210, while minimizing current flow in other directions. This design increases the efficiency of the memory cell structure 202 and reduces current leakage of the memory cell structure 202.

[0080] The channel extends in the z-direction between the source / drain region 206 and the source / drain region 208, and / or between the source / drain region 206 and the source / drain region 210. Thus, the gate length and the channel length of the transistor in the memory cell structure 202 refer to their dimensions in the z-direction. The source / drain regions 208 and 210 are in direct physical contact with portions of the channel layer 212 that are located on the sidewalls of the gate 214. The source / drain region 206 is in direct physical contact with a portion of the channel layer 212 that is located below the bottom surface of the gate 214.

[0081] The memory cell structure 202 also includes a gate dielectric layer 216. The gate dielectric layer 216 is located between the channel layer 212 and the gate 214. Portions 216a of the gate dielectric layer 216 are arranged in a similar manner as the channel layer 212. For example, the portions 216a of the gate dielectric layer 216 are U-shaped layers. The portions 216a of the gate dielectric layer 216 are located between the gate 214 and the source / drain regions 208 and 210. The portions 216a of the gate dielectric layer 216 are also located below the bottom surface of the gate 214, such that the portions 216a of the gate dielectric layer 216 are located between the bottom surface of the gate 214 and the source / drain region 206.

[0082] The gate dielectric layer 216 further includes portions 216b that extend in the x-y plane in the semiconductor assembly 200, such that the portions 216b of the gate dielectric layer 216 are located above the top surfaces of the source / drain regions 208 and / or 210. The portions 216b of the gate dielectric layer 216 are in direct physical contact with the top surfaces of the source / drain regions 208 and / or 210. The portions 216b of the gate dielectric layer 216 extend laterally outward from the portions 216a of the gate dielectric layer 216, and can extend in the x-direction across multiple memory cell structures 202, as shown in the example of Figure 2A

[0083] The memory cell structure 202 includes a source / drain interconnect line 218 that is electrically coupled with the storage structure 204 and the source / drain region 206. The source / drain interconnect line 218 can include a via, a pillar, a column, and / or another type of extension structure that extends in the z-direction.

[0084] The gate 214 can be electrically and / or physically coupled with a word line conductive structure 220 of the semiconductor assembly 200. In some examples, the word line conductive structure 220 extends in the y-direction in the semiconductor assembly 200, which is substantially perpendicular to the x-direction and the z-direction. Additionally and / or alternatively, the word line conductive structure 220 extends in the x-direction. The word line conductive structure 220 can include a metal layer, a trench, a conductive trace, and / or another type of conductive structure.

[0085] ​Source / drain regions 208 and / or 210 may be electrically coupled to bit line conductive structure 222 via source / drain interconnects 224 and / or source / drain interconnects 226, respectively. Source / drain interconnects 224 and 226 may each include vias, pillars, columns, and / or other types of extension structures extending in the z-direction. Bit line conductive structure 222 extends in the x-direction of semiconductor component 200. Additionally and / or alternatively, bit line conductive structure 222 extends in the y-direction. Bit line conductive structure 222 may include metal layers, trenches, conductive traces, and / or other types of conductive structures. Character line conductive structure 220 and bit line conductive structure 222 may each be coupled to circuitry, including control circuitry, read buffers, write buffers, and / or other types of circuitry within semiconductor component 200.

[0086] Figure 2B The memory cell structure 202 is illustrated along... Figure 2A The cross-sectional view shows section AA, which is located at the center of gate 214. Figure 2B As shown, the memory cell structure 202 may be contained within a plurality of back-end dielectric layers of the semiconductor component 200. These plurality of back-end dielectric layers may be located in the back-end of line (BEOL) region of the semiconductor component 200. In some instances, the memory cell structure 202 may be located in another region of the semiconductor component 200, such as the front-end of line (FEOL) region of the semiconductor component 200.

[0087] The aforementioned plurality of back-end dielectric layers may include dielectric layer 228, an etchstop layer (ESL) 230 above dielectric layer 228, dielectric layer 232 above ESL 230, ESL 234 above dielectric layer 232, dielectric layer 236 above ESL 234, ESL 238 above dielectric layer 236, dielectric layer 240 above ESL 238, ESL 242 above dielectric layer 240, dielectric layer 244 above ESL 242, and / or dielectric layer 246 above dielectric layer 244. Dielectric layers 228, 232, 240, 244, 246, ESL 230, ESL 234, ESL 238, and ESL 242 may each include one or more dielectric materials. Examples of dielectric materials include oxides, nitrides, and silicon oxide (SiO2). x ), silicon nitride (Si x N y), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low-k dielectric materials (e.g., dielectric materials having a dielectric constant less than 3.9), high-k dielectric materials (e.g., dielectric materials having a dielectric constant greater than 3.9), and / or other suitable dielectric materials.

[0088] The storage structure 204 can be included in the dielectric layer 228 and can extend through the ESL 230. In other examples, the source / drain interconnect 218 can be coupled with a top surface of the storage structure 204 and can extend through the dielectric layer 232, the ESL 234, and / or the dielectric layer 236. The source / drain interconnect 218 can include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys thereof, and / or combinations of the foregoing materials.

[0089] One or more liners 248 can be included between the source / drain interconnect 218 and the dielectric layer 232, the dielectric layer 236, and the ESL 234. The liners 248 can include adhesion liners (e.g., liners included to promote adhesion between the source / drain interconnect 218 and surrounding layers), barrier layers (e.g., barrier layers included to reduce or minimize diffusion of the material of the source / drain interconnect 218 into surrounding layers), and / or other types of liners. Example materials for the liners 248 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0090] The source / drain region 206 can be located on the source / drain interconnect 218 such that the source / drain region 206 is electrically and / or physically coupled with the source / drain interconnect 218. The source / drain region 206 can be located in the dielectric layer 240 and can extend through the ESL 238. The source / drain region 206 can include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al), among others.

[0091] One or more liners 250 can be located between the source / drain region 206 and the dielectric layer 240 and / or the ESL 238. The liners 250 can include barrier liners that prevent migration of material from the source / drain region 206 into surrounding layers, adhesion layers that promote adhesion between the source / drain region 206 and surrounding layers, and / or other types of liners. Examples of the liners 250 include tantalum nitride (TaN), titanium nitride (TiN), and / or other suitable liners, among others.

[0092] The gate 214 extends through the dielectric layer 244, through the ESL 242, and / or through the dielectric layer 240. The gate 214 is located over the source / drain region 206. The gate 214 can include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al), among others. The channel layer 212 and portions 216a of the gate dielectric layer are included between the gate 214 and the dielectric layer 240, the gate 214 and the ESL 242, the gate 214 and the dielectric layer 244, and / or the gate 214 and the source / drain region 206. Portions 216b of the gate dielectric layer 216 can be included between the dielectric layer 244 and the dielectric layer 246.

[0093] In some examples, the channel layer 212 includes a semiconductor material, such as silicon (Si), among others. In some examples, the channel layer 212 can include one or more metal oxide materials or metal oxide semiconductor materials. In some examples, the channel layer 212 is an n-type channel that includes tin oxide (SnO x , such as SnO2), indium oxide (In x O y , such as In2O3), zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO or IGZO), indium tin oxide (ITO), and / or another n-type metal oxide material. In some examples, the channel layer 212 is a p-type channel that includes nickel oxide (NiO), copper oxide (Cu x O, such as Cu2O), copper aluminum oxide (CuAlO x , such as CuAlO2), copper gallium oxide (CuGaO x , such as CuGaO2), copper indium oxide (CuInO x , such as CuInO2), strontium copper oxide (SrCu x O y , such as SrCu2O2), tin oxide (SnO), and / or another p-type metal oxide material.

[0094] The gate dielectric layer 216 can include one or more dielectric materials, such as hafnium oxide (HfO x , such as HfO2), silicon oxide (SiO x , such as SiO2), aluminum oxide (Al x O y , such as Al2O3), zirconium oxide (Zr x O y ), titanium oxide (Ti x O y ), and / or silicon oxynitride (SiON), among others.

[0095] The source / drain region 206, gate 214, channel layer 212, and gate dielectric layer 216 may be part of the transistor structure 252 of the memory cell structure 202. The source / drain region 206 of the transistor structure 252 (e.g., through the source / drain interconnect 218) is electrically coupled to the storage structure 204 of the memory cell structure 202. The storage structure 204 is located below the transistor structure 252 in the z-direction.

[0096] The gate 214 of transistor structure 252 is electrically and / or physically coupled to a character line conductive structure 220 located above transistor structure 252 in the z-direction. The character line conductive structure 220 may be located in dielectric layer 246 and may be located on the top surface of gate 214. The character line conductive structure 220 may include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys of the foregoing materials, and / or combinations of the foregoing materials.

[0097] Figure 2C The memory cell structure 202 is illustrated along... Figure 2A The cross-sectional view of section BB in the figure shows section BB adjacent to the side of gate 214. (See figure) Figure 2C As shown, transistor structure 252 further includes source / drain regions 208 and / or source / drain regions 210. Source / drain regions 208 and 210 may be located in dielectric layer 244 and may be electrically coupled to bit line conductive structure 222 via source / drain interconnects 224 and 226, respectively. Source / drain regions 208 and / or 210 may be in direct physical contact with channel layer 212 located on opposite sidewalls of gate 214. A portion 216b of gate dielectric layer 216 may be in direct physical contact with the top surface of source / drain regions 208 and / or 210. In some embodiments, source / drain regions 210 and source / drain interconnects 226 are omitted from memory cell structure 202. The source / drain regions 208 and / or 210 may each include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al).

[0098] The source / drain interconnect lines 224 and 226 can be located in and can extend through the ESLs 234, 238, and 242, and the dielectric layers 236, 240, and 242. The source / drain interconnect lines 224 and 226 can each include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys of the foregoing materials, and / or combinations of the foregoing materials.

[0099] The bit line conductive structures 222 can be located in and / or on the dielectric layer 232. The bit line conductive structures 222 can include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), alloys of the foregoing materials, and / or combinations of the foregoing materials.

[0100] One or more liners 254 can be included between the bit line conductive structures 222 and the dielectric layer 232. The liners 254 can include adhesion liners (e.g., liners included to promote adhesion between the bit line conductive structures 222 and surrounding layers), barrier layers (e.g., barrier layers included to reduce or minimize diffusion of the material of the bit line conductive structures 222 into surrounding layers), and / or other types of liners. Examples of materials for the liners 250 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0101] One or more liners 256 can be included between the source / drain interconnect lines 224 and the dielectric layers 236 and / or 240, and / or between the source / drain interconnect lines 224 and the ESLs 234, 238, and / or 242. The liners 256 can include adhesion liners (e.g., adhesion liners included to promote adhesion between the source / drain interconnect lines 224 and surrounding layers), barrier layers (e.g., barrier layers included to reduce or minimize diffusion of the material of the source / drain interconnect lines 224 into surrounding layers), and / or other types of liners. Examples of materials for the liners 256 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0102] One or more liners 258 can be included between the source / drain interconnects 226 and the dielectric layers 236 and / or 240, and / or between the source / drain interconnects 226 and the ESLs 234, 238 and / or 242. The liners 258 can include adhesion liners (e.g., liner layers included to promote adhesion between the source / drain interconnects 226 and surrounding layers), barrier layers (e.g., barrier layers included to reduce or minimize diffusion of the material of the source / drain interconnects 226 to surrounding layers), and / or other types of liners. Examples of materials for the liners 258 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0103] One or more liners 260 can be included between the source / drain regions 208 and the dielectric layer 244, and / or between the source / drain regions 208 and the ESL 242. The liners 260 can include adhesion liners (e.g., liner layers included to promote adhesion between the source / drain regions 208 and surrounding layers), barrier layers (e.g., barrier layers included to reduce or minimize diffusion of the material of the source / drain regions 208 to surrounding layers), and / or other types of liners. Examples of materials for the liners 260 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0104] One or more liners 262 can be included between the source / drain regions 210 and the dielectric layer 244, and / or between the source / drain regions 210 and the ESL 242. The liners 262 can include adhesion liners (e.g., liner layers included to promote adhesion between the source / drain regions 210 and surrounding layers), barrier layers (e.g., barrier layers included to reduce or minimize diffusion of the material of the source / drain regions 210 to surrounding layers), and / or other types of liners. Examples of materials for the liners 262 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0105] As described above, the memory cell structure 202 is provided Figures 2A to 2C As an example. Other examples can differ with respect to the Figures 2A to 2C described above in relation to the memory cell structure 202.

[0106] Figures 3A to 3D is a diagram of an example embodiment 300 of the memory cell structure 202 described herein. Figure 3A is a perspective view of the example embodiment 300 of the memory cell structure 202. Figure 3B is a cross-sectional view of the example embodiment 300 of the memory cell structure 202 along the cross-sectional line A-A in Figure 3A through the center of the gate 214 of the memory cell structure 202.

[0107] As described above, the memory cell structure 202 is provided Figure 3AAs shown, gate 214 includes an extension structure extending in the z-direction. Gate 214 extends in the z-direction between source / drain regions 206 and 208 (and / or between source / drain regions 206 and 210), and is therefore referred to as a vertical gate. Gate 214 may include an approximately rectangular prism shape. Channel layer 212 is included on the sidewalls of gate 214 between gate 214 and source / drain regions 208 and 210 to form an approximately U-shaped channel.

[0108] like Figure 3B As shown, the U-shaped layer of channel layer 212 includes a sidewall segment 212a extending in the z-direction between source / drain region 206 and source / drain region 208, a sidewall segment 212b extending in the z-direction between source / drain region 206 and source / drain region 210, and a bottom segment 212c located between the bottom surface of gate 214 and source / drain region 206. Sidewall segments 212a and 212b are connected to the opposite ends of bottom segment 212c to form a U-shaped layer. By increasing the length of sidewall segments 212a and 212b in the z-direction of channel layer 212, the channel length (Lg, in) of the transistor in memory cell structure 202 is increased. Figure 3B The dimension D1 can be increased in the z direction without (or with minimal) increasing the dimensions of the memory cell structure 202 in the x and / or y directions.

[0109] In some instances, the channel length (dimension D1 in the z-direction) is between approximately 25 nanometers and approximately 50 nanometers. Choosing a channel length less than approximately 25 nanometers may result in a drop in the threshold voltage, which could lead to increased leakage of the transistors in the memory cell structure 202. Choosing a channel length greater than approximately 50 nanometers may result in insufficient drive current to program and / or erase the memory structure 204. If the channel length is between approximately 25 nanometers and approximately 50 nanometers, low current leakage of the transistors can be achieved without sacrificing the drive current used for programming and / or erasing the memory structure 204. However, other channel lengths, as well as channel lengths beyond approximately 25 nanometers to approximately 50 nanometers, are also within the scope of this disclosure.

[0110] like Figure 3BFurther shown, another example dimension D2 of the memory cell structure 202 includes a width of the gate 214 in the x-direction (or y-direction). In some examples, the dimension D2 is at least about 30 nanometers, and the dimension D2 is no greater than a distance between the sidewall segment 212a and the sidewall segment 212b of the channel layer 212. If the dimension D2 is less than about 30 nanometers, voids can occur in the gate 214 due to insufficient gap fill performance at the time of forming the gate 214. However, other values or ranges of the dimension D2 are within the scope of the present disclosure.

[0111] As Figure 3B Further shown in FIG. 2B, another example dimension D3 of the memory cell structure 202 includes a thickness of the gate 214 in the z-direction. In some examples, the dimension D3 is between about 40 nanometers and about 85 nanometers. If the dimension D3 is less than about 40 nanometers, the word line conductive structure 220 can not land on the gate 214. If the dimension D3 is greater than about 85 nanometers, voids can occur in the gate 214 due to insufficient gap fill performance at the time of forming the gate 214. If the dimension D3 is between about 40 nanometers and about 85 nanometers, the word line conductive structure 220 can be formed on the gate 214 while reducing the likelihood of voids in the gate 214. However, other values of the dimension D3 and channel lengths outside of about 40 nanometers and about 85 nanometers are within the scope of the present disclosure.

[0112] Other example dimensions of the memory cell structure 202 include a thickness of the source / drain regions 208 and / or 210 in the z-direction to an extension distance of the gate 214 over the portion 216a of the gate dielectric layer 216. In some examples, the thickness of the source / drain regions 208 and / or 210 can be between about 15 nanometers and about 30 nanometers to enable sufficiently high planarization uniformity for the source / drain regions 208 and / or 210 while enabling sufficient gap fill performance for the gate 214. However, other ranges of values are within the scope of the present disclosure. In some examples, the extension distance of the gate 214 over the portion 216a of the gate dielectric layer 216 is in a range of 0 nanometers to about 5 nanometers to enable the word line conductive structure 220 to be formed on the gate 214. However, other ranges of values are within the scope of the present disclosure.

[0113] Figure 3C With Figure 3D A detailed view of the channel layer 212 of the memory cell structure 202 in the example implementation 300 is illustrated. Figure 3C A perspective view of the channel layer 212 is illustrated, and Figure 3D A top view of the channel layer is illustrated. As Figure 3C With Figure 3DAs shown, the source / drain region 208 can be in direct physical contact with the sidewall segment 212a of the channel layer. The source / drain region 210 can be in direct physical contact with the sidewall segment 212b of the channel layer. The source / drain region 206 can be in direct physical contact with the bottom segment 212c of the channel layer.

[0114] A portion 216a of the gate dielectric layer 216 can be located between the sidewall segment 212a and the gate 214. A portion 216a of the gate dielectric layer 216 can be located between the sidewall segment 212b and the gate 214. A portion 216a of the gate dielectric layer 216 can be located between the bottom segment 212c and the gate 214.

[0115] As described above, a memory cell structure 202 is provided Figures 3A to 3D As examples. Other examples can differ Figures 3A to 3D from the related description of the illustrated examples of the memory cell structure 202.

[0116] Figures 4A to 4X is a diagram of an example embodiment 400 of the memory cell structure 202 described herein. In some examples, one or more of the semiconductor processing operations described in Figures 4A to 4X may be performed using one or more of the semiconductor processing tools 102-112 described herein. In some examples, one or more of the semiconductor processing operations described in Figures 4A to 4X may be performed using another semiconductor processing tool. Figures 4A to 4X Some of the diagrams in Figure 2A are cross-sectional views taken along the cut line A-A in Figures 4A to 4X , while some of the diagrams in Figure 2A are cross-sectional views taken along the cut line B-B in

[0117] Reference is made to Figure 4A A dielectric layer 228 can be formed in the semiconductor assembly 200. An ESL 230 can be formed over and / or on the dielectric layer 228. A storage structure 204 can be formed in the dielectric layer 228 through the ESL 230. A dielectric layer 232 can be formed over and / or on the ESL 230 and over and / or on the storage structure 204. The dielectric layer 228, the ESL 230, and the dielectric layer 232 can be arranged in the semiconductor assembly 200 along the z-direction. Top surfaces of the dielectric layer 228, the ESL 230, and the dielectric layer 232 can extend in the x-direction and the y-direction in the semiconductor assembly 200.

[0118] The deposition tool 102 can use a PVD technique, an ALD technique, a CVD technique, Figure 1The other types of deposition techniques described herein, and / or other suitable deposition techniques, are used to deposit dielectric layer 228, ESL 230, and / or dielectric layer 232. In some instances, after forming dielectric layer 228, ESL 230, and / or dielectric layer 232, a planarization tool 110 is used to planarize dielectric layer 228, ESL 230, and / or dielectric layer 232.

[0119] In some instances, forming the storage structure 204 includes forming a capacitor structure in the dielectric layer 228. The capacitor structure may include a thin-film capacitor structure (e.g., a planar capacitor structure), a DTC structure, and / or other types of capacitor structures. The capacitor structure may have a metal-insulator-metal (MIM) arrangement, wherein the bottom electrode and the top electrode are separated by an insulating layer. Additionally and / or alternatively, forming the storage structure 204 may include forming a phase change material structure, forming a resistive structure, forming a ferroelectric structure, and / or forming other types of storage structures.

[0120] like Figure 4B As shown, the bit line conductive structure 222 is formed in and / or on the dielectric layer 228. Forming the bit line conductive structure 222 may include forming a substrate 254 and forming the bit line conductive structure 222 on the substrate 254. In some embodiments, an etching tool 108 is used to etch the dielectric layer 228 and / or the dielectric layer 232 to form a trench in which the bit line conductive structure 222 is formed. The deposition tool 102 may use PVD technology, ALD technology, CVD technology, etc. Figure 1 The other types of deposition techniques described herein, and / or other suitable deposition techniques, are used to deposit the substrate 254. The deposition tool 102 and / or electroplating tool 112 may use PVD, ALD, CVD, or other technologies. Figure 1 The described deposition techniques, and / or other suitable deposition techniques, are used to deposit the bit line conductive structure 222. In some instances, a seed layer is first deposited on the substrate 254, and the bit line conductive structure 222 is deposited on the seed layer. In some instances, after forming the bit line conductive structure 222, a planarization tool 110 is used to planarize the bit line conductive structure 222.

[0121] like Figure 4C and Figure 4D As shown, ESL 234 can be formed above and / or on dielectric layer 232 (e.g., Figure 4C (as shown) and formed above and / or on the bit line conductive structure 222 (e.g. Figure 4D (As shown). Dielectric layer 236 may be formed above and / or on ESL 234. Deposition tool 102 may be used with PVD, ALD, CVD, or other technologies. Figure 1The described deposition techniques, and / or other suitable deposition techniques, are used to deposit the ESL 234 and / or the dielectric layer 236. In some examples, after forming the ESL 234 and / or the dielectric layer 236, the planarization tool 110 is used to planarize the ESL 234 and / or the dielectric layer 236.

[0122] As shown in Figure 4E A recess 402 is formed through the dielectric layer 236, through the ESL 234, and through the dielectric layer 232 to the storage structure 204. The recess 402 can be formed in the semiconductor assembly 200 in the z-direction such that the recess 402 extends from a top surface of the dielectric layer 236 to a top surface of the storage structure 204. The top surface of the storage structure 204 can be exposed through the recess 402.

[0123] In some examples, a pattern in a photoresist layer is used to etch the dielectric layer 236, the ESL 234, and / or the dielectric layer 232 to form the recess 402. In these examples, the deposition tool 102 can be used to form a photoresist layer on the dielectric layer 236. The exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric layer 236, the ESL 234, and / or the dielectric layer 232 based on the pattern to form the recess 402. In some examples, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some examples, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some examples, a hard mask layer is used as an alternative technique to form the recess 402 according to the pattern.

[0124] As shown in Figure 4F A liner layer 248 is formed on sidewalls and a bottom surface of the recess 402 (where the bottom surface of the recess 402 can correspond to the top surface of the storage structure 204). The liner layer 248 can be conformally deposited such that the liner layer 248 conforms to the profile of the recess 402. The deposition tool 102 can use PVD techniques, ALD techniques, CVD techniques, Figure 1 The described deposition techniques, and / or other suitable deposition techniques, are used to deposit the liner layer 248.

[0125] As further shown in Figure 4F The recess 402 can be filled with the source / drain interconnect line 218 on the liner layer 248. The source / drain interconnect line 218 extends in the z-direction through the dielectric layer 232, the ESL 234, and / or the dielectric layer 236. The deposition tool 102 and / or the plating tool 112 can use PVD techniques, ALD techniques, CVD techniques, Figure 1The described deposition techniques, and / or other suitable deposition techniques, are used to deposit the source / drain interconnects 218. In some instances, a seed layer is first deposited on the substrate 248, and the source / drain interconnects 218 are deposited on the seed layer. In some instances, after the source / drain interconnects 218 are formed, a planarization tool 110 is used to planarize the dielectric layer 236 and / or the top surface of the source / drain interconnects 218.

[0126] like Figure 4G As shown, ESL 238 can be formed above and / or on dielectric layer 236 and / or above and / or on source / drain interconnect 218. Dielectric layer 240 can be formed above and / or on ESL 238. Deposition tool 102 can use PVD technology, ALD technology, CVD technology, Figure 1 The other types of deposition techniques described herein, and / or other suitable deposition techniques, are used to deposit ESL 238 and / or dielectric layer 240. In some instances, after the formation of ESL 238 and / or dielectric layer 240, a planarization tool 110 is used to planarize ESL 238 and / or dielectric layer 240.

[0127] like Figure 4H As shown, source / drain regions 206 and associated substrates 250 are formed above and / or on source / drain interconnects 218. Source / drain regions 206 and associated substrates 250 may be formed in and / or through dielectric layers 240 and / or ESL 238.

[0128] To form the source / drain region 206 and the associated substrate 250, a recess may be formed through the dielectric layer 240 and / or through the ESL 238 to the source / drain interconnect 218. The top surface of the source / drain interconnect 218 is exposed through the recess. The recess may be formed in the z-direction from the top surface of the dielectric layer 240 to the top surface of the source / drain interconnect 218.

[0129] In some instances, the pattern in the photoresist layer is used to etch the dielectric layer 240 and / or ESL 238 to form a recess. In these instances, a deposition tool 102 can be used to form the photoresist layer on the dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 240 and / or ESL 238 based on the aforementioned pattern to form a recess. In some instances, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some instances, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some instances, a hard shielding layer is used as an alternative technique to form a recess according to the pattern.

[0130] The liner 250 can be formed on the sidewalls and bottom surface of the recess. The liner 250 can be deposited conformally, such that the liner 250 conforms to the contour of the recess. The liner 250 can also be formed on the top surface of the dielectric layer 240. The deposition tool 102 can use PVD technology, ALD technology, CVD technology, Figure 1 The other types of deposition techniques described herein, and / or other suitable deposition techniques, are used to deposit the liner 250.

[0131] The recess can then be filled with the source / drain interconnect 206 on the substrate 250. Thus, a source / drain region 206 can be formed on the source / drain interconnect 218. The deposition tool 102 and / or electroplating tool 112 can use PVD, ALD, CVD, or other technologies. Figure 1 The described other types of deposition techniques, and / or other suitable deposition techniques, are used to deposit the source / drain regions 206. In some instances, a seed layer is first deposited on the substrate 250, and the source / drain regions 206 are then deposited on the seed layer.

[0132] like Figure 4I As shown, after depositing the substrate 250 and the source / drain regions 206, a planarization tool 110 can be used to planarize the semiconductor component 200. The planarization tool 110 can remove the material of the substrate 250 and the source / drain regions 206 from the top surface of the dielectric layer 240.

[0133] like Figure 4J As shown, after the source / drain region 206 is formed, additional material is deposited on the dielectric layer 240. ESL 242 may be formed above and / or on the dielectric layer 240. Dielectric layer 244 may be formed above and / or on the ESL 242. The deposition tool 102 may use PVD, ALD, CVD, or other techniques. Figure 1The described type of deposition techniques, and / or other suitable deposition techniques, are used to deposit the additional materials of the dielectric layer 240, the ESL 242, and / or the dielectric layer 244. In some examples, the planarization tool 110 is used to planarize the dielectric layer 240, the ESL 242, and / or the dielectric layer 244.

[0134] As shown, the source / drain interconnect lines 224 are formed in and / or through the dielectric layers 236 and / or 240, and in and / or through the ESLs 234, 238, and / or 242, with the associated liners 256. The source / drain interconnect lines 226 are formed in and / or through the dielectric layers 236 and / or 240, and in and / or through the ESLs 234, 238, and / or 242, with the associated liners 258. The conductive layer 404, and one or more liners 406, are formed in the dielectric layer 244, and are coupled to the source / drain interconnect lines 224 and 226 in a dual damascene architecture. Figure 4K

[0135] A recess is formed through the dielectric layer 244, through the ESL 242, through the dielectric layer 240, through the ESL 238, through the dielectric layer 236, and / or through the ESL 234, to the bit line conductive structure 222. The recess can include a plurality of via portions of a dual damascene profile. A plurality of trench portions of the dual damascene profile can be formed in the dielectric layer 244. The deposition tool 102 can be used to form a photoresist layer on the dielectric layer 244. The exposure tool 104 can be used to expose the photoresist layer to a source of radiation to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etch tool 108 can be used to etch the dielectric layer 244, the ESL 242, the dielectric layer 240, the ESL 238, the dielectric layer 236, and / or the ESL 234, based on the aforementioned pattern, to form the dual damascene profile. In some examples, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or other types of etching operations. In some examples, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or other techniques). In some examples, a hard mask layer is used as an alternative technique to form the dual damascene profile according to the pattern.

[0136] The liners 256, 258, and / or 406 can be conformally deposited such that the liners 256, 258, and / or 406 conform to the dual damascene profile. The deposition tool 102 can use PVD techniques, ALD techniques, CVD techniques, Figure 1 ​Other suitable deposition techniques can be used to deposit the additional material of the dielectric layer 244. In some examples, after depositing the additional material of the dielectric layer 244, the planarization tool 110 is used to planarize the dielectric layer 244.

[0137] The source / drain interconnect lines 224 can be formed in via portions of a dual damascene profile on the liner 256. The source / drain interconnect lines 226 can be formed in via portions of a dual damascene profile on the liner 258. The conductive layer 404 can be formed in trench portions of a dual damascene profile on the liner 406. The deposition tool 102 and / or the electroplating tool 112 can use PVD techniques, ALD techniques, CVD techniques, Figure 1 Other suitable deposition techniques can be used to deposit the source / drain interconnect lines 224, the source / drain interconnect lines 226, and / or the conductive layer 404. In some examples, a seed layer is deposited on the liner 256, 258, and / or 406 prior to depositing the source / drain interconnect lines 224, the source / drain interconnect lines 226, and / or the conductive layer 404. In some examples, the planarization tool 110 is used to planarize the conductive layer 404.

[0138] As shown in FIG. 4A, the dielectric layer 240 is formed on the source / drain regions 206, 208, and 210. The dielectric layer 240 can be formed using PVD techniques, ALD techniques, CVD techniques, Figure 4L As shown in FIG. 4A, the dielectric layer 240 is formed on the source / drain regions 206, 208, and 210. The dielectric layer 240 can be formed using PVD techniques, ALD techniques, CVD techniques, Figure 4M As shown in FIG. 4A, the dielectric layer 240 is formed on the source / drain regions 206, 208, and 210. The dielectric layer 240 can be formed using PVD techniques, ALD techniques, CVD techniques, Figure 1 Other suitable deposition techniques can be used to deposit the additional material of the dielectric layer 244. In some examples, after depositing the additional material of the dielectric layer 244, the planarization tool 110 is used to planarize the dielectric layer 244.

[0139] As shown in FIG. 4A, the dielectric layer 240 is formed on the source / drain regions 206, 208, and 210. The dielectric layer 240 can be formed using PVD techniques, ALD techniques, CVD techniques, Figure 4L As shown in FIG. 4A, the dielectric layer 240 is formed on the source / drain regions 206, 208, and 210. The dielectric layer 240 can be formed using PVD techniques, ALD techniques, CVD techniques, Figure 4M As shown in FIG. 4A, the dielectric layer 240 is formed on the source / drain regions 206, 208, and 210. The dielectric layer 240 can be formed using PVD techniques, ALD techniques, CVD techniques,

[0140] In some instances, the pattern in the photoresist layer is used to etch dielectric layer 244, ESL 242, dielectric layer 240, and conductive layer 404 to form a recess 802. In these instances, a deposition tool 102 can be used to form the photoresist layer on dielectric layer 244. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch dielectric layer 244, ESL 242, dielectric layer 240, and conductive layer 404 based on the aforementioned pattern to form recess 408. In some instances, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some instances, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some instances, a hard shielding layer is used as an alternative technique to form the recess 408 according to the pattern.

[0141] like Figure 4N As shown, a channel layer 212 is formed, and a gate dielectric layer 216 is formed on the channel layer 212. The channel layer 212 is formed on the bottom surface and sidewalls of the recess 408 (where the bottom surface of the recess 408 corresponds to the top surface of the source / drain region 206). Excess material of the channel layer 212 may also be formed above the top surface of the dielectric layer 244 and / or on the top surface of the dielectric layer 244. A portion 216a of the gate dielectric layer 216 is formed on the sidewalls and bottom surface of the recess 408. A portion 216c of the gate dielectric layer 216 is formed above the top surface of the dielectric layer 244 and / or on the top surface of the dielectric layer 244. The deposition tool 102 can use PVD technology, ALD technology, CVD technology, Figure 1 The aforementioned deposition techniques, and / or other suitable deposition techniques, are used to conformally deposit the channel layer 212 and / or the gate dielectric layer 216. Thus, portions 216a of the channel layer 212 and the gate dielectric layer 216 conform to the cross-sectional profile of the recess 408. Therefore, the channel layer 212 located on the sidewalls of the recess 408, along with portions 216a of the gate dielectric layer 216, extends primarily in the z-direction of the semiconductor assembly 200.

[0142] like Figure 4NAs shown, the recess 408 is filled on the channel layer 212 with a sacrificial layer 410 on a portion 216a of the gate dielectric layer 216. Excess material of the sacrificial layer 410 is also formed over a portion 216c of the gate dielectric layer 216c. The sacrificial layer 410 comprises one or more materials, and this material has high etch selectivity relative to the material of the gate dielectric layer 216. This allows the sacrificial layer 410 to be subsequently etched away without (or with minimal) removal of the gate dielectric layer 216. Examples of materials for the sacrificial layer 410 include amorphous silicon (α-Si) and / or silicon nitride (SixNy, such as Si3N4), etc. The deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, and another type of deposition technology described in the link. Figure 1 and / or another suitable deposition technique to deposit the sacrificial layer 410.

[0143] like Figure 4O As shown, excess material of channel layer 212 is formed above and / or on the top surfaces of source / drain regions 208 and 210, along with a portion 216c of gate dielectric layer 216.

[0144] like Figure 4P and Figure 4Q As shown, a planarization operation is performed to planarize the sacrificial layer 410, the gate dielectric layer 216, and the channel layer 212. Planarization may stop at the source / drain regions 208 and 210. A planarization tool 110 can be used to perform the planarization operation to remove excess material from the sacrificial layer 410, remove a portion 216c of the gate dielectric layer 216, and remove excess material from the top surface of the channel layer 212 from the source / drain regions 208 and 210.

[0145] like Figure 4R As shown, after the planarization operation, the sacrificial layer 410 is removed from the recess 408. An etching tool 108 can be used to etch the sacrificial layer 410 to remove it from the semiconductor assembly 200. An etchant with a high etching rate for the material of the sacrificial layer 410 and a low etching rate for the material of the gate dielectric layer 216 can be used to etch the sacrificial layer 410. This minimizes the removal of the gate dielectric layer 216 when the sacrificial layer 410 is etched.

[0146] like Figure 4S and Figure 4T As shown, after removing the sacrificial layer 410, the remaining material of the gate dielectric layer 216 is conformally deposited in the recess 408, on the top surface of the dielectric layer 244, and on the top surfaces of the source / drain regions 208 and 210. The deposition tool 102 can be used with PVD, ALD, CVD, and another type of deposition technique described in the connection. Figure 1And / or another suitable deposition technique to deposit additional material for the gate dielectric layer 216. The deposition of additional material for the gate dielectric layer 216 results in the formation of portions 216b on the top surfaces of the source / drain regions 208 and 210.

[0147] like Figure 4U As shown, the recess 408 is filled with a conductive layer 412. The conductive layer 412 is formed on a portion 216a of the gate dielectric layer 216 in the recess 408, and on a portion 216b of the gate dielectric layer 216 on the dielectric layer 244. The deposition tool 102 and / or the electroplating tool 112 can be used with PVD technology, ALD technology, CVD technology, and another type of deposition technology described in the connection. Figure 1 And / or another suitable deposition technique to deposit the conductive layer 412. In some instances, a seed layer is first deposited on the gate dielectric layer 214 and the recess 408, and the conductive layer 412 is deposited on the seed layer.

[0148] like Figure 4V As shown, a planarization operation can be performed to planarize the conductive layer 412. The planarization tool 110 can be used to perform the planarization operation.

[0149] like Figure 4W Multiple portions of the conductive layer 412 are removed. The remaining portion of the conductive layer 412 corresponds to the gate 214 and is conductive to the character line structure 220 on the gate 214.

[0150] In some instances, the pattern in the photoresist layer is used to etch the conductive layer 412 to form the gate 214 and the character line conductive structure 220. In these instances, a deposition tool 102 can be used to form the photoresist layer on the conductive layer 412. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the conductive layer 412 based on the aforementioned pattern to form the gate 214 and the character line conductive structure 220. In some instances, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some instances, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some instances, a hard shielding layer is used as an alternative technique to form the gate 214 and the character line conductive structure 220 according to the pattern.

[0151] like Figure 4X As shown, dielectric layer 246 is formed around the character line conductive structure 220. Deposition tool 102 can be used with PVD, ALD, CVD, or other techniques. Figure 1The dielectric layer 246 may be deposited using other types of deposition techniques described herein, and / or other suitable deposition techniques. In some instances, after depositing the dielectric layer 246, a planarization tool 110 is used to planarize the dielectric layer 246. In other words, a fill operation is performed to fill the area around the character line conductive structure 220 with the dielectric layer 246, and then a CMP operation is performed to planarize the dielectric layer 246 (e.g., to make it coplanar with the character line conductive structure 220).

[0152] As mentioned above, providing Figures 4A to 4X As an example. Other examples can be compared with... Figures 4A to 4X The relevant descriptions differ.

[0153] Figure 5A and Figure 5B This is a diagram of an example embodiment 500 of the memory cell structure 202 disclosed herein. Figure 5A A perspective view of an example embodiment 500 of the memory cell structure 202 is shown, and Figure 5B An example embodiment 500 illustrating the memory cell structure 202 is shown along... Figure 5A The cross-sectional view of section AA in the diagram.

[0154] like Figure 5A and Figure 5B As shown, an example embodiment 500 of the memory cell structure 202 includes... Figures 2A to 2C as well as Figures 3A to 3D The memory cell structure 202 shown in Example Embodiment 300 has a similar structure and layer arrangement. However, in Example Embodiment 500 of the memory cell structure 202, the source / drain interconnect 218 is omitted. Instead, the source / drain region 206 extends fully between the channel layer 212 (located below the bottom surface of the gate 214) and the top surface of the storage structure 204, so that the source / drain region 206 is in direct physical contact with the storage structure 204.

[0155] In example embodiment 300 of the memory cell structure 202, the source / drain interconnect 218 makes it easier to control the outline of the memory cell structure 202 during its fabrication. However, in example embodiment 500 of the memory cell structure 202, omitting the source / drain interconnect 218 allows for the formation of the memory cell structure 202 using fewer lithography operations and associated photomasks.

[0156] like Figure 5A and Figure 5BAs further shown, the source / drain region 206 may gradually taper between its top surface and bottom surface. Therefore, the source / drain region 206 may have a width greater than the width of its bottom surface profile (in...). Figure 5B The width of the top section (indicated by dimension D5) is larger than that of the top section. Figure 5B (The dimension is indicated as D4). The cross-sectional width of the source / drain region 206 can be reduced from the top surface of the source / drain region 206 to the bottom surface of the source / drain region 206, thus forming a tapering. The tapering of the source / drain region 206 may be due to the etching rate at the top of the recess forming the source / drain region 206 being greater than the etching rate at the bottom of the recess forming the source / drain region 206.

[0157] As mentioned above, providing Figure 5A and Figure 5B As an example. Other examples can be compared with... Figure 5A and 5B The relevant descriptions differ.

[0158] Figures 6A to 6F This is a diagram of an exemplary embodiment 600 that forms the memory cell structure 202 disclosed herein. Specifically, exemplary embodiment 600 includes the formation of… Figure 5A and Figure 5B The example embodiment 500 illustrating the memory cell structure 202 is shown. In some instances, with... Figures 6A to 6F One or more of the semiconductor processing operations described herein can be performed using one or more of the semiconductor processing tools 102-112 described in this disclosure. In some instances, other semiconductor processing tools can be used to perform the operations. Figures 6A to 6F One or more of the semiconductor processing operations described herein. Figures 6A to 6F Some of the diagrams are along Figure 2A The cross-sectional view obtained by section line AA in the diagram, and Figures 6A to 6F Some of the diagrams are along Figure 2A The cross-sectional view obtained by section line BB in the diagram.

[0159] Please refer to Figure 6A Executable and Figures 4A to 4D Similar semiconductor processing operations are described in the description to form storage structure 204, bit line conductive structure 222 (not shown), dielectric layer 228, ESL 230, dielectric layer 232, ESL 234, dielectric layer 236, and substrate 254 (not shown).

[0160] like Figure 6B As shown, ESL 238 can be formed above and / or on dielectric layer 236, and dielectric layer 240 can be connected to... Figure 4GA similar arrangement is formed above and / or on ESL 238 as described herein. However, the formation of the source / drain interconnect 218 may be omitted before forming ESL 238 and dielectric layer 236.

[0161] like Figure 6C As shown, a recess 602 is formed through dielectric layer 240, through ESL 238, through dielectric layer 236, through ESL 234, and / or through dielectric layer 232 to the storage structure 204. The top surface of the storage structure 204 is exposed through the recess 602. The recess 602 may be formed in the z-direction from the top surface of dielectric layer 240 to the top surface of storage structure 204.

[0162] In some instances, the pattern in the photoresist layer is used to etch dielectric layers 240, 238, 236, 234, and / or 232 to form a recess 602. In these instances, a deposition tool 102 can be used to form the photoresist layer on the dielectric layer 240. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch dielectric layers 240, 238, 236, 234, and / or 232 based on the aforementioned pattern to form the recess 602. In some instances, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some instances, photoresist removal tools can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some instances, a hard shielding layer is used as an alternative technique to form the recess 602 according to the pattern.

[0163] like Figure 6D As shown, a liner 250 is formed on the sidewalls and bottom surface of the recess 602. The liner 250 can be deposited conformally, such that the liner 250 conforms to the contour of the recess 602. The liner 250 can also be formed on the top surface of the dielectric layer 240. The deposition tool 102 can use PVD technology, ALD technology, CVD technology, Figure 1 The other types of deposition techniques described herein, and / or other suitable deposition techniques, are used to deposit the liner 250.

[0164] like Figure 6D As further shown, the recess 602 can be filled with the source / drain region 206 on the substrate 250. Thus, the source / drain region 206 is formed on the storage structure 204, rather than on the source / drain interconnect 218. The deposition tool 102 and / or electroplating tool 112 can use PVD technology, ALD technology, CVD technology, Figure 1The described other types of deposition techniques, and / or other suitable deposition techniques, are used to deposit the source / drain regions 206. In some instances, a seed layer is first deposited on the substrate 250, and the source / drain regions 206 are deposited on the seed layer.

[0165] like Figure 6E As shown, after depositing the substrate 250 and the source / drain regions 206, the semiconductor assembly 200 can be planarized using a planarization tool 110. The planarization tool 110 can be executed to remove material from the top surface of the dielectric layer 240, as well as material from the substrate 250 and the source / drain regions 206.

[0166] like Figure 6F As shown, it can be used with Figures 4K to 4X Similar semiconductor processing operations are described herein to form source / drain regions 208 and 210 (not shown), channel layer 212, gate 214, gate dielectric layer 216, character line conductive structure 220, source / drain interconnects 224 and 226 (not shown), additional material of dielectric layer 240, ESL 242, dielectric layer 244, dielectric layer 246, and substrates 256, 258, 260, and 262 (not shown).

[0167] As mentioned above, providing Figures 6A to 6F As an example. Other examples can be compared with... Figures 6A to 6F The relevant descriptions differ.

[0168] Figure 7A and Figure 7B This is a diagram of an example embodiment 700 that discloses a memory cell structure 202. Figure 7A A perspective view of example embodiment 700 is shown, and Figure 7B An example embodiment 700 illustrating the memory cell structure 202 is shown along... Figure 7A The cross-sectional view of section AA in the diagram.

[0169] like Figure 7A and Figure 7B As shown, an example embodiment 700 of the memory cell structure 202 includes... Figures 2A to 2C as well as Figures 3A to 3DThe memory cell structure 202 illustrated in Example Embodiment 300 has a similar structure and layer arrangement. However, in Example Embodiment 700 of the memory cell structure 202, one or more diffusion barrier layers are included around the memory cell structure 202. For example, a diffusion barrier layer 702 may be located above the source / drain region 206 and around the bottom segment 212c of the channel layer 212 (and thus around the bottom of the gate 214). As another example, a diffusion barrier layer 704 may be located below the source / drain regions 208 and / or 210 and around a portion of the sidewall segment 212a of the channel layer 212b (and thus around the middle of the gate 214).

[0170] As described above, the channel layer 212 may include one or more metal-oxide-semiconductor materials, such as IGZO and / or ITO. These types of materials may be susceptible to contamination by the diffusion of elements and / or molecules, such as oxygen (O), nitrogen (N), hydrogen (H), and / or water (H2O). These contaminants can create vacancy defects in the metal-oxide-semiconductor material of the channel layer 212, leading to an increase in leakage current in the memory cell structure 202. Diffusion barrier layers 702 and 704 may be located around the channel layer 212 of the memory cell structure 202 to prevent or reduce the possibility of these contaminants and other contaminants diffusing into the channel layer 212 from below the diffusion barrier layer 702 and above the diffusion barrier layer 704.

[0171] In some instances, additional diffusion barrier layers and / or different arrangements of diffusion barrier layers 702 and / or 704 may be arranged in the semiconductor component 200. For example, diffusion barrier layer 702 (and / or another diffusion barrier layer) may be located below the storage structure 204. As another example, diffusion barrier layer 704 (and / or another diffusion barrier layer) may be located above the character line conductive structure 220.

[0172] The diffusion barrier layers 702 and / or 704 may each comprise one or more hydrogen barrier materials, one or more nitrogen barrier materials, and / or one or more oxygen barrier materials. Examples of such materials include alumina (Al₂O₃). x O y For example, Al2O3), silicon carbide (SiOC), chromium oxide (Cr) x O y For example, Cr2O3), other oxide-containing materials, and / or other materials.

[0173] As mentioned above, providing Figure 7A and Figure 7B As an example. Other examples can be compared with... Figure 7A and Figure 7B The relevant descriptions differ.

[0174] Figures 8A to 8D This is a diagram of an example embodiment 800 that forms the memory cell structure 202 described in this disclosure. Specifically, example embodiment 800 includes the formation of… Figure 7A and Figure 7B The example embodiment 700 of the memory cell structure 202 shown is an example. In some instances, Figures 8A to 8D One or more of the semiconductor processing operations described herein can be performed using one or more of the semiconductor processing tools 102-112 described in this disclosure. In some instances, using... Figures 8A to 8D One or more of the described semiconductor processing operations may be performed using another semiconductor processing tool. Figures 8A to 8D Some of the diagrams are along Figure 2A The cross-sectional view obtained by section line AA in the diagram, and Figures 8A to 8D Some of the diagrams are along Figure 2A The cross-sectional view obtained by section line BB in the diagram.

[0175] Please refer to Figure 8A Executable and Figures 4A to 4I Similar semiconductor processing operations are described in the description to form storage structure 204, source / drain region 206, source / drain interconnect 218, bit line conductive structure 222 (not shown), dielectric layer 228, ESL 230, dielectric layer 232, ESL 234, dielectric layer 236, ESL 238, dielectric layer 240, substrate 248, substrate 250, and substrate 254 (not shown).

[0176] like Figure 8B As shown, with Figure 4J Similar to the manner described herein, additional portions of dielectric layer 240 are formed over and / or on source / drain region 206, ESL 242 is formed over and / or on dielectric layer 240, and dielectric layer 244 is formed over and / or on ESL 242. However, diffusion barrier layers 702 and 704 are additionally formed during the formation of additional portions of dielectric layer 240, ESL 242, and dielectric layer 244. For example, diffusion barrier layer 702 may be formed over and / or on dielectric layer 240 and / or over and / or on source / drain region 206. Additional portions of dielectric layer 240 may be formed over and / or on diffusion barrier layer 702. ESL 242 may be formed over and / or on an additional portion of dielectric layer 240. Diffusion barrier layer 704 may be formed over and / or on ESL 242. Dielectric layer 244 may be formed over and / or on diffusion barrier layer 704.

[0177] Deposition tool 102 can use PVD technology, ALD technology, CVD technology, Figure 1 The other types of deposition techniques described herein, and / or other suitable deposition techniques, are used to deposit additional portions of dielectric layer 240, ESL 242, dielectric layer 244, diffusion barrier layer 702, and / or diffusion barrier layer 704. In some instances, after forming the additional portions of dielectric layer 240, ESL 242, dielectric layer 244, diffusion barrier layer 702, and / or dielectric layer 240, ESL 242, dielectric layer 244, diffusion barrier layer 702, and / or diffusion barrier layer 704, a planarization tool 110 is used to planarize the additional portions of dielectric layer 240, ESL 242, dielectric layer 244, diffusion barrier layer 702, and / or diffusion barrier layer 704.

[0178] After forming the additional portion of dielectric layer 240, ESL 242, dielectric layer 244, diffusion barrier layer 702 and / or diffusion barrier layer 704, conductive layer 404 (not shown), source / drain interconnects 224 and 226 (not shown), and substrates 256, 258 and 406 (not shown) may be connected to... Figure 4K It is formed in a similar manner to that described in [the text].

[0179] like Figure 8C As shown, a recess 802 is formed through dielectric layer 244, through diffusion barrier layer 704, through ESL 242, through an additional portion of dielectric layer 240, and through diffusion barrier layer 702 to the source / drain region 206. Forming the recess 802 involves removing multiple portions of conductive layer 404, resulting in the formation of source / drain regions 208 and 210 (not shown) and associated substrates 260 and / or 262, respectively. The top surface of the source / drain region 206 is exposed through the recess 802. The recess 802 may be formed in the z-direction from the top surface of dielectric layer 244 to the top surface of source / drain region 206.

[0180] In some examples, the pattern in the photoresist layer is used to etch the dielectric layer 244, diffusion barrier layer 704, ESL 242, additional portions of the dielectric layer 240, diffusion barrier layer 702, and conductive layer 404 to form a recess 802. In these examples, a deposition tool 102 can be used to form the photoresist layer on the dielectric layer 244. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 244, diffusion barrier layer 704, ESL 242, additional portions of the dielectric layer 240, diffusion barrier layer 702, and conductive layer 404 based on the aforementioned pattern to form the recess 802. In some examples, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some instances, photoresist removal tools can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some instances, a hard shielding layer is used as an alternative technique to form the recess 802 according to the pattern.

[0181] like Figure 8D As shown, it can execute with Figures 4N to 4X The aforementioned semiconductor processing operations are used to form the channel layer 212, the gate 214, and the gate dielectric layer 216 in the recess 802, and to form the character line conductive structure 220 and the dielectric layer 246.

[0182] As mentioned above, providing Figures 8A to 8D As an example. Other examples can be compared with... Figures 8A to 8D The relevant descriptions differ.

[0183] Figure 9A and Figure 9B This is a diagram of an example embodiment 900 of the memory cell structure 202 described herein. Figure 9A A perspective view of an example embodiment 900 of the memory cell structure 202 is shown, while Figure 9B This illustrates an example embodiment 900 of the memory cell structure 202 along... Figure 9A The cross-sectional view of section AA in the diagram.

[0184] like Figure 9A and Figure 9B As shown, an example embodiment 900 of the memory cell structure 202 includes and Figure 5A and Figure 5BThe depicted example embodiment 500 of the memory cell structure 202 is similar to the junction and layer arrangement of the example embodiment 900. Except for the tapered source / drain regions 206 and the omission of the source / drain interconnects 218, the diffusion barriers 702 and / or 704 are distributed around the channel layer 212 in the example embodiment 1000 of the memory cell structure 202. This enables one or more metal oxide semiconductor materials for the channel layer 212 to be combined with the tapered source / drain regions 206.

[0185] As described above, the provision of Figure 9A with Figure 9B is by way of example only. Other examples can differ with respect to the relevant details as Figure 9A and Figure 9B described in connection with the relevant descriptions.

[0186] Figures 10A to 10D is a diagram of an example embodiment 1000 of the memory cell structure 202 described herein. In particular, the example embodiment 1000 includes the formation of Figure 9A with Figure 9B the example embodiment 900 of the memory cell structure 202 shown in Figures 10A to 10D One or more of the semiconductor processing operations described in Figures 10A to 10D may be performed using one or more of the semiconductor processing tools 102-112 described herein. In some examples, one or more of the semiconductor processing operations described in Figures 10A to 10D may be performed using another semiconductor processing tool. Figure 2A Some of the figures in Figures 10A to 10D are cross-sectional views taken along the section line A-A in Figure 2A while some of the figures in are cross-sectional views taken along the section line B-B in

[0187] . Figure 10A Please refer to Figures 4A to 4D may be performed to form the storage structure 204, the source / drain regions 206 on the storage structure 204 (with the source / drain interconnects 218 omitted), the bit line conductive structure 222 (not shown), the dielectric layer 228, the ESL 230, the dielectric layer 232, the ESL 234, the dielectric layer 236, the ESL 238, the dielectric layer 240, the liner 250, and the liner 254 (not shown).

[0188] As shown in Figure 10B , the provision of Figure 4JIn some examples, the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 are formed using a PVD technique, an ALD technique, a CVD technique, another type of deposition technique described herein, and / or another suitable deposition technique. In some examples, after the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 are formed, the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 are planarized using the planarization tool 110.

[0189] The deposition tool 102 can deposit the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 using a PVD technique, an ALD technique, a CVD technique, Figure 1 another type of deposition technique described herein, and / or another suitable deposition technique. In some examples, after the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 are formed, the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 are planarized using the planarization tool 110.

[0190] After the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 are formed, the conductive layer 404 (not shown), the source / drain interconnects 224 and 226 (not shown), and the liners 256, 258, and 406 (not shown) can be formed using similar techniques as described herein. Figure 4K

[0191] As described above, the additional portions of the dielectric layer 240, the ESL 242, the dielectric layer 244, the diffusion barrier layer 702, and / or the diffusion barrier layer 704 can be formed using a PVD technique, an ALD technique, a CVD technique, Figure 10C ​As shown, a recess 1002 is formed through dielectric layer 244, through diffusion barrier layer 704, through ESL 242, through an additional portion of dielectric layer 240, and through diffusion barrier layer 702 to the source / drain region 206. Forming the recess 1002 involves removing multiple portions of conductive layer 404, resulting in the formation of source / drain regions 208 and 210 (not shown) and associated substrates 260 and / or 262, respectively. The top surface of the source / drain region 206 is exposed through the recess 1002. The recess 1002 may be formed in the z-direction from the top surface of dielectric layer 244 to the top surface of source / drain region 206.

[0192] In some instances, the pattern in the photoresist layer is used to etch the dielectric layer 244, diffusion barrier layer 704, ESL 242, additional portions of the dielectric layer 240, diffusion barrier layer 702, and conductive layer 404 to form a recess 1002. In these instances, a deposition tool 102 can be used to form the photoresist layer on the dielectric layer 244. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 244, diffusion barrier layer 704, ESL 242, additional portions of the dielectric layer 240, diffusion barrier layer 702, and conductive layer 404 based on the aforementioned pattern to form the recess 1002. In some instances, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some instances, photoresist removal tools can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some instances, a hard shielding layer is used as an alternative technique to form the recess 1002 according to the pattern.

[0193] like Figure 10D As shown, executable with Figures 4N to 4U The aforementioned semiconductor processing operations are used to form a channel layer 212, a gate 214 and a gate dielectric layer 216 located in the recess 1002, and to form a character line conductive structure 220 and a dielectric layer 246.

[0194] As mentioned above, providing Figures 10A to 10D As an example. Other examples can be compared with... Figures 10A to 10D The relevant descriptions differ.

[0195] Figure 11 This is a diagram of an example component of the component 1100 described in this disclosure. In some instances, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may include one or more components 1100 and / or one or more components of the component 1100. Figure 11As shown, the assembly 1100 can include a bus 1110, a processor 1120, a memory 1130, an input member 1140, an output member 1150, and / or a communication member 1160.

[0196] The bus 1110 can include one or more members capable of wired and / or wireless communication between members of the assembly 1100. For example, the bus 1110 can couple two or more members of the assembly 1100 together, such as by operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. For example, the bus 1110 can include an electrical connection (e.g., a wire, a trace, and / or a pin) and / or a wireless bus. The processor 1120 can include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or another type of processing member. The processor 1120 can be implemented in hardware, firmware, or a combination of hardware and software. In some examples, the processor 1120 can include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere in this disclosure. Figure 11

[0197] The memory 1130 can include volatile memory and / or non-volatile memory. For example, the memory 1130 can include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 1130 can include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 1130 can be a non-transitory computer-readable medium. The memory 1130 can store storage information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of the assembly 1100. In some examples, the memory 1130 can include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., the processor 1120), such as by the bus 1110. The communicative coupling between the processor 1120 and the memory 1130 can enable the processor 1120 to read and / or process information stored in and / or store information in the memory 1130.

[0198] ​Input component 1140 can enable component 1100 to receive input, such as user input and / or sensory input. For example, input component 1140 can include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, an angular velocity sensor, and / or a brake. Output component 1150 can enable component 1100 to provide outputs, such as through a display, a speaker, and / or a light emitting diode. Communication component 1160 can enable component 1100 to communicate with other components over wired and / or wireless connections. For example, communication component 1160 can include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0199] Component 1100 can perform one or more operations or processes described in the present disclosure. For example, a non-transitory computer-readable medium (e.g., memory 1130) can store a set of instructions (e.g., one or more instructions or code) for execution by processor 1120. Processor 1120 can execute the set of instructions to perform one or more operations or processes described in the present disclosure. In some examples, execution of the set of instructions by one or more processors 1120 can cause one or more processors 1120 and / or component 1100 to perform one or more operations or processes described in the present disclosure. In some examples, one or more operations or processes described in the present disclosure can be performed using hardware

[0200] Figure 11 The number and arrangement of components shown in FIG. 12 are provided as an example. Component 1100 can include additional components, fewer components, different components, or differently arranged components than those shown in FIG. 12. Additionally or alternatively, a set of components (e.g., one or more components) of component 1100 can perform one or more functions described as being performed by another set of components of component 1100. Figure 11

[0201] Figure 12 A flow diagram of example process 1200 related to forming a memory cell structure described in the present disclosure is shown in FIG. 12. In some examples, one or more semiconductor processing tools (e.g., one or more semiconductor processing tools 102-112) are used to perform one or more operations of process 1200. Figure 12 ​one or more process blocks in FIG. 12. Additionally or alternatively, one or more components of assembly 1100, such as processor 1120, memory 1130, input component 1140, output component 1150, and / or communication component 1160, can be used to perform one or more process blocks in FIG. 12. Figure 12 one or more process blocks in FIG. 12.

[0202] As shown in FIG. 12, process 1200 can include forming a first source / drain region, a memory cell structure in a semiconductor assembly (block 1210). For example, one or more of semiconductor processing tools 102-112 can be used to form first source / drain region 206 of memory cell structure 202 of semiconductor assembly 200, as described herein. Figure 12 As further shown in FIG. 12, process 1200 can include forming a plurality of dielectric layers over the first source / drain region (block 1220). For example, one or more of semiconductor processing tools 102-112 can be used to form a plurality of dielectric layers (e.g., dielectric layer 240, dielectric layer 244, ESL 242, diffusion barrier layer 702, diffusion barrier layer 704) over first source / drain region 206, as described herein.

[0203] Figure 12 As further shown in FIG. 12, process 1200 can include forming a first source / drain interconnect and a second source / drain interconnect in the plurality of dielectric layers (block 1230). For example, one or more of semiconductor processing tools 102-112 can be used to form the plurality of dielectric layers, first source / drain interconnect 224, and second source / drain interconnect 226, as described herein.

[0204] As further shown in FIG. 12, process 1200 can include forming a conductive layer over the plurality of dielectric layers and over the first source / drain interconnect and the second source / drain interconnect (block 1240). For example, one or more of semiconductor processing tools 102-112 can be used to form conductive layer 404 over the plurality of dielectric layers and over first source / drain interconnect 224 and second source / drain interconnect 226, as described herein. Figure 12 As further shown in FIG. 12, process 1200 can include forming a conductive layer over the plurality of dielectric layers and over the first source / drain interconnect and the second source / drain interconnect (block 1240). For example, one or more of semiconductor processing tools 102-112 can be used to form conductive layer 404 over the plurality of dielectric layers and over first source / drain interconnect 224 and second source / drain interconnect 226, as described herein.

[0205] Figure 12 As further shown in FIG. 12, process 1200 can include forming a conductive layer over the plurality of dielectric layers and over the first source / drain interconnect and the second source / drain interconnect (block 1240). For example, one or more of semiconductor processing tools 102-112 can be used to form conductive layer 404 over the plurality of dielectric layers and over first source / drain interconnect 224 and second source / drain interconnect 226, as described herein.

[0206] As further shown in FIG. 12, process 1200 can include forming a conductive layer over the plurality of dielectric layers and over the first source / drain interconnect and the second source / drain interconnect (block 1240). For example, one or more of semiconductor processing tools 102-112 can be used to form conductive layer 404 over the plurality of dielectric layers and over first source / drain interconnect 224 and second source / drain interconnect 226, as described herein. Figure 12 ​​Further, process 1200 can include forming a recess in the plurality of dielectric layers and through the conductive layer between the first source / drain interconnect and the second source / drain interconnect (block 1250). For example, one or more of semiconductor processing tools 102-112 can be used to form a recess 408 in the plurality of dielectric layers and through the conductive layer 404 between the first source / drain interconnect 224 and the second source / drain interconnect 226, as described herein. In some examples, forming the recess 408 through the conductive layer 404 forms a second source / drain region 208 over the first source / drain interconnect 224 and a third source / drain region 210 over the second source / drain interconnect 226.

[0207] As Figure 12 Further, process 1200 can include forming a channel layer (212) on the sidewalls and the bottom of the recess (block 1260). For example, one or more of semiconductor processing tools 102-112 can be used to form a channel layer 212 on the sidewalls and the bottom of the recess 408, as described herein.

[0208] As Figure 12 Further, process 1200 can include forming a gate dielectric layer on the channel layer in the recess (block 1270). For example, one or more of semiconductor processing tools 102-112 can be used to form a gate dielectric layer 216 on the channel layer 212 in the recess 408, as described herein.

[0209] As Figure 12 Further, process 1200 can include forming a gate on the gate dielectric layer (block 1280). For example, one or more of semiconductor processing tools 102-112 can be used to form a gate 214 on the gate dielectric layer 216, as described herein.

[0210] Process 1200 can include additional embodiments, such as any single embodiment or multiple embodiments described below or any combination of one or more other processes described elsewhere in the disclosure.

[0211] In a first embodiment, forming the gate dielectric layer 216 includes forming a first portion (e.g., portion 216a) of the gate dielectric layer 216 on the channel layer 212 in the recess 408, and forming a second portion (e.g., portion 216c) of the gate dielectric layer 216 on a top surface of the dielectric layer 244 of the plurality of dielectric layers, and the process 1200 includes filling the recess 408 with the sacrificial layer 410 on the gate dielectric layer 216 prior to forming the gate 214, removing the second portion of the gate dielectric layer 216 after filling the recess 408 with the sacrificial layer 410, removing the sacrificial layer 410 from the recess 408 after removing the second portion of the gate dielectric layer 216, depositing additional material of the first portion of the gate dielectric layer 216 in the recess 408, where depositing the additional material of the first portion of the gate dielectric layer 216 can form a third portion (e.g., portion 216b) of the gate dielectric layer 216 on the dielectric layer 244, and forming the gate 214 on the first portion of the gate dielectric layer 216 in the recess 408 after depositing the additional material of the first portion of the gate dielectric layer 216.

[0212] In a second embodiment, alone or in combination with the first embodiment, the process 1200 includes forming the word line conductive structure 220 on the gate 214 and on the third portion of the gate dielectric layer 216.

[0213] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the word line conductive structure 220 includes depositing a conductive layer 412 on the third portion of the gate dielectric layer 216 and on the gate 214, and removing portions of the conductive layer 412, where remaining portions of the conductive layer 412 correspond to the word line conductive structure 220.

[0214] Although Figure 12 Only example blocks of the process 1200 are illustrated, but in some embodiments, additional blocks can be added, fewer blocks can be used, different blocks can be used, or the blocks can be arranged in different orders. Figure 12 In addition or as an alternative, two or more blocks of the process 1200 can be performed in parallel.

[0215] Thus, the semiconductor device includes a memory cell structure, and the memory cell structure includes a transistor structure and a storage structure. The gate of the transistor structure extends in a direction substantially perpendicular to a surface of a substrate of the semiconductor device, which enables the gate length to be increased without increasing or minimizing the horizontal or lateral dimension of the memory cell structure. The channel layer can be a U-shaped layer because the channel layer is included on at least two of a sidewall and a bottom surface of the gate. The above design increases the channel area of the transistor structure, which enables low current leakage of the memory cell structure and enables high lateral density of the memory cell structure in the semiconductor device. The low current leakage of the memory cell structure enables data stored in the storage structure of the memory cell structure to have a longer duration between refreshes, which reduces the power consumption of the memory cell structure and also improves the power efficiency of the memory cell structure.

[0216] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of back end dielectric layers. The semiconductor device includes a memory cell structure located in the plurality of back end dielectric layers. The memory cell structure includes a storage structure and a transistor structure located above the storage structure. The transistor structure includes a first source / drain region, a second source / drain region located above the first source / drain region, a gate, and a channel layer. The gate extends between the first source / drain region and the second source / drain region. The channel layer extends between the first source / drain region and the second source / drain region. The channel layer is located on at least two sides of the gate and below a bottom surface of the gate. In some embodiments, a first section of the channel layer is located between the gate and the first source / drain region, and a second section of the channel layer is located between the gate and the second source / drain region. In some embodiments, the first section of the channel layer is located on a first side of the gate, and a third section of the channel layer is located on a second side of the gate, the second side being opposite the first side. In some embodiments, the channel layer includes a U-shaped channel layer. In some embodiments, the semiconductor device further includes a gate dielectric layer, wherein the gate dielectric layer extends between the first source / drain region and the second source / drain region, and the gate dielectric layer is included on at least two sidewalls of the gate and below the bottom surface of the gate. In some embodiments, the semiconductor device further includes a source / drain interconnect structure, wherein the source / drain interconnect structure is located above the storage structure and below the first source / drain region, and the first source / drain region is coupled to the storage structure through the source / drain interconnect structure. In some embodiments, the first source / drain region is in direct physical contact with the storage structure. In some embodiments, the channel layer includes a metal oxide semiconductor material, and the semiconductor device further includes one or more diffusion barrier layers located between the first source / drain region and the second source / drain region.

[0217] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of back end dielectric layers. The semiconductor device includes a memory cell structure located in the plurality of back end dielectric layers, and the memory cell structure includes a storage structure. The memory cell structure includes a first source / drain region. The memory cell structure includes a second source / drain region located above the first source / drain region. The memory cell structure includes a gate having an elongated shape in a direction substantially perpendicular to the plurality of back end dielectric layers. The first source / drain region is located below a bottom surface of the gate. The second source / drain region is located adjacent to opposing sidewalls of the gate. The memory cell structure includes a channel layer located on at least two sides of the gate and below the bottom surface of the gate. The first source / drain region is in contact with a bottom section of the channel layer located between the bottom surface of the gate and the first source / drain region. The second source / drain region is in contact with a sidewall section of the channel layer located between the sidewalls of the gate and the second source / drain region. In some embodiments, a first section of the channel layer is located between the bottom surface of the gate and the first source / drain region, and a third section of the channel layer is located between a second side of the gate and a third source / drain region. In some embodiments, the first side and the second side are opposing sides of the gate. In some embodiments, the channel layer includes a metal-oxide-semiconductor material, and the semiconductor device further includes a first diffusion barrier layer located above the first source / drain region and a second diffusion barrier layer located below the second source / drain region. In some embodiments, the first diffusion barrier layer and the second diffusion barrier layer each include an oxide-containing material. In some embodiments, the first diffusion barrier layer and the second diffusion barrier layer each include at least one of: aluminum oxide (AI2O3), silicon carbon oxide (SiOC), or chromium oxide (CrO). In some embodiments, the semiconductor device further includes a gate dielectric layer, and the gate dielectric layer includes a first portion located between the gate and the first source / drain region and a second portion located between the gate and the second source / drain region, and the second portion is located above a top surface of the second source / drain region. In some embodiments, the second portion of the gate dielectric layer is directly located on the top surface of the second source / drain region. x O y ), silicon carbon oxide (SiOC), or chromium oxide (Cr x O y ). In some embodiments, the semiconductor device further includes a gate dielectric layer, and the gate dielectric layer includes a first portion located between the gate and the first source / drain region and a second portion located between the gate and the second source / drain region, and the second portion is located above a top surface of the second source / drain region. In some embodiments, the second portion of the gate dielectric layer is directly located on the top surface of the second source / drain region.

[0218] As described in more detail above, some embodiments described herein provide a method. The method includes forming a first source / drain region of a memory cell structure in a semiconductor component. The method includes forming a plurality of dielectric layers over the first source / drain region. The method includes forming a first source / drain interconnect and a second source / drain interconnect in the plurality of dielectric layers. The method includes forming a conductive layer over the plurality of dielectric layers and over the first source / drain interconnect and the second source / drain interconnect. The method includes forming a recess in the plurality of dielectric layers and through the conductive layer, the recess positioned between the first source / drain interconnect and the second source / drain interconnect, wherein forming the recess through the conductive layer forms a second source / drain region over the first source / drain interconnect. The method includes forming a channel layer on sidewalls and a bottom surface of the recess. The method includes forming a gate dielectric layer on the channel layer in the recess. The method includes forming a gate on the gate dielectric layer. In some embodiments, forming the gate dielectric layer includes forming a first portion of the gate dielectric layer on the channel layer in the recess and forming a second portion of the gate dielectric layer on a top surface of a dielectric layer of the plurality of dielectric layers, and the method further includes filling the recess with a sacrificial layer on the gate dielectric layer before forming the gate, removing the second portion of the gate dielectric layer after filling the recess with the sacrificial layer, and replacing the sacrificial layer with the gate after removing the second portion of the gate dielectric layer. In some embodiments, replacing the sacrificial layer with the gate includes removing the sacrificial layer from the recess after removing the second portion of the gate dielectric layer, depositing additional material of the first portion of the gate dielectric layer in the recess, wherein depositing the additional material of the first portion of the gate dielectric layer forms a third portion of the gate dielectric layer on the dielectric layer, and forming the gate on the first portion of the gate dielectric layer in the recess after depositing the additional material of the first portion of the gate dielectric layer. In some embodiments, the method further includes forming a word line conductive structure on the gate and on the third portion of the gate dielectric layer, wherein forming the word line conductive structure includes depositing a conductive layer on the gate dielectric layer and on the third portion of the gate and removing portions of the conductive layer, wherein remaining portions of the conductive layer correspond to the word line conductive structure.

[0219] As used herein, depending on the context, "satisfies a threshold value" can refer to a value greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, and the like.

[0220] The foregoing overview of the features of several embodiments enables a person skilled in the art to better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced in the present disclosure. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor component, characterized in that, include: Multiple back-end dielectric layers; as well as A memory cell structure is located within the plurality of back dielectric layers, the memory cell structure comprising: Storage structure; and A transistor structure is located above the storage structure, the transistor structure comprising: First source / drain region; The second source / drain region is located above the first source / drain region; A gate, extending between the first source / drain region and the second source / drain region; and A channel layer extends between the first source / drain region and the second source / drain region, wherein the channel layer is contained on at least two sides of the gate and below the bottom surface of the gate.

2. The semiconductor component according to claim 1, characterized in that, The first segment of the channel layer is located between the gate and the first source / drain region; and The second segment of the channel layer is located between the gate and the second source / drain region.

3. The semiconductor component according to claim 1, characterized in that, Including: A gate dielectric layer extends between the first source / drain region and the second source / drain region. The gate dielectric layer is contained on at least two sidewalls of the gate and below the bottom surface of the gate.

4. The semiconductor component according to claim 1, characterized in that, Including: The source / drain interconnect structure is located above the storage structure and below the first source / drain region. The first source / drain region is coupled to the storage structure through the source / drain interconnect structure.

5. The semiconductor component according to claim 1, characterized in that, The first source / drain region is in direct physical contact with the storage structure.

6. A semiconductor component, characterized in that, include: Multiple back-end dielectric layers; as well as A memory cell structure is located within the plurality of back dielectric layers, the memory cell structure comprising: Storage structure; The first source / drain region is located above the storage structure; The second source / drain region is located above the first source / drain region; The gate has an extending shape in a direction perpendicular to the plurality of rear dielectric layers; and A channel layer is included on at least two sides of the gate and below the bottom surface of the gate, wherein the first source / drain region contacts a bottom segment of the channel layer, the bottom segment being located between the bottom surface of the gate and the first source / drain region. The second source / drain region is in contact with the sidewall segment of the channel layer, and the sidewall segment is located between the sidewall of the gate and the second source / drain region.

7. The semiconductor component according to claim 6, characterized in that, The channel layer comprises a metal-oxide-semiconductor material; and The semiconductor component further includes: A first diffusion barrier layer is located above the first source / drain region; and The second diffusion barrier layer is located below the second source / drain region.

8. The semiconductor component according to claim 7, characterized in that, The first diffusion barrier layer and the second diffusion barrier layer each comprise a material containing oxides.

9. The semiconductor component according to claim 6, characterized in that, Including: The gate dielectric layer includes: The first portion is located between the gate and the first source / drain region, and also between the gate and the second source / drain region; and The second part is located above the top surface of the second source / drain region.

10. The semiconductor component according to claim 9, characterized in that, The second portion of the gate dielectric layer is located directly on the top surface of the second source / drain region.

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