Selective passivation contact structure and double-sided selective TOPCon battery

Abstract

The utility model relates to the technical field of photovoltaic cells, and discloses a selective passivation contact structure and a double-sided selective TOPCon cell. The selective passivation contact structure comprises a silicon wafer, the back surface of the silicon wafer is sequentially provided with a first tunneling oxide layer and first boron-doped polycrystalline silicon, and a back surface electrode contact region of the first boron-doped polycrystalline silicon is also provided with second boron-doped polycrystalline silicon; the thickness of the first boron-doped polycrystalline silicon is smaller than that of the second boron-doped polycrystalline silicon, the crystallization rate of the first boron-doped polycrystalline silicon is larger than that of the second boron-doped polycrystalline silicon, and the doping concentration of the first boron-doped polycrystalline silicon is larger than that of the second boron-doped polycrystalline silicon. The selective passivation contact structure can reduce parasitic absorption of light, reduce recombination and improve the passivation effect and the transverse transmission performance of carriers, so that the open-circuit voltage, the short-circuit current, the fill factor and the cell efficiency of the double-sided selective TOPCon cell can be further improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to photovoltaic cell technical field, concretely relates to a kind of selective passivation contact structure and double-sided selective TOPCon cell. BACKGROUND

[0002] Double-sided TOPCon (Tunnel Oxide Passivated Contact) cell is an important means to improve the efficiency of traditional TOPCon cells. Among them, double-sided TOPCon cell refers to a solar cell with TOPCon structure on both the front and back surfaces of a silicon wafer. The TOPCon structure includes a tunnel oxide layer and a doped polysilicon deposited on the surface of the silicon wafer in sequence. On the basis of double-sided TOPCon cell, double-sided selective TOPCon cell is further prepared (for example, the tunnel oxide layer and the doped polysilicon are only located in the local area of the surface of the silicon wafer, which is usually referred to as the electrode contact area), which can further reduce the parasitic absorption caused by the polysilicon, thereby improving the photoelectric conversion efficiency of the cell.

[0003] Compared with the selective phosphorus-doped polysilicon, which has been studied more and is more mature, the selective boron-doped polysilicon is less studied and has high process difficulty. On the one hand, the solubility of boron atoms in polysilicon is low, so boron atoms are more likely to segregate to the interface oxide during the doping process. It is more difficult to obtain boron-doped polysilicon with excellent chemical passivation and high doping. On the other hand, unlike selective phosphorus-doped polysilicon, after patterning and removing the boron-doped polysilicon (also known as selective removal or local removal), it is necessary to ensure that there is a certain concentration of boron-doped layer in the non-electrode contact area to improve the lateral transmission current of the cell and avoid the sharp decrease of the fill factor.

[0004] Currently, there are two common methods for preparing selective boron-doped polysilicon. One common method is as shown in CN117334788A: first, a boron-doped emitter is prepared on the surface (e.g., the front surface) of the silicon wafer; then, the boron-silicon glass is locally opened by laser; and then, a local tunnel oxide layer and a local boron-doped polysilicon are prepared in the laser opening area on the surface of the boron-doped emitter. The selective passivation contact structure with selective boron-doped polysilicon prepared by this method needs to undergo two high-temperature boron diffusion processes (the boron-doped emitter needs to undergo one boron diffusion process; and the preparation of the local boron-doped polysilicon also needs to undergo one high-temperature annealing process, which also involves boron diffusion). The process steps are increased, and the two high-temperature boron diffusion processes are likely to cause more surface recombination, which increases the surface recombination of the selective passivation contact structure and is not conducive to the improvement of the cell efficiency (i.e., the photoelectric conversion efficiency of the cell).

[0005] Another common preparation method is: as shown in the publication CN117096201A, a tunneling oxide layer and an intrinsic polysilicon are prepared on the surface of the silicon wafer in sequence; then boron diffusion is performed to make the intrinsic polysilicon form a boron-doped polysilicon with a high doping concentration, and part of the boron atoms pass through the tunneling oxide layer to form a P+ doped layer with a low doping concentration in the silicon wafer. Although this preparation method is relatively simple, a certain number of boron atoms passing through the tunneling oxide layer will seriously affect the passivation effect of the tunneling oxide layer.

[0006] In summary, no matter which of the above preparation methods is used, the selective passivation contact structure prepared by these methods contains a selective boron-doped polysilicon, and the boron-doped polysilicon is prepared in the electrode contact area, and the boron emitter is prepared in the non-electrode contact area; this will result in that the passivation effect of the non-electrode contact area is not improved, and even the passivation effect is decreased, and the problem of recombination is aggravated. Practical new type content

[0007] The utility model aims at overcoming the prior art's insufficient, provides a kind of selective passivation contact structure and double-face selective TOPCon battery.

[0008] Based on this, the utility model discloses a kind of selective passivation contact structure,

[0009] Including: silicon wafer, the back surface of the silicon wafer is equipped with first tunneling oxide layer and first boron-doped polysilicon in sequence, and the back surface electrode contact area of the first boron-doped polysilicon is further equipped with second boron-doped polysilicon;

[0010] The thickness of the first boron-doped polysilicon is less than the second boron-doped polysilicon, the crystallization rate of the first boron-doped polysilicon is greater than the second boron-doped polysilicon, and the doping concentration of the first boron-doped polysilicon is greater than the second boron-doped polysilicon.

[0011] Preferably, the area of the second boron-doped polysilicon of the back surface electrode contact area accounts for 40-70% of the total area of the back surface.

[0012] Preferably, the thickness of the first tunneling oxide layer is 0.5-2nm.

[0013] Preferably, the thickness of the first boron-doped polysilicon is 10-30nm, and the thickness of the second boron-doped polysilicon is 150-300nm.

[0014] Preferably, the crystallization rate of the first boron-doped polysilicon is 60-80%, and the doping concentration is 1-3E20cm -3 ; the crystallization rate of the second boron-doped polysilicon is 40-60%, and the doping concentration is 6-9E19cm -3 .

[0015] Preferably, the selective passivation contact structure further comprises a second tunneling oxide layer and a phosphorus doped polysilicon, which are sequentially arranged on the front electrode contact area of the silicon wafer.

[0016] Further preferably, the second tunneling oxide layer has a thickness of 0.5-2 nm.

[0017] Further preferably, the phosphorus doped polysilicon has a thickness of 50-150 nm and a doping concentration of 3-6E20 cm -3 .

[0018] The utility model discloses a double -sided selective TOPCon battery, it includes the selective passivation contact structure of the utility model content above-mentioned, the surface of the front electrodeless contact area of silicon wafer is the rough surface of pyramid structure, and the front electrodeless contact area of silicon wafer rough surface and the front of phosphorus doped polysilicon of front electrode contact area all are sequentially provided with front passivation film and front antireflection film, and the back of the first boron doped polysilicon of back electrodeless contact area and the back of the second boron doped polysilicon of back electrode contact area all are sequentially provided with back passivation film and back antireflection film.

[0019] The selective TOPCon battery further comprises a front electrode and a back electrode, the front electrode sequentially passes through the front antireflection film and the front passivation film and then is in ohmic contact with the phosphorus doped polysilicon of the front electrode contact area, and the back electrode sequentially passes through the back antireflection film and the back passivation film and then is in ohmic contact with the second boron doped polysilicon of the back electrode contact area.

[0020] Preferably, the front passivation film and the back passivation film are both Al2O3 films with a thickness of 2-10 nm, and the front antireflection film and the back antireflection film are both silicon nitride films with a thickness of 60-80 nm.

[0021] Compared with the prior art, the utility model at least has the following beneficial effects:

[0022] The selective passivation contact structure of the utility model, through the first tunneling oxide layer reserved in the back and (compared with the second boron-doped polysilicon) the first boron-doped polysilicon with higher boron-doped concentration and higher crystallization rate, realizes passivation contact, replaces the boron-doped emitter of the traditional non-electrode contact area through the first boron-doped polysilicon with thinner thickness, higher boron-doped concentration and higher crystallization rate, further reduces surface recombination, improves the passivation effect of the non-electrode contact area, and also realizes good carrier lateral transmission. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 It is a cross-sectional structure schematic view of a double-sided selective TOPCon battery of the utility model.

[0024] The figure number explanation: silicon wafer 1;First tunneling oxide layer 2;First boron-doped polysilicon 3;Second boron-doped polysilicon 4;Second tunneling oxide layer 5;Phosphorus-doped polysilicon 6;Back Al2O3 film 7;Front Al2O3 film 8;Back silicon nitride film 9;Front silicon nitride film 10;Back electrode 11;Front electrode 12. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned purpose, features and advantages of the utility model more obvious and easy to understand, the utility model is further explained in detail below by combining with the drawings and specific embodiment.

[0026] EMBODIMENT

[0027] The preparation method of a double-sided selective TOPCon battery of the utility model, refer to Figure 1 , including the following preparation steps:

[0028] Step 1, the silicon wafer 1 is cleaned and polished.

[0029] In step 1, the silicon wafer 1 is preferably an N-type single crystal silicon wafer, the thickness of the silicon wafer 1 is 130-180 μm (e.g. 130 μm), the resistivity of the silicon wafer 1 is 0.5-1.5 Ω-cm (e.g. 1 Ω-cm), and the size of the silicon wafer 1 is 182.2 mm x 183.75 mm. The solution used for cleaning and polishing is a heated alkali solution, the alkali solution is a NaOH solution or a KOH solution (e.g. a NaOH solution), the concentration of the alkali solution is 0.5-4 vol% (e.g. 1.5 vol%), the heating temperature of the alkali solution is 40-70 °C (e.g. 60 °C), and the time for cleaning and polishing using the alkali solution is 150-400 s (e.g. 200 s).

[0030] In step 2, a first tunneling oxide layer 2 and a first intrinsic amorphous silicon layer with a relatively high crystallization rate are sequentially deposited on the back surface of the silicon wafer 1. It should be noted that the first intrinsic amorphous silicon layer is still amorphous silicon even though it has a relatively high crystallization rate because it has not been subjected to high temperature crystallization conversion treatment at about 800 °C.

[0031] In step 2, the first tunneling oxide layer 2 is prepared by one of the following methods: thermal oxidation, wet oxidation, nitric acid oxidation, ozone oxidation, and vapor deposition (e.g. vapor deposition), and the thickness of the first tunneling oxide layer 2 is 0.5-3 nm, preferably 0.5-2 nm (e.g. 1 nm).

[0032] In step 2, the first intrinsic amorphous silicon layer is deposited by chemical vapor deposition, preferably at least one of the following methods: LPCVD (low pressure chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), and APCVD (atmospheric pressure chemical vapor deposition), e.g. LPCVD, at a deposition temperature of 400-700 °C (e.g. 600 °C), a thickness of 10-30 nm (e.g. 20 nm), and a crystallization rate of 15-40% (e.g. 25%).

[0033] In step 3, a second intrinsic amorphous silicon layer with a relatively low crystallization rate is deposited on the back surface of the first intrinsic amorphous silicon layer. That is, the thickness of the second intrinsic amorphous silicon layer is greater than that of the first intrinsic amorphous silicon layer, and the crystallization rate of the second intrinsic amorphous silicon layer is lower than that of the first intrinsic amorphous silicon layer.

[0034] In step 3, the second intrinsic amorphous silicon layer is deposited by PVD (physical vapor deposition) at a deposition temperature of 100-300 °C (e.g. 300 °C), a thickness of 150-300 nm (e.g. 250 nm), and a crystallization rate of 3-20% (e.g. 10%).

[0035] The second intrinsic amorphous silicon is prepared by PVD, and its preparation temperature is lower, so the crystallization rate of the second intrinsic amorphous silicon is lower; the first intrinsic amorphous silicon is prepared by chemical vapor deposition such as LPCVD, and its preparation temperature is higher, so the crystallization rate of the first intrinsic amorphous silicon is higher.

[0036] Step 4: Boron diffusion doping is performed on the back surface of the silicon wafer 1 treated in step 3 by a diffusion-boosting-post-oxidation process (i.e., the boron diffusion doping process includes the following three stages in sequence: diffusion, boosting and post-oxidation), so that the first intrinsic amorphous silicon and the second intrinsic amorphous silicon are respectively converted into the first boron-doped polysilicon 3 and the second boron-doped polysilicon 4. Thus, after step 4, the full-area passivation contact structure composed of the first tunnel oxide layer 2, the first boron-doped polysilicon 3 and the second boron-doped polysilicon 4 is formed on the back surface of the silicon wafer 1, and boron-silicon glass (BSG) is formed on the back surface of the second boron-doped polysilicon 4. In addition, the boron diffusion doping also forms a wrap-around layer and BSG in the local area of the front surface and the edge of the silicon wafer 1.

[0037] The first boron-doped polysilicon 3 is formed by boron diffusion doping of the first intrinsic amorphous silicon, and the second boron-doped polysilicon 4 is formed by boron diffusion doping of the second intrinsic amorphous silicon. Therefore, the thickness of the first boron-doped polysilicon 3 is still less than that of the second boron-doped polysilicon 4 (the thickness of the first boron-doped polysilicon 3 refers to the thickness of the first intrinsic amorphous silicon, and the thickness of the second boron-doped polysilicon 4 refers to the thickness of the second intrinsic amorphous silicon); and because there is a difference in crystallization rate between the first intrinsic amorphous silicon and the second intrinsic amorphous silicon, during the boron diffusion doping in step 4, the boron diffusion source is more likely to migrate to the place with higher crystallization rate (such as the first intrinsic amorphous silicon), so the doping concentration of the first boron-doped polysilicon 3 is greater than that of the second boron-doped polysilicon 4, and the crystallization rate of the first boron-doped polysilicon 3 is still higher than that of the second boron-doped polysilicon 4. After boron diffusion doping, the crystallization rate of the first boron-doped polysilicon 3 is improved compared with that of the first intrinsic amorphous silicon, and the crystallization rate of the first boron-doped polysilicon 3 is 60-80% (such as 75%); and the crystallization rate of the second boron-doped polysilicon 4 is also improved compared with that of the second intrinsic amorphous silicon, and the crystallization rate of the second boron-doped polysilicon 4 is 40-60% (such as 55%).

[0038] In step 4, the boron diffusion source for boron diffusion doping is BCl3 or BBr3 (such as BCl3); the diffusion temperature is 800-880℃ (such as 840℃), the boosting temperature is 850-950℃ (such as 910℃), and the post-oxidation temperature is 850-900℃ (such as 890℃). The sheet resistance after boron diffusion doping is 250-450Ω / □ (such as 300Ω / □), the doping concentration of the first boron-doped polysilicon 3 is 1-3E20cm -3 (1.5E20cm -3), the doping concentration of the second boron-doped polysilicon 4 is 6-9E19 cm -3 (8E19 cm -3 ); the thickness of the BSG is 30-70 nm (e.g., 50 nm).

[0039] Step 5: removing the sputtering layer and the BSG formed on the front surface and the edge of the silicon wafer 1 by chain cleaning, while retaining the BSG on the back surface as a back surface protection layer.

[0040] In step 5, the solution for chain cleaning is an acid solution, preferably an HF solution, and the concentration of the solution is 3-10 vol% (e.g., 5 vol%).

[0041] Step 6: performing alkali polishing treatment on the front surface of the silicon wafer 1 to completely remove the sputtering layer (e.g., boron-doped layer) formed on the front surface due to boron diffusion doping.

[0042] In step 6, the alkali solution used for alkali polishing is a NaOH solution or a KOH solution (e.g., a NaOH solution), the concentration of the alkali solution is 0.5-4 vol% (e.g., 1.5 vol%), the reaction temperature for alkali polishing is 50-70°C (e.g., 60°C), and the time for alkali polishing is 150-400 s (e.g., 250 s).

[0043] Step 7: sequentially depositing a second tunnel oxide layer 5 and phosphorus-doped amorphous silicon on the front surface of the silicon wafer 1.

[0044] In step 7, the deposition method for the second tunnel oxide layer 5 and the phosphorus-doped amorphous silicon is PECVD or PVD (e.g., PVD), the thickness of the second tunnel oxide layer 5 is 0.5-2 nm (e.g., 0.8 nm), and the thickness of the phosphorus-doped amorphous silicon is 50-150 nm (e.g., 80 nm).

[0045] Step 8: performing high-temperature annealing on the silicon wafer 1 to activate the phosphorus atoms in the phosphorus-doped amorphous silicon and convert the phosphorus-doped amorphous silicon into phosphorus-doped polysilicon 6.

[0046] In step 8, the temperature for high-temperature annealing is 800-900°C (e.g., 850°C), and after annealing, the doping concentration of the phosphorus-doped polysilicon 6 is 3-6E20 cm -3 (4.5E20 cm -3 ); the thickness of the phosphorus-doped polysilicon 6 is the same as the thickness of the phosphorus-doped amorphous silicon.

[0047] After step 8, the full-area passivation contact structure composed of the second tunnel oxide layer 5 and the phosphorus-doped polysilicon 6 is formed on the front surface of the silicon wafer 1, and the phosphorus-silicon glass (PSG) is formed on the front surface of the phosphorus-doped polysilicon 6.

[0048] Step 9, laser patterning (i.e. laser selective processing) is performed on the backside and the frontside of the silicon wafer 1 after step 8. The BSG on the backside non-electrode contact area and the PSG on the frontside non-electrode contact area are selectively etched away by the laser.

[0049] In step 9, the frontside and the backside are laser patterned with the same process conditions. Take the backside laser patterning as an example, the process conditions are as follows: the laser is an infrared continuous laser, the laser wavelength is 700-2500 nm (e.g. 1064 nm), the equivalent diameter of the laser spot is 100-400 μm (e.g. 100 μm), the laser power is 50-100 W (e.g. 100 W), the laser scanning speed is 15000-50000 mm / s (e.g. 30000 mm / s), the area of the backside laser patterning accounts for 30-60% (e.g. 58%) of the total area of the backside, and thus the area of the second boron-doped polysilicon of the backside electrode contact area prepared in step 10 accounts for 40-70% (e.g. 42%) of the total area of the backside.

[0050] Step 10, etching is performed by using an alkaline solution to etch away the phosphorus-doped polysilicon 6 on the frontside non-electrode contact area and the second tunneling oxide layer 5 on the frontside non-electrode contact area (at this time, the frontside of the silicon wafer 1 on the frontside non-electrode contact area is exposed), and to etch away the second boron-doped polysilicon 4 on the backside non-electrode contact area which is thicker and has a lower crystallization rate.

[0051] The phosphorus-doped polysilicon 6 on the frontside non-electrode contact area and the second tunneling oxide layer 5 on the frontside non-electrode contact area and the second boron-doped polysilicon 4 on the backside non-electrode contact area (which has a lower doping concentration, a lower crystallization rate and is thicker) are etched away by the alkaline solution, while the first boron-doped polysilicon 3 on the backside non-electrode contact area and the first tunneling oxide layer 2 on the backside non-electrode contact area are both retained. The second tunneling oxide layer 5 and the phosphorus-doped polysilicon 6 on the frontside electrode contact area are not etched because they are protected by the PSG (because the etching rate of the alkaline solution on the phosphorus-doped polysilicon 6 is much higher than that on the PSG). Moreover, the first tunneling oxide layer 2 and the first boron-doped polysilicon 3 and the second boron-doped polysilicon 4 on the backside electrode contact area are also not etched because they are protected by the BSG; the first boron-doped polysilicon 3 on the backside non-electrode contact area is not etched by the alkaline solution because of its higher doping concentration and higher crystallization rate (i.e. the second boron-doped polysilicon 4 on the backside non-electrode contact area is etched away and the first boron-doped polysilicon 3 on the backside non-electrode contact area is retained by using the difference between the doping concentration and the crystallization rate of the second boron-doped polysilicon 4 and the first boron-doped polysilicon 3), and the first tunneling oxide layer 2 on the backside non-electrode contact area is also retained because it is protected by the first boron-doped polysilicon 3.

[0052] This is because: the etching rate of the alkaline solution to the second boron-doped polysilicon 4 is much greater than that to the BSG, so the second boron-doped polysilicon 4 of the back electrode contact area is not etched due to the protection of the BSG. The etching rate of the alkaline solution to the boron-doped polysilicon decreases with the increase of the boron doping concentration, and when the boron doping concentration is increased to 1E20cm -3 At this time, the etching is basically stopped; and the crystallization rate is related to the defect density, the higher the crystallization rate, the lower the defect density, which also causes the etching rate of the alkaline solution to decrease. Therefore, the high doping concentration and high crystallization rate of the relatively thin first boron-doped polysilicon 3 of the back non-electrode contact area jointly prevent the etching of the alkaline solution, so that the first boron-doped polysilicon 3 of the back non-electrode contact area and the first tunnel oxide layer 2 of the back non-electrode contact area are both retained, while the second boron-doped polysilicon 4 of the back non-electrode contact area is etched away. In this way, the parasitic absorption of light is reduced, good lateral transmission is achieved, and high-efficiency passivation effect is ensured.

[0053] In step 10, the alkaline solution is a NaOH solution or a KOH solution (such as a NaOH solution), the concentration of the alkaline solution is 0.5-4 vol% (preferably 1-3 vol%, such as 1 vol%), the etching temperature is 40-70°C (such as 60°C), and the etching time is 150-450 s (such as 200 s).

[0054] Among them, the above steps 2-4 and steps 9-10 are a preparation method of a selective boron-doped polysilicon passivation contact structure in this embodiment. The selective boron-doped polysilicon passivation contact structure, as shown in Figure 1 It includes: a silicon wafer 1, a first tunnel oxide layer 2 and a first boron-doped polysilicon 3 arranged on the back surface of the silicon wafer 1, and a second boron-doped polysilicon 4 arranged on the back electrode contact area of the first boron-doped polysilicon 3.

[0055] Among them, the above steps 2-10 are a preparation method of a selective passivation contact structure in this embodiment. The selective passivation contact structure, as shown in Figure 1 It includes: a silicon wafer 1, a selective boron-doped polysilicon passivation contact structure arranged on the back surface of the silicon wafer 1, and a selective phosphorus-doped polysilicon 6 passivation contact structure (the selective phosphorus-doped polysilicon 6 passivation contact structure includes a second tunnel oxide layer 5 and a phosphorus-doped polysilicon 6 arranged on the front electrode contact area of the silicon wafer 1 in sequence) arranged on the front surface of the silicon wafer 1.

[0056] In step 11, a pyramid structure of the front surface is formed on the front surface of the silicon wafer 1 exposed in the front non-electrode contact area by an alkaline texturing process, and the PSG of the front electrode contact area and the BSG of the back electrode contact area are removed by cleaning.

[0057] In step 11, the alkaline texturing process uses NaOH solution or KOH solution (such as KOH solution), the heating temperature is 30-70℃ (such as 65℃), and the texturing time is 100-300s (such as 200s).

[0058] In step 12, ALD (atomic layer deposition) method is used to deposit 2-10nm (such as 6nm) thick Al2O3 film on the front and back surfaces of the silicon wafer 1 treated in step 11 as a passivation film. At this time, the front surface of the silicon wafer 1 exposed in the non-electrode contact area and the front surface of the phosphorus-doped polysilicon 6 in the front electrode contact area are both deposited with the front Al2O3 film 8; and the back surface of the first boron-doped polysilicon 3 exposed in the non-electrode contact area and the back surface of the second boron-doped polysilicon 4 in the back electrode contact area are both deposited with the back Al2O3 film 7.

[0059] In step 13, PECVD method is used to deposit 60-80nm (such as 75nm) thick silicon nitride film on the front and back surfaces of the silicon wafer 1 treated in step 12 as an anti-reflection film. At this time, the front surface of the front Al2O3 film 8 is deposited with the front silicon nitride film 10; and the back surface of the back Al2O3 film 7 is deposited with the back silicon nitride film 9.

[0060] In step 14, the front and back surfaces of the silicon wafer 1 treated in step 13 are respectively subjected to metallization treatment to form the front electrode 12 and the back electrode 11 respectively. The front electrode 12 makes ohmic contact with the phosphorus-doped polysilicon 6 in the front electrode contact area after passing through the front silicon nitride film 10 and the front Al2O3 film 8 in sequence. And the back electrode 11 makes ohmic contact with the second boron-doped polysilicon 4 in the back electrode contact area after passing through the back silicon nitride film 9 and the back Al2O3 film 7 in sequence.

[0061] After step 14, a kind of double-sided selective TOPCon cell as shown in Figure 1 is obtained.

[0062] The double-sided selective TOPCon cell prepared by the utility model can reduce parasitic absorption to the maximum extent, and can realize passivation contact, reduce surface recombination, improve passivation performance of the backside non-electrode contact area and carrier lateral transport performance, and further reduce recombination, further improve passivation performance, and reduce process steps.

[0063] Comparative example

[0064] The preparation method of the double-sided selective TOPCon cell of the comparative example is specifically referred to the preparation steps of the above embodiment, and the main difference from the above embodiment is that:

[0065] The comparative example omits step 2 of the above embodiment, and in step 3 of the above embodiment, the comparative example is changed to: a first tunneling oxide layer and an intrinsic amorphous silicon are directly deposited on the back of the silicon wafer in sequence, the preparation method and thickness of the first tunneling oxide layer of the comparative example are referred to the first tunneling oxide layer of step 2 of the above embodiment, the deposition mode of the intrinsic amorphous silicon of the comparative example is PVD, the deposition temperature is 300 DEG C, and the thickness of the intrinsic amorphous silicon of the comparative example is 250 nm (that is, the deposition mode and thickness of the intrinsic amorphous silicon of the comparative example are referred to the second intrinsic amorphous silicon of step 3 of the above embodiment); therefore, after the alkaline solution etching treatment of step 10 of the above embodiment, the silicon wafer of the backside non-electrode contact area of the comparative example is exposed, and the backside electrode contact area retains the first tunneling oxide layer and the boron-doped polycrystalline silicon.

[0066] Performance test

[0067] The double-sided selective TOPCon cells prepared in the above examples and the comparative examples are respectively subjected to performance testing, and the test results are shown in Table 1. In Table 1, Voc is open circuit voltage, FF is fill factor, Isc is short circuit current, and Eta is cell photoelectric conversion efficiency.

[0068] Table 1

[0069]

[0070]

[0071] As can be seen from the above test results in Table 1, compared with the double-sided selective TOPCon cell of the above comparative example, the open circuit voltage, fill factor, short circuit current and photoelectric conversion efficiency of the double-sided selective TOPCon cell prepared in the above examples of the utility model are further improved.

[0072] It can be seen that: the above examples of the utility model realize passivation contact by retaining the first tunneling oxide layer and the first boron-doped polysilicon with thin thickness, high boron-doped concentration and high crystallization rate on the back surface, replace the boron-doped emitter of the traditional non-electrode contact area with one layer of the first boron-doped polysilicon with thin thickness, high boron-doped concentration and high crystallization rate, further reduce surface recombination, improve the passivation effect of the non-electrode contact area, and also realize good carrier lateral transmission. Moreover, the selective phosphorus-doped polysilicon is placed on the light-receiving surface (i.e. the front surface), and the selective second boron-doped polysilicon is placed on the back surface. The first boron-doped polysilicon with thin thickness in the non-electrode contact area on the back surface basically does not cause current loss, and the parasitic absorption of light is reduced to the maximum extent. In this way, the open circuit voltage, short circuit current and fill factor of the double-sided selective TOPCon cell prepared in the above examples of the utility model are well improved, and the photoelectric conversion efficiency of the cell is further improved.

[0073] Although the preferred embodiments of the utility model embodiments have been described, those skilled in the art can make other changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the utility model embodiments.

[0074] The above describes the technical solutions provided by the utility model in detail, and the principles and implementation manners of the utility model are described by applying specific examples. The above example description is only used to help understand the method and core idea of the utility model. Meanwhile, for those skilled in the art, the specific implementation manners and application scope will be changed according to the idea of the utility model. In conclusion, the content of the specification should not be understood as limiting the utility model.

Claims

1. A selective passivation contact structure, characterized in that, include: A silicon wafer, wherein a first tunneling oxide layer and a first boron-doped polysilicon are sequentially provided on the back side of the silicon wafer, and a second boron-doped polysilicon is also provided in the back electrode contact area of ​​the first boron-doped polysilicon. The thickness of the first boron-doped polysilicon is less than that of the second boron-doped polysilicon, the crystallinity of the first boron-doped polysilicon is greater than that of the second boron-doped polysilicon, and the doping concentration of the first boron-doped polysilicon is greater than that of the second boron-doped polysilicon.

2. The selective passivation contact structure according to claim 1, characterized in that, The area of ​​the second boron-doped polysilicon in the back electrode contact area accounts for 40-70% of the total back area.

3. The selective passivation contact structure according to claim 1, characterized in that, The thickness of the first tunneling oxide layer is 0.5–2 nm.

4. The selective passivation contact structure according to claim 1, characterized in that, The thickness of the first boron-doped polysilicon is 10–30 nm; the thickness of the second boron-doped polysilicon is 150–300 nm.

5. The selective passivation contact structure according to claim 1, characterized in that, The crystallinity of the first boron-doped polycrystalline silicon is 60-80%, and its doping concentration is 1-3E20cm⁻¹. -3 The crystallinity of the second boron-doped polycrystalline silicon is 40-60%, and its doping concentration is 6-9E19cm⁻¹. -3 .

6. The selective passivation contact structure according to claim 1, characterized in that, It also includes a second tunneling oxide layer and phosphorus-doped polycrystalline silicon sequentially disposed in the front electrode contact area of ​​the silicon wafer.

7. The selective passivation contact structure according to claim 6, characterized in that, The thickness of the second tunneling oxide layer is 0.5–2 nm.

8. The selective passivation contact structure according to claim 6, characterized in that, The phosphorus-doped polycrystalline silicon has a thickness of 50–150 nm and a doping concentration of 3–6E20 cm⁻¹. -3 .

9. A bifacial selective TOPCon battery, characterized in that, It includes a selective passivation contact structure as described in any one of claims 1-8; the surface of the non-electrode contact area on the front side of the silicon wafer is a textured surface with a pyramid structure; a front passivation film and a front anti-reflection film are sequentially provided on the front side of the textured surface of the silicon wafer in the non-electrode contact area and the front side of the phosphorus-doped polysilicon in the front electrode contact area; a back passivation film and a back anti-reflection film are sequentially provided on the back side of the first boron-doped polysilicon in the back non-electrode contact area and the second boron-doped polysilicon in the back electrode contact area. The selective TOPCon cell further includes a front electrode and a back electrode; the front electrode passes through the front antireflection film and the front passivation film in sequence, and then makes ohmic contact with the phosphorus-doped polycrystalline silicon in the contact area of ​​the front electrode; the back electrode passes through the back antireflection film and the back passivation film in sequence, and then makes ohmic contact with the second boron-doped polycrystalline silicon in the contact area of ​​the back electrode.

10. A bifacial selective TOPCon battery according to claim 9, characterized in that, Both the front passivation film and the back passivation film are Al2O3 films with a thickness of 2-10 nm; both the front antireflection film and the back antireflection film are silicon nitride films with a thickness of 60-80 nm.

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