Solar cell

Abstract

The utility model provides a solar cell, and the cell comprises a silicon substrate which comprises a first main surface and a second main surface, and the first main surface is provided with a first groove; the first functional layer is formed in the first groove and other parts of the first main surface; the first main surface is provided with a first grid line electrode and a second grid line electrode, a part of the first grid line electrode is located in the first groove and is higher than the first groove, the first grid line electrode and the second grid line electrode are overlapped at the position of the first groove, and the second grid line electrode covers the peripheral surface of the first grid line electrode at the overlapped position to form a first main surface covering part; the first main surface covering part comprises a first side surface covering part and a second side surface covering part which cover the surfaces of the two sides of the first grid line electrode respectively, and one end, close to the first main surface, of at least one of the first side surface covering part and the second side surface covering part extends into the first groove. According to the invention, the overlapping area of the grid line electrode can be increased without increasing the shading area, and the use performance of the battery is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a solar cell. BACKGROUND

[0002] The solar cell needs to use metal electrodes to transport the current generated by the cell under light to the external circuit, and the electrodes of the cell include front electrodes and back electrodes. Due to the consideration of the shading of incident light, the front electrodes generally use an "H" type structure (including main grids and fine grids). From the perspective of electrical design of the cell, the contribution of grid line resistance to the total series resistance depends on the resistivity and volume of the grid line, and in the case of a certain length, it depends on the width and height of the grid line. From the optical point of view, reducing the width of the grid line can reduce the shading area of the grid line, so that more incident light enters the front of the cell to improve the performance of the cell.

[0003] At present, the mainstream grid line pattern in the industry mainly includes the following three schemes: the first scheme is to design the fine grid to directly intersect with the main grid line. This scheme will make the overlapping area of the fine grid and the main grid paste too small, causing the current in the fine grid to be collected to the main grid, and the resistance is too high, thereby affecting the electrical performance; the second scheme is to design a connection structure similar to the legs of a centipede on the main grid, and the contact end point on the fine grid line is designed to overlap and connect with the connection structure; the third scheme is to set a gradual line on the area of the fine grid lapped with the main grid, which gradually narrows from the main grid to both sides. The above-mentioned second and third schemes will increase the printing area, thereby increasing the shading area and affecting the performance of the cell.

[0004] Therefore, it is urgent to provide a solar cell to solve the above technical problems. CONTENT OF THE INVENTION

[0005] Based on this, in order to overcome the defects of the prior art, the present application provides a solar cell and a preparation method thereof, which solves the problem of large lap joint resistance and large printing area of the main fine grid lap joint area in the prior art, which easily affects the electrical performance.

[0006] In order to achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0007] In one aspect, the application provides a solar cell, comprising: a silicon substrate comprising a first main surface and a second main surface, the first main surface being provided with a plurality of first grooves extending into the silicon substrate; a first functional layer formed on the first grooves and other parts of the first main surface; the first main surface of the silicon substrate is further provided with a plurality of first grid electrodes and second grid electrodes, which are arranged on the surface of the first functional layer away from the silicon substrate, a part of the first grid electrodes is located in the first grooves and is higher than the first grooves, the first grid electrodes and the second grid electrodes overlap each other at the positions of the first grooves, and at the overlapping positions, the second grid electrodes cover the peripheral surfaces of the first grid electrodes to form a first main surface covering part; the first main surface covering part comprises a first side surface covering part and a second side surface covering part which are oppositely arranged and respectively cover the two side surfaces of the first grid electrodes, and at least one of the first side surface covering part and the second side surface covering part extends into the corresponding first groove near one end of the first main surface of the silicon substrate.

[0008] Preferably, the solar cell further comprises: a second functional layer, third grid electrodes and fourth grid electrodes; the second main surface is provided with a plurality of second grooves extending into the silicon substrate, the second functional layer is arranged on the second grooves and other parts of the second main surface; a plurality of third grid electrodes and fourth grid electrodes are arranged on the surface of the second functional layer away from the silicon substrate, a part of the third grid electrodes is located in the second grooves and is higher than the second grooves, the third grid electrodes and the fourth grid electrodes overlap each other at the positions of the second grooves, and at the overlapping positions, the fourth grid electrodes cover the peripheral surfaces of the third grid electrodes to form a second main surface covering part; the second main surface covering part comprises a third side surface covering part and a fourth side surface covering part which are oppositely arranged and respectively cover the two side surfaces of the third grid electrodes, and at least one of the third side surface covering part and the fourth side surface covering part extends into the corresponding second groove near one end of the second main surface of the silicon substrate.

[0009] Preferably, the first side surface covering part and the second side surface covering part both extend into the corresponding first groove near one end of the first main surface of the silicon substrate; and / or, the third side surface covering part and the fourth side surface covering part both extend into the corresponding second groove near one end of the second main surface of the silicon substrate.

[0010] Preferably, the silicon substrate comprises an N-type silicon substrate; the first functional layer comprises an emitter layer, a first passivation layer and a first passivation anti-reflection layer arranged in sequence from inside to outside; the first grid electrodes or the second grid electrodes penetrate the first passivation anti-reflection layer and the first passivation layer to contact the emitter layer at the bottom positions of the first grooves.

[0011] Preferably, the first side cover and / or the second side cover extends to the side of the first recess, and the side of the first recess is in contact with the first passivation anti-reflection layer.

[0012] Preferably, the second functional layer comprises, from inside to outside, a tunneling oxide layer, a doped polysilicon layer, and a second passivation anti-reflection layer; and the third gate electrode or the fourth gate electrode penetrates the second passivation anti-reflection layer at the bottom of the second recess and is in contact with the doped polysilicon layer.

[0013] Preferably, the third side cover and / or the fourth side cover extends to the side of the second recess, and the side of the second recess is in contact with the second passivation anti-reflection layer.

[0014] Preferably, the length L of the first recess is greater than the width of the first gate electrode; the width W of the first recess is less than or equal to the width of the second gate electrode; the length L of the second recess is greater than the width of the third gate electrode; the width W of the second recess is less than or equal to the width of the fourth gate electrode; and / or, the width of the first gate electrode and the third gate electrode is 40-80 μm; the width of the second gate electrode and the fourth gate electrode is 15-30 μm; the length L of the first recess and the second recess is 0.1-1 mm; the width W of the first recess and the second recess is 10-30 μm; and the depth h of the first recess and the second recess is 2-10 μm.

[0015] Preferably, the first gate electrode is a fine gate electrode and the second gate electrode is a main gate electrode; or, the first gate electrode is a main gate electrode and the second gate electrode is a fine gate electrode; the third gate electrode is a fine gate electrode and the fourth gate electrode is a main gate electrode; or, the third gate electrode is a main gate electrode and the fourth gate electrode is a fine gate electrode.

[0016] Preferably, the width of the main gate electrode is 40-80 μm, and the height is 6-15 μm; the width of the fine gate electrode is 15-30 μm, and the height is 6-15 μm.

[0017] In another aspect, the application also provides a preparation method of a solar cell, which comprises:

[0018] S1, performing groove processing on the first main surface of the silicon substrate to obtain a first recess;

[0019] S2, forming a first functional layer on the first recess and other parts of the first main surface;

[0020] S3, forming a first gate line electrode and a second gate line electrode on the side of the first functional layer away from the silicon substrate, and the first gate line electrode protrudes outward from the first groove, the second gate line electrode overlaps the first gate line electrode, and at the overlapping part, the second gate line electrode covers the outer peripheral surface of the first gate line electrode to form a first main surface covering part, the first main surface covering part includes a first side surface covering part and a second side surface covering part oppositely arranged and respectively covering the two side surfaces of the first gate line electrode, and at least one of the first side surface covering part and the second side surface covering part extends to the corresponding first groove near one end of the first main surface of the silicon substrate.

[0021] Preferably, the S1 further includes grooving the second main surface of the silicon substrate to obtain a second groove; before the S3, the method further includes: forming a second functional layer on the second groove and other parts of the second main surface; the method further includes: forming a third gate line electrode and a fourth gate line electrode on the side of the second functional layer away from the silicon substrate, and the third gate line electrode protrudes outward from the second groove, the third gate line electrode overlaps the fourth gate line electrode, and at the overlapping part, the fourth gate line electrode covers the outer peripheral surface of the third gate line electrode to form a second main surface covering part, the second main surface covering part includes a third side surface covering part and a fourth side surface covering part oppositely arranged and respectively covering the two side surfaces of the third gate line electrode, and at least one of the third side surface covering part and the fourth side surface covering part extends to the corresponding second groove near one end of the second main surface of the silicon substrate.

[0022] Preferably, the S1 specifically includes: oxidizing the first main surface and the second main surface of the silicon substrate to form a mask oxide layer on the surface; laser processing the first main surface and the second main surface of the silicon substrate after oxidation; wherein the laser processing region corresponds to the overlapping region of the first gate line electrode and the second gate line electrode and the third gate line electrode and the fourth gate line electrode respectively; etching the laser region of the silicon substrate after laser processing in an alkali solution; removing the mask oxide layer of the silicon substrate after etching by acid washing to obtain a silicon substrate with the first groove and the second groove.

[0023] Preferably, the laser processing laser parameters are as follows: the laser is a laser wavelength of 500-550 nanometers, the laser spot side length is 10-30 μm, and the length of the laser line along the direction of the fine gate electrode is 0.1-1 mm; the alkali washing parameters of the alkali solution are as follows: the alkali solution contains at least one of KOH, NaOH and TMAH, the alkali solution contains etching additives, the alkali solution etching time is 200-1000 s, and the etching depth is 2-10 μm.

[0024] Preferably, the first functional layer comprises an emitter layer, a first passivation layer and a first passivation anti-reflection layer, and the S2 comprises: forming a first diffusion source on the bottom wall, side wall and other parts of the first recess of the first main surface of the silicon substrate, and performing diffusion treatment to form a continuous emitter layer and a first doped silicon glass layer on the bottom wall, side wall and other parts of the first recess; removing the first doped silicon glass layer formed on the first main surface and the periphery of the silicon substrate and the bottom wall and side wall of the first recess; forming a continuous first passivation layer on the emitter layer surface of the first main surface of the silicon substrate and the bottom wall and side wall of the first recess, and forming the first passivation anti-reflection layer on the surface of the first passivation layer.

[0025] Preferably, the second functional layer comprises a tunneling oxide layer, a doped polysilicon layer and a second passivation anti-reflection layer, and the S2 comprises: forming a continuous tunneling oxide layer on the bottom wall, side wall and other parts of the second recess of the second main surface of the silicon substrate, and forming a second diffusion source on the surface of the tunneling oxide layer, and performing diffusion treatment to form a continuous doped polysilicon layer and a second doped silicon glass layer on the surface of the tunneling oxide layer; removing the second doped silicon glass layer formed on the second main surface and the periphery of the silicon substrate and the bottom wall and side wall of the second recess; forming a continuous second passivation anti-reflection layer on the surface of the doped polysilicon layer of the second main surface of the silicon substrate and the bottom wall and side wall of the second recess.

[0026] The beneficial effects of the present application are as follows:

[0027] The silicon substrate in the present application comprises a first main surface and a second main surface, a first groove of a certain depth is formed on the first main surface at the overlapping position of the first grid line electrode and the second grid line electrode, part of the first grid line electrode is located in the first groove and is higher than the first groove, the second grid line electrode covers the outer circumferential surface of the first grid line electrode at the overlapping position to form a first main surface covering part, at least one end of the first side surface covering part in the first main surface covering part and the second side surface covering part extend into the first groove during printing. Due to the existence of the first groove, when the first grid line electrode and the second grid line electrode are printed in the groove of lower height, the depth of the groove increases the height of the grid line, and at the same time, the entire contour circumference of the grid line is also increased, when the first grid line electrode and the second grid line electrode overlap at the position of the first groove, the overlapping area of the first grid line electrode and the second grid line electrode can be increased without increasing the light shielding area, thereby reducing the overlapping resistance existing in the connection of the first grid line electrode and the second grid line electrode, and when the current of the first grid line electrode converges to the second grid line electrode, the resistance is reduced, and due to the reduction of the overlapping resistance, under the premise of the same electrical performance, the width of the first grid line electrode and the second grid line electrode can be reduced, thereby solving the problem of large light shielding area of the first grid line electrode and the second grid line electrode in the connection area, and effectively increasing the overlapping area of the connection area to ensure the use performance of the battery. Compared with the way of not setting the groove on the first main surface of the silicon substrate, but making the grid line wider to increase the contact area, although the present application increases the process by opening the groove, the contact area of the first grid line electrode and the second grid line electrode can be increased without increasing the light shielding area, so that the optimization of the first grid line electrode and the second grid line electrode at the connection and the preparation method thereof in the present application solve the problems of large overlapping resistance existing in the main and fine grid connection structure of the existing solar cell, or the large paste printing area of the main and fine grid connection area easily affecting the electrical performance. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a cross-sectional schematic view of the solar cell in the present embodiment;

[0029] Figure 2 is a schematic view of the intersection of the first grid line electrode and the second grid line electrode at the position of the first groove in the present embodiment;

[0030] Figure 3 is a partial schematic view of the first main surface covering part in the present embodiment;

[0031] Figure 4 is a partial schematic view of the second main surface covering part in the present embodiment;

[0032] Figure 5 is a cross-sectional schematic view of the silicon substrate in the present embodiment;

[0033] Figure 6Fig. 2 is a cross-sectional view of forming a mask oxide layer on a silicon substrate in the embodiment;

[0034] Figure 7 Fig. 3 is a cross-sectional view of forming a first groove and a second groove on a silicon substrate in the embodiment;

[0035] Figure 8 Fig. 4 is a cross-sectional view of removing the mask oxide layer from the silicon substrate in the embodiment;

[0036] Figure 9 Fig. 5 is a cross-sectional view of forming a textured surface on a first main surface and a bottom of the first groove of the silicon substrate in the embodiment;

[0037] Figure 10 Fig. 6 is a cross-sectional view of forming an emitter layer with a height difference on the first main surface and a first passivation anti-reflection layer and a doped polysilicon layer with a height difference on a second main surface of the silicon substrate in the embodiment;

[0038] Figure 11 Fig. 7 is a cross-sectional view of forming a first passivation layer and a first passivation anti-reflection layer on the first main surface and a second passivation anti-reflection layer on the second main surface of the silicon substrate in the embodiment.

[0039] Reference signs:

[0040] 1, silicon substrate; 11, first groove; 12, second groove; 13, emitter layer; 14, first passivation layer; 15, first passivation anti-reflection layer; 16, first passivation anti-reflection layer; 17, doped polysilicon layer; 18, second passivation anti-reflection layer; 19, mask oxide layer; 2, first gate line electrode; 3, second gate line electrode; 4, first main surface covering portion; 41, first side surface covering portion; 42, second side surface covering portion; 43, front top surface covering portion; 5, third gate line electrode; 6, fourth gate line electrode; 7, second main surface covering portion; 71, third side surface covering portion; 72, fourth side surface covering portion; 73, back top surface covering portion. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0042] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The shape, number and proportion of the components when actually implemented can be arbitrarily changed, and the layout pattern of the components can also be more complex.

[0043] The orientations or positional relationships indicated by terms such as "upper," "lower," "left," "right," "middle," "longitudinal," "lateral," "horizontal," "inner," "outer," "radial," and "circumferential" used in this specification are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the purpose of simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] This application provides a solar cell and its fabrication method, which solves the problems of high overlap resistance and large printing area of ​​the main-fine grid connection structure in existing solar cells, which easily affect electrical performance.

[0045] The following describes in detail a solar cell provided in this embodiment with reference to the accompanying drawings. Figures 1-3 As shown, the solar cell includes a silicon substrate 1 and a first functional layer. The silicon substrate 1 includes a first main surface and a second main surface. The first main surface is provided with a plurality of first grooves 11 extending into the silicon substrate 1 (e.g., ...). Figure 2 As shown, the first functional layer is formed on the first main surface of the first groove 11 and other parts. The first main surface of the silicon substrate 1 is also provided with a plurality of first gate electrodes 2 and second gate electrodes 3. The first gate electrodes 2 and second gate electrodes 3 are disposed on the surface of the first functional layer facing away from the silicon substrate 1. A portion of the first gate electrodes 2 is located in the first groove 11 and is higher than the first groove 11. The first gate electrodes 2 and the second gate electrodes 3 overlap each other at the position of the first groove 11, and at the overlap, the second gate electrodes 3 cover the outer peripheral surface of the first gate electrodes 2 to form a first main surface covering portion 4. The first main surface covering portion 4 includes a first side covering portion 41 and a second side covering portion 42 that are disposed opposite to each other and respectively cover the two sides of the first gate electrodes 2. At least one end of the first side covering portion 41 and the second side covering portion 42 near the first main surface of the silicon substrate 1 extends into the corresponding first groove 11.

[0046] The connecting position of the first gate line electrode 2 and the second gate line electrode 3 is optimized in the embodiment. A plurality of first grooves 11 are arranged on the first main surface of the silicon substrate 1. The arrangement position of the first grooves 11 is determined according to the connecting position of the first gate line electrode 2 and the second gate line electrode 3. When the printed screen layout is determined, the connecting position of the first gate line electrode 2 and the second gate line electrode 3 is confirmed. Thus, the overlapping position of the first gate line electrode 2 and the second gate line electrode 3 on the first main surface of the silicon substrate 1 is determined. In other words, the position of the first groove 11 corresponds to the connecting position of the first gate line electrode 2 and the second gate line electrode 3. During printing, part of the first gate line electrode 2 is located in the first groove 11 and is higher than the first groove 11. The second gate line electrode 3 covers the outer circumferential surface of the first gate line electrode 2 at the position of the first groove 11 to form a first main surface covering portion 4. The first main surface covering portion 4 includes oppositely arranged first side surface covering portions 41 and second side surface covering portions 42 and a normal top surface covering portion 43 connecting the first side surface covering portions 41 and the second side surface covering portions 42. The first side surface covering portions 41 and the second side surface covering portions 42 cover the two side surfaces of the first gate line electrode 2, respectively. The normal top surface covering portion 43 covers the top surface of the first gate line electrode 2. At least one of the first side surface covering portions 41 and the second side surface covering portions 42 extends to the corresponding first groove 11 near one end of the first main surface. Thus, the first groove 11 can increase the overlapping area of the first gate line electrode 2 and the second gate line electrode 3. In other words, when the first gate line electrode 2 is printed in the first groove 11 with a low pile on the first main surface, the overall height of the first gate line electrode 2 is increased due to the first groove 11 (compared with the case where the first groove 11 is not arranged, the first gate line electrode 2 in the embodiment needs to be filled into the first groove 11 during printing). Meanwhile, the overall contour length of the first gate line electrode 2 is increased (compared with the case where the first groove 11 is not arranged, the first gate line electrode 2 in the embodiment increases the path length in the first groove 11 during printing). When the second gate line electrode 3 overlaps the first gate line electrode 2, the second gate line electrode 3 overlaps the first gate line electrode 2 along the contour of the first gate line electrode 2 in the first groove 11. Thus, the overlapping area of the first gate line electrode 2 and the second gate line electrode 3 is increased without increasing the light shielding area. When the current in the second gate line electrode 3 is collected to the first gate line electrode 2, the resistance is reduced. Thus, the problem of large light shielding area of the first gate line electrode 2 and the second gate line electrode 3 at the connecting region is solved. Meanwhile, the overlapping area of the connecting region is effectively increased to ensure the use performance of the battery.

[0047] Please refer to Figure 1 and Figure 4As shown, in the present embodiment, it is also required to be explained that the solar cell further comprises a second functional layer, a third grid line electrode 5 and a fourth grid line electrode 6; the second main surface is provided with a plurality of second grooves 12 extending into the silicon substrate 1, and the second functional layer is arranged on the second grooves 12 and other parts of the second main surface; a plurality of third grid line electrodes 5 and fourth grid line electrodes 6 are arranged on the surface of the second functional layer away from the silicon substrate 1, and part of the third grid line electrodes 5 is located in the second grooves 12 and is higher than the second grooves 12; the third grid line electrodes 5 and the fourth grid line electrodes 6 overlap each other at the position of the second grooves 12, and the fourth grid line electrodes 6 cover the outer peripheral surface of the third grid line electrodes 5 to form a second main surface covering part 7 at the overlapping position; the second main surface covering part 7 comprises a third side surface covering part 71, a fourth side surface covering part 72 and a back top surface covering part 73 connecting the two, the third side surface covering part 71 and the fourth side surface covering part 72 are oppositely arranged and respectively cover the opposite two side surfaces of the third grid line electrodes 5, the back top surface covering part 73 covers the top surface of the third grid line electrodes 5, and at least one of the third side surface covering part 71 and the fourth side surface covering part 72 extends to the corresponding second groove 12 at one end close to the second main surface of the silicon substrate 1. Similarly, the arrangement of the plurality of second grooves 12 on the second main surface of the silicon substrate 1 is also determined according to the positions of the third grid line electrodes 5 and the fourth grid line electrodes 6 corresponding to the printed screen pattern, and will not be described in detail here.

[0048] As shown in Figure 1 , Figure 3 and Figure 4 , in some embodiments, one end of the first side surface covering part 41 and the second side surface covering part 42 close to the first main surface of the silicon substrate 1 is located in the corresponding first groove 11; one end of the third side surface covering part 71 and the fourth side surface covering part 72 close to the second main surface of the silicon substrate 1 is located in the corresponding second groove 12; by locating both ends of the first side surface covering part 41 and the second side surface covering part 42 in the first groove 11, the profile perimeter of the grid lines and the overlapping area of the first grid line electrode 2 and the second grid line electrode 3 can be further increased; by locating both ends of the third side surface covering part 71 and the fourth side surface covering part 72 in the second groove 12, the profile perimeter of the grid lines and the overlapping area of the third grid line electrode 5 and the fourth grid line electrode 6 can be further increased.

[0049] As shown in Figure 1 and Figure 2As shown, in the embodiment, it is also needed to be explained that the first gate line electrode 2 and the second gate line electrode 3 in the embodiment are both provided as a plurality of, the plurality of first gate line electrodes 2 are arranged at equal intervals along the first direction x, and the first gate line electrodes 2 extend along the second direction y; the plurality of second gate line electrodes 3 are arranged at equal intervals along the second direction y, and the second gate line electrodes 3 extend along the first direction x, the first direction x and the second direction y are perpendicular to each other, thereby, the plurality of first gate line electrodes 2 and the second gate line electrodes 3 intersect to form a plurality of connection points, the positions and the number of the first grooves 11 are one-to-one corresponding to the positions and the number of the connection points, it can be understood that the first grooves 11 provided on the first main surface of the silicon substrate 1 in the embodiment are not opened on the whole surface along the extension direction of the first gate line electrode 2 or the second gate line electrode 3, but are locally opened according to the position of the connection point of the first gate line electrode 2 or the second gate line electrode 3.

[0050] The third gate line electrode 5 and the fourth gate line electrode 6 in the embodiment are both provided as a plurality of, the plurality of third gate line electrodes 5 are arranged at equal intervals along the first direction x, and the third gate line electrodes 5 extend along the second direction y; the plurality of fourth gate line electrodes 6 are arranged at equal intervals along the second direction y, and the fourth gate line electrodes 6 extend along the first direction x, the first direction x and the second direction y are perpendicular to each other, thereby, the plurality of third gate line electrodes 5 and the fourth gate line electrodes 6 intersect to form a plurality of connection points, the positions and the number of the second grooves 12 are one-to-one corresponding to the positions and the number of the connection points, it can be understood that the second grooves 12 provided on the second main surface of the silicon substrate 1 in the embodiment are not opened on the whole surface along the extension direction of the third gate line electrode 5 or the fourth gate line electrode 6, but are locally opened according to the position of the connection point of the third gate line electrode 5 or the fourth gate line electrode 6.

[0051] Please continue to refer to Figure 1 and Figure 2 As shown, the first gate line electrode 2 is a fine gate electrode and the second gate line electrode 3 is a main gate electrode, or, the first gate line electrode 2 is a main gate electrode and the second gate line electrode 3 is a fine gate electrode. The third gate line electrode 5 is a fine gate electrode and the fourth gate line electrode 6 is a main gate electrode, or, the third gate line electrode 5 is a main gate electrode and the fourth gate line electrode 6 is a fine gate electrode. In the embodiment, the first gate line electrode 2 is provided as a first main surface main gate, the second gate line electrode 3 is provided as a first main surface fine gate, the third gate line electrode 5 is provided as a second main surface main gate, and the fourth gate line electrode 6 is provided as a second main surface fine gate, for example, the number of the first gate line electrode 2 can be set to 16, and the number of the second gate line electrode 3 can be set to 130; the number of the third gate line electrode 5 can be set to 16, and the number of the fourth gate line electrode 6 can be set to 180.

[0052] In some embodiments, the width of the first gate electrode 2 and the third gate electrode 5 is 40-80 μm, such as 40 μm, 50 μm, 60 μm, 70 μm, or 80 μm, and the height is 6-15 μm, such as 6 μm, 8 μm, 10 μm, 12 μm, or 15 μm. Preferably, the width of the first gate electrode 2 and the third gate electrode 5 is 50 μm and the height is 10 μm. The width of the second gate electrode 3 and the fourth gate electrode 6 is 15-30 μm, such as 15 μm, 18 μm, 20 μm, 25 μm, 28 μm, or 30 μm, and the height is 6-15 μm, such as 6 μm, 9 μm, 10 μm, 12 μm, or 15 μm. Preferably, the width of the second gate electrode 3 and the fourth gate electrode 6 is 20 μm and the height is 10 μm. It should be noted that the width of the main gate electrode is 40-80μm and the height is 6-15μm; the width of the fine gate electrode is 15-30μm and the height is 6-15μm.

[0053] The first groove 11 is rectangular at the intersection of the first gate electrode 2 and the second gate electrode 3. The longer side of this rectangle extends along the first direction x, i.e., the length of the second gate electrode 3 (the fine gate on the first main surface), and the wider side extends along the second direction y, i.e., the length of the first gate electrode 2 (the main gate on the first main surface). The length of the rectangle is greater than the width of the first gate electrode 2, ensuring that both sides of the first gate electrode 2 are within the groove when printed at the position of the first groove 11. Similarly, the second groove 12 is rectangular at the intersection of the third gate electrode 5 and the fourth gate electrode 6. The longer side of this rectangle extends along the first direction x, i.e., the length of the fourth gate electrode 6 (the fine gate on the second main surface), and the wider side extends along the second direction y, i.e., the length of the third gate electrode 5 (the main gate on the second main surface). The length of the rectangle is greater than the width of the third gate electrode 5.

[0054] In some embodiments, the depths h of the first groove 11 and the second groove 12 are equal, and each is 2-10 μm, such as 2 μm, 4 μm, 6 μm, 8 μm, or 10 μm, etc. If the depth h is too shallow, the profile perimeter of the grid line cannot meet the requirements, and the purpose of the utility model cannot be achieved. Since the thickness dimension of the silicon substrate 1 is limited, if the depth h is too deep, the silicon substrate 1 is easily affected. Therefore, in the embodiment, the depth h of the first groove 11 and the second groove 12 is 2-10 μm according to the above factors. When the laser is used to etch the positions of the first groove 11 and the second groove 12, the etching depth is 2-10 μm, so that the depth h of the first groove 11 and the second groove 12 formed is 2-10 μm. Thus, due to the existence of the first groove 11, the first main surface of the silicon substrate 1 undergoes B diffusion to form an emitter layer 13 with a height difference. That is, the connection of the first grid electrode 2 and the second grid electrode 3 is the emitter layer 13 with a height difference, and the height difference of the emitter layer 13 is 2-10 μm, that is, the depth h of the first groove 11. Due to the existence of the second groove 12, the second main surface of the silicon substrate 1 is polished, and the tunneling oxide layer 16 and the doped polysilicon layer 17 with a height difference are deposited on the second main surface. The height difference is consistent with the first main surface.

[0055] The length L of the first groove 11 is greater than the width of the first grid electrode 2 (the first main surface main grid), and the length L of the second groove 12 is greater than the width of the third grid electrode 5 (the second main surface main grid). Preferably, the length L of the first groove 11 and the second groove 12 is 0.1-1 mm, such as 0.1 mm, 0.4 mm, 0.6 mm, 0.9 mm, or 1 mm, etc. If the length L is too short, the profile perimeter of the grid line also cannot meet the requirements, and the purpose of the utility model cannot be achieved. If the length L is too long, more slurry will be consumed. Therefore, in the embodiment, the length L of the first groove 11 and the second groove 12 is 0.1-1 mm according to the above factors.

[0056] The width W of the first groove 11 is less than or equal to the width of the second grid electrode 3 such as the first main surface fine grid, and the width W of the second groove 12 is less than or equal to the width of the fourth grid electrode 6 such as the second main surface fine grid. Preferably, the width W of the first groove 11 and the second groove 12 is 10-30 μm, such as 10 μm, 12 μm, 16 μm, 18 μm, 20 μm, 24 μm, 28 μm, 30 μm, etc. If the width W is greater than the width of the fine grid, it will cause the fine grid to increase the width of the line width when printed in the groove, the light shielding area becomes larger, and the electrical performance is affected. Therefore, in the embodiment, the width W of the first groove 11 and the second groove 12 is less than or equal to the width of the fine grid according to the above factors.

[0057] In the embodiment, it is also to be noted that the silicon substrate 1 can be set as an N-type silicon substrate, and of course can also be set as a P-type silicon substrate, and in the embodiment, only the N-type silicon substrate is taken as an example for description.

[0058] Please refer to Figure 1 and Figure 3 , the first functional layer includes the emitter layer 13, the first passivation layer 14 and the first passivation anti-reflection layer 15, the first main surface of the N-type silicon substrate and the bottom of the first groove 11 form a high-low different textured surface, and the emitter layer 13, the first passivation layer 14 and the first passivation anti-reflection layer 15 are sequentially arranged from inside to outside above the textured surface, and the emitter layer 13 between the first main surface and the bottom of the first groove 11 is connected to each other, and the first passivation layer 14 and the first passivation anti-reflection layer 15 are also connected to each other respectively, in other words, the emitter layer 13, the first passivation layer 14 and the first passivation anti-reflection layer 15 are sequentially arranged from inside to outside on the side surface of the first groove 11. The first gate line electrode 2 and the second gate line electrode 3 are arranged on the surface of the first passivation anti-reflection layer 15, the first gate line electrode 2 or the second gate line electrode 3 sequentially penetrates the first passivation anti-reflection layer 15 and the first passivation layer 14 at the bottom position of the first groove 11 and then contacts the emitter layer 13, mainly penetrating the first passivation anti-reflection layer 15 and the first passivation layer 14 to contact the emitter layer 13, therefore, if the first gate line electrode 2 is set as a first main surface fine gate, the first gate line electrode 2 penetrates the first passivation anti-reflection layer 15 and the first passivation layer 14 at the bottom position of the first groove 11 to contact the emitter layer 13; if the second gate line electrode 3 is set as a first main surface fine gate, the second gate line electrode 3 penetrates the first passivation anti-reflection layer 15 and the first passivation layer 14 at the bottom position of the first groove 11 to contact the emitter layer 13. The second gate line electrode 3 overlaps the first gate line electrode 2 at the position of the first groove 11 and covers the outer peripheral surface of the first gate line electrode 2 to form a first main surface covering part 4, the first side surface covering part 41 and the second side surface covering part 42 in the first main surface covering part 4 respectively contact the first passivation anti-reflection layer 15 on the side surface of the first groove 11, if the second gate line electrode 3 is set as a first main surface fine gate, the second gate line electrode 3 also penetrates the first passivation anti-reflection layer 15 and the first passivation layer 14 at the side surface position of the first groove 11 to contact the emitter layer 13.

[0059] Please refer to Figure 1 and Figure 4As shown, the second functional layer includes a tunneling oxide layer 16, a doped polysilicon layer 17, and a second passivation anti-reflection layer 18. The second main surface of the N-type silicon substrate and the bottom of the second groove 12 are sequentially provided with the tunneling oxide layer 16, the doped polysilicon layer 17, and the second passivation anti-reflection layer 18 from inside to outside, and the tunneling oxide layers 16 covering the second main surface and the bottom of the second groove 12 are connected to each other, and the doped polysilicon layers 17 and the second passivation anti-reflection layers 18 are also connected to each other, respectively. In other words, the side surface of the second groove 12 is also sequentially provided with the tunneling oxide layer 16, the doped polysilicon layer 17, and the second passivation anti-reflection layer 18 from inside to outside. The third gate line electrode 5 and the fourth gate line electrode 6 are provided on the surface of the second passivation anti-reflection layer 18, and the third gate line electrode 5 or the fourth gate line electrode 6 penetrates the second passivation anti-reflection layer 18 to contact the doped polysilicon layer 17 at the bottom position of the second groove 12, mainly in the form of a fine gate penetrating the second passivation anti-reflection layer 18 to contact the doped polysilicon layer 17. Therefore, if the third gate line electrode 5 is set as a fine gate on the second main surface, the third gate line electrode 5 penetrates the second passivation anti-reflection layer 18 to contact the doped polysilicon layer 17 at the bottom position of the second groove 12; if the fourth gate line electrode 6 is set as a fine gate on the second main surface, the fourth gate line electrode 6 penetrates the second passivation anti-reflection layer 18 to contact the doped polysilicon layer 17 at the bottom position of the second groove 12. The fourth gate line electrode 6 overlaps the third gate line electrode 5 at the position of the second groove 12 and covers the outer peripheral surface of the third gate line electrode 5 to form a second main surface covering part 7, and the third side surface covering part 71 and the fourth side surface covering part 72 of the second main surface covering part 7 extend the side surface inside the second groove 12 and contact the second passivation anti-reflection layer 18 on the side surface of the second groove 12, respectively. If the fourth gate line electrode 6 is set as a fine gate on the second main surface, the fourth gate line electrode 6 also penetrates the second passivation anti-reflection layer 18 to contact the doped polysilicon layer 17 at the position of the side surface of the second groove 12.

[0060] In the present application, a method for preparing a solar cell is also provided, which comprises the following specific preparation steps:

[0061] S1, performing groove processing on the first main surface of the silicon substrate 1 to obtain a first groove 11;

[0062] S2, forming a first functional layer on the first groove 11 and other parts of the first main surface;

[0063] S3, forming the first gate line electrode 2 and the second gate line electrode 3 on the side of the first functional layer away from the silicon substrate 1, and the first gate line electrode 2 protrudes outwardly from the first groove 11, the second gate line electrode 3 overlaps the first gate line electrode 2, and the second gate line electrode 3 covers the outer peripheral surface of the first gate line electrode 2 to form a first main surface covering part 4 at the overlapping part, the first main surface covering part 4 includes a first side surface covering part 41 and a second side surface covering part 42 which are oppositely arranged and respectively cover the surfaces on both sides of the first gate line electrode 2, and at least one of the first side surface covering part 41 and the second side surface covering part 42 extends to the corresponding first groove 11 near the end of the first main surface of the silicon substrate 1.

[0064] In the present embodiment, it is to be noted that S1 further includes performing groove processing on the second main surface of the silicon substrate 1 to obtain the second groove 12.

[0065] The following will be described in detail with respect to S1:

[0066] First, the silicon substrate 1 (as shown in Figure 5 In the present embodiment, the silicon substrate 1 is selected as an N-type silicon substrate, and the resistivity of the N-type silicon substrate is 1.0 Ω. The resistivity of the N-type silicon substrate and the size of the single crystal silicon wafer are not limited in the present embodiment.

[0067] Performing groove processing on the first main surface of the silicon substrate 1 to obtain the first groove 11, and performing groove processing on the second main surface to obtain the second groove 12, which specifically adopts the following steps:

[0068] S11, performing double-sided oxidation on the first main surface and the second main surface of the silicon substrate 1, and forming a mask oxide layer 19 (as shown in Figure 6 on the surfaces, and the thickness of the mask oxide layer 19 is 40 nm. The preparation method of the mask oxide layer 19 can be thermal oxidation or PECVD (Plasma Enhanced Chemical Vapor Deposition) oxidation, and the preferred method for preparing the oxide layer is PECVD oxidation, which can mainly ensure the process time and production capacity in production;

[0069] S12, laser processing is performed on the first main surface and the second main surface of the oxidized silicon substrate 1, i.e. laser local patterning film processing, wherein the laser processing region corresponds to the overlapping region of the first grid electrode 2 and the second grid electrode 3 and the third grid electrode 5 and the fourth grid electrode 6 respectively; in one example, the laser processing laser parameters are as follows: laser wavelength of 500-550 nm, for example, it can be 500 nm, 510 nm, 525 nm, 530 nm, 532 nm, 540 nm, 550 nm, etc., laser spot side length of 10-30 μm, for example, it can be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc. The laser spot side length is less than or equal to the fine grid width. Preferably, the laser wavelength is 532 nm, the laser side length is 20 μm, and the laser line length along the fine grid direction is 0.1-1 mm, preferably 0.5 mm.

[0070] S13, etching the laser region of the silicon substrate 1 in an alkaline solution to form the first groove 11 and the second groove 12 (as shown in Figure 7 The alkaline solution has the following parameters: the alkaline solution contains at least one of KOH, NaOH and TMAH, the alkaline solution contains etching additives, the etching time of the alkaline solution is 200-1000 s, for example, it can be 200 s, 400 s, 550 s, 600 s, 780 s, 950 s, 1000 s, etc., preferably 400 s, and the etching depth is 2-10 μm, for example, it can be 2 μm, 4 μm, 6 μm, 7.5 μm, 8 μm, 10 μm, etc., preferably 4 μm.

[0071] S14, removing the mask oxide layer 19 of the etched silicon substrate 1 by acid washing to obtain a silicon substrate 1 with a first groove 11 and a second groove 12 (as shown in Figure 8 .

[0072] The following will be described in detail with respect to S2:

[0073] The first functional layer includes an emitter layer 13, a first passivation layer 14 and a first passivation anti-reflection layer 15.

[0074] S21, forming a first diffusion source on the bottom wall, side surface and other parts of the first groove 11 of the first main surface of the silicon substrate 1, and performing diffusion treatment to form a continuous emitter layer 13 and a first doped silicon glass layer on the bottom wall, side surface and other parts of the first groove 11.

[0075] In this embodiment, it should be noted that texturing is performed on the bottom wall and other parts of the first groove 11 on the first main surface of the silicon substrate 1. A trough-type texturing device is used to perform texturing on the first main surface of the silicon substrate 1 and the bottom of the first groove 11 to form a pyramid base structure (e.g., ...) on the first main surface of the silicon substrate 1 and the bottom of the first groove 11. Figure 9 As shown in the figure, this reduces the reflectivity of incident light and improves photon utilization. Then, a first diffusion source, such as a boron diffusion source, is formed on the bottom wall, side, and other parts of the first groove 11 on the first main surface of the silicon substrate 1. A diffusion process is performed to form a continuous emitter layer 13 and a first doped silicon glass layer with a height difference on the bottom wall, side, and other parts of the first groove 11. That is, the emitter layer 13 is part of the silicon substrate 1 (the area of ​​the first main surface and the bottom wall and side of the first groove 11). In other words, boron diffusion is performed on the first main surface of the silicon substrate 1 and the bottom wall and side of the first groove 11. Boron will diffuse from the surface of the first main surface of the silicon substrate 1 into the silicon substrate 1 (diffused to a predetermined position from the first main surface) and from the bottom wall and side of the first groove 11 into the first groove 11 (diffused to a predetermined position from the bottom wall and side of the first groove 11). Thus, the area of ​​boron diffusion in the silicon substrate 1 forms the emitter layer 13. Specifically, a boron-doped source is diffused into the silicon substrate 1 using a high-temperature boron diffusion process to form an emitter layer 13 in the silicon substrate 1. Since a first groove 11 exists on the first main surface of the silicon substrate 1, and boron diffusion is performed on the bottom wall and sides of the first groove 11, an emitter layer 13 with a height difference is formed on the first main surface of the silicon substrate 1 during the boron diffusion process. The textured pyramid size after texturing is 5 μm, and the sheet resistance after boron diffusion is preferably 300 Ω / □.

[0076] In one example, the diffusion process forms a first doped silicon glass layer, such as a borosilicate glass layer, on the first main surface, the second main surface, and the periphery of the silicon substrate 1, as well as on the bottom wall and sides of the first groove 11. The peripheral borosilicate glass layer is prone to short circuits, and the surface borosilicate glass layer affects subsequent passivation, so it needs to be removed. Currently, etching mainly uses a wet method, first removing the second main surface and the peripheral borosilicate glass layer in a chain cleaning machine, and then processing the first main surface. For example, specifically, at room temperature, the diffused silicon substrate 1 is etched twice using an HF solution to remove BSG from the edges of the silicon substrate 1 and the second main surface. The silicon substrate 1 is then cleaned in a chain cleaning machine by floating on water (the second main surface is in contact with the acid solution) to remove the BSG from the second main surface. The acid solution mainly consists of 24.5% HF, and the main chemical reaction equations include:

[0077] HF + SiO2 → SiF4 + H2O

[0078] SiF4 + HF → H2SiF6.

[0079] S22, forming a continuous first passivation layer 14 on the first main surface of the silicon substrate 1 and the surface of the emitter layer 13 of the bottom wall and side surface of the first groove 11, and forming a first passivation anti-reflection layer 15 on the surface of the first passivation layer 14.

[0080] In this embodiment, it should be noted that, as shown in Figure 11 the first passivation layer 14 is formed on the first main surface of the silicon substrate 1 and the surface of the emitter layer 13 of the bottom wall and side surface of the first groove 11 by PECVD, which can reduce the recombination rate of the first main surface, increase the secondary reflection, and form a first passivation anti-reflection layer 15 such as a silicon nitride film on the surface of the first passivation layer 14. In industrial production, PECVD equipment is often used to prepare a silicon nitride anti-reflection film. The main process is to use glow discharge to heat the sample to a predetermined temperature, then introduce appropriate amounts of reaction gases SiH4 and NH3, and the gases undergo a series of chemical reactions and plasma reactions to form a solid thin film, i.e. a silicon nitride thin film, on the surface of the sample.

[0081] Before S3, the method further includes: forming a second functional layer on the second groove 12 and other parts of the second main surface, the second functional layer including a tunneling oxide layer 16, a doped polysilicon layer 17, and a second passivation anti-reflection layer 18.

[0082] In the embodiment, it is to be noted that the first main surface and the second main surface of the silicon substrate 1 are a pair of surfaces of the silicon substrate 1 opposite to each other. The bottom wall, the side surface and other parts of the second groove 12 on the second main surface of the silicon substrate 1 are formed into a polished surface structure by using a back etching process, specifically, the bottom wall, the side surface and other parts of the second groove 12 on the second main surface of the silicon substrate 1 are etched by using an alkali solution such as KOH solution and an additive, so that the bottom wall, the side surface and other parts of the second groove 12 on the second main surface of the silicon substrate 1 are formed into a polished surface structure, the depth of the first groove 11 and the second groove 12 remains unchanged, then the polished surface structure is cleaned by using hydrochloric acid and hydrofluoric acid, so that better polishing performance can be achieved and the process cost can be reduced. Then, a continuous tunnel oxide layer 16 is formed on the bottom wall, the side surface and other parts of the second groove 12 on the second main surface of the silicon substrate 1 by using a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method, the thickness of the tunnel oxide layer 16 is 10-100 nm, for example, can be 10 nm, 30 nm, 50 nm, 75 nm, 80 nm, 100 nm, etc., and a second diffusion source is formed on the surface of the tunnel oxide layer 16, so that the surface of the tunnel oxide layer 16 is formed into a continuous doped polysilicon layer 17 and a second doped silicon glass layer through diffusion treatment. Specifically, an intrinsic amorphous silicon layer is deposited on the surface of the tunnel oxide layer 16 on the second main surface and the bottom wall and the side surface of the second groove 12 of the silicon substrate 1, then the intrinsic amorphous silicon layer is doped with a second diffusion source such as phosphorus, and the doped atoms are subjected to high-temperature activation treatment. During the high-temperature activation treatment, the microcrystalline silicon phase is completely converted into a polycrystalline silicon phase, so that a continuous doped polysilicon layer 17 (as shown in Figure 10 The second main surface and the first main surface of the silicon substrate 1 are cleaned by using a tank type alkali cleaning device and an acid cleaning device, so as to remove the tunnel oxide layer 16, the doped polysilicon layer 17 and the boron silicon glass layer (BSG) formed on the first main surface of the silicon substrate 1, and the second doped silicon glass layer, i.e., the phosphorus silicon glass layer (PSG) on the second main surface and the periphery of the silicon substrate 1 and the bottom wall and the side surface of the second groove 12. Finally, a continuous second passivation anti-reflection layer 18 (as shown in Figure 11 is prepared on the surface of the doped polysilicon layer 17 on the second main surface and the bottom wall and the side surface of the second groove 12 of the silicon substrate 1 by using a PECVD method.

[0083] The S3 will be described in detail as follows.

[0084] In the present embodiment, it is to be noted that the present embodiment is mainly described by taking the example of the second grid line electrode 3 burning through the first passivation layer 14 and the first passivation anti-reflection layer 15 on the bottom and side of the first recess 11 to form an ohmic contact with the emitter layer 13, the main grid electrode paste is screen printed on the first passivation anti-reflection layer 15 on the first main surface by a screen printing machine, and then the main grid electrode paste is dried to obtain the first grid line electrode 2, part of the first grid line electrode 2 is located in the first recess 11 and is higher than the first recess 11; the fine grid electrode paste is screen printed on the first passivation anti-reflection layer 15 on the first main surface by a screen printing machine, the second grid line electrode 3 is burned through the first passivation layer 14 and the first passivation anti-reflection layer 15 on the bottom and side of the first recess 11 to form an ohmic contact with the emitter layer 13 by high-temperature sintering, and then the fine grid electrode paste is dried, the position of the second grid line electrode 3 in the first recess 11 overlaps the first grid line electrode 2 during printing, and the second grid line electrode 3 covers the outer peripheral surface of the first grid line electrode 2 to form a first main surface covering portion 4 (as shown in Figure 1 ). The first main surface covering portion 4 includes a first side covering portion 41 and a second side covering portion 42 oppositely arranged and respectively covering the two side surfaces of the first grid line electrode 2, and one end of the first side covering portion 41 and the second side covering portion 42 close to the first main surface of the silicon substrate 1 extends into the corresponding first recess 11 (as shown in Figure 3 ).

[0085] The method further comprises: forming a third grid line electrode 5 and a fourth grid line electrode 6 on the side of the second functional layer away from the silicon substrate 1, and the third grid line electrode 5 protrudes outwardly from the second recess 12, the third grid line electrode 5 overlaps the fourth grid line electrode 6, and the fourth grid line electrode 6 covers the outer peripheral surface of the third grid line electrode 5 to form a second main surface covering portion 7 at the overlapping position, the second main surface covering portion 7 includes a third side covering portion 71 and a fourth side covering portion 72 oppositely arranged and respectively covering the two side surfaces of the third grid line electrode 5, and one end of at least one of the third side covering portion 71 and the fourth side covering portion 72 close to the second main surface of the silicon substrate 1 extends into the corresponding second recess 12.

[0086] In the present embodiment, it is to be noted that the present embodiment is mainly described by taking the fourth grid line electrode 6 burning through the second passivation anti-reflection layer 18 at the bottom and side of the second groove 12 to form an ohmic contact with the doped polysilicon layer 17 as an example. The main grid electrode paste is screen printed on the second passivation anti-reflection layer 18 on the second main surface by a screen printer, and then the electrode paste is dried to obtain the third grid line electrode 5, part of the third grid line electrode 5 is located in the second groove 12 and is higher than the second groove 12. The fine grid electrode paste is screen printed on the second passivation anti-reflection layer 18 on the second main surface by a screen printer, the fourth grid line electrode 6 is burned through the second passivation anti-reflection layer 18 at the bottom and side of the second groove 12 to form an ohmic contact with the doped polysilicon layer 17 by high-temperature sintering, and then the fine grid electrode paste is dried. When printing, the position of the fourth grid line electrode 6 in the second groove 12 overlaps the third grid line electrode 5, and the fourth grid line electrode 6 covers the outer peripheral surface of the third grid line electrode 5 to form a second main surface covering portion 7 (as shown in Figure 1 ). The second main surface covering portion 7 includes oppositely arranged third side surface covering portions 71 and fourth side surface covering portions 72, which respectively cover the two side surfaces of the third grid line electrode 5, and the two ends of the third side surface covering portions 71 and the fourth side surface covering portions 72 close to the second main surface of the silicon substrate 1 extend into the corresponding second groove 12 (as shown in Figure 4 ).

[0087] In one example, the main grid electrode paste is silver-aluminum paste; the fine grid electrode paste is silver paste.

[0088] The implementation principle of the present embodiment is: a first groove 11 of a certain depth is formed at the lap joint of the first grid line electrode 2 and the second grid line electrode 3 on the first main surface of the silicon substrate 1, when the first grid line electrode 2 is printed in the first groove 11 of a lower height, the presence of the first groove 11 increases the height of the first grid line electrode 2, and at the same time, the second grid line electrode 3 covers the outer peripheral surface of the first grid line electrode 2 at the lap joint to form a first main surface covering portion 4, which increases the entire contour circumference of the second grid line electrode 3 (the total length of the second grid line electrode 3 printed on the first main surface of the silicon substrate 1), and then when the first grid line electrode 2 is lapped with the second grid line electrode 3, the lap joint area of the first grid line electrode 2 and the second grid line electrode 3 is increased without increasing the light shielding area, and when the current in the second grid line electrode 3 converges to the first grid line electrode 2, the resistance is reduced, thereby solving the problem of large light shielding area of the first grid line electrode 2 and the second grid line electrode 3 at the connection area, and effectively increasing the overlap area of the connection area, and ensuring the use performance of the battery.

[0089] The above descriptions are only the preferred embodiments of the present application, and are not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that, include: The silicon substrate (1) includes a first main surface and a second main surface, wherein the first main surface is provided with a plurality of first grooves (11) extending into the silicon substrate (1); The first functional layer comprises a first groove (11) and other portions formed on the first main surface; The first main surface of the silicon substrate (1) is further provided with a plurality of first gate electrodes (2) and second gate electrodes (3), which are disposed on the surface of the first functional layer facing away from the silicon substrate (1). Part of the first gate electrode (2) is located in the first groove (11) and is higher than the first groove (11). The first gate electrode (2) and the second gate electrode (3) overlap each other at the position of the first groove (11), and at the overlap, the second gate electrode (3) covers the outer peripheral surface of the first gate electrode (2) to form a first main surface covering part (4). The first main surface covering portion (4) includes a first side covering portion (41) and a second side covering portion (42) that are disposed opposite to each other and cover the two sides of the first gate electrode (2). At least one of the first side covering portion (41) and the second side covering portion (42) extends into the corresponding first groove (11) near the first main surface of the silicon substrate (1).

2. The solar cell according to claim 1, characterized in that, The solar cell further includes: a second functional layer, a third grid electrode (5) and a fourth grid electrode (6); The second main surface is provided with a plurality of second grooves (12) extending into the silicon substrate (1), and the second functional layer is provided in the second grooves (12) and other parts of the second main surface; A plurality of the third gate electrodes (5) and the fourth gate electrodes (6) are disposed on the surface of the second functional layer facing away from the silicon substrate (1). A portion of the third gate electrodes (5) is located in the second groove (12) and is higher than the second groove (12). The third gate electrodes (5) and the fourth gate electrodes (6) overlap each other at the position of the second groove (12), and at the overlap, the fourth gate electrodes (6) cover the outer peripheral surface of the third gate electrodes (5) to form a second main surface covering portion (7). The second main surface covering portion (7) includes a third side covering portion (71) and a fourth side covering portion (72) that are disposed opposite to each other and cover the two sides of the third gate electrode (5), and at least one of the third side covering portion (71) and the fourth side covering portion (72) extends into the corresponding second groove (12) near the second main surface of the silicon substrate (1).

3. The solar cell according to claim 2, characterized in that, The first side cover (41) and the second side cover (42) extend into the corresponding first groove (11) at one end near the first main surface of the silicon substrate (1); And / or, the third side cover (71) and the fourth side cover (72) extend from one end near the second main surface of the silicon substrate (1) into the corresponding second groove (12).

4. The solar cell according to claim 2 or 3, characterized in that, The silicon substrate (1) includes an N-type silicon substrate; The first functional layer includes an emitter layer (13), a first passivation layer (14), and a first passivation antireflection layer (15) arranged sequentially from the inside out; The first gate electrode (2) or the second gate electrode (3) penetrates the first passivation antireflection layer (15) and the first passivation layer (14) at the bottom position of the first groove (11) and contacts the emitter layer (13).

5. The solar cell according to claim 4, characterized in that, The first side cover (41) and / or the second side cover (42) extend into the first groove (11) and contact the first passivation antireflection layer (15) on the side of the first groove (11).

6. The solar cell according to claim 4, characterized in that, The second functional layer includes a tunneling oxide layer (16), a doped polysilicon layer (17), and a second passivation antireflection layer (18) arranged sequentially from the inside out; The third gate electrode (5) or the fourth gate electrode (6) penetrates the second passivation antireflection layer (18) at the bottom of the second groove (12) and contacts the doped polysilicon layer (17).

7. The solar cell according to claim 6, characterized in that, The third side cover (71) and / or the fourth side cover (72) extend into the second groove (12) and contact the second passivation antireflection layer (18) on the side of the second groove (12).

8. The solar cell according to claim 2, characterized in that, The length L of the first groove (11) is greater than the width of the first gate electrode (2); The width W of the first groove (11) is less than or equal to the width of the second gate electrode (3); The length L of the second groove (12) is greater than the width of the third gate electrode (5); The width W of the second groove (12) is less than or equal to the width of the fourth gate electrode (6); And / or, The widths of the first gate electrode (2) and the third gate electrode (5) are both 40-80 μm; The widths of the second gate electrode (3) and the fourth gate electrode (6) are both 15-30 μm; The length L of both the first groove (11) and the second groove (12) is 0.1-1mm; The width W of both the first groove (11) and the second groove (12) is 10-30 μm; The depth h of the first groove (11) and the second groove (12) is 2-10 μm.

9. The solar cell according to claim 2, characterized in that, The first gate electrode (2) is a fine gate electrode and the second gate electrode (3) is a main gate electrode; or, the first gate electrode (2) is a main gate electrode and the second gate electrode (3) is a fine gate electrode. The third gate electrode (5) is a fine gate electrode and the fourth gate electrode (6) is a main gate electrode; or, the third gate electrode (5) is a main gate electrode and the fourth gate electrode (6) is a fine gate electrode.

10. The solar cell according to claim 9, characterized in that, The width of the main gate electrode is 40μm-80μm, and the height is 6-15μm; The width of the fine gate electrode is 15-30 μm; the height is 6-15 μm.

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