Display device

Abstract

A display device according to one or more embodiments of the present disclosure includes: a substrate; a display unit on the substrate and including first to third sub-pixels configured to emit light of different colors; a first phase delay unit on the display unit and including first phase delay plates respectively overlapping the first to third sub-pixels and having different phase differences from each other; a first polarizing plate on the first phase delay unit; a second phase delay unit on the first polarizing plate and including second phase delay plates overlapping the first to third sub-pixels, respectively, and having different phase differences from each other; and a polarizing element layer on the second phase delay unit and including a pancake lens. In the display device, since the phase retardation plates having different thicknesses for each sub-pixel are disposed on the display unit, a ghosting phenomenon for each wavelength can be improved, thereby improving brightness and light emission efficiency of the display device.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0078776, filed on June 18, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0096821, filed on July 23, 2024, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Aspects of embodiments of the present disclosure relate to a display device and an electronic device including the same. BACKGROUND

[0003] With the development of information technology, the importance of a display device, which is a medium for connecting a user and information, is emerging. In response thereto, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0004] Recently, a head-mounted display (HMD) is being developed. The HMD is a display device that implements virtual reality (VR) or augmented reality (AR) in which a user wears the HMD in the form of glasses or a helmet and forms a focal point at a distance close to the eyes. A high-resolution panel is applied to the HMD, and thus a pixel that can be applied to the high-resolution panel is required.

[0005] The above information disclosed in this BACKGROUND section is only for enhancing the understanding of the background of the present disclosure, and therefore it can contain information that does not form the prior art. SUMMARY

[0006] The present disclosure aims to provide a display device in which a ghosting phenomenon for each wavelength is improved.

[0007] Aspects of the present disclosure are not limited to the above-described aspects, and other technical aspects not described will be clearly understood by those skilled in the art from the following description.

[0008] According to some embodiments of the disclosure, a display device is provided, the display device including: a substrate; a display unit on the substrate and including first to third sub-pixels configured to emit different colors of light; a first phase delay unit on the display unit and including first phase delay plates respectively superposed with the first to third sub-pixels and having different phase differences from each other; a first polarizing plate on the first phase delay unit; a second phase delay unit on the first polarizing plate and including second phase delay plates respectively superposed with the first to third sub-pixels and having different phase differences from each other; and a polarizing element layer on the second phase delay unit and including a thin pancake lens.

[0009] In some embodiments, each of the first and second phase delay plates can have a phase difference corresponding to a wavelength of light emitted by a corresponding superimposed sub-pixel among the first to third sub-pixels.

[0010] In some embodiments, each of the first and second phase delay plates can have a thickness different from each other according to a wavelength of light emitted by a corresponding superimposed sub-pixel among the first to third sub-pixels.

[0011] In some embodiments, a wavelength of light emitted by the first sub-pixel can be longer than a wavelength of light emitted by the second sub-pixel and a wavelength of light emitted by the third sub-pixel, and a wavelength of light emitted by the second sub-pixel can be longer than a wavelength of light emitted by the third sub-pixel.

[0012] In some embodiments, among the first and second phase delay plates, a phase delay plate superimposed with the first sub-pixel can have a thickness greater than thicknesses of a phase delay plate superimposed with the second sub-pixel and a phase delay plate superimposed with the third sub-pixel.

[0013] In some embodiments, among the first and second phase delay plates, a phase delay plate superimposed with the second sub-pixel can have a thickness greater than a thickness of a phase delay plate superimposed with the third sub-pixel.

[0014] In some embodiments, each of the first and second phase delay plates can be a 1 / 4 phase delay plate.

[0015] In some embodiments, the first and second phase delay plates superimposed with the first to third sub-pixels, respectively, can be superimposed with each other, and the first and second phase delay units can have substantially the same structure.

[0016] In some embodiments, each of the first and second phase delay plates can include liquid crystal molecules.

[0017] In some embodiments, the first phase delay unit can further include a first light blocking pattern surrounding the first phase delay plate, and the second phase delay unit can further include a second light blocking pattern surrounding the second phase delay plate.

[0018] In some embodiments, the polarizing element layer can be superimposed with the first to third sub-pixels.

[0019] In some embodiments, the polarizing element layer can include a half mirror on the second phase delay unit, a third phase delay unit on the half mirror, a second polarizing plate on the third phase delay unit, and at least one lens between the half mirror and the second polarizing plate.

[0020] In some embodiments, the polarizing element layer can include at least one first lens between the half mirror and the third phase delay unit.

[0021] In some embodiments, the polarizing element layer can include a second lens on the second polarizing plate.

[0022] In some embodiments, the third phase delay unit can have substantially the same structure as the first phase delay unit and the second phase delay unit.

[0023] In some embodiments, the second polarizing plate can have substantially the same structure as the first polarizing plate.

[0024] In some embodiments, the polarizing element layer can further include a third polarizing plate on the second polarizing plate.

[0025] In some embodiments, the third polarizing plate can be an absorption-type polarizing plate.

[0026] In some embodiments, the first polarizing plate can be a wire grid polarizing plate.

[0027] In some embodiments, the display device can further include a microlens array between the second phase delay unit and the polarizing element layer.

[0028] According to some embodiments disclosed, there is provided an electronic device including a processor configured to provide input image data, and a display device configured to display an image based on the input image data, and the display device includes a substrate, a display unit on the substrate and including first to third sub-pixels configured to emit different colors of light, a first phase delay unit on the display unit and including first phase delay plates respectively overlapping the first to third sub-pixels and having different phase differences from each other, a first polarizing plate on the first phase delay unit, a second phase delay unit on the first polarizing plate and including second phase delay plates respectively overlapping the first to third sub-pixels and having different phase differences from each other, and a polarizing element layer on the second phase delay unit and including a pancake lens.

[0029] In the display device, since the phase delay plates having different thicknesses for each sub-pixel are disposed on the display unit, the ghosting phenomenon for each wavelength can be improved, thereby improving the brightness and light emission efficiency of the display device.

[0030] Effects according to embodiments are not limited by what is illustrated above, and various effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0031] The above and other features of this disclosure will become more apparent from the accompanying drawings, which describe embodiments of the present disclosure in a further detailed manner:

[0032] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure;

[0033] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram of one sub-pixel of a sub-pixel;

[0034] Figure 3 This illustrates some embodiments according to the present disclosure. Figure 2 Circuit diagram of the sub-pixel;

[0035] Figure 4 This illustrates some embodiments according to the present disclosure. Figure 1 A floor plan of the display panel;

[0036] Figure 5 This is an exploded perspective view showing a portion of a display device according to some embodiments of the present disclosure;

[0037] Figure 6 This illustrates some embodiments according to the present disclosure. Figure 5 A planar image of one pixel in a pixel;

[0038] Figure 7 It is according to some embodiments of this disclosure along Figure 6 A schematic cross-sectional view taken by line I-I';

[0039] Figure 8 These are schematic cross-sectional views according to some other embodiments of this disclosure;

[0040] Figure 9 These are schematic cross-sectional views according to some other embodiments of this disclosure;

[0041] Figure 10 This is a block diagram illustrating some embodiments of a display system according to some embodiments of the present disclosure;

[0042] Figure 11 This illustrates some embodiments according to the present disclosure. Figure 10 A perspective view of an application example of the display system; and

[0043] Figure 12 This illustrates some embodiments according to the present disclosure. Figure 11 An image of a head-mounted display device worn by a user. Detailed Implementation

[0044] Hereinafter, embodiments will be described in greater detail with reference to the accompanying drawings, in which like numerals will denote like elements throughout the drawings. The disclosure may, however, be embodied in various different forms, and should not be construed as being limited only to the embodiments set forth herein. Rather, these embodiments are provided as examples so that the disclosure will be thorough and complete, and will fully convey the aspects and features of the disclosure to those skilled in the art. Therefore, processes, elements, and techniques not necessary to an understanding of the aspects and features of the disclosure can not be described, and the same reference numerals can be used throughout the drawings and written description to indicate the same elements. Redundant descriptions thereof can not be repeated.

[0045] When certain embodiments can be implemented differently, a specific process sequence can be different from the described sequence. For example, two processes described in succession can be performed simultaneously or substantially simultaneously, or can be performed in an order opposite to the described sequence.

[0046] In the drawings, the relative sizes, thicknesses, and ratios of elements, layers, and regions can be exaggerated and / or simplified for clarity. For ease of explanation, spatial relative terms such as "below," "under," "lower," "beneath," "above," "upper," and the like, can be used herein for describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0047] In the drawings, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis can be perpendicular or substantially perpendicular to each other, or can represent mutually different directions that are not perpendicular to each other.

[0048] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“first,”“second,”“third,” and / or the like elements, components, regions, layers or sections described below can be termed a“second,”“third,” or a“fourth” element, component, region, layer or section, without departing from the spirit and scope of the present disclosure.

[0049] It will be understood that when an element or layer is referred to as being“on” another element or layer, “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or one or more intervening elements or layers can be present. In like manner, when a layer, region or element is referred to as being“electrically connected” to another layer, region or element, it can be directly electrically connected to the other layer, region or element and / or can be indirectly electrically connected to the other layer, region or element with one or more intervening layers, regions or elements therebetween. In addition, it will also be understood that when an element or layer is referred to as being“between” two elements or layers, it can be the only element or layer between the two elements or layers or one or more intervening elements or layers can also be present.

[0050] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms“a,”“an” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms“comprises,”“comprising,”“includes” and / or“including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term“and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression“A and / or B” means A, B, or A and B. When a phrase such as“at least one of’ precedes a list of two or more items, the phrase is directed to any combination of those items, including the individual items listed, and is not limited to the list as a whole. For example, the expression“at least one of a, b, and c” indicates that a, b, c, a and b, a and c, b and c, or a, b, and c are all possible.

[0051] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in a measurement or calculation that would be recognized by those of ordinary skill in the art. Moreover, use of "can" as describing embodiments of the present disclosure indicates "one or more embodiments of the present disclosure." As used herein, the term "use" and variations thereof can be considered synonymous and interchangeable with the term "utilize" and variations thereof, respectively.

[0052] The electronic device or electric device and / or any other related device or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or combination of software, firmware, and hardware. For example, various components of these devices can be formed on one integrated circuit (IC) chip or on separate IC chips. Also, various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, various components of these devices can be a process or thread, running on one or more processors, executing computer program instructions and interacting with other system components for performing the various functionalities described herein in one or more computing devices. The computer program instructions are stored in a memory which can be implemented using any suitable memory (e.g., random access memory (RAM), read only memory (ROM), etc.). The computer program instructions can also be stored in any other non-transitory computer-readable medium such as a CD-ROM, flash drive, etc. Also, those skilled in the art should appreciate that functions of various computing devices, described herein, can be combined or integrated into a single computing device, or functions of a particular computing device can be distributed across one or more other computing devices.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0054] Figure 1 is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0055] Referring to Figure 1 , the display device 100 can include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0056] The display panel 110 includes sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through the first to m-th gate lines GL1 to GLm. The sub-pixels SP can be connected to the data driver 130 through the first to n-th data lines DL1 to DLn.

[0057] Each of the sub-pixels SP can include at least one light emitting element configured to generate light. Accordingly, each of the sub-pixels SP can generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP can configure one pixel PXL (e.g., included in one pixel PXL). For example, as shown in FIG. 1A, three sub-pixels SP can configure one pixel PXL. In other words, one pixel PXL can include two or more sub-pixels SP. Figure 1

[0058] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 can output a gate signal to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. In some embodiments, the gate control signal GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing at which a data signal is applied, and the like.

[0059] In some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction can be provided. For example, the gate driver 120 can include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver can operate under the control of the controller 150.

[0060] The gate driver 120 can be provided at one side of the display panel 110. However, embodiments are not limited thereto. For example, the gate driver 120 can be divided into two or more physically and / or logically divided drivers, and such drivers can be provided at one side of the display panel 110 and another side of the display panel 110 opposite to the one side. As described above, the gate driver 120 can be provided around the display panel 110 in various shapes according to embodiments.

[0061] ​The data driver 130 is connected to the sub-pixels SP arranged in a column direction through first to nth data lines DL1 to DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In some embodiments, the data control signal DCS can include a source start pulse, a source shift clock, and / or a source output enable signal, etc.

[0062] The data driver 130 can apply data signals having gradation voltages corresponding to the image data DATA to the first to nth data lines DL1 to DLn using voltages from the voltage generator 140. When the gate signal is applied to each of the first to mth gate lines GL1 to GLm, data signals corresponding to the image data DATA can be applied to the first to nth data lines DL1 to DLn. Accordingly, the corresponding sub-pixels SP can generate light corresponding to the data signals. Thus, an image is displayed on the display panel 110.

[0063] In some embodiments, the gate driver 120 and the data driver 130 can include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0064] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages and provide the generated voltages to components of the display apparatus 100. For example, the voltage generator 140 can be configured to generate a plurality of voltages by receiving an input voltage from outside of the display apparatus 100, adjusting the received voltage, and regulating the adjusted voltage.

[0065] The voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS can be provided to the sub-pixels SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a voltage level (e.g., a relatively low voltage level or a low voltage) lower than the voltage level of the first power voltage VDD. In some other embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of the display apparatus 100.

[0066] Further, the voltage generator 140 can generate various voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light emitting element of the sub-pixel SP, a predetermined reference voltage can be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 can generate such a reference voltage.

[0067] The controller 150 can control the overall operation of the display device 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0068] The controller 150 can convert the input image data IMG to fit the display device 100 or display panel 110, and output image data DATA. In some embodiments, the controller 150 can output image data DATA by arranging the input image data IMG to fit the sub-pixels SP of the row unit.

[0069] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included within a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separated components within a single driver integrated circuit (DIC). In some other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a component distinguishable from the driver integrated circuit (DIC) (e.g., separate from or not integrated with the driver integrated circuit (DIC)).

[0070] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In some embodiments, the temperature sensor 160 may be positioned adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0071] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In some embodiments, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to temperature data TEP. For example, the controller 150 can control data signals and a first power voltage VDD and a second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0072] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram of one subpixel within a subpixel. Figure 2 InFigure 1 Among the subpixels SP, a subpixel SPij arranged in an i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and a j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0073] Referring to Figure 2 , the subpixel SPij can include a subpixel circuit SPC and a light emitting element LD.

[0074] The light emitting element LD is connected between a first power voltage node VDDN and a second power voltage node VSSN. For example, the first power voltage node VDDN can be a node that transmits a first power voltage VDD, and the second power voltage node VSSN is a node that transmits a second power voltage VSS. Figure 1 Figure 1 The anode electrode AE of the light emitting element LD can be connected to the first power voltage node VDDN through the subpixel circuit SPC, and the cathode electrode CE of the light emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light emitting element LD can be connected to the first power voltage node VDDN through one or more transistors included in the subpixel circuit SPC.

[0075] The subpixel circuit SPC can be connected to an i-th gate line GLi among first to m-th gate lines GL1 to GLm of the display panel 100, an i-th emission control line ELi among first to m-th emission control lines EL1 to ELm of the display panel 100, and

[0076] a j-th data line DLj among first to n-th data lines DL1 to DLn of the display panel 100. The subpixel circuit SPC can be configured to control the light emitting element LD according to signals received through these signal lines. Figure 1 Figure 1 The subpixel circuit SPC can operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi can include one or more sub-gate lines. In some embodiments, as shown in Figure 1 , the i-th gate line GLi can include a first sub-gate line SGL1 and a second sub-gate line SGL2. The subpixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the subpixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0077] The subpixel circuit SPC can operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi can include one or more sub-gate lines. In some embodiments, as shown in Figure 2 , the i-th gate line GLi can include a first sub-gate line SGL1 and a second sub-gate line SGL2. The subpixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the subpixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0078] ​The sub-pixel circuit SPC can operate in response to an emission control signal received through the i-th emission control line ELi. In some embodiments, the i-th emission control line ELi can include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to an emission control signal received through a corresponding sub-emission control line.

[0079] The sub-pixel circuit SPC can receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust a current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light emitting element LD according to the stored voltage in response to an emission control signal received through the i-th emission control line ELi. Accordingly, the light emitting element LD can generate light of a luminance corresponding to the data signal.

[0080] Figure 3 is a circuit diagram illustrating a sub-pixel of Figure 2 according to some embodiments of the disclosure.

[0081] Referring to Figure 3 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light emitting element LD.

[0082] The sub-pixel circuit SPC can be connected to an i-th gate line GLi', an i-th emission control line ELi', and a j-th data line DLj. Compared to the i-th gate line GLi of Figure 2 , the i-th gate line GLi' can further include a third sub-gate line SGL3. Compared to the i-th emission control line ELi of Figure 2 , the i-th emission control line ELi' can include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0083] The sub-pixel circuit SPC can include a first transistor T1 to a sixth transistor T6 and a first capacitor C1 and a second capacitor C2.

[0084] The first transistor T1 can be connected between the first power voltage node VDDN and a first node N1. A gate of the first transistor T1 can be connected to a second node N2, and thus, the first transistor T1 can be turned on according to a voltage level of the second node N2. The first transistor T1 can be referred to as a driving transistor.

[0085] The second transistor T2 can be connected between the jth data line DLj and the second node N2. A gate of the second transistor T2 can be connected to the first sub-gate line SGL1, and thus, the second transistor T2 can be turned on in response to a gate signal of the first sub-gate line SGL1. The second transistor T2 can be referred to as a switching transistor.

[0086] The third transistor T3 can be connected between the first node N1 and the second node N2. A gate of the third transistor T3 can be connected to the second sub-gate line SGL2, and thus, the third transistor T3 can be turned on in response to a gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 can be connected between the first node N1 and the anode electrode AE of the light emitting element LD. A gate of the fourth transistor T4 can be connected to the second sub-emission control line SEL2, and thus, the fourth transistor T4 can be turned on in response to an emission control signal of the second sub-emission control line SEL2.

[0088] The fifth transistor T5 can be connected between the anode electrode AE of the light emitting element LD and an initialization voltage node VINTN. The initialization voltage node VINTN can be configured to transmit an initialization voltage. In some embodiments, the initialization voltage can be provided by a voltage generator 140 of Figure 1 In some other embodiments, the initialization voltage can be provided by an external device of the display apparatus 100. A gate of the fifth transistor T5 can be connected to the third sub-gate line SGL3, and thus, the fifth transistor T5 can be turned on in response to a gate signal of the third sub-gate line SGL3.

[0089] The sixth transistor T6 can be connected between the first power voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 can be connected to the first sub-emission control line SEL1, and thus, the sixth transistor T6 can be turned on in response to an emission control signal of the first sub-emission control line SEL1.

[0090] The first capacitor C1 can be connected between the second transistor T2 and the second node N2. The second capacitor C2 can be connected between the first power voltage node VDDN and the second node N2.

[0091] As described above, the sub-pixel circuit SPC can include the first to sixth transistors T1 to T6 and the first and second capacitors C1 and C2. However, embodiments are not limited thereto. The sub-pixel circuit SPC can be implemented as any of various types of circuits including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC can include two transistors and one capacitor. According to embodiments of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' can be variable (e.g., can vary).

[0092] The first to sixth transistors T1 to T6 can be P-type transistors. Each of the first to sixth transistors T1 to T6 can be a metal oxide silicon field effect transistor (MOSFET). However, embodiments are not limited thereto. For example, at least one of the first to sixth transistors T1 to T6 can be an N-type transistor.

[0093] In some embodiments, the first to sixth transistors T1 to T6 can include amorphous silicon semiconductors, single-crystal silicon semiconductors, polycrystalline silicon semiconductors, and / or oxide semiconductors, etc.

[0094] The light emitting element LD can include an anode electrode AE, a cathode electrode CE, and a light emitting layer. The light emitting layer can be disposed between the anode electrode AE and the cathode electrode CE. After a data signal transmitted through the j-th data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 can be turned on when the emission control signals of the first and second sub-emission control lines SEL1 and SEL2 are enabled to be low. In addition, the first transistor T1 can be turned on according to the voltage of the second node N2, and thus, a current can flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD can emit light according to the amount of the flowing current.

[0095] Figure 4 is a plan view illustrating a display panel DP corresponding to the display panel 110 of FIG. 1, according to some embodiments of the present disclosure. Figure 1

[0096] Referring to Figure 4 , the display panel DP corresponding to the display panel 110 of FIG. 1, according to some embodiments of the present disclosure. Figure 1 Some embodiments of the display panel DP corresponding to the display panel 110 of FIG. 1 can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0097] The display panel DP can include a substrate SUB, sub-pixels SP, and pads ("pads" are also referred to as "bond pads" or "solder pads") PD. ​

[0098] When the display panel DP is used as a display for a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, augmented reality (AR) device, etc., the display panel DP can be positioned very close to the user's eyes. In this case, relatively highly integrated subpixels SP can be used. In some embodiments, the display panel DP can have a relatively high resolution (e.g., pixel density). To increase the integration of the subpixels SP, the substrate SUB can be a silicon substrate. The subpixels SP and / or the display panel DP can be formed on the substrate SUB, which may be a silicon substrate. A display device 100 including a display panel DP formed on a substrate SUB that is a silicon substrate (see example...) Figure 1 This can be referred to as an OLED on silicon (OLEDoS) display device.

[0099] Subpixels SP can be disposed on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix shape along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiments are not limited to this. For example, subpixels SP can be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, subpixels SP can be arranged in a pentiline shape. ® (Trademark of Samsung Display Co., Ltd.) Shape arrangement. For example, subpixels SP can be arranged in an RGBG matrix structure. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0100] Two or more sub-pixels SP can be used to construct a pixel PXL.

[0101] Components used to control subpixels SP can be set on the substrate SUB in the non-display area NDA. For example, lines connected to subpixels SP (such as...) Figure 1 The first gate line GL1 to the m gate line GLm and the first data line DL1 to the n data line DLn can be set in the non-display area NDA.

[0102] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated into the non-display area NDA of the display panel DP. In some embodiments, Figure 1 The gate driver 120 can be mounted on the display panel DP and can be located in the non-display area NDA. In some other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In some embodiments, the temperature sensor 160 can be located in the non-display area NDA to sense the temperature of the display panel DP.

[0103] The pad PD can be positioned on the substrate SUB within the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wirelines. For example, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn.

[0104] The pad PD can connect the display panel DP to the display device 100 (see example). Figure 1 Other components of ). In some embodiments, it can be obtained from the pad PD. Figure 1 The driver integrated circuit (DIC) provides voltages and signals for the operation of components included in the display panel (DP). For example, first data lines DL1 to nth data lines DLn can be connected to the driver integrated circuit (DIC) via a pad (PD). For example, a first power voltage VDD and a second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad (PD). For example, when the gate driver 120 is mounted on the display panel (DP), the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad (PD).

[0105] In some embodiments, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. In some embodiments, the circuit board may be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit (DIC) may be mounted on the circuit board to be electrically connected to the pad PD.

[0106] In some embodiments, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA can have shapes such as polygons, circles, semicircles, and ellipses.

[0107] In some embodiments, the display panel DP may have a flat display surface. In some other embodiments, the display panel DP may have a display surface that is at least partially circular. In some embodiments, the display panel DP may be flexible, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may comprise a material with flexible properties (e.g., suitable flexibility).

[0108] Figure 5 This is an exploded perspective view illustrating a portion of a display device according to some embodiments of the present disclosure. Figure 5 For clarity and conciseness, the diagram illustrates the relationship between the display panel DP and... Figure 4 The portion corresponding to pixels PXL1 and PXL2 within the pixel PXL. Similarly, the portion of the display panel DP corresponding to the remaining pixels PXL can be constructed.

[0109] Reference Figure 4 andFigure 5 Each of the first and second pixels PXL1 and PXL2 can include the first, second, and third sub-pixels SP1, SP2, and SP3. However, embodiments are not limited thereto. For example, each of the first and second pixels PXL1 and PXL2 can include four sub-pixels or two sub-pixels.

[0110] In Figure 5 When viewed from a third direction DR3 crossing the first and second directions DR1 and DR2, the first, second, and third sub-pixels SP1, SP2, and SP3 can have a quadrangular shape, and can have a size equal to or substantially equal to each other. However, embodiments are not limited thereto. The first, second, and third sub-pixels SP1, SP2, and SP3 can be modified to have various shapes.

[0111] The display panel DP can include a substrate SUB, a display unit DPP, a first polarizing element layer PEL1, a microlens array MLA, an overcoat layer OC, a cover window CW, and a second polarizing element layer PEL2.

[0112] In some embodiments, the substrate SUB can include a silicon wafer substrate formed using a semiconductor process. The substrate SUB can include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material can include silicon, germanium, and / or silicon germanium. The substrate SUB can be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In some other embodiments, the substrate SUB can include a glass substrate. In yet some other embodiments, the substrate SUB can include a polyimide (PI) substrate.

[0113] The display unit DPP can be disposed on the substrate SUB. The display unit DPP can include a pixel circuit layer PCL, a light emitting element layer LDL, a package layer TFE, and a color filter layer CFL. In addition, the display unit DPP can include the first to third sub-pixels SP1 to SP3. The first to third sub-pixels SP1 to SP3 can emit different colors of light. That is, the first to third sub-pixels SP1 to SP3 can respectively emit light having different wavelengths.

[0114] The pixel circuit layer PCL can be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL can include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL can serve as at least a part of circuit elements, lines, etc. The conductive patterns can include copper, but embodiments are not limited thereto.

[0115] The circuit elements can include sub-pixel circuits SPCs for each of the first, second, and third sub-pixels SP1, SP2, and SP3 (see, for example, FIG. 2). The sub-pixel circuits SPCs can be configured to drive the first, second, and third sub-pixels SP1, SP2, and SP3.Figure 2 The sub-pixel circuit SPC can include transistors and one or more capacitors. Each transistor can include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superposed with the semiconductor portion. In some embodiments, when the substrate SUB is provided as a silicon substrate, the semiconductor portion can be included in the substrate SUB, and the gate electrode can be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In some embodiments, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. Each capacitor can include electrodes spaced apart from each other. For example, each capacitor can include electrodes spaced apart from each other on a plane defined by the first direction DR1 and the second direction DR2. For example, each capacitor can include electrodes spaced apart from each other on the third direction DR3 with an insulating layer interposed therebetween.

[0116] The lines of the pixel circuit layer PCL can include signal lines, e.g., gate lines, emission control lines, data lines, etc., connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The lines can also include a line connected to the first power voltage node VDDN of the power supply circuit PSC. Further, the lines can also include a line connected to the second power voltage node VSSN of the power supply circuit PSC. Figure 2 Figure 2 The lines of the pixel circuit layer PCL can include signal lines, e.g., gate lines, emission control lines, data lines, etc., connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The lines can also include a line connected to the first power voltage node VDDN of the power supply circuit PSC. Further, the lines can also include a line connected to the second power voltage node VSSN of the power supply circuit PSC.

[0117] The light emitting element layer LDL can include an anode electrode AE, a pixel defining layer PDL, a light emitting structure EMS, and a cathode electrode CE.

[0118] The anode electrode AE can be provided on the pixel circuit layer PCL. The anode electrode AE can contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE can include an opaque conductive material capable of reflecting light, although embodiments are not limited thereto.

[0119] The pixel defining layer PDL can be provided on the anode electrode AE. The pixel defining layer PDL can include an opening OP exposing a portion of each of the anode electrodes AE. According to the opening OP of the pixel defining layer PDL, emission areas EMA1 to EMA3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively, can be defined (see, e.g., FIG. 1B). Figure 6 Alternatively, it can be understood that emission areas corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 are defined according to the anode electrode AE. In a region adjacent to a boundary between adjacent sub-pixels SP, the pixel defining layer PDL can include a partition causing a discontinuous portion (e.g., discontinuity) to be formed in the light emitting structure EMS. For example, it can be understood that emission areas corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively, are defined according to the partition of the pixel defining layer PDL. ​

[0120] In some embodiments, the pixel definition layer PDL can include an inorganic material. For example, the pixel definition layer PDL can include a plurality of stacked inorganic layers. For example, the pixel definition layer PDL can include silicon oxide SiO x and silicon nitride SiN x In some other embodiments, the pixel definition layer PDL can include an organic material. However, the material of the pixel definition layer PDL is not limited thereto.

[0121] The light emitting structure EMS can be disposed on the anode electrode AE exposed by the opening OP of the pixel definition layer PDL. The light emitting structure EMS can include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, and / or a hole transport layer configured to transport holes, etc.

[0122] In some embodiments, the light emitting structure EMS can fill the opening OP of the pixel definition layer PDL, and can be disposed entirely on the pixel definition layer PDL. In other words, the light emitting structure EMS can extend across the first to third sub-pixels SP1 to SP3. For example, at least a portion of layers in the light emitting structure EMS can be disconnected or bent at a boundary between the first to third sub-pixels SP1 to SP3. However, embodiments are not limited thereto. For example, portions of the light emitting structure EMS corresponding to the first to third sub-pixels SP1 to SP3 can be separated from each other, and each of the portions can be disposed in the opening OP of the pixel definition layer PDL.

[0123] The cathode electrode CE can be disposed on the light emitting structure EMS. The cathode electrode CE can extend across the first to third sub-pixels SP1 to SP3. As described above, the cathode electrode CE can be disposed as a common electrode for the first to third sub-pixels SP1 to SP3.

[0124] The cathode electrode CE can be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE can be formed of a metal material or a transparent conductive material and have a relatively thin (e.g., small) thickness. In some embodiments, the cathode electrode CE can include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In some other embodiments, the cathode electrode CE can include at least one of silver (Ag), magnesium (Mg), and a mixture thereof. However, the material of the cathode electrode CE is not limited thereto.

[0125] It can be appreciated that any of the anode electrodes AE, a portion of the light emitting structure EMS superposed therewith, and a portion of the cathode electrode CE superposed therewith configure one light emitting element LD (see, for example, FIG. 1B). Figure 2). In other words, each of the light emitting elements LD of the first to third sub-pixels SP1 to SP3 can include one anode electrode AE, a portion of the light emitting structure EMS superposed therewith, and a portion of the cathode electrode CE superposed therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transported into a light emitting layer of the light emitting structure EMS to form an exciton, and when the exciton transitions from an excited state to a ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the light emitting layer. According to the configuration of the light emitting layer, the wavelength range of the generated light can be determined.

[0126] A packaging layer TFE can be disposed on the cathode electrode CE. The packaging layer TFE can cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The packaging layer TFE can be configured to prevent or substantially reduce penetration of oxygen and / or moisture, etc. into the light emitting element layer LDL. In some embodiments, the packaging layer TFE can include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer can include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ), etc. For example, the organic layer can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the packaging layer TFE are not limited thereto.

[0127] To improve the packaging efficiency of the packaging layer TFE, the packaging layer TFE can further include a thin film including aluminum oxide (AlO x ). The thin film including aluminum oxide can be positioned on an upper surface of the packaging layer TFE facing the color filter layer CFL and / or a lower surface of the packaging layer TFE facing the light emitting element layer LDL.

[0128] The thin film including aluminum oxide can be formed by an atomic layer deposition (ALD) method. However, embodiments are not limited thereto. The packaging layer TFE can further include a thin film formed of at least one of various materials suitable for improving the packaging efficiency.

[0129] A color filter layer CFL can be disposed between the encapsulation layer TFE and the first polarizing element layer PEL1. The color filter layer CFL can be configured to filter light emitted from the light emitting structure EMS and selectively output light of a wavelength range or color corresponding to each sub-pixel SP. The color filter layer CFL can include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively, and each of the color filters CF can pass light of a wavelength range corresponding to the corresponding sub-pixel SP. For example, the color filter CF corresponding to the first sub-pixel SP1 can pass red light, the color filter CF corresponding to the second sub-pixel SP2 can pass green light, and the color filter CF corresponding to the third sub-pixel SP3 can pass blue light. At least a portion of the color filters CF can be omitted according to light emitted from the light emitting structure EMS of each sub-pixel SP.

[0130] The first polarizing element layer PEL1 can be disposed on the color filter layer CFL. The first polarizing element layer PEL1 can include polarizing elements and can convert a polarization state of light emitted by each of the first sub-pixel SP1 to the third sub-pixel SP3. The first polarizing element layer PEL1 can include a polarizing plate (e.g., a first polarizing plate POL1, refer to Figure 7 ) and phase delay plates (e.g., a first phase delay plate PRP1, refer to Figure 7 ) corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Since the corresponding phase delay plates can have different phase differences according to wavelengths of light emitted by the first sub-pixel SP1 to the third sub-pixel SP3, the corresponding phase delay plates can convert a polarization state of light according to wavelengths of light respectively emitted by the first sub-pixel SP1 to the third sub-pixel SP3.

[0131] A microlens array MLA can be disposed on the first polarizing element layer PEL1. The microlens array MLA can include microlenses MLS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0132] In some embodiments, at least a portion of the color filter CF of the color filter layer CFL and at least a portion of the microlens MLS of the microlens array MLA can be shifted in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel definition layer PDL. For example, in a central region of the display area DA, a center of the color filter CF and a center of the microlens MLS can be aligned with or superposed on a center of the corresponding opening OP of the pixel definition layer PDL when viewed in the third direction DR3. For example, in the central region of the display area DA, the opening OP of the pixel definition layer PDL can be fully superposed on the corresponding color filter CF of the color filter layer CFL and the corresponding microlens MLS of the microlens array MLA. In a region of the display area DA adjacent to the non-display area NDA, a center of the color filter CF and a center of the microlens MLS can be shifted in the plane direction from a center of the corresponding opening OP of the pixel definition layer PDL when viewed in the third direction DR3. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel definition layer PDL can be partially superposed on the corresponding color filter CF of the color filter layer CFL and the corresponding microlens MLS of the microlens array MLA. Thus, at the center of the display area DA, light emitted from the light emitting structure EMS can be effectively output in a normal direction of the display surface. At the periphery of the display area DA, light emitted from the light emitting structure EMS can be effectively output in a direction tilted at a set (e.g., preset or predetermined) angle with respect to the normal direction of the display surface.

[0133] An overcoat layer OC can be disposed on the microlens array MLA. The overcoat layer OC can cover the microlens array MLA, the first polarizing element layer PEL1, the color filter layer CFL, the encapsulation layer TFE, the light emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC can include various materials suitable for protecting the layers thereunder from foreign substances such as dust or moisture. For example, the overcoat layer OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer OC can include an epoxy resin, but embodiments are not limited thereto. The overcoat layer OC can have a refractive index lower than that of the microlens array MLA.

[0134] A cover window CW can be disposed on the overcoat layer OC. The cover window CW is configured to protect the layers thereunder. The cover window CW can have a refractive index higher than that of the overcoat layer OC. The cover window CW can include glass, but embodiments are not limited thereto. For example, the cover window CW can be an encapsulation glass configured to protect the components disposed thereunder. In some other embodiments, the cover window CW can be omitted.

[0135] A second polarizing element layer PEL2 can be disposed on the cover window CW. The second polarizing element layer PEL2 can include polarizing members PM overlaid with the first and second pixels PXL1 and PXL2, respectively.

[0136] The second polarizing element layer PEL2 can include polarizing elements and can convert a polarization state of light emitted by each of the first to third sub-pixels SP1 to SP3. Further, the second polarizing element layer PEL2 can include a pancake lens. The pancake lens is a lens using a folded optics, and means a lens structure in which a plurality of lenses and polarizing elements are overlaid.

[0137] Figure 6 is a plan view showing one of the pixels of Figure 5 , for a clear and brief description, the first pixel PXL1 among the first and second pixels PXL1 and PXL2 of Figure 6 is schematically shown. The remaining pixels PXL can be configured similarly to the first pixel PXL1. Figure 5

[0138] Referring to Figure 5 and Figure 6 , the first pixel PXL1 can include the first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0139] The first sub-pixel SP1 can include a first emission area EMA1 and a non-emission area NEA around (e.g., surrounding) the first emission area EMA1. The second sub-pixel SP2 can include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third sub-pixel SP3 can include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0140] The first emission area EMA1 can be an area in which light is emitted from a portion of the light emitting structure EMS (see, e.g., FIG. 1A) corresponding to the first sub-pixel SP1. The second emission area EMA2 can be an area in which light is emitted from a portion of the light emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 can be an area in which light is emitted from a portion of the light emitting structure EMS corresponding to the third sub-pixel SP3. Figure 5

[0141] is a schematic cross-sectional view taken along line I-I’ of Figure 7 , for a clear and brief description, the first pixel PXL1 among the first and second pixels PXL1 and PXL2 of Figure 6 is schematically shown. The remaining pixels PXL can be configured similarly to the first pixel PXL1. Figure 7 Figure 5 ​​a display unit DPP, a first polarizing element layer PEL1, a microlens array MLA, an overcoat layer OC, a cover window CW, and a second polarizing element layer PEL2.

[0142] Referring to Figure 7 The display unit DPP can include first to third sub-pixels SP1 to SP3. The first to third sub-pixels SP1 to SP3 can respectively emit light having different wavelengths. For example, the first sub-pixel SP1 can emit red light, the second sub-pixel SP2 can emit green light, and the third sub-pixel SP3 can emit blue light. Because the wavelength of red light is the longest among the three and the wavelength of blue light is the shortest among the three, the wavelength of light emitted by the first sub-pixel SP1 can be longer than the wavelengths of light emitted by the second sub-pixel SP2 and the third sub-pixel SP3, and the wavelength of light emitted by the second sub-pixel SP2 can be longer than the wavelength of light emitted by the third sub-pixel SP3. However, embodiments are not limited thereto.

[0143] The first polarizing element layer PEL1 can be disposed on the display unit DPP. The first polarizing element layer PEL1 can include first phase retardation units PR1, a first polarizing plate POL1, and second phase retardation units PR2.

[0144] The first phase retardation units PR1 can be disposed on the display unit DPP. The first phase retardation units PR1 can include first phase retardation plates PRP1 that convert a polarization state of light. For example, each of the first phase retardation plates PRP1 can be a 1 / 4 phase retardation plate. That is, the polarization state of light passing through the first phase retardation plates PRP1 can be converted from linear polarization to circular polarization, or can be converted from circular polarization to linear polarization. Each of the first phase retardation plates PRP1 can include liquid crystal molecules. The liquid crystal molecules can be oriented in a preset direction.

[0145] The first phase retardation plates PRP1 can be respectively overlapped with the first to third sub-pixels SP1 to SP3 and can be spaced apart from each other. The first phase retardation plates PRP1 respectively corresponding to the first to third sub-pixels SP1 to SP3 can respectively have phase differences corresponding to the wavelengths of light emitted by the first to third sub-pixels SP1 to SP3. Accordingly, the first phase retardation plates PRP1 respectively corresponding to the first to third sub-pixels SP1 to SP3 can have different phase differences.

[0146] Specifically, since each of the first phase delay plates PRP1 can be a 1 / 4 phase delay plate, the phase difference can be λ / 4. Accordingly, the respective first phase delay plates PRP1 can have different phase differences according to the wavelength of light passing through the respective first phase delay plates PRP1. For example, the phase difference of the first phase delay plate PRP1 superimposed with the first sub-pixel SP1 can be (the center wavelength of red light) / 4, the phase difference of the first phase delay plate PRP1 superimposed with the second sub-pixel SP2 can be (the center wavelength of green light) / 4, and the phase difference of the first phase delay plate PRP1 superimposed with the third sub-pixel SP3 can be (the center wavelength of blue light) / 4. Accordingly, the phase difference of the first phase delay plate PRP1 superimposed with the first sub-pixel SP1 can be the greatest, and the phase difference of the first phase delay plate PRP1 superimposed with the third sub-pixel SP3 can be the smallest.

[0147] Further, the respective first phase delay plates PRP1 can have different thicknesses according to the wavelength of light emitted by the superimposed sub-pixel among the first sub-pixel SP1 to the third sub-pixel SP3. The phase difference of each of the first phase delay plates PRP1 can be calculated by the following equation.

[0148] Equation

[0149] Γ = 2π x Δn | n e -n o | x d / λ

[0150] (where, Γ: phase difference, n e : refractive index of horizontal component, n o : refractive index of vertical component, Δn: difference between refractive index of vertical component and refractive index of horizontal component, d: thickness, λ: wavelength)

[0151] That is, according to the above equation, the thickness d of the first phase delay plate PRP1 can increase as the phase difference Γ of each of the first phase delay plates PRP1 increases and the wavelength λ of light passing through each of the first phase delay plates PRP1 increases.

[0152] Therefore, the thickness d1 of the first phase delay plate PRP1 overlaid with the first sub-pixel SP1 can be the largest because the first phase delay plate PRP1 overlaid with the first sub-pixel SP1 has the largest phase difference and the wavelength of light passing through the first phase delay plate PRP1 is the largest. Also, the thickness d3 of the first phase delay plate PRP1 overlaid with the third sub-pixel SP3 can be the smallest because the first phase delay plate PRP1 overlaid with the third sub-pixel SP3 has the smallest phase difference and the wavelength of light passing through the first phase delay plate PRP1 is the smallest. That is, the first phase delay plate PRP1 overlaid with the first sub-pixel SP1 can have a thickness d1 greater than the thickness of the first phase delay plate PRP1 overlaid with the second sub-pixel SP2 and the third sub-pixel SP3, respectively, and the first phase delay plate PRP1 overlaid with the second sub-pixel SP2 can have a thickness d2 greater than the thickness of the first phase delay plate PRP1 overlaid with the third sub-pixel SP3.

[0153] By controlling the thickness of each of the first phase delay plates PRP1, the respective first phase delay plates PRP1 can have different phase differences according to the overlaid sub-pixels. Therefore, light having different wavelengths emitted from the first sub-pixel SP1 to the third sub-pixel SP3 can be converted from linear polarization that is not elliptical polarization to complete circular polarization while passing through the first phase delay plates PRP1, respectively, and from circular polarization to complete linear polarization.

[0154] Also, the first phase delay unit PR1 can include a first light blocking pattern LSP1 surrounding the first phase delay plates PRP1. The first light blocking pattern LSP1 can absorb light incident on the first light blocking pattern LSP1 to prevent or substantially reduce color mixing.

[0155] A first polarization plate POL1 can be disposed on the first phase delay unit PR1. The first polarization plate POL1 can be a linear polarization plate. For example, the first polarization plate POL1 can be a wire grid polarization plate. That is, the first polarization plate POL1 can have a structure in which metal wires MW are disposed in the first direction DR1. The first polarization plate POL1 can transmit a P polarization component of light incident among light, which is parallel to the first direction DR1 that is an arrangement direction of the metal wires MW, and reflect an S polarization component of light, which is perpendicular to the first direction DR1 that is the arrangement direction of the metal wires MW.

[0156] A second phase delay unit PR2 can be disposed on the first polarization plate POL1. The second phase delay unit PR2 can have the same structure as the first phase delay unit PR1.

[0157] Specifically, the second phase delay unit PR2 can include second phase delay plates PRP2 that convert a polarization state of light. For example, each of the second phase delay plates PRP2 can be a 1 / 4 phase delay plate. Each of the second phase delay plates PRP2 can include liquid crystal molecules. The liquid crystal molecules can be oriented in a preset direction.

[0158] The second phase delay plates PRP2 can be respectively overlapped with the first to third sub-pixels SP1 to SP3 and can be spaced apart from each other. The first phase delay plates PRP1 and the second phase delay plates PRP2 respectively overlapped with the first to third sub-pixels SP1 to SP3 can be overlapped (e.g., overlapped) with each other. That is, the first phase delay plate PRP1 and the second phase delay plate PRP2 overlapped with the first sub-pixel SP1 can be overlapped with each other, the first phase delay plate PRP1 and the second phase delay plate PRP2 overlapped with the second sub-pixel SP2 can be overlapped with each other, and the first phase delay plate PRP1 and the second phase delay plate PRP2 overlapped with the third sub-pixel SP3 can be overlapped with each other.

[0159] The second phase delay plates PRP2 corresponding to the first to third sub-pixels SP1 to SP3, respectively, can have a phase difference corresponding to a wavelength of light emitted by the first to third sub-pixels SP1 to SP3. Accordingly, the second phase delay plates PRP2 corresponding to the first to third sub-pixels SP1 to SP3, respectively, can have different phase differences. Similarly to the first phase delay plates PRP1, the phase difference of the second phase delay plate PRP2 overlapped with the first sub-pixel SP1 can be the greatest, and the phase difference of the second phase delay plate PRP2 overlapped with the third sub-pixel SP3 can be the smallest.

[0160] Further, the respective second phase delay plates PRP2 can have different thicknesses according to wavelengths of light emitted by the overlapped sub-pixel among the first to third sub-pixels SP1 to SP3. Similarly to the first phase delay plates PRP1, as the phase difference of each of the second phase delay plates PRP2 increases and the wavelength of light passing through each of the second phase delay plates PRP2 increases, the thickness of the second phase delay plate PRP2 can increase. Accordingly, the second phase delay plate PRP2 overlapped with the first sub-pixel SP1 can have a greater thickness than the thickness of the second phase delay plates PRP2 respectively overlapped with the second sub-pixel SP2 and the third sub-pixel SP3, and the second phase delay plate PRP2 overlapped with the second sub-pixel SP2 can have a greater thickness than the thickness of the second phase delay plate PRP2 overlapped with the third sub-pixel SP3.

[0161] By controlling the thickness of each of the second phase retardation plates PRP2, the corresponding second phase retardation plates PRP2 can have different phase differences according to the superposed sub-pixels. Accordingly, the light having different wavelengths emitted from the first sub-pixel SP1 to the third sub-pixel SP3 can be converted from linear polarization that is not elliptical polarization to complete circular polarization and from circular polarization to complete linear polarization while passing through the second phase retardation plates PRP2, respectively.

[0162] Further, the second phase retardation unit PR2 can include a second light blocking pattern LSP2 surrounding the second phase retardation plates PRP2. The second light blocking pattern LSP2 can absorb light incident on the second light blocking pattern LSP2 to prevent or substantially reduce color mixing.

[0163] The first polarization plate POL1 can transmit a P polarization component of light parallel to the first direction DR1 that is an arrangement direction of the metal wires MW among the light emitted from the display unit DPP and can reflect an S polarization component of light perpendicular to the first direction DR1 that is the arrangement direction of the metal wires MW. The S polarization component reflected by the first polarization plate POL1 can pass through the first phase retardation unit PR1, can be converted into circularly polarized light, and can be incident on the display unit DPP. The light converted into circularly polarized light can be reflected again by the metal layer (e.g., an anode electrode AE and a cathode electrode CE) of the display unit DPP, can pass through the first phase retardation unit PR1, and can be converted into a P polarization component. The P polarization component can pass through the first polarization plate POL1, can pass through the second phase retardation unit PR2, and can be converted into circularly polarized light. Figure 5

[0164] The microlens array MLA can be disposed on the first polarization element layer PEL1. The microlens array MLA can include microlenses MLS superposed with the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the microlenses MLS can improve light emission efficiency by outputting light emitted from the light emitting structure EMS to an intended path. The microlens array MLA can have a relatively high refractive index. For example, the microlens array MLA can have a refractive index higher than that of the outer coating layer OC. In some embodiments, the microlenses MLS can include an organic material. In some embodiments, the microlenses MLS can include an acrylic material. However, the material of the microlenses MLS is not limited thereto.

[0165] The outer coating layer OC can cover the microlens array MLA on the microlens array MLA. The cover window CW can be disposed on the outer coating layer OC.

[0166] The second polarization element layer PEL2 can be disposed on the cover window CW. The second polarization element layer PEL2 can include a pancake lens.

[0167] ​The second polarizing element layer PEL2 can be entirely superimposed with the first to third sub-pixels SP1 to SP3. Each of the polarizing members PM (see, for example, FIG. 6B) included in the second polarizing element layer PEL2 can be superimposed with one pixel PXL1 or PXL2 (see, for example, FIG. 6A) including the first to third sub-pixels SP1 to SP3. That is, one polarizing member PM can be provided per one pixel PXL1 or PXL2. Figure 5 Figure 5

[0168] The second polarizing element layer PEL2 can include a half mirror HM, a lens LS, a third phase retardation unit PR3, and a second polarizing plate POL2.

[0169] The half mirror HM can be provided on the cover window CW. The half mirror HM can transmit light (e.g., light incident from a lower portion of the half mirror HM) incident in a third direction DR3 and reflect light (e.g., light incident from an upper portion of the half mirror HM) incident in a direction opposite to the third direction DR3.

[0170] The third phase retardation unit PR3 can be provided on the half mirror HM. The third phase retardation unit PR3 can have the same structure as the first and second phase retardation units PR1 and PR2. Thus, the third phase retardation unit PR3 can include third phase retardation plates PRP3 that convert a polarization state of light. Each of the third phase retardation plates PRP3 can be a 1 / 4 phase retardation plate. The third phase retardation plates PRP3 corresponding to the first to third sub-pixels SP1 to SP3, respectively, can have different phase differences. The respective third phase retardation plates PRP3 can have different thicknesses according to wavelengths of light emitted by the superimposed sub-pixel among the first to third sub-pixels SP1 to SP3. Further, the third phase retardation unit PR3 can include a third light blocking pattern LSP3 that surrounds the third phase retardation plates PRP3. The third light blocking pattern LSP3 can absorb light incident on the third light blocking pattern LSP3 to prevent or substantially reduce color mixing.

[0171] The second polarizing plate POL2 can be provided on the third phase retardation unit PR3. The second polarizing plate POL2 can be a reflective polarizing plate. Thus, the second polarizing plate POL2 can reflect a portion of incident light and transmit a portion of incident light.

[0172] ​​In some embodiments, the second polarizing plate POL2 can have the same structure as the first polarizing plate POL1. For example, the second polarizing plate POL2 can be a wire grid polarizing plate. That is, the second polarizing plate POL2 can have a structure in which metal wires MW are disposed in the first direction DR1. The second polarizing plate POL2 can transmit a P polarization component of light among incident light that is parallel to the first direction DR1 that is the arrangement direction of the metal wires MW, and reflect an S polarization component of light that is perpendicular to the first direction DR1 that is the arrangement direction of the metal wires MW.

[0173] At least one lens LS can be disposed between the half mirror HM and the second polarizing plate POL2. The lens LS can have a structure in which a convex lens and a concave lens are combined. Thereby, the lens LS can magnify an image.

[0174] In some embodiments, the lens LS can be disposed between the half mirror HM and the third phase delay unit PR3. In some other embodiments, the lens LS can be disposed between the third phase delay unit PR3 and the second polarizing plate POL2. In yet some other embodiments, the lens LS can be disposed between the half mirror HM and the third phase delay unit PR3 and between the third phase delay unit PR3 and the second polarizing plate POL2, respectively. However, embodiments are not limited thereto.

[0175] Light that passes through the first polarizing element layer PEL1 and is converted into circularly polarized light can be transmitted through the half mirror HM, can pass through the third phase delay unit PR3, and can be converted into linearly polarized light. The light converted into linearly polarized light can be reflected by the second polarizing plate POL2, can pass through the third phase delay unit PR3 again, and can be converted into circularly polarized light again. The light converted into circularly polarized light again can be reflected by the half mirror HM, can be incident on the third phase delay unit PR3, can pass through the third phase delay unit PR3, and can be converted into linearly polarized light again. The light converted into linearly polarized light can be transmitted through the second polarizing plate POL2, and can be emitted to the outside of the display device 101.

[0176] In some embodiments, since the phase delay plate having a different thickness for each sub-pixel is disposed on the display unit DPP, the phase delay unit can achieve a phase difference of 1 / 4 wavelength with respect to light of all wavelengths emitted by the sub-pixel, respectively. Accordingly, since linear polarization is converted into complete circular polarization and circular polarization is converted into complete linear polarization with respect to light of all wavelengths emitted by the sub-pixel, ghosting phenomenon for each wavelength can be improved. Further, the brightness and light emission efficiency of the display device 101 can be improved.

[0177] Figure 8 is a schematic cross-sectional view according to some other embodiments of the disclosure.

[0178] The display device 102 according to some embodiments is different from the display device 101 described above in that the second polarizing element layer PEL2 includes the first lens LS1 to the third lens LS3. Therefore, the content that can overlap with the above is briefly described or not repeated. Figure 7

[0179] Referring to Figure 8 , the second polarizing element layer PEL2 can include the half mirror HM, the first lens LS1, the second lens LS2, the third phase retardation unit PR3, the second polarizing plate POL2, and the third lens LS3.

[0180] The first lens LS1 can be disposed between the half mirror HM and the third phase retardation unit PR3. The second lens LS2 can be disposed between the first lens LS1 and the third phase retardation unit PR3. The third lens LS3 can be disposed on the second polarizing plate POL2. Each of the first lens LS1 to the third lens LS3 can have a structure in which a convex lens and a concave lens are combined. Thereby, the first lens LS1 to the third lens LS3 can magnify an image.

[0181] Because the second polarizing element layer PEL2 includes three lenses, an image can be further magnified, and chromatic aberration of the lenses can be reduced. Thereby, display quality of the display device 102 can be improved. Embodiments are not limited thereto, and the second polarizing element layer PEL2 can include four or more lenses.

[0182] Figure 9 is a schematic cross-sectional view according to still other embodiments of the disclosure.

[0183] The display device 103 according to some embodiments is different from the display device 102 described above in that the display device 103 further includes the third polarizing plate POL3. Therefore, the content that can overlap with the above is briefly described or not repeated. Figure 8 Referring to

[0184] , the second polarizing element layer PEL2 can include the half mirror HM, the first lens LS1, the second lens LS2, the third phase retardation unit PR3, the second polarizing plate POL2, the third lens LS3, and the third polarizing plate POL3. Figure 9

[0185] ​​The third polarizing plate POL3 can be disposed on the third lens LS3. The third polarizing plate POL3 can be an absorption-type polarizing plate. Since the third polarizing plate POL3 can be disposed at the uppermost portion of the display device 103, when external light incident on the display device 103 is reflected by the second polarizing element layer PEL2, the third polarizing plate POL3 can absorb the reflected light. That is, the third polarizing plate POL3 can prevent or substantially block external light from being reflected and emitted to the outside of the display device 103. Accordingly, external light reflection of the display device 103 can be prevented, or the amount or frequency of external light reflection can be substantially reduced.

[0186] Figure 10 is a block diagram illustrating some embodiments of a display system according to some embodiments of the present disclosure.

[0187] Referring to Figure 10 , the display system 1000 can include a processor 1100 and one or more display devices 1210 and 1220.

[0188] The processor 1100 can perform various tasks and calculations. In some embodiments, the processor 1100 can include an application processor, a graphics processor, a microprocessor, and / or a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system, and can control the other components.

[0189] In Figure 10 , the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1, and can be connected to the second display device 1220 through a second channel CH2.

[0190] Through the first channel CH1, the processor 1100 can transmit first image data IMG1 and first control signals CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signals CTRL1. The first display device 1210 can be configured similarly to the display device 100 described with reference to Figure 1 . For example, the first image data IMG1 and the first control signals CTRL1 can be provided as input image data IMG and control signals CTRL, respectively. Figure 1

[0191] Through the second channel CH2, the processor 1100 can transmit second image data IMG2 and second control signals CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signals CTRL2. The second display device 1220 can be configured similarly to the display device 100 described with reference to​Figure 1 The described display apparatus 100 is similarly configured. For example, the second image data IMG2 and the second control signal CTRL2 can be provided as Figure 1 input image data IMG and a control signal CTRL of

[0192] The display system 1000 can include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, an ultra-mobile personal computer (UMPC), etc. Also, the display system 1000 can include at least one of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc.

[0193] Figure 11 is a perspective view showing an application example of a display system according to some embodiments of the present disclosure. Figure 10

[0194] Referring to Figure 11 , Figure 10 The display system 1000 of

[0195] The head-mounted display apparatus 2000 can include a head-mounted band 2100 and a display apparatus accommodating case 2200. The head-mounted band 2100 can be connected to the display apparatus accommodating case 2200. The head-mounted band 2100 can include a horizontal band and / or a vertical band for fixing the display apparatus accommodating case 2200 to a head of a user. The horizontal band can be configured to surround a side of the head of the user, and the vertical band can be configured to surround an upper portion of the head of the user. However, embodiments are not limited thereto. For example, the head-mounted band 2100 can be implemented in the form of a spectacle frame, a helmet, etc.

[0196] The display apparatus accommodating case 2200 can accommodate Figure 10 the first display apparatus 1210 and the second display apparatus 1220 of Figure 10 the processor 1100.

[0197] Figure 12 is a perspective view showing an application example of a display system according to some embodiments of the present disclosure. Figure 11

[0198] Referring to Figure 12 ​​In the head-mounted display device 2000, a first display panel DP1 of the first display device 1210 and a second display panel DP2 of the second display device 1220 are disposed. The head-mounted display device 2000 can further include one or more lenses LLNS and RLNS.

[0199] Within the display device housing 2200, the right-eye lens RLNS can be disposed between the first display panel DP1 and the user's right eye. Within the display device housing 2200, the left-eye lens LLNS can be disposed between the second display panel DP2 and the user's left eye.

[0200] An image output from the first display panel DP1 can be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 to be directed toward the user's right eye. The right-eye lens RLNS can perform an optical function for adjusting a viewing distance between the first display panel DP1 and the user's right eye.

[0201] An image output from the second display panel DP2 can be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 to be directed toward the user's left eye. The left-eye lens LLNS can perform an optical function for adjusting a viewing distance between the second display panel DP2 and the user's left eye.

[0202] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS can include an optical lens having a thin-pie-shaped cross-section. In embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS can include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel can output an image corresponding to the sub-regions of the multi-channel lens, respectively, and the output images can pass through the respective corresponding sub-regions and can be viewed by the user.

[0203] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the attached drawings, it will be evident for those skilled in the art that various changes can be made in form and details without departing from the spirit and scope of the application as defined by the following claims and their equivalents.

Claims

1. A display device, characterized by comprising: The display device includes: a substrate; a display unit on the substrate and including first, second, and third sub-pixels configured to emit different colors of light; a first phase delay unit on the display unit and including first phase delay plates respectively superposed with the first to third sub-pixels and having different phase differences from each other; a first polarizing plate on the first phase delay unit; a second phase delay unit on the first polarizing plate and including second phase delay plates respectively superposed with the first to third sub-pixels and having different phase differences from each other; and a polarizing element layer on the second phase delay unit and including a thin pancake lens.

2. The display device according to claim 1, wherein Each of the first and second phase delay plates has a phase difference corresponding to a wavelength of light emitted by a corresponding superposed sub-pixel among the first to third sub-pixels.

3. The display device according to claim 2, wherein Each of the first and second phase delay plates has a thickness different from each other according to the wavelength of the light emitted by the corresponding superposed sub-pixel among the first to third sub-pixels.

4. The display device according to claim 3, wherein A wavelength of light emitted by the first sub-pixel is longer than a wavelength of light emitted by the second sub-pixel and a wavelength of light emitted by the third sub-pixel, and the wavelength of the light emitted by the second sub-pixel is longer than the wavelength of the light emitted by the third sub-pixel.

5. The display device according to claim 4, wherein Among the first and second phase delay plates, a phase delay plate superposed with the first sub-pixel has a thickness greater than thicknesses of a phase delay plate superposed with the second sub-pixel and a phase delay plate superposed with the third sub-pixel.

6. The display device according to claim 5, wherein Among the first and second phase delay plates, the phase delay plate superposed with the second sub-pixel has a thickness greater than a thickness of the phase delay plate superposed with the third sub-pixel.

7. The display device according to claim 2, wherein Each of the first and second phase delay plates is a 1 / 4 phase delay plate.

8. The display device according to claim 7, wherein The first and second phase delay plates respectively superposed with the first to third sub-pixels are superposed with each other, and The first and second phase delay units have the same structure.

9. The display device according to claim 1, wherein The polarizing element layer is superposed with the first to third sub-pixels.

10. The display device according to claim 9, wherein The polarizing element layer includes: a half mirror on the second phase delay unit; a third phase delay unit on the half mirror; a second polarizing plate on the third phase delay unit; and at least one lens between the half mirror and the second polarizing plate.

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