Chip, packaging structure, circuit board assembly and electronic equipment

Abstract

The utility model relates to a chip, a packaging structure, a circuit board assembly and electronic equipment. The chip comprises a processor and a plurality of power supply control units, the processor comprises a plurality of power supply domains, the plurality of power supply control units are correspondingly connected with the plurality of power supply domains, and each power supply control unit is used for connecting or disconnecting a power supply path of the power supply domain connected with the power supply control unit; wherein the chip comprises a first area and a second area, the processor is arranged in the first area, and the plurality of power supply control units are arranged in the second area. According to the invention, the power supply control unit and the processor are arranged in different areas, the working frequency of the power supply control unit does not impact the working frequency of the processor, the working frequency of the processor can reach the expected working frequency, the power consumption of the processor is reduced, the operation speed of the processor is high, and the user experience is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of chips, and in particular, to a chip, a packaging structure, a circuit board assembly, and an electronic device. BACKGROUND

[0002] A chip generally refers to an integrated circuit, which is a microcircuit that integrates transistors, resistors, capacitors, and other electronic components on a single substrate through a specific technology. The main function of a chip is to perform specific electronic functions, such as data processing, signal amplification, and information storage. Chips are ubiquitous in modern technology and daily life, from supercomputers to smartphones, from automation equipment to smart homes, and chips are the core components. SUMMARY

[0003] To overcome the problems in the related art, the present disclosure provides a chip, a packaging structure, a circuit board assembly, and an electronic device.

[0004] According to a first aspect of some example embodiments of the present disclosure, a chip is provided, comprising:

[0005] a processor comprising a plurality of power domains;

[0006] a plurality of power control units corresponding to the plurality of power domains, each power control unit being configured to connect or disconnect a power supply path of the power domain connected to the power control unit;

[0007] wherein the chip comprises a first region and a second region, the processor is disposed in the first region, and the plurality of power control units are disposed in the second region.

[0008] In some example embodiments of the present disclosure, the power domain comprises a plurality of branch domains and a plurality of parallel first branches, each first branch connecting at least one branch domain.

[0009] A first end of each power control unit is connected to the power supply path, and a second end of each power control unit is connected to the first branch of the corresponding power domain.

[0010] In some example embodiments of the present disclosure, a plurality of power control units are arranged in an array in the second region, the plurality of power control units are one-to-one connected to the plurality of power domains, and each power control unit comprises at least one control switch.

[0011] In some example embodiments of the present disclosure, each power control unit comprises at least two control switches, and the first region comprises opposite first and second sides.

[0012] In the same power supply control unit, a part of the control switches are arranged on a first side of the first region, and another part of the control switches are arranged on a second side of the first region.

[0013] In some example embodiments of the present disclosure, the power supply control units and the power supply domains connected with the power supply control units are located in the same deposition layer of the chip.

[0014] In some example embodiments of the present disclosure, the first region and the second region do not overlap on the plane where the chip is located.

[0015] According to a second aspect of the embodiments of the present disclosure, a packaging structure is provided, comprising a packaging substrate and any one of the chips according to the first aspect of the present disclosure, the chip is packaged in the packaging substrate, and the power supply control units of the chip are electrically connected with the packaging substrate, and the power supply control units are used to open or close the power supply path between the packaging substrate and the power supply domains of the chip.

[0016] In some example embodiments of the present disclosure, the packaging substrate is provided with a current sharing circuit, the current sharing circuit comprises a plurality of parallel second branches, and each second branch is electrically connected with at least one first branch of the power supply domains.

[0017] In some example embodiments of the present disclosure, the packaging substrate is provided with an input circuit, and the packaging substrate is provided with a power supply circuit, the first end of each power supply control unit is connected with the power supply circuit, and the second end of each power supply control unit is connected with the current sharing circuit.

[0018] In some example embodiments of the present disclosure, the packaging substrate and the chip are stacked, and the packaging substrate and the chip are electrically connected through first pads.

[0019] According to a third aspect of the embodiments of the present disclosure, a circuit board assembly is provided, comprising a circuit board, and the circuit board is electrically connected with any one of the packaging structures according to the second aspect of the present disclosure.

[0020] In some example embodiments of the present disclosure, the packaging substrate of the packaging structure is electrically connected with the circuit board through second pads.

[0021] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, comprising any one of the circuit board assemblies according to the third aspect of the present disclosure.

[0022] The technical scheme provided by the embodiment of the present disclosure can have the following beneficial effects: in the present disclosure, since the power control unit and the processor are arranged in different areas, the working frequency of the power control unit does not impact the working frequency of the processor, the working frequency of the processor can reach the expected working frequency, the power consumption of the processor is reduced, the operation speed of the processor is fast, and the user experience is improved.

[0023] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure, in conjunction with the description.

[0025] Figure 1 is a schematic diagram of a chip according to an exemplary embodiment.

[0026] Figure 2 is a schematic diagram of a chip according to an exemplary embodiment.

[0027] Figure 3 is a schematic diagram of a packaging structure according to an exemplary embodiment.

[0028] Figure 4 is a schematic diagram of a packaging structure according to an exemplary embodiment.

[0029] Figure 5 is a schematic diagram of a packaging structure according to an exemplary embodiment.

[0030] Figure 6 is a schematic diagram of a packaging structure according to an exemplary embodiment.

[0031] Figure 7 is a schematic diagram of a circuit board assembly according to an exemplary embodiment.

[0032] Figure 8 is a schematic diagram of a circuit board assembly according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is only exemplary and explanatory, and is not restrictive of the present disclosure.

[0034] Power Domain is a technical concept used to manage the power supply state of different modules or areas in integrated circuit design. By dividing independent power supply areas, power domain realizes power control of different circuit modules. When some areas or modules do not need to work, the power supply of the area or the module can be cut off to achieve the purpose of optimizing power consumption and improving energy efficiency. For example, a processor can include multiple functional modules. Functional modules working at the same voltage and with cohesive functions can be divided into a logical group. One logical group divided in this way is a power domain. The power domain can be a logical division, which can include the connection relationship of physical entities and power lines.

[0035] Through research and testing, it is found that when the power control unit used to connect or disconnect the connection between the power domain and the power path is arranged in the processor, the power control unit will cause an impact on the working frequency of the processor when it works, resulting in a decrease in the working frequency of the processor. The working frequency of the processor cannot reach the expected working frequency, the operation speed of the processor is reduced, and the user experience is affected.

[0036] In order to avoid the impact of the power control unit on the working frequency of the processor when it works, the present disclosure provides a chip. By adjusting the setting position of the power control unit used to control the power supply path of the power domain, the power control unit and the processor are arranged in different areas of the chip, thereby reducing the impact of the power control unit on the working frequency of the processor and improving the working performance of the processor.

[0037] In an exemplary embodiment, as Figure 1As shown, the embodiment shows a chip 122, which includes a processor 1221, which is the core part of the chip, which undertakes the functions of instruction processing, data operation, control coordination, storage management, terminal processing, system call, etc. According to different application scenarios of the processor, the processor in the chip in the present disclosure can include a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), a tensor processing unit (TPU), an intelligent processing unit (IPU), etc. In one example, the chip in the present disclosure can be a chip of an electronic device for core data processing, wherein the electronic device can be a mobile phone, a tablet computer, a notebook computer, a wearable device, a sensor, etc. A device with a data processing function. The processor 1221 can be the main CPU of the electronic device, and the main CPU can be a large core. The large core has higher performance than other types of CPUs, has higher main frequency, larger cache and stronger computing power, and is used to process tasks with high computing demand, such as complex calculation, graphics rendering, large game and scientific calculation, etc. The processor 1221 can also be other types of processors, such as GPU, NPU, DPU, TPU, IPU, etc.

[0038] The processor 1221 includes multiple power domains (not shown in the figure), and the chip 122 also includes multiple power control units 1222. The power domains are electrically connected to the power control units 1222, and the multiple power control units 1222 are correspondingly connected to the multiple power domains. Each power control unit 1222 is used to connect or disconnect the power supply path of the power domain to which it is connected, thereby supplying or de-energizing the power domain. In one example, the correspondence between the multiple power domains and the multiple power control units 1222 can be one-to-one, meaning one power domain is electrically connected to one power control unit 1222. In another example, the correspondence between the multiple power domains and the multiple power control units 1222 can also be many-to-one, meaning multiple power domains are connected to one power control unit 1222, so that the power supply path of multiple power domains can be connected or disconnected through one power control unit 1222. For example, when there is no hierarchical relationship between the multiple power domains, a one-to-one correspondence can be used between the power domains and the power control units 1222, thereby ensuring that multiple power domains can be controlled individually. For example, when there is a "parent-child relationship" between multiple power domains, a many-to-one correspondence can be adopted between the power domain and the power control unit 1222, thereby ensuring that multiple power domains belonging to the same "parent" can be controlled simultaneously.

[0039] It should be noted that, referring to Figure 1 The diagram shows the device distribution on a cross-section of the chip. In reality, each structure is arranged in an array perpendicular to the plane of the paper or the display. Figure 1 The image shows a power control unit 1222, and multiple cross sections are provided along a direction perpendicular to the paper or display, with the power control unit 1222 provided on each cross section.

[0040] Chip 122 includes a first region 1223 and a second region 1224. Processor 1221 is disposed in the first region 1223, and multiple power control units 1222 are disposed in the second region 1224. The first region 1223 and the second region 1224 are different physical regions. The second region 1224 is located on the periphery of the first region 1223; that is, the second region 1224 can be a peripheral circuit region. Of course, it is understood that in some possible cases, the first region 1223 and the second region 1224 can also be arranged side-by-side. This disclosure does not restrict the position of the first region 1223 and the second region 1224, as long as physical isolation exists between the second region 1224 and the first region 1223, ensuring that the power control units 1222 are not located within the processor 1221. (Reference) Figure 1 As shown, the first region 1223 and the second region 1224 are two non-overlapping regions, meaning that the power control unit 1222 is located outside the processor 1221.

[0041] The power supply control unit 1222 can be a block head switch (BHS), which can include one or more pull-up transistors or metal oxide semiconductor devices. The power supply control unit 1222 can also be any other device that can be used to connect or disconnect the power supply path of the corresponding power supply domain.

[0042] The power supply control unit 1222 can be controlled to turn on or off by a low-power management module inside the chip 122. The control signal of the low-power management module can be connected to the signal terminal of the power supply control unit 1222 to control the power supply control unit 1222 to turn on or off. Compared with introducing a control signal from outside the chip 122, using the low-power management module inside the chip 122 to control the power supply control unit 1222 to turn on or off reduces the number of connection lines between the chip 122 and the outside. The power supply control unit 1222 can also be controlled to turn on or off by a control signal from other devices.

[0043] The power supply domain can or can not include branch domains, which are sub-domains of the power supply domain. In the case where the power supply domain does not include branch domains, the power supply control unit 1222 can be directly connected to the power supply domain. In the case where the power supply domain includes multiple parallel branch domains, the power supply control unit 1222 can be connected to the multiple parallel branch domains through, for example, a current sharing circuit. Branches of the current sharing circuit are connected to the branch domains to share current among the multiple parallel branch domains, so that the current is evenly distributed among the multiple parallel branch domains. The current sharing circuit refers to a circuit design whose core purpose is to ensure that the current is evenly distributed among multiple parallel loads or modules. The current sharing circuit can be arranged in the chip 122 or in the packaging substrate to which the chip 122 is packaged. The current sharing capability of the current sharing circuit arranged in the packaging substrate is stronger than that arranged in the chip 122.

[0044] In this embodiment, since the power supply control unit for connecting or disconnecting the power supply path of the power supply domain is arranged in a different area from the processor, the working frequency of the power supply control unit does not affect the working frequency of the processor. The working frequency of the processor can reach the expected working frequency, reducing the power consumption of the processor, increasing the processing speed of the processor, and improving the user experience.

[0045] In some possible embodiments, the first area 1223 and the second area 1224 do not overlap on the plane on which the chip 122 is arranged. For example, as shown in FIG. 12, the first area 1223 and the second area 1224 do not overlap on the plane on which the chip 122 is arranged. Figure 1As shown, the second region 1224 is located at the periphery of the first region 1223 in the plane where the chip 122 is located, and the second region 1224 and the first region 1223 do not overlap. Of course, it can be understood that, in some possible cases, the first region 1223 and the second region 1224 can also be regions arranged side by side in the plane where the chip 122 is located, and the disclosure does not limit the positions of the first region 1223 and the second region 1224 as long as the first region 1223 and the second region 1224 do not overlap. The first region 1223 and the second region 1224 do not overlap, and the processor 1221 and the power control unit 1222 are arranged in the two regions that do not overlap.

[0046] In this embodiment, the first region and the second region do not overlap in the plane where the chip is located, which can ensure that the power control unit is not arranged in the processor, the working frequency of the power control unit does not cause an impact on the working frequency of the processor, the working frequency of the processor can reach the expected working frequency, the power consumption of the processor is reduced, the processing speed of the processor is fast, and the user experience is improved.

[0047] In some possible embodiments, as Figure 2 As shown, the power domain of the chip 122 in this embodiment includes a plurality of branch domains (not shown in the figure) and a plurality of parallel first branches 1225, and each first branch 1225 is connected to at least one branch domain. The branch domain is a subdomain of the power domain, and for a plurality of branch domains in the same power domain, power supply or power-off needs to be performed at the same time. The first branch 1225 can be a part of the power supply path of the branch domain located in the power domain, and a plurality of first branches 1225 of the same power domain are in a parallel relationship to simultaneously supply power or cut off power to a plurality of branch domains of the power domain. In one example, the correspondence between the plurality of first branches 1225 and the plurality of branch domains can be one-to-one, that is, one first branch 1225 is connected to one branch domain; in another example, the correspondence between the plurality of first branches 1225 and the plurality of branch domains can also be one-to-many, that is, one first branch 1225 is connected to a plurality of branch domains.

[0048] The first end of each power control unit 1222 is connected to the power supply path, and the second end of each power control unit 1222 is connected to the first branch 1225 of the corresponding power domain. The first end of the power control unit 1222 is connected to the power supply path, and the second end is connected to a plurality of parallel first branches 1225 of the corresponding power domain, and each first branch 1225 is connected to a corresponding branch domain, so that one power control unit 1222 can be used to control a plurality of branch domains of the corresponding power domain, and power supply or power-off is simultaneously performed on the plurality of branch domains.

[0049] The second end of the power control unit 1222 is connected to the first branch 1225 of the corresponding power domain. The second end of the power control unit 1222 can be connected to a current sharing circuit, and the branches of the current sharing circuit are connected to the first branches 1225 of the corresponding power domains, so that the current is evenly distributed in the multiple parallel branch domains. Alternatively, as shown in the figure, the second end of the power control unit 1222 is directly connected to the first branch 1225 of the corresponding power domain. Figure 2

[0050] In this embodiment, one power control unit corresponding to a power domain can simultaneously connect or disconnect the power supply paths of multiple branch domains of the power domain, reducing the number of power control units, reducing the size of the chip, and reducing the cost.

[0051] In some possible embodiments, the multiple power control units 1222 of the chip 122 are arranged in an array in the second region 1224. The array arrangement means that multiple identical devices are arranged according to a certain rule, which has the advantages of improving production efficiency, reducing parasitic parameters, facilitating maintenance and upgrading, improving electrical performance, standardization and consistency, and the like. The array mode of the power control units 1222 can be adjusted. For example, the power control units 1222 can be arranged along the arrangement mode of the power domains, so as to facilitate wiring. For example, the power control units 1222 can be arranged in one column or two columns.

[0052] In order to improve the control reliability and accuracy, the multiple power control units 1222 are connected one by one with the multiple power domains, that is, one power control unit 1222 controls the on-off of the power of one power domain, so as to separately control the power supply and power-off of each power domain.

[0053] Each power control unit 1222 includes at least one control switch. The low-power management module inside the chip 122 can be used to control the opening and closing of the at least one control switch. The power control unit 1222 can include one control switch or multiple control switches. When each power control unit 1222 includes one control switch, the control switch is used to connect or disconnect the power supply path of the corresponding power domain under the control of the low-power management module. At this time, a control switch with good control performance can be selected. When each power control unit 1222 includes multiple control switches, the multiple control switches can be simultaneously opened and closed under the control of the low-power management module, and are used to connect or disconnect the power supply circuit of the corresponding power domain. The control signals generated by other devices can also be used to control the opening and closing of the control switches of the power control unit 1222.

[0054] ​In the embodiment, the plurality of power supply control units are arranged in an array, the performance and integration of the chip are improved, and the production efficiency is improved, and the maintenance is facilitated. Each power supply domain corresponds to a separate power supply control unit, so that the connection or disconnection of the power supply path of each power supply domain can be controlled individually, and the power supply paths do not affect each other.

[0055] In some possible embodiments, each power supply control unit 1222 of the chip 122 includes at least two control switches 1222a and 1222b. In actual applications, the maximum current value that can be continuously carried by one control switch may be smaller than the current value required by the corresponding power supply domain, at this time, a plurality of control switches are needed to form one power supply control unit 1222 to increase the current value that can be carried by the entire power supply control unit 1222, and the plurality of control switches jointly connect or disconnect the power supply path of the corresponding power supply domain.

[0056] The first region 1223 of the chip 1222 includes opposite first and second sides, and in the same power supply control unit 1222, part of the control switches are arranged on the first side of the first region 1223, and the other part of the control switches are arranged on the second side of the first region 1223. For example, Figure 2 The first side can be the left side of the first region 1223, and the second side can be the right side of the first region 1223. For example, Figure 2 The first side can be the left side of the first region 1223, and the second side can be the right side of the first region 1223. For example,

[0057] The low-power consumption management module inside the chip 122 can be used to control the at least two control switches in one power supply control unit 1222 to be simultaneously turned on and turned off, or control signals generated by other devices can be used to control the at least two control switches in one power supply control unit 1222 to be simultaneously turned on and turned off. It should be noted that, Figure 2 The device distribution on one section of the chip is shown in the figure, and the actual structures are arranged in an array along the direction perpendicular to the paper or the display, that is, Figure 2 The two control switches 1222a and 1222b belonging to one power supply control unit 1222 are shown in FIG. 1, and a plurality of sections are also arranged along the direction perpendicular to the paper or the display, and each section is provided with a power supply control unit 1222, and each power supply control unit 1222 includes two control switches 1222a and 1222b.

[0058] In this embodiment, a power control unit includes multiple control switches. These multiple control switches connect or disconnect the power supply path of a corresponding power domain, which can provide a larger power supply current to the power domain and meet the power domain's energy requirements.

[0059] In some possible embodiments, the power control unit 1222 and the power domain connected to the power control unit 1222 are located on the same deposition layer of the chip 122. The deposition layer of the chip refers to various thin film layers formed during chip manufacturing using thin film deposition technology. The fact that the power control unit 1222 and the power domain connected to the power control unit 1222 are located on the same deposition layer of the chip 122 means that the power control unit 1222 and the power domain connected to the power control unit 1222 coexist on a physical structure layer formed during chip manufacturing using the same or the same type of thin film deposition process.

[0060] In this embodiment, the power control unit and the power domain connected to it are located on the same deposition layer of the chip, which can improve the chip's integration, shorten the connection length between the power control unit and the power domain, reduce power consumption, and improve the chip's performance.

[0061] In one exemplary embodiment, such as Figure 3 As shown in the figure, this embodiment illustrates a packaging structure 12. A packaging structure refers to a structure that encapsulates a semiconductor integrated circuit chip within a casing, primarily serving to mount, fix, seal, and protect the chip, as well as enhance its electrothermal performance. A packaging structure typically includes several parts such as a substrate, chip, wires, packaging casing, and leads.

[0062] The packaging structure 12 includes a packaging substrate 121 and a chip 122 as described in any of the above embodiments, with the chip 122 packaged within the packaging substrate 121. The packaging substrate is a substrate used to establish electrical connections between the chip and the printed circuit board, serving functions such as carrying, protecting, fixing, and supporting the chip, providing heat dissipation channels, and realizing electrical and physical connections between the chip and the printed circuit board. In this embodiment, the chip 122 can be packaged within the packaging substrate 121 using HBPOP (High Bandwidth Package-on-Package) or COWOS (Chip-on-Wafer-on-Substrate) packaging technologies, or other feasible packaging technologies. HBPOP is an advanced semiconductor packaging technology that combines high bandwidth and stacked packaging advantages, primarily used to improve inter-chip data transfer rates and integration density. COWOS is a 2.5D / 3D advanced packaging technology designed for high-performance computing, artificial intelligence chips, and high-bandwidth memory integration, significantly improving chip performance, interconnect density, and energy efficiency through multi-layer stacking and heterogeneous integration.

[0063] It should be noted that the chip 122 in the present disclosure can be packaged on the packaging substrate 121 by using the above-mentioned stacked packaging technology, or can be packaged on the packaging substrate 121 by using a conventional packaging technology. The improvement of the structure of the chip 122 in the present disclosure is not affected by the packaging process.

[0064] The plurality of power supply control units 1222 of the chip 122 are electrically connected with the packaging substrate 121. The power supply control unit 1222 is used to open or close the power supply path between the packaging substrate 121 and the power supply domain of the chip 122. The power supply control unit 1222 can be electrically connected with the packaging substrate 121 by a bonding pad, or can be electrically connected with the packaging substrate 121 by any other feasible manner, such as a wire bonding manner. The packaging substrate 121 can include a power supply circuit. The external device provides power to the power supply circuit, for example, a power management chip packaged on a circuit board of the packaging substrate 121 provides power to the power supply circuit in the packaging substrate 121, or other external devices provide power to the power supply circuit in the packaging substrate 121. The power supply control unit 1222 in the chip 122 is electrically connected with the packaging substrate 121, and is used to open or close the power supply path between the packaging substrate 121 and the power supply domain, which can be to open or close the power supply path between the power supply circuit in the packaging substrate 121 and the power supply domain.

[0065] In the embodiment, the chip is packaged on the packaging substrate, and the power supply control unit is electrically connected with the packaging substrate to open or close the power supply path between the packaging substrate and the power supply domain.

[0066] The current sharing circuit refers to a circuit design whose core purpose is to ensure that the current is evenly distributed in multiple parallel loads or modules. When the power supply domain includes multiple branch domains, a current sharing circuit needs to be set to make the current evenly distributed in multiple parallel branch domains. After research and detection, it is found that when the current sharing circuit is set in the chip, the problem of insufficient power supply at the center point will occur. In order to avoid the problem of insufficient power supply at the center point, in some possible embodiments, as shown in Figure 4 The packaging substrate 121 of the packaging structure 12 sets the current sharing circuit 1211. The current sharing circuit 1211 set in the packaging substrate 121 has stronger current sharing capability than the current sharing circuit set in the chip, and the problem of insufficient power supply at the center point will not occur.

[0067] The current sharing circuit 1211 includes a plurality of parallel second branches 1212. Each second branch 1212 is electrically connected with at least one first branch 1225 of the power supply domain. As known from the above embodiment, each first branch 1225 is electrically connected with at least one branch domain, so that the current sharing circuit 1211 can make the current evenly distributed in the plurality of parallel branch domains. Figure 4Based on the indicated orientation, the power control unit 1222 includes at least two control switches 1222a and 1222b located on the left and right sides of the processor 1221, respectively. The current sharing circuit 1211 can be electrically connected to multiple control switches of the power control unit 1222, thereby enabling the power control unit 1222 to connect or disconnect the power supply path of the corresponding power domain.

[0068] The second branch 1212 can be electrically connected to the first branch 1225 via a pad, or via any other feasible method, such as wire bonding.

[0069] In this embodiment, the current sharing circuit is placed in the packaging substrate to enhance the current sharing capability of the current sharing circuit and avoid the problem of insufficient power supply at the center point.

[0070] In some possible embodiments, such as Figure 5 As shown, the packaging substrate 121 of the packaging structure 12 is provided with a power supply circuit 1213. The power supply circuit 1213 of the packaging substrate 121 can be used to introduce power from the outside, for example, by introducing power from the power management chip on the motherboard circuit board through the packaging substrate 121, or by introducing power from other feasible devices.

[0071] The first terminal of each power control unit 1222 is connected to the power supply circuit 1213, and the second terminal of each power control unit 1222 is connected to the current sharing circuit 1211. The first and second terminals of the power control unit 1222 can be connected to the power supply circuit 1213 and the current sharing circuit 1211 respectively via solder pads, or via any other feasible method, such as wire bonding. Figure 5 The first line in the middle is 125. Figure 5In the processor 1221, the power control unit 1222 includes at least two control switches 1222a and 1222b located on the left and right sides of the processor 1221, respectively. The first terminal of the power control unit 1222 is connected to the power supply circuit 1213; alternatively, the first terminal of each control switch may be connected to the power supply circuit 1213. The second terminal of the power control unit 1222 is connected to the current sharing circuit 1211; alternatively, the second terminal of each control switch may be connected to the current sharing circuit 1211. In this embodiment, the current first enters the power supply circuit 1213 of the packaging substrate 121 through the first terminal of the power supply circuit 1213 and the power supply circuit 1222 through the electrical connection between the power supply circuit 1213 and the power supply circuit 1222. Then, when the multiple control switches are turned on, the current enters the current sharing circuit 1211 of the packaging substrate 121 through the multiple control switches and the electrical connection between the multiple control switches and the current sharing circuit 1211 of the packaging substrate 121. Then, the current enters the first branch 1225 through the second branch 1212 of the current sharing circuit 1211 and the first branch 1225 of the power domain. Finally, the current reaches the branch domain through the first branch 1225.

[0072] In this embodiment, a power supply circuit is provided on the packaging substrate, and the power is evenly distributed and transmitted to multiple branch domains of the power domain of the chip through a current sharing circuit. The first terminal of the power control unit is connected to the power supply circuit, and the second terminal of the power control unit is connected to the current sharing circuit. The current sharing circuit is connected to the first branch of the power domain through a second branch. Therefore, the power control unit can be used to connect or disconnect the power supply path of the corresponding power domain.

[0073] In some possible embodiments, such as Figure 6 As shown, the packaging substrate 121 and the chip 122 of the packaging structure 12 are stacked. The stacking arrangement refers to the vertical stacking of the packaging substrate 121 and the chip 122, which can achieve higher performance, smaller size, faster response speed and less energy consumption.

[0074] The packaging substrate 121 and the chip 122 are electrically connected via a first pad 123. Pad connection refers to the interconnection of the pads of two devices using soldering technology, thereby achieving electrical connection. Pad connection is widely used in various electronic devices, enabling high-density, high-reliability circuit connections. The stacked packaging substrate and chip can be electrically connected using the first pad 123 through a hybrid bonding method.

[0075] In this embodiment, the stacked arrangement of the packaging substrate and the chip can improve the integration and performance of the packaging structure. The packaging substrate and the chip are electrically connected via solder pads, ensuring a stable and reliable connection that is easy to manufacture and maintain.

[0076] In one exemplary embodiment, such asFigure 7 As shown in the illustration, this embodiment depicts a circuit board assembly 1, including a circuit board 11. A circuit board is a device that uses an insulating material as a substrate and lays metal circuitry on it through chemical or mechanical processing to connect and support various electronic components. In this embodiment, the circuit board 11 may include a device for supplying electrical power to the packaging structure 12.

[0077] The circuit board 11 is connected to any of the package structures 12 in the above embodiments. The circuit board 11 can be connected to the package structure 12 via solder pads, or via other feasible methods, such as wire bonding. Figure 7 The second line is 126.

[0078] In some possible embodiments, such as Figure 8 As shown, the packaging substrate 121 of the packaging structure 12 of the circuit board assembly 1 is electrically connected to the circuit board 11 via the second pad 124. Pad connection refers to connecting the pads of two devices to each other through soldering technology to achieve electrical connection. Pad connection is widely used in various electronic devices. Through pad connection, high-density and high-reliability circuit connections can be achieved.

[0079] In this embodiment, the circuit board and the packaging substrate in the circuit board assembly are electrically connected by solder pads, which makes the connection stable and reliable, and easy to manufacture and maintain.

[0080] In one exemplary embodiment, an electronic device is provided, including any of the circuit board components 1 described in the above embodiments. By employing the circuit board component 1 described in the above embodiments, the core processing capabilities of the electronic device can be effectively improved, enhancing the user experience.

[0081] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0082] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A chip, characterized by The chip comprises: a processor comprising a plurality of power domains; a plurality of power control units corresponding to the plurality of power domains, each power control unit being configured to connect or disconnect a power supply path of the power domain connected to the power control unit; wherein the chip comprises a first region and a second region, the processor is disposed in the first region, and the plurality of power control units are disposed in the second region.

2. The chip according to claim 1, characterized in that, The power domain comprises a plurality of branch domains and a plurality of parallel first branches, each first branch being connected to at least one branch domain. The first end of each power control unit is connected to the power supply path, and the second end of each power control unit is connected to the first branch of the corresponding power domain.

3. The chip according to any one of claims 1 to 2, characterized in that, The plurality of power control units are arranged in an array in the second region, and each power control unit comprises at least one control switch.

4. The chip of claim 3, wherein Each power control unit comprises at least two control switches, and the first region comprises opposite first and second sides. In the same power control unit, a portion of the control switches are disposed on the first side of the first region, and another portion of the control switches are disposed on the second side of the first region.

5. The chip of claim 3, wherein, The power control unit and the power domain connected to the power control unit are located in the same deposition layer of the chip.

6. The chip of claim 1, wherein In the plane of the chip, the first region and the second region do not overlap.

7. A package structure, characterized by, The package substrate and the chip of any one of claims 1 to 6 are packaged in the package substrate, and the plurality of power control units of the chip are electrically connected to the package substrate, and the power control units are configured to open or close the power supply path between the package substrate and the power domain of the chip.

8. The package structure of claim 7, wherein, The package substrate is provided with a current sharing circuit, and the current sharing circuit comprises a plurality of parallel second branches, each second branch being electrically connected to at least one first branch of the power domain.

9. The package structure of claim 8, wherein, The package substrate is provided with a power supply circuit, the first end of each power control unit is connected to the power supply circuit, and the second end of each power control unit is connected to the current sharing circuit.

10. The package structure of any one of claims 7 to 9, wherein, The package substrate and the chip are stacked, and the package substrate and the chip are electrically connected through a first pad.

11. A circuit board assembly, characterized by The circuit board is electrically connected to the package structure of any one of claims 7 to 10.

12. The circuit board assembly of claim 11, wherein, The package substrate of the package structure is electrically connected to the circuit board through a second pad.

13. An electronic device, comprising: The circuit board assembly of claim 11 or 12.

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