Simple voltage screening circuit

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By using a simple voltage screening circuit with Zener diodes and transistors to detect the voltage range, the stability problem of electronic equipment under wide voltage input is solved, and voltage screening and power supply control are realized, reducing the risk of failure.

CN224037088UActive Publication Date: 2026-03-24GUANGZHOU XINGYI ELECTRONICS TECH CO LTD

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Patent Information

Application Number: CN202520709167.9
Authority / Receiving Office: CN · China
Patent Type: Utility models(China)
Current Assignee / Owner
Filing Date: 2025-04-15
Publication Date: 2026-03-24
Estimated Expiration: 2035-04-15

AI Technical Summary

Technical Problem

Existing electronic devices lack a minimum input voltage limit when operating with a wide voltage range, leading to uncertainty in device stability and potential failure risks.

Method used

A simple voltage screening circuit was designed, which uses components such as DZ1 and DZ2 Zener diodes, NMOS and PNP transistors to detect and limit the voltage range, ensuring that power is supplied only when the voltage is between the lower and upper limits.

Benefits of technology

It achieves effective voltage screening, prevents equipment from being powered under unstable voltage, reduces the risk of equipment failure, and is low in cost, requires few components, and is easy to set up.

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Abstract

The utility model discloses a simple voltage screening circuit, which comprises a VCCIN, a VCCOUT, an output control circuit, a lower limit voltage detection circuit and an upper limit voltage detection circuit, the output control circuit is connected with the VCCOUT, one end of the lower limit voltage detection circuit is connected with the VCCIN, the other end of the lower limit voltage detection circuit is connected with the output control circuit, one end of the upper limit voltage detection circuit is connected with the VCCIN, and the other end of the upper limit voltage detection circuit is connected with the VCCOUT. The other end is connected with the output control circuit. The voltage screening circuit is low in cost and easy to use, power can be normally output to a corresponding load through the VCCOUT only when the voltage amplitude of the VCCIN is between the lower limit voltage and the upper limit voltage of the voltage screening circuit, and power cannot be output to the corresponding load through the VCCOUT under other conditions. Whether the current power supply voltage is within the range supported by the equipment or not can be judged, and power supply to the internal load is closed when the current power supply voltage is not within the range supported by the equipment.

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Description

TECHNICAL FIELD

[0001] The utility model relates to the field of integrated circuit, concretely relates to a simple voltage screening circuit. BACKGROUND

[0002] Now more and more electronic equipment support wide voltage input, such as 5V to 20V, and even can reach higher voltage.

[0003] Although the electronic equipment on the market supports wide voltage input, but often just simply limit the highest input voltage, and do not limit the minimum input voltage, and some electronic equipment still can start the device when input voltage does not reach the power supply voltage, but the stability of the device at this time is uncertain, and it is easy to cause device failure or even damage due to unstable power supply voltage. INVENTION CONTENTS

[0004] The utility model aims at providing a simple voltage screening circuit to solve at least one of the above technical problems.

[0005] According to one aspect of the utility model, a simple voltage screening circuit is provided, comprising:

[0006] VCC_IN for connecting external power supply interface;

[0007] VCC_OUT for connecting internal power supply interface;

[0008] Output control circuit, the output control circuit is connected with VCC_OUT;

[0009] Lower limit voltage detection circuit, one end of the lower limit voltage detection circuit is connected with VCC_IN, and the other end is connected with output control circuit;And

[0010] Upper limit voltage detection circuit, one end of the upper limit voltage detection circuit is connected with VCC_IN, and the other end is connected with output control circuit.

[0011] Further, the lower limit voltage detection circuit includes DZ1 zener diode, when the voltage of VCC_IN input exceeds the voltage stabilizing value of DZ1 zener diode, the upper limit voltage detection circuit starts to work.

[0012] Further, the lower limit voltage detection circuit further includes R1 resistance, R2 resistance and NMOS tube, the negative pole of DZ1 zener diode is connected with VCC_IN, the positive pole of DZ1 zener diode is connected with one end of R1 resistance, the other end of R1 resistance is connected to ground, the positive pole of DZ1 zener diode is connected with one end of R2 resistance, the other end of R2 resistance is connected with the gate of NMOS tube, the source of NMOS tube is connected to ground, and the drain of NMOS tube is connected with output control circuit.

[0013] Further, the upper limit voltage detection circuit comprises a DZ2 zener diode, when the voltage inputted by VCC_IN exceeds the voltage of the DZ1 zener diode, the upper limit voltage detection circuit starts to work, the voltage inputted by VCC_IN passes through the upper limit voltage detection circuit, when the voltage inputted by VCC_IN does not exceed the voltage of the DZ2 zener diode, the voltage inputted by VCC_IN passes through the output control circuit to supply VCC_OUT.

[0014] Further, the upper limit voltage detection circuit further comprises a R3 resistor, a R4 resistor and a PNP transistor, the negative electrode of the DZ2 zener diode is connected with one end of the R3 resistor, the other end of the R3 resistor is connected with VCC_IN, the negative electrode of the DZ2 zener diode is connected with one end of the R4 resistor, the other end of the R4 resistor is connected with the base of the PNP transistor, the positive electrode of the DZ2 zener diode is connected to the ground, the emitter of the PNP transistor is connected with VCC_IN, the collector of the PNP transistor is connected with the output control circuit.

[0015] Further, the output control circuit comprises a PMOS transistor, when the voltage inputted by VCC_IN exceeds the voltage of the DZ1 zener diode and does not exceed the voltage of the DZ2 zener diode, the source and the drain of the PMOS transistor are conductive, the voltage inputted by VCC_IN passes through the PMOS transistor to supply VCC_OUT.

[0016] Further, the output control circuit further comprises a R5 resistor and a R6 resistor, one end of the R5 resistor is connected with the drain of the NMOS transistor, the other end of the R5 resistor is connected with the collector of the PNP transistor, the other end of the R5 resistor is connected with one end of the R6 resistor, the other end of the R6 resistor is connected with the gate of the PMOS transistor, the source of the PMOS transistor is connected with VCC_IN, the drain of the PMOS transistor is connected with VCC_OUT.

[0017] Further, the lower limit voltage detection circuit comprises a DZ1 zener diode, a NMOS transistor, a R1 resistor and a R2 resistor, the upper limit voltage detection circuit comprises a DZ2 zener diode, a PNP transistor, a R3 resistor and a R4 resistor, the output control circuit comprises a PMOS transistor, a R5 resistor and a R6 resistor,

[0018] the negative electrode of the DZ1 zener diode is connected with VCC_IN, the positive electrode of the DZ1 zener diode is connected with one end of the R1 resistor, the other end of the R1 resistor is connected to the ground, the positive electrode of the DZ1 zener diode is connected with one end of the R2 resistor, the other end of the R2 resistor is connected with the gate of the NMOS transistor, the source of the NMOS transistor is connected to the ground, the drain of the NMOS transistor is connected with one end of the R5 resistor,

[0019] The negative electrode of the DZ2 zener diode is connected with one end of the R3 resistor, the other end of the R3 resistor is connected with the VCC_IN, the negative electrode of the DZ2 zener diode is connected with one end of the R4 resistor, the other end of the R4 resistor is connected with the base electrode of the PNP triode, the positive electrode of the DZ2 zener diode is connected to the ground, the emitter electrode of the PNP triode is connected with the VCC_IN, the collector electrode of the PNP triode is connected with the other end of the R5 resistor,

[0020] The other end of the R5 resistor is connected with one end of the R6 resistor, the other end of the R6 resistor is connected with the gate electrode of the PMOS tube, the source electrode of the PMOS tube is connected with the VCC_IN, and the drain electrode of the PMOS tube is connected with the VCC_OUT.

[0021] Further, the DZ1 zener diode sets the lower limit voltage of screening.

[0022] Further, the DZ2 zener diode sets the upper limit voltage of screening.

[0023] The beneficial effects of the utility model are:

[0024] (1) the screening of the upper limit voltage and the lower limit voltage can be realized by using fewer components, the cost is low, and the use is simple;

[0025] (2) the lower limit voltage and the upper limit voltage of screening are respectively set by the DZ1 zener diode and the DZ2 zener diode, the voltage range that can be used by the VCC_OUT connected with the internal power supply interface can be limited between the lower limit voltage and the upper limit voltage, only when the voltage amplitude of the VCC_IN connected with the external power supply interface is between the lower limit voltage and the upper limit voltage of the utility model, the corresponding load can be normally powered through the VCC_OUT, and the corresponding load cannot be powered through the VCC_OUT in other cases;

[0026] (3) whether the current power supply voltage is within the range supported by the equipment can be judged through the voltage screening circuit of the utility model, and the power supply for the internal load is turned off when the current power supply voltage is not within the range supported by the equipment;

[0027] (4) the setting of the upper limit voltage and the lower limit voltage can be directly completed by replacing the corresponding zener diode, which is very convenient. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a circuit diagram of a simple voltage screening circuit of the utility model. DETAILED DESCRIPTION

[0029] Clearly, the described embodiments are merely part of the embodiments of the utility model, rather than all the embodiments.

[0030] Referring to Figure 1 A simple voltage screening circuit, including VCC_IN, lower limit voltage detection circuit, upper limit voltage detection circuit, output control circuit and VCC_OUT.

[0031] Referring to Figure 1 VCC_IN is used for connecting external power interface, VCC_OUT is used for connecting internal power interface.

[0032] Referring to Figure 1 Lower limit voltage detection circuit includes DZ1 zener diode, NMOS tube, R1 resistance and R2 resistance, upper limit voltage detection circuit includes DZ2 zener diode, PNP triode, R3 resistance and R4 resistance, and output control circuit includes PMOS tube, R5 resistance and R6 resistance.

[0033] Referring to Figure 1 The negative electrode of DZ1 zener diode is connected with VCC_IN, the positive electrode of DZ1 zener diode is connected with one end of R1 resistance, the other end of R1 resistance is connected to ground, the positive electrode of DZ1 zener diode is connected with one end of R2 resistance, the other end of R2 resistance is connected with the gate electrode of NMOS tube, the source electrode of NMOS tube is connected to ground, the drain electrode of NMOS tube is connected with one end of R5 resistance, one end of R3 resistance is connected with the negative electrode of DZ2 zener diode, the other end of R3 resistance is connected with VCC_IN, one end of R4 resistance is connected with the negative electrode of DZ2 zener diode, the other end of R4 resistance is connected with the base electrode of PNP triode, the positive electrode of DZ2 zener diode is connected to ground, the emitter electrode of PNP triode is connected with VCC_IN, the collector electrode of PNP triode is connected with the other end of R5 resistance, the other end of R5 resistance is connected with one end of R6 resistance, the other end of R6 resistance is connected with the gate electrode of PMOS tube, the source electrode of PMOS tube is connected with VCC_IN, the drain electrode of PMOS tube is connected with VCC_OUT, DZ1 zener diode sets the lower limit voltage of screening, and DZ2 zener diode sets the upper limit voltage of screening.

[0034] Referring to Figure 1When the voltage of VCC IN connected with the external power supply interface does not exceed the voltage of DZ1 zener diode, DZ1 zener diode is not conductive and equivalent to open circuit, at this time, R1 resistor and R2 resistor are in series, the gate of NMOS is connected to the ground through R1 resistor and R2 resistor, at this time, the voltage difference between the gate and the source of NMOS is 0, the drain and the source of NMOS are not conductive, R5 resistor can be regarded as not connected to the ground, at this time, DZ2 zener diode is also not conductive and equivalent to open circuit, the emitter and the collector of PNP transistor are not conductive and equivalent to open circuit, resulting in that the PMOS part circuit does not constitute a complete circuit, and the PMOS can also be regarded as open circuit, and VCC IN cannot be supplied to VCC OUT through the PMOS.

[0035] Referring to Figure 1 When the voltage of VCC IN connected with the external power supply interface exceeds the voltage of DZ1 zener diode, the voltage difference between the two sides of DZ1 zener diode is clamped by DZ1 zener diode, R1 resistor will divide a voltage, and the voltage will be pulled up to the gate of NMOS through R2 resistor, when the voltage difference between the gate and the source of NMOS is greater than the threshold voltage of the gate and the source of NMOS, at this time, the gate and the drain of NMOS are conductive, and R5 resistor is equivalent to be directly connected to the ground, the upper limit voltage detection circuit is activated, and the upper limit voltage detection circuit starts to work, and the voltage input by VCC IN is subjected to the upper limit voltage detection circuit.

[0036] Referring to Figure 1 When the voltage of VCC IN connected with the external power supply interface does not exceed the voltage of DZ2 zener diode, DZ2 zener diode is not conductive and equivalent to open circuit, R3 resistor and R4 resistor are in series, the base of PNP transistor is pulled up, at this time, the base of PNP transistor can be regarded as being connected to VCC IN, the voltage difference between the emitter and the base of PNP transistor is 0, so the emitter and the collector of PNP transistor are not conductive and equivalent to R5 resistor and R6 resistor being in series and directly connected to the ground, at this time, the voltage difference between the gate and the source of PMOS is greater than the threshold voltage of the source and the gate of PMOS, so that the source and the drain of PMOS are conductive, at this time, VCC IN can be supplied to VCC OUT through the PMOS.

[0037] Referring to Figure 1When the voltage of the VCC_IN connected with the external power interface exceeds the voltage of the DZ2 zener diode, the DZ2 zener diode is turned on to clamp the voltage on both sides, and the voltage is transmitted to the base of the PNP transistor through the R4 resistor. When the voltage difference between the emitter and the base of the PNP transistor is greater than the threshold voltage of the emitter and the base of the PNP transistor, the emitter and the collector of the PNP transistor are turned on. At this time, the collector of the PNP transistor can be regarded as being connected to the VCC_IN, and the gate of the PMOS transistor is connected to the VCC_IN through the R6 resistor. It can be considered that the voltage difference between the source and the gate of the PMOS transistor is 0, and the source and the drain of the PMOS transistor are not turned on. The VCC_OUT is controlled, and the VCC_IN cannot be supplied to the VCC_OUT through the PMOS transistor.

[0038] Referring to Figure 1 The voltage screening circuit can detect and control the power supply output of the internal power interface. The lower limit voltage and the upper limit voltage are set by the DZ1 zener diode and the DZ2 zener diode respectively. When the voltage amplitude of the VCC_IN input exceeds the lower limit voltage, the NMOS transistor is turned on, and the upper limit voltage detection circuit starts to work. Conversely, the upper limit voltage detection circuit does not work. The upper limit voltage detection circuit is composed of the DZ2 zener diode, the R3 resistor, the R4 resistor and the PNP transistor. When the voltage amplitude of the VCC_IN input is less than the upper limit voltage, the PNP transistor is not turned on. Conversely, the PNP transistor is turned on. The output control circuit is composed of the PMOS transistor, the R5 resistor and the R6 resistor. When the NMOS transistor of the lower limit voltage detection circuit is not turned on, the upper limit voltage detection circuit and the output control circuit do not work, so that the power supply output of the VCC_OUT is turned off. When the NMOS transistor of the lower limit voltage detection circuit is turned on, the upper limit voltage detection circuit works. When the voltage amplitude of the VCC_IN does not exceed the upper limit voltage, the PNP transistor is not turned on, and the output control circuit is not controlled, so that the power supply output of the VCC_OUT is turned on. If the voltage amplitude of the VCC_IN exceeds the upper limit voltage, the PNP transistor is turned on, and the output control circuit is controlled, so that the power supply output of the VCC_OUT is turned off. That is, only when the voltage amplitude of the VCC_IN is between the lower limit voltage and the upper limit voltage set by the utility model, the VCC_IN can normally output power to the corresponding load through the VCC_OUT. In other cases, the VCC_OUT cannot output power to the corresponding load.

[0039] Referring to Figure 1The voltage screening circuit of the utility model, with fewer components, can realize the screening of upper limit voltage and lower limit voltage, has low cost and is simple to use; the lower limit voltage and the upper limit voltage of screening are respectively set through DZ1 voltage stabilizing diode and DZ2 voltage stabilizing diode, the voltage range that VCC_OUT for connecting the internal power supply interface can use can be limited between the lower limit voltage and the upper limit voltage, only when the voltage amplitude of VCC_IN for connecting the external power supply interface is between the lower limit voltage and the upper limit voltage of the utility model, the corresponding load can be normally powered through VCC_OUT, and the corresponding load cannot be powered through VCC_OUT in other cases; through the voltage screening circuit of the utility model, whether the current power supply voltage is within the range supported by the equipment can be judged, and the power supply to the internal load is turned off when not within the supported range; in addition, the setting of the upper limit voltage and the lower limit voltage can be directly completed by replacing the corresponding voltage stabilizing diode, which is very convenient.

[0040] The above only some embodiments of the utility model, aim at explaining the technical means of the utility model, and are not to limit the technical range of the utility model. The technical personnel in the art make the improvement of the utility model in combination with the existing common knowledge, all fall into the protection range of the utility model.

Claims

1. A simple voltage screening circuit, characterized in that, include: VCC_IN is used to connect to an external power supply interface; VCC_OUT is used to connect to the internal power interface; The output control circuit is connected to VCC_OUT. The lower limit voltage detection circuit has one end connected to VCC_IN and the other end connected to the output control circuit; and An upper limit voltage detection circuit is provided, with one end connected to VCC_IN and the other end connected to the output control circuit.

2. The voltage screening circuit according to claim 1, characterized in that, The lower limit voltage detection circuit includes a DZ1 Zener diode. When the voltage input to VCC_IN exceeds the Zener value of the DZ1 Zener diode, the upper limit voltage detection circuit starts to work.

3. The voltage screening circuit according to claim 2, characterized in that, The lower limit voltage detection circuit also includes resistors R1 and R2 and an NMOS transistor. The cathode of the DZ1 Zener diode is connected to VCC_IN, the anode of the DZ1 Zener diode is connected to one end of resistor R1, the other end of resistor R1 is connected to ground, the anode of the DZ1 Zener diode is connected to one end of resistor R2, the other end of resistor R2 is connected to the gate of the NMOS transistor, the source of the NMOS transistor is connected to ground, and the drain of the NMOS transistor is connected to the output control circuit.

4. The voltage screening circuit according to claim 3, characterized in that, The upper limit voltage detection circuit includes a DZ2 Zener diode. When the voltage input to VCC_IN exceeds the Zener voltage of the DZ1 Zener diode, the upper limit voltage detection circuit starts to work. The voltage input to VCC_IN passes through the upper limit voltage detection circuit. When the voltage input to VCC_IN does not exceed the Zener voltage of the DZ2 Zener diode, the voltage input to VCC_IN is supplied to VCC_OUT through the output control circuit.

5. The voltage screening circuit according to claim 4, characterized in that, The upper limit voltage detection circuit also includes resistors R3 and R4 and a PNP transistor. The cathode of the DZ2 Zener diode is connected to one end of resistor R3, and the other end of resistor R3 is connected to VCC_IN. The cathode of the DZ2 Zener diode is connected to one end of resistor R4, and the other end of resistor R4 is connected to the base of the PNP transistor. The anode of the DZ2 Zener diode is connected to ground. The emitter of the PNP transistor is connected to VCC_IN. The collector of the PNP transistor is connected to the output control circuit.

6. The voltage screening circuit according to claim 5, characterized in that, The output control circuit includes a PMOS transistor. When the voltage input to VCC_IN exceeds the voltage regulation value of the DZ1 Zener diode but does not exceed the voltage regulation value of the DZ2 Zener diode, the source and drain of the PMOS transistor are turned on, and the voltage input to VCC_IN is supplied to VCC_OUT through the PMOS transistor.

7. The voltage screening circuit according to claim 6, characterized in that, The output control circuit also includes resistors R5 and R6. One end of resistor R5 is connected to the drain of the NMOS transistor, and the other end of resistor R5 is connected to the collector of the PNP transistor. The other end of resistor R5 is connected to one end of resistor R6, and the other end of resistor R6 is connected to the gate of the PMOS transistor. The source of the PMOS transistor is connected to VCC_IN, and the drain of the PMOS transistor is connected to VCC_OUT.

8. The voltage screening circuit according to claim 1, characterized in that, The lower limit voltage detection circuit includes a Zener diode (DZ1), an NMOS transistor, resistors R1 and R2; the upper limit voltage detection circuit includes a Zener diode (DZ2), a PNP transistor, resistors R3 and R4; and the output control circuit includes a PMOS transistor, resistors R5 and R6. The negative terminal of the DZ1 Zener diode is connected to VCC_IN, the positive terminal of the DZ1 Zener diode is connected to one end of resistor R1, the other end of resistor R1 is connected to ground, the positive terminal of the DZ1 Zener diode is connected to one end of resistor R2, the other end of resistor R2 is connected to the gate of the NMOS transistor, the source of the NMOS transistor is connected to ground, and the drain of the NMOS transistor is connected to one end of resistor R5. The cathode of the DZ2 Zener diode is connected to one end of resistor R3, and the other end of resistor R3 is connected to VCC_IN. The cathode of the DZ2 Zener diode is connected to one end of resistor R4, and the other end of resistor R4 is connected to the base of the PNP transistor. The anode of the DZ2 Zener diode is connected to ground. The emitter of the PNP transistor is connected to VCC_IN, and the collector of the PNP transistor is connected to the other end of resistor R5. The other end of resistor R5 is connected to one end of resistor R6, the other end of resistor R6 is connected to the gate of PMOS transistor, the source of PMOS transistor is connected to VCC_IN, and the drain of PMOS transistor is connected to VCC_OUT.

9. The voltage screening circuit according to any one of claims 2 to 8, characterized in that, The DZ1 Zener diode is set to the lower limit voltage for screening.

10. The voltage screening circuit according to any one of claims 4 to 8, characterized in that, The DZ2 Zener diode is set to the upper limit voltage for screening.