Semiconductor test structure
By setting mutually spaced two-dimensional array test cells and dummy gates in the semiconductor test structure, the problem of over-wearing caused by excessive polysilicon density and area is solved, and the yield and stability of the test structure are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-03-24
AI Technical Summary
In semiconductor testing structures, excessive density and area of polysilicon can lead to over-scraping or the formation of dish-shaped depressions during planarization, affecting the accuracy and stability of test results.
Multiple test cells are arranged in a two-dimensional array with spacing between them, and dummy gates are set between adjacent test cells to reduce the gate area and density. The distance is adjusted by setting dummy active regions to reduce the risk of planarization.
This effectively reduces the risk of excessively low gate height during planarization, improves the yield and stability of semiconductor test structures, and ensures the accuracy and effectiveness of testing.
Smart Images
Figure CN224037816U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technology, and in particular to a semiconductor testing structure. Background Technology
[0002] Generally, in test cells for the equivalent gate oxide thickness (EOT) of MOS devices, polysilicon (PO) is a long strip structure arranged along the width of the channel. For 28nm MOS devices, when the width of each polysilicon strip is greater than or equal to 0.5µm, multiple polysilicon strips tend to be too densely packed, resulting in excessive polysilicon density within the test cell and an excessively large area occupied by polysilicon in the test cell.
[0003] However, if the density of polysilicon in the test cell is too high, and the area occupied by polysilicon in the test cell is too large, over-grinding or dish-shaped depressions may easily occur during the subsequent planarization of the interconnect layer. This results in the final polysilicon gate having an excessively low height, and in severe cases, the high-k layer on the active area may be damaged. Utility Model Content
[0004] Therefore, it is necessary to provide a semiconductor test structure to reduce the gate density in the active region and reduce or even avoid the risk of over-wearing or dish-shaped depressions during the fabrication of the semiconductor test structure.
[0005] This application provides a semiconductor test structure, including:
[0006] Multiple test units are arranged in a two-dimensional array, with adjacent test units spaced apart. Each test unit includes an active region located within a substrate and a gate located on the active region.
[0007] Multiple dummy gates are located on the substrate, and the dummy gates are disposed between the gates of two adjacent test units along a first direction, wherein the extending direction of the gates is a second direction, and the first direction and the second direction are perpendicular to each other.
[0008] In one embodiment, the semiconductor test structure further includes a plurality of pseudo-active regions disposed within a substrate between two adjacent test units along the second direction.
[0009] In one embodiment, along a direction perpendicular to the surface of the substrate, the sum of the projected areas of all the dummy gates and all the projected areas of the gates accounts for 10% to 65% of the total surface area of the substrate.
[0010] In one embodiment, along a direction perpendicular to the surface of the substrate, a portion of the orthographic projection of the pseudo-gate coincides with a portion of the orthographic projection of the active region, while the remaining orthographic projection of the pseudo-gate is separate from the orthographic projection of the active region.
[0011] In one embodiment, the orthographic projection of the dummy gate is elongated along a direction perpendicular to the surface of the substrate, and the extension direction of the dummy gate is the same as the extension direction of the gate.
[0012] In one embodiment, the length of the dummy gate is the same as the length of the gate, and the width of the dummy gate is smaller than the width of the gate.
[0013] In one embodiment, the orthogonal projection of the gate coincides with the orthogonal projection of the active region along a direction perpendicular to the surface of the substrate.
[0014] In one embodiment, the semiconductor test structure further includes:
[0015] An interconnect layer is disposed at a distance from the active region on the side of the gate.
[0016] A first electrical connector is located between the gate and the interconnect layer, and is connected to both the gate and the interconnect layer;
[0017] The second electrical connector is located on the active region between the gate and the dummy gate and is connected to the interconnect layer.
[0018] In one embodiment, along a direction perpendicular to the surface of the substrate, the orthographic projection of the first electrical connector coincides with the orthographic projection of the gate and the orthographic projection of the interconnect layer, and the orthographic projection of the first electrical connector is separate from the orthographic projection of the active region.
[0019] In one embodiment, the interconnect layer is made of a conductive material, which includes at least copper or aluminum.
[0020] An unexpected effect of this application is that by setting up multiple test units that are spaced apart from each other and arranged in a two-dimensional array, and setting up multiple dummy gates between the gates of two adjacent test units along the first direction, the gate area and gate density in the semiconductor test structure are reduced, thereby reducing the risk of excessively low gate height due to excessive polishing during the subsequent planarization process, and thus improving the yield and stability of the semiconductor test structure. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a schematic diagram of an equivalent gate oxide layer thickness testing structure provided for a related technology.
[0023] Figure 2 This is a schematic diagram of a semiconductor test structure provided in one embodiment of this application.
[0024] The reference numerals in the figures include: 100-semiconductor substrate; 101-AA region; 110-gate structure; 120-metal layer; 121-electrical connector; 200-substrate; 201-active region; 202-pseudo-active region; 210-gate; 211-pseudo-gate; 220-interconnect layer; 221-first electrical connector; 222-second electrical connector. Detailed Implementation
[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0028] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0029] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0030] Figure 1 This is a schematic diagram of an equivalent gate oxide layer thickness testing unit provided for a related technology. (See also...) Figure 1 A typical equivalent oxide thickness (EOT) test structure includes a semiconductor substrate 100, an active area (AA) region 101 within the semiconductor substrate 100, and a gate structure (Poly, PO) on the semiconductor substrate 100. Along a direction perpendicular to the surface of the semiconductor substrate 100, the orthographic projection of the AA region 101 and the orthographic projection of the gate structure 110 partially coincide. Both the orthographic projections of the AA region 101 and the gate structure 110 are elongated, and the extension direction of the orthographic projection of the AA region 101 is perpendicular to the extension direction of the orthographic projection of the gate structure 110.
[0031] Continue reading Figure 1 The equivalent gate oxide thickness test structure also includes a metal layer 120, which is located on the side of the gate structure 110 away from the AA region 101. It should be noted that an insulating medium is provided between the metal layer 120 and both the gate structure 110 and the AA region 101, and the metal layer 120 is electrically connected to the gate structure 110 and / or the AA region 101 via an electrical connector 121.
[0032] Since the gate structure 110 is an elongated strip extending along the width direction of the AA region 101, a larger width of the gate structure 110 will increase its total area. Simultaneously, the dense arrangement of the gate structures 110 on the semiconductor substrate 100 will result in an excessively high density. For example, in a 28nm equivalent gate oxide thickness test structure, if the width of the gate structure 110 is greater than 0.5μm, then the area of the gate structure 110 is too large, and the density of the gate structure 110 (or the ratio of the area of the gate structure 110 to the surface area of the semiconductor substrate 100) is too high.
[0033] However, when the gate area or gate density in the equivalent gate oxide thickness test structure is too large, over-grinding can easily occur during the planarization process in the subsequent metal layer fabrication, resulting in an excessively low gate structure height; or, over-etching can easily occur during the fabrication of electrical interconnects; simultaneously, the high-dielectric-constant layer on the AA region is also more susceptible to damage. All of these aforementioned defects negatively impact the test results of the equivalent gate oxide thickness test structure, thus affecting the accuracy of the test results.
[0034] Therefore, it is necessary to provide a semiconductor test structure to reduce the gate density in the active region and reduce or even avoid the risk of over-wearing or dish-shaped depressions during the fabrication of the semiconductor test structure.
[0035] Figure 2 This is a schematic diagram of a semiconductor test structure provided in one embodiment of this application. (See also...) Figure 2 One embodiment of this application provides a semiconductor test structure comprising: multiple test units arranged in a two-dimensional array. Figure 2 The area highlighted by the dashed line is one of the test units and multiple dummy gates 211 (Dummy Poly, DPO). Adjacent test units are spaced apart. The test unit includes an active area 201 (AA) located in the substrate 200 and a gate 210 located on the active area 201. Multiple dummy gates 211 are located on the substrate 200 and are disposed between the gates 210 of two adjacent test units along the first direction (i.e., the X direction). The extension direction of the gate 210 is the second direction (i.e., the Y direction), and the first direction and the second direction are perpendicular to each other.
[0036] It is important to emphasize that, because the gates within each test cell of a semiconductor test structure are isolated from each other, therefore, in comparison... Figure 1 and Figure 2 It can be seen that, with Figure 1 Compared to the gate structure 110 in the previous embodiment, the area of a single gate 210 provided in one embodiment of this application is significantly smaller. That is, by setting an independent gate 210 in each test unit, this application reduces the area of a single gate 210, thereby reducing or avoiding the risk of dishing at the gate location during subsequent planarization processing, and thus improving the quality and accuracy of the semiconductor test structure.
[0037] The semiconductor test structure described above reduces the gate area and gate density within the semiconductor test structure by setting multiple test units spaced apart from each other and arranged in a two-dimensional array, and setting multiple dummy gates between the gates of two adjacent test units along the first direction. This reduces the risk of excessively low gate height due to over-polishing during the subsequent planarization process, thereby improving the yield and stability of the semiconductor test structure.
[0038] In one embodiment, both the gate and the dummy gate are made of polysilicon (PO). Optionally, a dielectric layer (not shown) is disposed between the gate and the substrate, and between the dummy gate and the substrate, and the dielectric layer is made of a high dielectric constant material.
[0039] Continue reading Figure 2In one embodiment, the orthographic projection of the gate 210 coincides with the orthographic projection of the active region 201 in a direction perpendicular to the surface of the substrate 200, to ensure the normal operation of the semiconductor test structure.
[0040] See Figure 2 In one embodiment, along a direction perpendicular to the surface of the substrate 200, the sum of the projected areas of all dummy gates 211 and all gates 210 accounts for 10% to 65% of the total surface area of the substrate 200.
[0041] See Figure 2 In one embodiment, along a direction perpendicular to the surface of the substrate 200, a portion of the dummy gate 211 (e.g.) Figure 2 The orthographic projection corresponding to 211a in the image coincides with the orthographic projection of the active region 201, and the remaining pseudo-grating 211 (e.g. Figure 2 The orthographic projection corresponding to 211b) in the active region 201 is separated from the orthographic projection of the active region 201.
[0042] It should be noted that, in different embodiments of this application, the morphology, number and specific arrangement of the dummy gates can be adjusted according to the specific morphology of the semiconductor test structure. Under the premise of meeting the process requirements, those skilled in the art can set the morphology, number and specific arrangement of the dummy gates according to their professional knowledge and test requirements in order to reduce the gate area or gate density in the semiconductor test structure.
[0043] In one embodiment, the orthographic projection shape of the dummy gate along the direction perpendicular to the substrate surface can be rectangular, trapezoidal, or polygonal, and the number of dummy gates disposed between two adjacent gates can be several; and when multiple dummy gates are disposed between two adjacent gates, the distance between different dummy gates can be the same or different. Preferably, when multiple dummy gates are disposed between two adjacent gates, the distance between different dummy gates is the same, so as to reduce or avoid the risk of over-polishing or dish-shaped depressions in the area where dummy gates are disposed during subsequent planarization processing.
[0044] For example, see Figure 2 Along a direction perpendicular to the surface of the substrate 200, the orthographic projection of the dummy gate 211 is elongated, and the extension direction of the dummy gate 211 (i.e., the length direction of the dummy gate 211) is the same as the extension direction of the gate 210 (i.e., the length direction of the gate 210). Optionally, the length of the dummy gate 211 is the same as the length of the gate 210, and the width of the dummy gate 211 is smaller than the width of the gate 210.
[0045] Continue reading Figure 2In one embodiment, the semiconductor test structure further includes a plurality of dummy active areas 202 (DAAs) disposed within a substrate 200 between two adjacent test units along a second direction (i.e., the Y direction).
[0046] It should be noted that by setting the pseudo-active region 202, the distance between two adjacent test cells along the second direction (i.e., the Y direction) can be increased, thereby expanding the area of each repeating cell in the semiconductor test structure (the area of the repeating cell is the sum of the areas of a test cell and a pseudo-active region), thereby reducing the ratio of the total surface area of the gate 210 to that of the substrate 200, and thus reducing the gate density in the semiconductor test structure.
[0047] In other embodiments of this application, the gate area and gate density can be reduced by adjusting the distance between adjacent test units or by adjusting the arrangement of different semiconductor structures, provided that the test requirements are met, so as to improve the yield and test accuracy of the semiconductor test structure. This is something that those skilled in the art can easily deduce based on common sense and professional knowledge, and will not be elaborated on here.
[0048] Continue reading Figure 2 In one embodiment, the semiconductor test structure further includes an interconnect layer 220, a first electrical connector 221, and a second electrical connector 222. The interconnect layer 220 is spaced apart on the side of the gate 210 away from the active region 201. The first electrical connector 221 is located between the gate 210 and the interconnect layer 220 and is connected to both the gate 210 and the interconnect layer 220. The second electrical connector 222 is located on the active region 201 between the gate 210 and the dummy gate 211 and is connected to the interconnect layer 220, to ensure that the semiconductor test structure can operate normally and meet the corresponding test requirements.
[0049] In one embodiment, the interconnect layer 220 is made of a conductive material, and the conductive material includes at least copper (Cu) or aluminum (Al). In other embodiments of this application, the conductive material used to fabricate the interconnect layer can also be other commonly used metals or alloys, which is common knowledge known to those skilled in the art and will not be elaborated upon here. Optionally, the first electrical connector 221 and the second electrical connector 222 are also made of conductive materials. For example, the materials of the first electrical connector 221 and the second electrical connector include copper (Cu), aluminum (Al), or tungsten (W).
[0050] In one embodiment, an interlayer dielectric layer (not shown in the figure) is further disposed on the side of the gate away from the active region, and the interconnect layer, the first electrical connector, and the second electrical connector are all disposed within the interlayer dielectric layer. Optionally, the material of the interlayer dielectric layer includes an insulating material, which includes at least one of silicon oxide and silicon nitride.
[0051] Continue reading Figure 2 In one embodiment, along a direction perpendicular to the surface of the substrate 200, the orthographic projection of the first electrical connector 221 coincides with the orthographic projection of the gate 210 and the orthographic projection of the interconnect layer 220, and the orthographic projection of the first electrical connector 221 is separate from the orthographic projection of the active region 201.
[0052] The following is based on Figure 2 Taking the semiconductor test structure shown as an example, this paper introduces the application of the semiconductor test structure provided in one embodiment of this application for testing the equivalent gate oxide thickness (EOT).
[0053] See Figure 2 When the maximum width of the gate 210 in the semiconductor test structure is 1 μm, the number of test cells included in the semiconductor test structure is, for example, 480. (Comparison) Figure 1 and Figure 2 With the same total area, a typical equivalent gate oxide thickness (EOT) test structure typically contains 546 EOT test cells. Furthermore, the area of a single gate within the semiconductor test structure is significantly smaller than the area of the gate structure in a typical EOT test structure.
[0054] It is evident that the semiconductor test structure provided in this application can reduce the number of test units within the same area by approximately 12% while meeting test requirements. Furthermore, with the same total area, the reduction in the number of test units indicates that the gate density within the semiconductor test structure is also reduced accordingly.
[0055] Therefore, compared with a typical equivalent gate oxide thickness testing structure, the semiconductor testing structure provided in one embodiment of this application can reduce the risk of excessively low gate height due to over-grinding during subsequent planarization processing by reducing the gate area and gate density, thereby avoiding other structural defects caused by excessively low gate height. At the same time, this application ensures the effectiveness and accuracy of the test without increasing the total area of the semiconductor testing structure, which helps control the production cost of the semiconductor testing structure.
[0056] It should be noted that the semiconductor test structure provided in this application can not only be used for equivalent gate oxide thickness testing, but can also be configured as other semiconductor structures according to actual needs. That is, the design concept provided in this application can be used to optimize the specific construction of other semiconductor structures to reduce or avoid process risks caused by excessive gate area or gate density in the semiconductor structure fabrication process, thereby improving the yield and performance of the semiconductor structure. This application does not impose any limitations on this.
[0057] An unexpected effect of this application is that by setting up multiple test units that are spaced apart from each other and arranged in a two-dimensional array, and setting up multiple dummy gates between the gates of two adjacent test units along the first direction, the gate area and gate density in the semiconductor test structure are reduced, thereby reducing the risk of excessively low gate height due to excessive polishing during the subsequent planarization process, and thus improving the yield and stability of the semiconductor test structure.
[0058] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0059] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0060] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.
Claims
1. A semiconductor test structure, characterized by, The semiconductor test structure comprises: a plurality of test units arranged in a two-dimensional array, and two adjacent test units are spaced apart, each test unit comprising an active region in a substrate and a gate on the active region; a plurality of dummy gates on the substrate, and the dummy gates are arranged between the gates of two adjacent test units in a first direction, wherein the extension direction of the gates is a second direction, and the first direction and the second direction are perpendicular to each other.
2. The semiconductor test structure of claim 1, wherein, The semiconductor test structure further comprises a plurality of dummy active regions in the substrate between two adjacent test units in the second direction.
3. The semiconductor test structure of claim 1, wherein, The total area of the projection of all the dummy gates and the projection of all the gates accounts for 10% to 65% of the total area of the surface of the substrate in the direction perpendicular to the surface of the substrate.
4. The semiconductor test structure of claim 1, wherein, In the direction perpendicular to the surface of the substrate, the projection of part of the dummy gates partially overlaps with the projection of the active region, and the projection of the remaining dummy gates is separated from the projection of the active region.
5. The semiconductor test structure of claim 1 or 4, wherein, In the direction perpendicular to the surface of the substrate, the projection of the dummy gate is in the shape of a long strip, and the extension direction of the dummy gate is the same as the extension direction of the gate.
6. The semiconductor test structure of claim 5, wherein, The length of the dummy gate is the same as the length of the gate, and the width of the dummy gate is smaller than the width of the gate.
7. The semiconductor test structure of claim 1 or 4, wherein, In the direction perpendicular to the surface of the substrate, the projection of the gate partially overlaps with the projection of the active region.
8. The semiconductor test structure of claim 1, wherein, The semiconductor test structure further comprises: an interconnection layer spaced apart from the side of the gate away from the active region; a first electrical connection between the gate and the interconnection layer, and connected to the gate and the interconnection layer; a second electrical connection on the active region between the gate and the dummy gate, and connected to the interconnection layer.
9. The semiconductor test structure of claim 8, wherein, In the direction perpendicular to the surface of the substrate, the projection of the first electrical connection overlaps with the projection of the gate and the projection of the interconnection layer, and the projection of the first electrical connection is separated from the projection of the active region.
10. The semiconductor test structure of claim 8, wherein, The material of the interconnection layer is a conductive material, and the conductive material at least comprises metal copper or metal aluminum.