Current mirror ORING circuit based on PMOS field effect transistor

Abstract

The utility model provides a current mirror ORING circuit based on a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor. The current mirror ORING circuit comprises a first PMOS field effect transistor and a comparator, the current input end of the first PMOS field effect transistor is connected with the first input end of the comparator; the current output end of the first PMOS field effect transistor is connected with the second input end of the comparator; the grid electrode of the first PMOS field effect transistor is connected with the output end of the comparator; an external direct current signal is input to the current input end of the first PMOS field effect transistor; when the first input end voltage of the comparator is higher than the second input end voltage of the comparator, a conduction control signal of the comparator is transmitted to the first PMOS field effect transistor, and the current output end of the first PMOS field effect transistor outputs a direct current signal. The ORING circuit is realized through the combination of the P-channel enhanced MOSFET and the comparator, and BIAS voltage does not need to be introduced, so that the circuit is simplified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply circuit, in particular to a current mirror ORING circuit based on PMOS field effect tube. BACKGROUND

[0002] ORING circuits are divided into two categories: one is the traditional semiconductor diode; the other is a dedicated integrated IC controller. The working mode of the two types of ORING circuits is to be connected in series to the corresponding working circuit to limit the current to flow in one direction only.

[0003] The patent document with the publication number CN102545868A is cited here, which discloses an ORing Fet blocking circuit, which selectively controls the turn-on or turn-off of the field effect tube by using two transistors. Compared with the conventional ORing circuit using a comparator, the influence of the input offset of the comparator on the ORing control can be avoided, the efficiency of the ORing control is effectively improved, and the circuit structure is simple and easy to implement.

[0004] However, the existing ORING circuit structure is still relatively complex.

[0005] It should be noted that the information in the above background section is only used to strengthen the understanding of the background of the present application, and therefore can include technical information that is not known or easily inferred by those skilled in the art. CONTENT OF THE INVENTION

[0006] In view of the above problems, the present application is proposed to provide an ORING circuit based on PMOS field effect tube to overcome the above problems or at least partially solve the above problems.

[0007] The present application provides an ORING circuit based on PMOS field effect tube, comprising: a first PMOS field effect tube and a comparator.

[0008] The current input end of the first PMOS field effect tube is connected to the first input end of the comparator; the current output end of the first PMOS field effect tube is connected to the second input end of the comparator; the gate of the first PMOS field effect tube is connected to the output end of the comparator.

[0009] An external DC signal is input to the current input end of the first PMOS field effect tube.

[0010] When the first input end voltage of the comparator is higher than the second input end voltage of the comparator, the conduction control signal of the comparator is transmitted to the first PMOS field effect tube, and the current output end of the first PMOS field effect tube outputs a DC signal.

[0011] Further, when the first input terminal voltage of the comparator is not higher than the second input terminal voltage of the comparator, the cutoff control signal of the comparator is transmitted to the first PMOS field effect tube.

[0012] Further, the current input terminal of the first PMOS field effect tube is a drain; and the current output terminal of the first PMOS field effect tube is a source.

[0013] Further, the current input terminal of the first PMOS field effect tube is a source; and the current output terminal of the first PMOS field effect tube is a drain.

[0014] Further, the comparator comprises a second PMOS field effect tube and a third PMOS field effect tube.

[0015] The current input terminal of the first PMOS field effect tube is connected with the source of the second PMOS field effect tube; the gate of the second PMOS field effect tube is connected with the drain of the second PMOS field effect tube, one end of a resistor R1 and the gate of the third PMOS field effect tube; and the other end of the resistor R1 is grounded.

[0016] The current output terminal of the first PMOS field effect tube is connected with the source of the third PMOS field effect tube; the drain of the third PMOS field effect tube is connected with the gate of the first PMOS field effect tube and one end of a resistor R2; and the other end of the resistor R2 is grounded.

[0017] Further, the comparator comprises a fourth PMOS field effect tube and a fifth PMOS field effect tube.

[0018] The current input terminal of the first PMOS field effect tube is connected with the source of the fourth PMOS field effect tube; the drain of the fourth PMOS field effect tube is connected with the gate of the first PMOS field effect tube and one end of a resistor R2; and the other end of the resistor R2 is grounded.

[0019] The current output terminal of the first PMOS field effect tube is connected with the source of the fifth PMOS field effect tube; the gate of the fifth PMOS field effect tube is connected with the drain of the fifth PMOS field effect tube, one end of a resistor R1 and the gate of the fourth PMOS field effect tube; and the other end of the resistor R1 is grounded.

[0020] Further, the comparator comprises a first PNP triode and a second PNP triode.

[0021] The current input end of the first PMOS field effect tube is connected with the emitter of the first PNP triode; the base of the first PNP triode is connected with the collector of the first PNP triode, one end of the resistor R2 and the base of the second PNP triode; the other end of the resistor R2 is grounded;

[0022] The current output end of the first PMOS field effect tube is connected with the emitter of the second PNP triode; the collector of the second PNP triode is connected with the gate of the first PMOS field effect tube and one end of the resistor R1; the other end of the resistor R1 is grounded.

[0023] Further, the resistance values of the resistor R1 and the resistor R2 are 1KΩ-100KΩ.

[0024] Further, the model of the first PMOS field effect tube is AP3101A.

[0025] Further, the model of the comparator is LBSS84DW1T1G.

[0026] The application has the following advantages:

[0027] In the embodiment of the application, in view of the complex structure of the existing ORING circuit, the application provides a solution for realizing the ORING circuit by combining the P-channel enhancement mode MOSFET and the comparator, specifically: the current input end of the first PMOS field effect tube is connected with the first input end of the comparator; the current output end of the first PMOS field effect tube is connected with the second input end of the comparator; the gate of the first PMOS field effect tube is connected with the output end of the comparator; the external direct current signal is input to the current input end of the first PMOS field effect tube; when the voltage of the first input end of the comparator is higher than the voltage of the second input end of the comparator, the conduction control signal of the comparator is transmitted to the first PMOS field effect tube, and the current output end of the first PMOS field effect tube outputs the direct current signal. The ORING circuit is realized by combining the P-channel enhancement mode MOSFET and the comparator, without introducing the BIAS voltage, thereby simplifying the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the application, the following will briefly introduce the drawings needed to be used in the description of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0029] Figure 1 is a structural block diagram of a current mirror ORING circuit based on a PMOS field effect tube provided by an embodiment of the application;

[0030] Figure 2 is a working principle logic diagram of a PMOS field effect transistor-based current mirror ORING circuit according to an embodiment of the present application;

[0031] Figure 3 is a first circuit structure diagram of a PMOS field effect transistor-based current mirror ORING circuit according to an embodiment of the present application;

[0032] Figure 4 is a second circuit structure diagram of a PMOS field effect transistor-based current mirror ORING circuit according to an embodiment of the present application;

[0033] Figure 5 is a third circuit structure diagram of a PMOS field effect transistor-based current mirror ORING circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the objectives, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0035] The inventors found through analysis of the prior art that the ORING circuit composed of diodes usually has the following defects:

[0036] 1) High power loss: the forward voltage drop of ordinary diodes is relatively high, usually around 0.7V (silicon diodes) or 0.2V (Schottky diodes); in the case of large current, this will cause significant power loss and heat;

[0037] 2) Low efficiency: due to high power loss, the efficiency of ordinary diodes is relatively low, especially in high current applications; this will cause the overall efficiency of the system to decrease;

[0038] 3) High demand for thermal management: due to high power loss, ordinary diodes require better heat dissipation measures, such as heat sinks and larger PCB space, for thermal management;

[0039] 4) Slow response speed: the response speed of ordinary diodes is relatively slow, which cannot quickly detect and respond to power failures; this may cause the system to fail to switch to backup power in time when the power fails;

[0040] 5) Poor reverse current blocking capability: ordinary diodes perform poorly in reverse current blocking, which may cause reverse current to flow into the system, affecting system stability.

[0041] At the same time, for the ORing circuit composed of a dedicated integrated IC controller, there are usually the following defects:

[0042] 1) High cost: Since the ORing circuit uses more components (such as MOSFET, controller, etc.), its cost is higher than that of ordinary diodes; this may not be the best choice in some cost-sensitive applications;

[0043] 2) High complexity: The ORing circuit is usually composed of MOSFET and controller, which is much more complex to design and implement than ordinary diodes; precise control logic and drive circuit are required, which increases the difficulty of design and maintenance;

[0044] 3) Small power: For ORING controllers with internal integrated MOSFET, the rated current is usually only 500mA; this limits its application in high-power scenarios;

[0045] 4) Low voltage resistance: Similarly, for ORING controllers with internal integrated MOSFET, the rated voltage is usually only about 6V, suitable only for 5V and below voltage scenarios; limiting its application scenarios in 12V power supply widely used in life and industrial control;

[0046] 5) High requirement for power quality: Special integrated IC controllers have higher requirements for input power quality, as power fluctuations may affect the working state of the internal MCU controller, and thus affect the stability of the circuit.

[0047] In addition, the comparator of some existing technical solutions needs to provide an additional BIAS voltage, which must be greater than Vout+0.7V and less than Vout+6V to work normally, which has voltage limitations; at the same time, the quality of the BIAS power supply will affect the overall power quality of the system, and if there is ripple or other types of interference on the BIAS power supply, it will also flow into the output end of the circuit. The comparator of some existing technical solutions uses two NPN transistors, which will have current flowing through the comparator when working, which is easy to cause power consumption and heat. Some existing technical solutions use N-channel enhancement mode MOSFET as the main control device, which makes the ORING circuit structure still relatively complex.

[0048] Based on the above systematic analysis of the prior art, one of the core technical ideas of the present application is to realize the ORING circuit by combining the P-channel enhancement mode MOSFET and the comparator, without introducing the BIAS voltage, thereby simplifying the circuit.

[0049] It should be noted that, in any embodiment of the present application, since the P-channel enhancement mode MOSFET and the N-channel enhancement mode MOSFET have different control principles as the ORING current control device, the two cannot be replaced with each other.

[0050] Referring to Figure 1 , a PMOS-based current mirror ORING circuit is shown, which comprises a first PMOS and a comparator.

[0051] The current input end of the first PMOS is connected with the first input end of the comparator; the current output end of the first PMOS is connected with the second input end of the comparator; and the gate of the first PMOS is connected with the output end of the comparator.

[0052] An external DC signal is input to the current input end of the first PMOS.

[0053] When the voltage at the first input end of the comparator is higher than the voltage at the second input end of the comparator, the on-off control signal of the comparator is transmitted to the first PMOS, and the current output end of the first PMOS outputs a DC signal.

[0054] In the embodiment of the present application, in view of the fact that the existing ORING circuit structure is relatively complex, the present application provides a solution for realizing the ORING circuit by combining the P-channel enhancement mode MOSFET and the comparator, specifically: the current input end of the first PMOS is connected with the first input end of the comparator; the current output end of the first PMOS is connected with the second input end of the comparator; the gate of the first PMOS is connected with the output end of the comparator; an external DC signal is input to the current input end of the first PMOS; when the voltage at the first input end of the comparator is higher than the voltage at the second input end of the comparator, the on-off control signal of the comparator is transmitted to the first PMOS, and the current output end of the first PMOS outputs a DC signal. By combining the P-channel enhancement mode MOSFET and the comparator to realize the ORING circuit, there is no need to introduce a BIAS voltage, thereby simplifying the circuit.

[0055] In the following, a PMOS-based current mirror ORING circuit in the present exemplary embodiment will be further described.

[0056] It should be noted that, referring to Figure 2, by comparing the first input end and the second input end voltage of the comparator, only when the external power source connected to the current input end of the first PMOS field effect transistor is a positive voltage, the first PMOS field effect transistor is turned on, thereby realizing the power reverse connection protection and the function of the ORING circuit, i.e. the ideal diode.

[0057] Compared with the prior art solution of adopting the NMOS field effect transistor and being driven by the BIAS voltage, the first PMOS field effect transistor is used as the power MOSFET in the present application, and the BIAS voltage is not needed, and the circuit is simplified. Compared with the prior art solution of adopting two NPN type triodes, the comparator in the present application can include two P-channel enhancement mode MOSFETs, and there is almost no static current when working, and therefore the present application is more energy-saving. The present application also does not need the BIAS voltage for driving, and therefore it is easier to obtain a clean and stable power supply output.

[0058] With reference to Figure 1 In an embodiment of the present application, when the first input end voltage of the comparator is not higher than the second input end voltage of the comparator, the cutoff control signal of the comparator is transmitted to the first PMOS field effect transistor.

[0059] It should be noted that, with reference to Figure 2 , by comparing the first input end and the second input end voltage of the comparator, if the input voltage connected to the current input end of the first PMOS field effect transistor is removed or disappears, the first PMOS field effect transistor is cut off, thereby realizing the function of preventing the current from flowing back.

[0060] With reference to Figure 3 In an embodiment of the present application, the current input end of the first PMOS field effect transistor is the drain; and the current output end of the first PMOS field effect transistor is the source.

[0061] With reference to Figure 4 In an embodiment of the present application, the current input end of the first PMOS field effect transistor is the source; and the current output end of the first PMOS field effect transistor is the drain.

[0062] With reference to Figures 3-4 In a specific embodiment of the present application, the comparator can be a comparator composed of a double P-channel MOSET and a corresponding resistor; the first PMOS field effect transistor is used as the power MOSFET; the voltage on both sides of the direct current power supply is judged by the comparator, and the power MOSFET is turned on and off correspondingly. The MOSFET in any embodiment of the present application can be a P-channel enhancement mode MOSFET. Only when the input voltage of the direct current power supply is higher than the output voltage of the direct current power supply, the control circuit of the comparator controls the power MOSFET to be turned on, so that the power current can only flow in one direction.

[0063] It should be noted that the embodiment needs 5 electronic components in total: 2 resistors, 3 MOSFETs and corresponding connecting components between the circuits, such as PCB, flying wire or etching circuit on wafer. For the convenience of description, the PCB circuit is taken as an example in the description of other embodiments of the application, and the type of the connected circuit should not be a limitation of the application.

[0064] The circuit core of the embodiment is composed of only three P-channel MOSFETs, which significantly reduces the PCB design difficulty and cost compared with the special integrated IC controller, has high performance, and does not need to consider the power supply of the MCU in the special integrated IC controller, and the requirement for the power supply quality is also more relaxed; compared with the traditional diode, the working loss and heat of the circuit can be significantly reduced, and the efficiency is high; the voltage resistance and power of the circuit of the embodiment can be adjusted arbitrarily according to the actual working condition, and has great flexibility.

[0065] Reference Figure 3 In an embodiment of the application, the comparator comprises a second PMOS field effect transistor and a third PMOS field effect transistor.

[0066] The current input end of the first PMOS field effect transistor is connected with the source of the second PMOS field effect transistor; the gate of the second PMOS field effect transistor is connected with the drain of the second PMOS field effect transistor, one end of a resistor R1 and the gate of the third PMOS field effect transistor; the other end of the resistor R1 is grounded.

[0067] The current output end of the first PMOS field effect transistor is connected with the source of the third PMOS field effect transistor; the drain of the third PMOS field effect transistor is connected with the gate of the first PMOS field effect transistor and one end of a resistor R2; the other end of the resistor R2 is grounded.

[0068] It should be noted that in the mirror ratio circuit composed of two MOSFETs in the embodiment, the sources of the two MOSFETs are respectively used as two input ends of the comparator, and are respectively used for detecting the voltages of the power input and output. When the power input voltage is higher than the power output, the second PMOS field effect transistor is saturated and turned on, the third PMOS field effect transistor is cut off, the drain of the third PMOS field effect transistor is grounded through the resistor R2, and since the gate of the first PMOS field effect transistor is also connected to the drain of the third PMOS field effect transistor, the first PMOS field effect transistor is grounded and turned on. On the contrary, if the input voltage is removed, the third PMOS field effect transistor is saturated and turned on, the gate of the first PMOS field effect transistor is pulled up and cut off, thereby realizing the anti-current backflow function. In addition, since the comparator uses the PMOS field effect transistor, the first PMOS field effect transistor will only be turned on when the power input end provides a positive voltage, thereby realizing the power reverse connection protection function.

[0069] With reference to Figure 4 In an embodiment of the present application, the comparator comprises a fourth PMOS field effect transistor and a fifth PMOS field effect transistor.

[0070] The current input end of the first PMOS field effect transistor is connected with the source of the fourth PMOS field effect transistor; the drain of the fourth PMOS field effect transistor is connected with the gate of the first PMOS field effect transistor and one end of a resistor R2; the other end of the resistor R2 is grounded.

[0071] The current output end of the first PMOS field effect transistor is connected with the source of the fifth PMOS field effect transistor; the gate of the fifth PMOS field effect transistor is connected with the drain of the fifth PMOS field effect transistor, one end of a resistor R1 and the gate of the fourth PMOS field effect transistor; the other end of the resistor R1 is grounded.

[0072] It should be noted that the combined structure of the fourth PMOS field effect transistor and the fifth PMOS field effect transistor in the embodiment can be an alternative to the combined structure of the second PMOS field effect transistor and the third PMOS field effect transistor, and since the principle is basically similar, the related parts are referred to the above embodiment.

[0073] With reference to Figure 5 In an embodiment of the present application, the comparator comprises a first PNP transistor and a second PNP transistor.

[0074] The current input end of the first PMOS field effect transistor is connected with the emitter of the first PNP transistor; the base of the first PNP transistor is connected with the collector of the first PNP transistor, one end of a resistor R2 and the base of the second PNP transistor; the other end of the resistor R2 is grounded.

[0075] The current output end of the first PMOS field effect transistor is connected with the emitter of the second PNP transistor; the collector of the second PNP transistor is connected with the gate of the first PMOS field effect transistor and one end of a resistor R1; the other end of the resistor R1 is grounded.

[0076] It should be noted that the combination structure of the first PNP triode and the second PNP triode in this embodiment can be an alternative to the combination structure of the second PMOS field effect transistor and the third PMOS field effect transistor, and the relevant parts refer to the above embodiment since the principle is basically similar. It should be noted that since the Ube voltage of the triode is generally not greater than 6V, when the output voltage is greater than 12V, the triode connected to the external power supply can be reversely broken down, resulting in a reverse voltage on the input side of the power supply. The double-PNP triode scheme has a greater limitation on the input voltage than the double-P-MOSFET scheme.

[0077] In an embodiment of the present application, the resistance R1 and the resistance R2 have a resistance value of 1KΩ-100KΩ.

[0078] It should be noted that the functions of R1 and R2 are to limit the current between the drain and the source of the MOSFET, and the values can be 1K-100K. It should be noted that the greater the values of the two resistors, the slower the overall response speed of the system, but too low resistance values will also increase the static power consumption of the overall circuit.

[0079] In an embodiment of the present application, the first PMOS field effect transistor is AP3101A.

[0080] It should be noted that the first PMOS field effect transistor can also be SI2101. When selecting the first PMOS field effect transistor, the VGS voltage resistance of the MOSFET needs to be greater than the controlled DC power supply voltage, and the actual current size can be reasonably selected.

[0081] In an embodiment of the present application, the comparator is LBSS84DW1T1G.

[0082] It should be noted that when selecting the comparator, the VGS voltage resistance of the MOSFET of the comparator needs to be greater than the controlled DC power supply voltage in actual application. In addition, since the junction capacitance of the MOSFET will affect the response speed of the design, the comparator does not need to carry power current, and a model with smaller junction capacitance can be preferred to improve the response time of the system.

[0083] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic creative concept. Therefore, the appended claims are intended to include the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0084] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other closure, are intended to cover the non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include those elements alone but can include other elements not expressly listed or even include elements inherent in such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0085] The above describes in detail the current mirror ORING circuit based on the PMOS field effect tube provided by the present application. The principles and implementation modes of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A PMOS field effect transistor based current mirror ORING circuit, characterized by, include: First PMOS field-effect transistor and comparator; The current input terminal of the first PMOS field-effect transistor is connected to the first input terminal of the comparator; The current output terminal of the first PMOS field-effect transistor is connected to the second input terminal of the comparator; the gate of the first PMOS field-effect transistor is connected to the output terminal of the comparator. An external DC signal is input to the current input terminal of the first PMOS field-effect transistor; When the voltage at the first input terminal of the comparator is higher than the voltage at the second input terminal of the comparator, the conduction control signal of the comparator is transmitted to the first PMOS field-effect transistor, and the current output terminal of the first PMOS field-effect transistor outputs a DC signal.

2. The circuit of claim 1, wherein, When the voltage at the first input terminal of the comparator is not higher than the voltage at the second input terminal of the comparator, the cutoff control signal of the comparator is transmitted to the first PMOS field-effect transistor.

3. The circuit of claim 1, wherein, The current input terminal of the first PMOS field-effect transistor is the drain; the current output terminal of the first PMOS field-effect transistor is the source.

4. The circuit of claim 1, wherein, The current input terminal of the first PMOS field-effect transistor is the source; the current output terminal of the first PMOS field-effect transistor is the drain.

5. The circuit of claim 1, wherein, The comparator includes: a second PMOS field-effect transistor and a third PMOS field-effect transistor; The current input terminal of the first PMOS field-effect transistor is connected to the source of the second PMOS field-effect transistor; the gate of the second PMOS field-effect transistor is connected to the drain of the second PMOS field-effect transistor, one end of resistor R1 is connected to the gate of the third PMOS field-effect transistor; the other end of resistor R1 is grounded. The current output terminal of the first PMOS field-effect transistor is connected to the source of the third PMOS field-effect transistor; the drain of the third PMOS field-effect transistor is connected to the gate of the first PMOS field-effect transistor and one end of resistor R2; the other end of resistor R2 is grounded.

6. The circuit of claim 1, wherein, The comparator includes: a fourth PMOS field-effect transistor and a fifth PMOS field-effect transistor; The current input terminal of the first PMOS field-effect transistor is connected to the source of the fourth PMOS field-effect transistor; the drain of the fourth PMOS field-effect transistor is connected to the gate of the first PMOS field-effect transistor and one end of resistor R2; the other end of resistor R2 is grounded. The current output terminal of the first PMOS field-effect transistor is connected to the source of the fifth PMOS field-effect transistor; the gate of the fifth PMOS field-effect transistor is connected to the drain of the fifth PMOS field-effect transistor, one end of resistor R1 is connected to the gate of the fourth PMOS field-effect transistor; the other end of resistor R1 is grounded.

7. The circuit of claim 1, wherein, The comparator includes: a first PNP transistor and a second PNP transistor; The current input terminal of the first PMOS field-effect transistor is connected to the emitter of the first PNP transistor; the base of the first PNP transistor is connected to the collector of the first PNP transistor, one end of resistor R2 is connected to the base of the second PNP transistor; the other end of resistor R2 is grounded. The current output end of the first PMOS field effect tube is connected with the emitter of the second PNP triode; the collector of the second PNP triode is connected with the gate of the first PMOS field effect tube and one end of a resistor R1; the other end of the resistor R1 is grounded.

8. The circuit of any one of claims 5-7, wherein, The resistance values of the resistor R1 and the resistor R2 are 1KΩ-100KΩ.

9. The circuit of claim 1, wherein, The model of the first PMOS field effect tube is AP3101A.

10. The circuit of claim 1, wherein, The model of the comparator is LBSS84DW1T1G.

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