High electron mobility transistor device and electronic device

Abstract

The embodiment of the utility model relates to a high electron mobility transistor device and an electronic device. A high electron mobility transistor device includes: a heterostructure including a channel layer and a barrier layer, the barrier layer extending onto the channel layer along a first axis; a dielectric protection layer extending onto the barrier layer along a first axis; and a gate region extending along the first axis onto the dielectric protection layer, in which the dielectric protection layer has a thickness of less than 10 nm along the first axis.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to high electron mobility transistor (HEMT) devices and electronic devices. BACKGROUND

[0002] HEMT devices are known, in which a conductive channel is based on the formation of a layer of two-dimensional electron gas (2DEG) with high mobility at a heterostructure, i.e. at an interface between semiconductor materials with different bandgaps. For example, HEMT devices are known based on a heterostructure between a layer of aluminium gallium nitride (AlGaN) barrier and a layer of gallium nitride (GaN) channel.

[0003] HEMT devices based on AlGaN / GaN heterostructures offer various advantages, making them particularly suitable and widely used for different applications. For example, the high breakdown threshold of HEMT devices is used for high-performance power switches; the high mobility of the electrons in the conductive channel allows the manufacture of high-frequency amplifiers; moreover, the high concentration of electrons in the 2DEG allows obtaining low ON (conducting) state resistance (Ron). ON Furthermore, HEMT devices for radio frequency (RF) applications generally have better RF performance compared to similar silicon devices.

[0004] Typically, GaN / AlGaN HEMTs operate in depletion mode, also known as "D-mode", and are therefore normally open. In particular, in D-mode HEMTs, a gate structure placed on top of the barrier layer is biased to a negative gate voltage in terms of drain and source bias, to deplete the 2DEG.

[0005] In more detail, there are two generally known solutions for manufacturing D-mode HEMTs: either with a gate structure that forms a Schottky-type contact with the barrier layer, or with an insulating gate structure. In the first case, the gate structure has a metal gate region (e.g. Ni-Au or Pt) that is in contact with the barrier layer and therefore forms a Schottky-type contact with the barrier layer. In the second case, the gate structure has a metal gate region and a gate insulating layer (e.g. SiO2) interposed between the metal gate region and the barrier layer, to prevent the generation of gate current. The thickness of the gate insulating layer is higher than 10 nm and is typically equal to about 20 nm. This allows obtaining a negative "pinch-off" voltage at gate voltage values lower than about -10 V, thus avoiding the turn-off of the HEMT device under operating conditions of high drain voltage (e.g. up to 650 V).

[0006] However, several practical applications also use GaN / AlGaN HEMTs operating in enhancement mode, also known as "E-mode", and are therefore normally closed. These devices allow safe operation and ensure the simplification of the driving circuit.

[0007] Different methods are known for obtaining normally-off HEMTs, such as the use of a recessed p-GaN type gate structure or the incorporation of fluorine plasma under the metal gate region. In particular, the pGaN type gate structure is the one most commonly used in products currently available on the market, since it has outstanding electrical performances and is easier to manufacture with respect to the other solutions described above.

[0008] In detail, the pGaN type HEMT has a gate structure comprising a metal gate region and a channel modulation region, which is of pGaN (gallium nitride with P-type conductivity due to, for example, doping with magnesium) and extends between the metal gate region and the barrier layer. It is known that the presence of the channel modulation region changes the band diagram of the HEMT and makes it normally-off.

[0009] However, none of the known solutions currently allows both D-mode and E-mode HEMTs of the pGaN gate type to be manufactured in an integrated manner, while maintaining the high electrical performances of these devices. As a result, it is currently not possible in practice to have both types of devices on a single wafer and small size support.

[0010] In fact, it has been verified that the known solutions that try to integrate E-mode HEMTs of the pGaN gate type with D-mode HEMTs having a Schottky type gate structure include D-mode HEMTs with highly degraded electrical performances. This is because, during the step of forming the gate structure of the D-mode HEMT, an etching of the oxide covering the barrier layer is used, which is removed in the zone where the gate structure is expected to be formed, to locally expose the barrier layer so that a Schottky contact can be formed. This etching damages the upper surface of the barrier layer, which is intended to come into contact with the metal gate region. In particular, the etching introduces traps in the barrier layer for the charge carriers and this causes instabilities in the gate voltage and a higher on-state resistance. In more detail, the damage to the barrier layer causes a leakage current of the reverse-biased Schottky junction and makes the pinch-off voltage very sensitive to various manufacturing process factors.

[0011] On the contrary, it is known that, especially if for high power applications (i.e. for drain voltages that can reach 650 V), no currently available solution allows to integrate both pGaN-gate type E-mode HEMTs and D-mode HEMTs with insulating gate structure into the same manufacturing process. In fact, the high thickness of the gate insulating layer for D-mode HEMTs makes the manufacturing of these D-mode HEMTs incompatible with the manufacturing process flow of pGaN-gate type E-mode HEMTs. Currently, D-mode HEMTs with insulating gate structure and pGaN-gate type E-mode HEMTs are manufactured separately and the two types of HEMTs are then assembled on a single support. As a result, their manufacturing is not integrated and, as a consequence, it is not a monolithic solution. SUMMARY

[0012] According to the present disclosure, a high electron mobility transistor device and an electronic device overcoming the drawbacks of the prior art are provided.

[0013] According to a first aspect, a high electron mobility transistor device is provided. The high electron mobility transistor device comprises: a heterostructure comprising a channel layer and a barrier layer, the barrier layer extending on a first surface of the channel layer; a dielectric protection layer of a dielectric material, the dielectric protection layer extending on a first surface of the barrier layer, the first surface of the barrier layer opposite to the channel layer along a first direction; a first conductive terminal extending fully through the dielectric protection layer and the barrier layer along the first direction; and a gate region extending on the dielectric protection layer.

[0014] In some embodiments, the dielectric protection layer has a first thickness along the first direction, the first thickness being less than 10 nm.

[0015] In some embodiments, the first thickness of the dielectric protection layer is in the range of 1 nm to 7 nm.

[0016] In some embodiments, the dielectric protection layer is of one of the following materials: aluminum oxide, silicon oxide, silicon nitride, and aluminum nitride.

[0017] In some embodiments, the channel layer is of gallium nitride and the barrier layer is of a gallium nitride based alloy.

[0018] In some embodiments, the dielectric protection layer is directly between the barrier layer and the gate region.

[0019] In some embodiments, the high electron mobility transistor device is of depletion mode.

[0020] In some embodiments, the gate region forms, with the dielectric protection layer, an insulating gate structure of the high electron mobility transistor device.

[0021] In some embodiments, the high electron mobility transistor device further comprises a passivation layer on the dielectric protection layer, the passivation layer having a first gap along a second direction, the second direction being transverse to the first direction, the gate region being in the first gap.

[0022] According to a second aspect, an electronic device is provided. The electronic device comprises a heterostructure, a dielectric layer, a first conductive terminal, a gate region, and a passivation layer. The heterostructure comprises a channel layer and a barrier layer. The channel layer has a first surface. The barrier layer is on the first surface of the channel layer, the barrier layer having a first surface opposite the channel layer along a first direction. The dielectric layer is on the first surface of the barrier layer. The first conductive terminal has a first surface opposite a second surface along the first direction, the first conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction. The gate region is on the dielectric layer. The passivation layer is on the first surface of the barrier layer, the passivation layer comprising a first opening exposing the dielectric layer, the gate region being in the first opening, the passivation layer completely covering the first surface of the first conductive terminal.

[0023] In some embodiments, the second surface of the first conductive terminal is coplanar with the first surface of the channel layer.

[0024] In some embodiments, the electronic device further comprises a second conductive terminal, the second conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction.

[0025] In some embodiments, the passivation layer further comprises: a first portion having a first depth along the first direction; and a second portion having a second depth along the first direction, the second depth being greater than the first depth.

[0026] In some embodiments, the gate region comprises: a first portion having a first width along a second direction, the second direction being transverse to the first direction, the first portion being in direct contact with the first portion of the passivation layer; and a second portion having a second width along the second direction, the second width being greater than the first width, the second portion being physically separated from the second portion of the passivation layer along the second direction.

[0027] According to various embodiments of the present disclosure, high electron mobility transistor devices and electronic devices with improved performance can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0028] For a better understanding of the present disclosure, preferred embodiments will now be described, by way of non-limiting examples only, with reference to the accompanying drawings in which:

[0029] Figure 1 A cross-section of the present HEMT device according to one embodiment is shown;

[0030] Figures 2A-2J A cross-section of the present HEMT device according to one embodiment is shown; Figure 1cross-sections of other HEMT devices that can be integrated with the HEMT device of

[0031] Figures 3A-3C cross-sections of other HEMT devices that can be integrated with the HEMT device of Figure 1

[0032] Figure 4 cross-sections of electronic assemblies comprising the HEMT device of Figure 1 Figure 3C

[0033] In particular, the figures are shown with reference to a three-axial Cartesian system defined by an X-axis, a Y-axis and a Z-axis, which are orthogonal to each other.

[0034] In the following description, elements common to different embodiments have been indicated using the same reference numerals. DETAILED DESCRIPTION

[0035] Figure 1 A HEMT device (also referred to as a first HEMT device) 50 is shown, which is in particular normally-on and thus a depletion "D-mode" HEMT device.

[0036] The HEMT device 50 is particularly suitable for use in RF applications, such as for example 4G and 5G base stations, portable phones, RF cooking devices, drying and heating devices, avionics devices and systems, L-band and S-band radars, etc., including evolutions and variants of the technology.

[0037] The HEMT device 50 is formed into a body 55, which has a first surface 55A and a second surface 55B, and comprises a substrate 60, a heterostructure 62 extending over the substrate 60, and a dielectric passivation layer 67 extending over the heterostructure 62.

[0038] The substrate 60 of semiconductor material (for example, silicon or silicon carbide, sapphire (AI2O3) or other materials) extends between the second surface 55B of the body 55 and a respective surface 60A, which is opposite to the first surface 55A along the Z-axis.

[0039] The heterostructure 62 comprises a compound semiconductor material having elements of group III-V and extends onto the surface 60A of the substrate 60.

[0040] ​​​The heterostructure 62 is formed by a channel layer 64 of a first semiconductor material and a barrier layer 66 of a second semiconductor material. The first semiconductor material is, for example, gallium nitride (GaN) or a gallium nitride-based ternary alloy, such as InGaN (intrinsic gallium nitride). The channel layer 64 extends onto the substrate 60 and has a surface 64A opposite to surface 60A along the Z-axis. The second semiconductor material is, for example, a gallium nitride-based ternary or quaternary alloy, such as Al. x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x Al, AlScN (here, intrinsic aluminum gallium nitride AlGaN), and barrier layer 66 extends between surface 64A and surface 66A of channel layer 64, with surface 66A opposite to surface 64A along the Z-axis.

[0041] According to an embodiment not shown, the HEMT device 50 may further include a nucleation layer and a buffer layer between the substrate 60 and the heterostructure 62, with the buffer layer extending over the nucleation layer. Specifically, the nucleation layer is made of a material that allows the channel layer 64 to nucleate on the substrate 60, thereby reducing lattice mismatch between the channel layer 64 and the substrate 60. For example, the nucleation layer is made of aluminum nitride (AlN). Furthermore, the buffer layer is made of a material that reduces the drain current of the zero-bias IDSS of the HEMT device 50, for example, it is made of carbon-doped GaN.

[0042] The dielectric protective layer 67 extends onto the surface 66A of the barrier layer 66 and forms the first surface 55A of the body 55.

[0043] The dielectric protective layer 67 is a dielectric material such as aluminum oxide (Al2O3), silicon oxide (SiO2), silicon nitride (Si3N4), and aluminum nitride (AlN).

[0044] The dielectric protective layer 67 has a thickness t measured along the Z-axis. d Thickness t d Less than 10nm and especially between about 1nm and about 7nm (including boundary values).

[0045] As better described below, dielectric protection layer 67 allows the barrier layer 66 to be protected during the manufacture of HEMT device 50, preventing the formation of charge carrier traps in barrier layer 66, which would degrade the electrical performance of HEMT device 50.

[0046] HEMT device 50 may also include a passivation layer 68, which is a dielectric material, or is formed by a stack of dielectric materials such as, for example, silicon nitride and silicon oxide, and extends onto the first surface 55A of body 55.Figure 1 In the example of Fig. 6, the case is exemplarily shown in which the passivation layer 68 is formed by a single layer of dielectric material, however it can likewise have a more complex structure of the passivation layer 68 (as for example shown in Fig. 5). Figure 2J

[0047] The HEMT device 50 further comprises a source region 70 and a drain region 72, which extend in direct electrical contact with the heterostructure 62, and a gate region 74, which extends between the source region 70 and the drain region 72 and on the dielectric protection layer 67, so as to be physically insulated from the heterostructure 62 and to be electrically coupled to the heterostructure 62 by means of physical phenomena such as tunnel effect.

[0048] The body 55 houses an active region 76, as indicated by the dashed line in Fig. 6, which houses, in use, the conductive channel of the HEMT device 50. Figure 1

[0049] The source region 70 and the drain region 72 are of electrically conductive material (for example metallic material) and extend in depth into the body 55, completely through the dielectric protection layer 67 and the barrier layer 66 and up to the surface 64A of the channel layer 64.

[0050] In practice, the source region 70 and the drain region 72 form, respectively, the source electrode S and the drain electrode D of the HEMT device 50.

[0051] In detail, the source region 70 and the drain region 72 form an ohmic contact with the heterostructure 62, in particular with the channel layer 64.

[0052] According to different embodiments, not illustrated here, the source region 70 and the drain region 72 can extend only partially through the barrier layer 66 and end within the barrier layer 66.

[0053] According to different embodiments, not illustrated here, the source region 70 and the drain region 72 can extend only through the insulating layer 68 and the dielectric protection layer 67 up to the surface 66A of the barrier layer 66 and therefore do not need to extend in depth into the barrier layer 66.

[0054] According to other embodiments, not illustrated here, the source region 70 and the drain region 72 can also extend partially through the channel layer 64 and end in the channel layer 64.

[0055] Furthermore, the source region 70 and the drain region 72 can extend in depth differently from each other into the body 55.

[0056] ​​In practice, depending on the specific application of the HEMT device 50 and on the specific manufacturing process used to obtain the source region 70 and the drain region 72, the source region 70 and the drain region 72 can be in direct ohmic contact with the channel layer 64 or in electrical contact with the channel layer 64 due to different physical phenomena (e.g. due to tunneling effect).

[0057] The gate region 74 is of electrically conductive material (e.g. metallic material) and, depending on the specific application, can be formed by a single electrically conductive layer or by a stack of electrically conductive layers including, for example, gold, nickel, titanium, etc.

[0058] The dielectric protection layer 67 is directly interposed between the barrier layer 66 and the gate region 74 along the Z axis. In other words, the dielectric protection layer 67 extends in contact with both the barrier layer 66 and the gate region 74.

[0059] The gate region 74 forms the gate electrode G of the HEMT device 50.

[0060] In particular, the gate region 74 is physically insulated with respect to the heterostructure 62 thanks to the dielectric protection layer 67. In other words, the gate region 74, together with the portion of the dielectric protection layer 67 vertically aligned (i.e. aligned along the Z axis) with the gate region 74, forms an insulated gate structure of the HEMT device 50. However, a tunneling phenomenon can exist between the gate region 74 and the heterostructure 62, which makes the gate region 74 electrically coupled to the heterostructure 62.

[0061] In particular, the dielectric protection layer 67 extends uniformly between the barrier layer 66 and the passivation layer 68 or the gate region 74. Alternatively, the dielectric protection layer 67 can extend locally between the barrier layer 66 and the gate region 74, so it can not extend under the passivation layer 68. Nonetheless, the dielectric protection layer 67 is present at least at the gate region 74.

[0062] For example, the gate region 74 can comprise a surface portion 74A and an upper portion 74B which are continuous with each other. The surface portion 74A extends onto the dielectric protection layer 67 and through the passivation layer 68, while the upper portion 74B extends onto the surface portion 74A and partially over the passivation layer 68.

[0063] In detail, the passivation layer 68 extends on both the drain region 72 and the source region 70, for example so that the gate region 74 is partially exposed.

[0064] In the following, with reference to Figures 2A-2J the manufacturing steps of the HEMT device 50 are described, in particular the manufacturing steps leading to the formation of the gate region 74 superimposed on the dielectric protection layer 67.

[0065] Figures 2A-2JThe manufacturing of the gate region 74 superimposed on the dielectric protection layer 67 is focused on, and the known (concurrent, previous and / or subsequent) steps for forming other components of the HEMT device 50, such as electrical contact metallization, general electrical connections and any other elements useful or necessary for the operation of the HEMT device 50, which are known per se and not shown here, are not illustrated.

[0066] Figure 2A A cross-section of a workpiece 100 having a first surface 100A (corresponding to the surface 66a of the substrate 60) and a second surface 100B opposite each other along the Z axis is shown during a manufacturing step of the HEMT device 50. Figure 1 The elements common to what has been described with reference to the cross-section of the workpiece 100 and shown in Figure 1 are indicated with the same reference numerals and, since they are known per se, are not described in detail again. Figure 1

[0067] In the workpiece 100, the substrate 60 and the heterostructure 62 comprising the channel layer 64 and the barrier layer 66 have already been formed.

[0068] Subsequently, as shown in Figure 2B , a dielectric layer 102 of a dielectric layer material (such as AI2O3, SiO2, Si3N4, AIN) is formed on the first surface 100A of the workpiece body 100.

[0069] The dielectric layer 102 has a thickness along the Z axis less than 10 nm and in particular comprised between about 1 nm and about 7 nm, including the limit values, and is formed, for example, by atomic layer deposition (ALD). For example, water-based ALD is used, performed (thermally or by plasma) at about 300°C.

[0070] At the end of the manufacturing step, the dielectric layer 102 will form the dielectric protection layer 67 of the HEMT device 50. Figure 1

[0071] In particular, in the embodiment of Figure 1 , the dielectric layer 102 formed as described herein has defined the dielectric protection layer 67, while for other embodiments of the HEMT device 50 other manufacturing steps can be envisaged to obtain the dielectric protection layer 67 starting from the dielectric layer 102.

[0072] For example, in the case where the dielectric protection layer 67 extends only under the gate region 74, an etching is performed with reference to Figure 2B ​​The dielectric layer 102 described is formed after the etching is performed. The portion of the dielectric layer 102 that is not vertically aligned with the gate region 74 is selectively removed, leaving the portion of the dielectric layer 102 that is vertically aligned with the gate region 74 and forms the dielectric protective layer 67.

[0073] Referring again to the HEMT device 50 according to the embodiments described in detail herein, in Figure 2B At the end of the steps, a dielectric protective layer 67 is formed. As a result, the subsequent figures show a dielectric protective layer 67 instead of a dielectric layer 102. As previously described, the dielectric protective layer 67 forms the body 55 together with the heterostructure 62 and the substrate 60.

[0074] Subsequently, as Figure 2C As shown, a first insulating layer 104 of insulating material (such as silicon oxide) is formed on the dielectric protective layer 67 (e.g., on the first surface 55A of the body 55).

[0075] In detail, the first insulating layer 104 is formed on Figure 1 The gate region 74 of the HEMT device 50 will be formed at the location where it will be formed. More specifically, a first insulating layer 104 is selectively formed at the location where the gate region 74 will subsequently be formed and is formed laterally along the x-axis to the location where the gate region 74 will be formed (e.g., on both sides of the gate region 74, for a few micrometers or a fraction of a micrometer, e.g., 0.4 μm, starting from the gate region 74). At the end of the manufacturing step, the first insulating layer 104 will be formed. Figure 1 The passivation layer 68 of the HEMT device 50.

[0076] The first insulating layer 104 has a thickness between about 20 nm and about 100 nm (e.g., equal to 50 nm) and is formed, for example, based on plasma (e.g., SiH4 plasma) by chemical vapor deposition (CVD). CVD is performed to uniformly deposit an oxide layer on the dielectric protective layer 67, and then chemical etching (e.g., based on CF4) is performed on the deposited layer to leave the portion of the deposited layer forming the first insulating layer 104, rather than selectively removing the remaining portion of the deposited layer.

[0077] Subsequently, as Figure 2D As shown, a second insulating layer 106 of passivating material (such as silicon nitride) may be formed on the first insulating layer 104 and on the area of ​​the dielectric protective layer 67 exposed by the first insulating layer 104. However, this second insulating layer 106 is optional and may be absent in different embodiments of the HEMT device 50.

[0078] The second insulating layer 106 has a thickness along the Z-axis comprised between about 40 nm and about 150 nm, and for example equal to about 80 nm, and is formed for example by CVD, which is performed for depositing the second insulating layer 106 in a uniform manner as previously described.

[0079] At the end of the manufacturing steps, the second insulating layer 106 will form part of the passivation layer 68 of the HEMT device 50. Figure 1

[0080] Subsequently, as shown in Fig. 4, the source region 70 and the drain region 72 are formed. Figure 2E

[0081] In particular and in a manner not shown since known per se, one or more chemical etchings are performed (for example based on BCl3or ALE processes) to create respective trenches for the source region 70 and the drain region 72. The trenches are formed through the second insulating layer 106, the dielectric protection layer 67 and the barrier layer 66, at which the source region 70 and the drain region 72 are to be formed, respectively. For example, this etching step is performed using a mask that exposes the areas of the second insulating layer 106 where the source region 70 and the drain region 72 are to be formed, respectively, and which is removed after the etching step. Thereafter, the source region 70 and the drain region 72 are formed in the respective trenches, for example by means of: forming a mask that exposes the trenches covering the remaining portions of the second insulating layer 106; metal deposition (for example, a Ti / AlCu / TiN stack) in the trenches and on the mask; removing the mask and the metal deposition present thereon; thermal annealing (for example, at about 560 °C).

[0082] Subsequently, as shown in Fig. 5, a third insulating layer 108 of passivation material (such as silicon nitride) can be formed on the second insulating layer 106 and on the source region 70 and the drain region 72. Figure 2F The third insulating layer 108 has a thickness along the Z-axis comprised between about 40 nm and about 150 nm, and for example equal to about 80 nm, and is formed for example by CVD, which is performed for depositing the third insulating layer 108 in a uniform manner as previously described.

[0083] At the end of the manufacturing steps, the third insulating layer 108 will form part of the passivation layer 68 of the HEMT device 50.

[0084] Figure 1

[0085] Subsequently, as shown in Fig. 5, a third insulating layer 108 of passivation material (such as silicon nitride) can be formed on the second insulating layer 106 and on the source region 70 and the drain region 72. Figure 2G ​​​​As shown, a working window (or opening) 110 is formed through the second insulating layer 106 and the third insulating layer 108 to expose the first insulating layer 104. For example, the first insulating layer 104 is only partially exposed, that is, portions of the second insulating layer 106 and the third insulating layer 108 may remain on the first insulating layer 104 at their extreme portions along the X-axis. The working window 110 is formed at the location where the gate region 74 will be formed, specifically, it is formed at the location where the gate region 74 will be formed and in the region laterally to the gate region 74 along the X-axis.

[0086] The working window 110 is formed by selective chemical etching of the second insulating layer 106 and the third insulating layer 108 to expose the first insulating layer 104 without etching it. For example, the chemical etching can be based on BCl3 or performed using an ALE process and is carried out using a mask that exposes the area of ​​the second insulating layer 106 that will form the working window 110 and be removed after the etching step.

[0087] Subsequently, as Figure 2H As shown, a fourth insulating layer 112 of insulating material (such as tetraethyl orthosilicate (TEOS)) is formed on the third insulating layer 108 and the first insulating layer 104 exposed by the working window 110.

[0088] The fourth insulating layer 112 has a thickness along the Z-axis, which is between about 80 nm and about 350 nm, and is, for example, equal to about 150 nm. The fourth insulating layer 112 is formed, for example, by CVD, which is performed to deposit the fourth insulating layer 112 in a uniform manner as described above.

[0089] At the end of the manufacturing process, the fourth insulating layer 112 will be formed. Figure 1 The passivation layer 68 of the HEMT device 50.

[0090] Subsequently, as Figure 2I As shown, a gate window (or opening) 114 is formed through the fourth insulating layer 112 and the first insulating layer 104 to expose the dielectric protective layer 67 at the location where the gate region 74 will be formed. For example, the gate window 114 has a narrower width along the X-axis than the width of the previously described working window 110, such that portions of the fourth insulating layer 112 and the first insulating layer 104 can be held adjacent to the gate region 74 when formed.

[0091] The gate window 114 is formed by means of a selective chemical etching step of the fourth insulating layer 112 and of the first insulating layer 104, to expose the dielectric protection layer 67 without etching the dielectric protection layer 67 and thus exposing the underlying barrier layer 66. For example, considering the case in which the fourth insulating layer 112 and the first insulating layer 104 are of the same material and thus only one chemical etching is sufficient in this step, the chemical etching can be based on a fluorinated solvent or, in any case, on a chemical solvent configured to etch the material of the fourth insulating layer 112 and of the first insulating layer 104 without etching the material of the dielectric protection layer 67. For example, the chemical etching is performed using a mask that exposes the area of the fourth insulating layer 112 that will form the gate region 74 and that is removed after the etching step.

[0092] Subsequently, as shown in Figure 2J the gate region 74 is formed on the dielectric protection layer 67, in the gate window 114.

[0093] In particular, a mask that exposes the gate window 114 (and possibly also the area of the fourth insulating layer 112 contiguous to the gate window 114) is formed, covering the rest of the fourth insulating layer 112, then a metal deposition (for example, of a Ti / AlCu / TiN stack) is performed on the mask and in the gate window 114 (and possibly also on the area of the fourth insulating layer 112 exposed by the gate window 114), a removal of the mask and of the metal deposition present thereon is performed, and finally a thermal annealing (for example, at about 560°C) is performed. In particular, if the mask for the metal deposition exposes only the gate window 114, the gate region 74 will be aligned with the gate window 114 and thus will comprise only the surface portion 74A, while if the mask for the metal deposition also exposes the area of the fourth insulating layer 112 contiguous to the gate window 114, the gate region 74 will also extend on the fourth insulating layer 112 outside the gate window 114 and thus will comprise both the surface portion 74A and the upper portion 74B.

[0094] Further manufacturing steps of the HEMT device 50 can then be carried out, not shown and not described herein, as they are known (for example, formation of metallization layers, etc.).

[0095] The advantages provided by the present disclosure are evident from the examination of the features of the present disclosure made in accordance with the present disclosure.

[0096] In particular, the manufacturing process described previously allows the integration of the manufacturing of D-mode HEMTs and E-mode HEMTs with a pGaN gate structure, so that these two solutions are unified and thus reduce their complexity and manufacturing costs.

[0097] In fact, the dielectric protection layer 67 preventsFigure 2I The chemical etching in the surface 66A of the barrier layer 66 performed for forming the gate region 74 damages the barrier layer 66, introduces traps for the charge carriers of the barrier layer 66 and causes a degradation of the electrical performances of the HEMT device 50. However, the reduced thickness of the dielectric protection layer 67 does not make the manufacturing of the D-mode type HEMT device 50 incompatible with the manufacturing of the known E-mode HEMTs.

[0098] In detail, during the chemical etching of the barrier layer 66 Figure 2I The presence of the dielectric protection layer 67 during the chemical etching of the barrier layer 66 allows the threshold voltage of the HEMT device 50 to be stabilized, the gate leakage current under reverse bias conditions to be reduced and the on-resistance to be reduced. Moreover, the thickness of the dielectric protection layer 67 modifies the pinch-off voltage and therefore this parameter can be changed during the design step on the basis of the dielectric protection layer 67. In more detail, for a gate voltage lower than the pinch-off voltage, and the same pinch-off voltage, the drain leakage current decreases as the thickness of the dielectric protection layer 67 increases.

[0099] In more detail, it has been verified that these advantages can be achieved even if the dielectric protection layer 67 covers the only region of the barrier layer 66 located at the gate region 74 (for example, it is vertically aligned with the gate region 74).

[0100] In particular, the HEMT device 50 is particularly suitable for working at low power, i.e. with drain voltage values generally lower than or equal to about 12 V. This further simplifies the structure of the HEMT device 50, since in this case, for example, there can be no field plate.

[0101] Finally, it is clear that modifications and / or additions of parts of the disclosure herein described and illustrated can be made without thereby departing from the scope of the disclosure as defined in the appended claims.

[0102] For example, the different embodiments described can be combined with each other to provide other solutions.

[0103] Moreover, although Figures 2A-2J With reference to the manufacturing of the HEMT device 50 in depletion mode, the process described herein is compatible with the simultaneous manufacturing of at least one other HEMT device (also referred to as second device HEMT), in particular in enrichment mode and for example with a pGaN type gate structure, starting from the same work body 100.

[0104] Figure 3C An HEMT device 80 in enrichment mode is shown, obtained by means of the manufacturing process previously described and starting from the same work body 100 used for manufacturing the HEMT device 50. Therefore, the HEMT device 80 and the HEMT device 50 are integrated with each other and define a monolithic solution.

[0105] Specifically, HEMT device 80 and HEMT device 50 are included in electronic components (such as... Figure 4 In the figure (shown using reference numeral 90), the details of the electronic components are monolithic and formed starting from the working body 100, such that HEMT device 80 and HEMT device 50 share substrate 60 and heterostructure 62.

[0106] like Figure 4 As exemplarily shown, the depletion mode HEMT device 50 and the enrichment mode HEMT device 80 can be lateral to each other, for example, they are arranged side by side along the X-axis.

[0107] Specifically, the HEMT device 80 has a pGaN-type gate structure.

[0108] For reference Figures 3A-3C As shown, the fabrication of HEMT device 80 occurs by performing the same fabrication steps previously described, wherein, prior to the formation of dielectric layer 102, Figure 2A Local formation of a channel modulation region is added on the barrier layer 66. The channel modulation region is pGaN (e.g., gallium nitride with P-type conductivity due to magnesium doping).

[0109] The channel modulation region (such as) Figure 3A (As shown by reference numeral 130 in the accompanying drawings) it will be part of the gate structure 132 of the HEMT device 80 together with the gate region 74.

[0110] In detail, after execution Figure 2A Following the steps previously described, the channel modulation region 130 is formed. Figure 3A On the surface 66A of the barrier layer 66.

[0111] More specifically, this occurs by uniformly depositing a pGaN layer (not shown and having a thickness, for example, between about 30 nm and about 150 nm) on the surface 66A of the barrier layer 66. Subsequently, chemical etching is performed on the pGaN layer to place a portion thereon where the gate structure of the HEMT device 80 will form and thus the channel modulation region 130 will be formed, rather than removing the remaining portion of the pGaN layer that will not be part of the gate structure of the HEMT device 80. Specifically, this occurs by forming a mask on the pGaN layer, the mask covering the portion of the pGaN layer intended to form the channel modulation region 130 and exposing the remaining portion of the pGaN layer, performing etching using known techniques with the aid of the mask to remove the portion of the pGaN layer that will not be part of the gate structure, and finally removing the mask to obtain… Figure 3A The structure shown.

[0112] Subsequently, as Figure 3BAs shown, the dielectric layer 102 is formed in a manner similar to that previously described on both the channel modulation region 130 and the region of the barrier layer 66 exposed by the channel modulation region 130.

[0113] In the embodiment considered here, the dielectric layer 102 defines the dielectric protection layer 67.

[0114] Nevertheless and similarly to what was previously described, other steps can be performed to form the dielectric protection layer 67 starting from the dielectric layer 102. For example, in the case where the dielectric protection layer 67 extends only under the gate region 74 of the HEMT device 50, the formation of the dielectric layer 102 is followed by an etching which selectively removes the portions of the dielectric layer 102 which are not intended to be vertically aligned with the gate region 74 of the HEMT device 50, leaving conversely the portions of the dielectric layer 102 which are intended to be vertically aligned with the gate region 74 of the HEMT device 50 and thus form the dielectric protection layer 67.

[0115] Similarly, if it is desired to have a Schottky contact between the channel modulation region 130 and the gate region 74 of the HEMT device 80, this chemical etching can be used to remove only the portions of the dielectric layer 102 which extend over the channel modulation region 130.

[0116] Returning to Figure 3B the embodiment of FIG. 1, the steps are similar to those previously described with reference to Figures 2C-2J FIG. 2 and are therefore not described in detail, which leads to Figure 3C the structure of the HEMT device 80 shown in FIG. 1.

[0117] The HEMT device (50) is outlined as comprising: a heterostructure (62) comprising a channel layer (64) and a barrier layer (66), the barrier layer (66) extending onto the channel layer (64) along a first axis (Z); a dielectric protection layer (67) of a dielectric material, the dielectric protection layer (67) extending onto the barrier layer (66) along the first axis (Z); and a gate region (74) extending onto the dielectric protection layer (67) along the first axis (Z), wherein the dielectric protection layer (67) has a thickness (t d ) along the first axis (Z) which is less than 10 nm.

[0118] The thickness (t d ) of the dielectric protection layer (67) is between 1 nm and 7 nm.

[0119] The dielectric protection layer (67) is of one of the following materials: aluminum oxide, silicon oxide, silicon nitride and aluminum nitride.

[0120] The channel layer (64) is of gallium nitride or a gallium nitride-based alloy and the barrier layer (66) is of a gallium nitride-based alloy, in particular of AlGaN.

[0121] The dielectric protection layer (67) is directly interposed between the barrier layer (66) and the gate region (74) along the first axis (Z).

[0122] The HEMT device (50) is depletion mode.

[0123] The gate region (74) and the dielectric protection layer (67) form an insulated gate structure of the HEMT device (50).

[0124] The electronic assembly (90) is profiled to comprise a depletion mode HEMT device (50) and a further HEMT device (80) of enrichment mode integrated with each other.

[0125] The further HEMT device (80) has a pGaN type gate structure.

[0126] The process of manufacturing the HEMT device (50) comprising the heterostructure (62) is profiled to comprise a channel layer (64) and a barrier layer (66) extending on the channel layer (64) along a first axis (Z), the manufacturing process comprising the steps of: forming a dielectric protection layer (67) of dielectric material on the barrier layer (66); and forming a gate region (74) on the dielectric protection layer (67), wherein the dielectric protection layer (67) has a thickness (t d ) along the first axis (Z) of less than 10 nm.

[0127] The manufacturing process further comprises the steps of: forming a plurality of insulating layers (104, 106, 108, 112) on the dielectric protection layer (67); and forming a gate window (114) through the insulating layers (104, 106, 108, 112) to at least partially expose the dielectric protection layer (67), wherein the step of forming the gate region (74) occurs by means of the gate window (114).

[0128] The step of forming the gate window (114) comprises performing one or more chemical etchings configured to selectively remove at least a portion of the insulating layers (104, 106, 108, 112) without removing the dielectric protection layer (67).

[0129] The step of forming the insulating layers (104, 106, 108, 112) includes: forming a first insulating layer (104) of the insulating layers (104, 106, 108, 112) on the dielectric protection layer (67), the first insulating layer (104) being of insulating material; sequentially forming a second insulating layer (106) and a third insulating layer (108) of the insulating layers (104, 106, 108, 112) on the first insulating layer (104), the second insulating layer (106) and the third insulating layer (108) being of passivation material; forming a work window (110) through the second insulating layer (106) and the third insulating layer (108) to at least partially expose the first insulating layer (104); and forming a fourth insulating layer (112) of the insulating layers (104, 106, 108, 112) through the work window (110) and on the exposed first insulating layer (104), the fourth insulating layer (112) being of insulating material, wherein the step of forming the gate window (114) includes performing the one or more chemical etches configured to selectively remove the fourth insulating layer (112) and the first insulating layer (104) to at least partially expose the dielectric protection layer (67).

[0130] The manufacturing process further includes, between the step of forming the second insulating layer (106) and the step of forming the third insulating layer (108): a step of forming source and drain regions (70, 72) of the HEMT device (50) through the second insulating layer (106) and the barrier layer (66), and a step of forming the third insulating layer (108), the step of forming the third insulating layer (108) including forming the third insulating layer (108) on the second insulating layer (106), the source and drain regions (70, 72).

[0131] The manufacturing process further includes, before the step of forming the dielectric protection layer (67): a step of locally forming a channel modulation region (130) of pGaN on the barrier layer (66), the channel modulation region (130) being configured to be included in a gate structure (132) of a further HEMT device (80) transverse to the HEMT device (50); and the step of forming the dielectric protection layer (67), the step of forming the dielectric protection layer (67) including forming the dielectric protection layer (67) on the channel modulation region (130) and the barrier layer (66) exposed by the channel modulation region (130).

[0132] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified to adopt various concepts of the various patents, applications, and publications to provide further embodiments.

[0133] These and other alterations can be made to the embodiments in light of the above detailed description. In general, the terms used in the appended claims should not be construed to limit the claims of the application to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims should not be limited by the disclosure.

Claims

1. A high electron mobility transistor device, characterized by, comprising: a heterostructure including a channel layer and a barrier layer extending over a first surface of the channel layer; a dielectric protection layer extending over a first surface of the barrier layer, the first surface of the barrier layer opposing the channel layer along a first direction; a first conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction; and a gate region extending over the dielectric protection layer. The dielectric protection layer has a first thickness along the first direction that is less than 10 nm.

2. The high electron mobility transistor device of claim 1, wherein, The first thickness of the dielectric protection layer is in a range from 1 nm to 7 nm.

3. The high electron mobility transistor device of claim 2, wherein, The dielectric protection layer is directly between the barrier layer and the gate region.

4. The high electron mobility transistor device of claim 1, wherein, The high electron mobility transistor device is depletion mode.

5. The high electron mobility transistor device of claim 1, wherein, The gate region and the dielectric protection layer form an insulated gate structure of the high electron mobility transistor device.

6. The high electron mobility transistor device of claim 1, wherein, Further comprising a passivation layer over the dielectric protection layer, the passivation layer having a first gap along a second direction, the second direction being transverse to the first direction, the gate region being in the first gap.

7. The high electron mobility transistor device of claim 1, wherein, comprising:

8. An electronic device, comprising: a heterostructure including: a channel layer having a first surface; and a barrier layer over the first surface of the channel layer, the barrier layer having a first surface opposing the channel layer along a first direction; a dielectric protection layer over the first surface of the barrier layer; a first conductive terminal having a first surface opposing a second surface along the first direction, the first conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction; a gate region over the dielectric protection layer; and a passivation layer over the first surface of the barrier layer, the passivation layer including a first opening exposing the dielectric protection layer, the gate region being in the first opening, the passivation layer completely covering the first surface of the first conductive terminal. The second surface of the first conductive terminal is coplanar with the first surface of the channel layer.

9. The electronic device of claim 8, wherein, Further comprising a second conductive terminal extending completely through the dielectric protection layer and the barrier layer along the first direction.

10. The electronic device of claim 9, wherein, The passivation layer further includes:

11. The electronic device of claim 8, wherein, a first portion having a first depth along the first direction; and a second portion having a second depth along the first direction, the second depth being greater than the first depth. The gate region includes:

12. The electronic device of claim 11, wherein, a first portion having a first width along a second direction, the second direction being transverse to the first direction, the first portion being in direct contact with the first portion of the passivation layer; and a second portion having a second width along the second direction, the second width being greater than the first width, the second portion being physically separated from the second portion of the passivation layer along the second direction. ​

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