MOSFET chip structure and MOSFET chip for optical MOSFET relay
By optimizing the active and terminal regions of the MOSFET chip and adjusting the doping concentration and thickness, the problem of high on-resistance in the opto-MOS relay was solved, enabling its application in high-voltage fields and improving its economic efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2026-03-27
AI Technical Summary
The MOSFET chips in existing optical MOS relays have high on-resistance, which limits their application in high-voltage fields, and increasing the chip area to reduce on-resistance is not economical.
By increasing the active area of the MOSFET chip and optimizing parameters such as the terminal area and gate oxide thickness, the on-resistance can be reduced. Specific measures include adjusting the doping concentration and thickness range to ensure that the active area accounts for 70%-85% and the terminal area accounts for 15%-30%.
Without increasing chip area, it effectively reduces on-resistance, improves device efficiency, and achieves economic improvement.
Smart Images
Figure CN224054688U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of semiconductor device especially relates to a MOSFET chip structure and be used for light MOSFET relay's MOSFET chip. BACKGROUND
[0002] The MOSFET in the light MOS relay has the problem of large on-resistance (especially breakdown voltage > 400V), which limits the application of light MOS relay in high-voltage field; by increasing the MOSFET chip area, the on-resistance can be reduced, but it is not economical. SUMMARY
[0003] The technical problem to be solved by the embodiments of the utility model is that increasing the MOSFET chip area to reduce the on-resistance is not economical.
[0004] To solve the above problems, the embodiments of the utility model disclose a MOSFET chip structure and a MOSFET chip for light MOSFET relay. The active area is increased, and then the active area resistance is reduced, achieving the effect of reducing the MOSFET on-resistance.
[0005] On the one hand, the utility model provides a MOSFET chip structure, which comprises an active area and a terminal area; the terminal area surrounds the four sides of the active area; the proportion of the total area of the terminal area to the single chip area of the MOSFET chip is between 15% and 30%; the proportion of the total area of the active area to the single chip area of the MOSFET chip is between 70% and 85%.
[0006] Further technical solutions are that the active area comprises a drift region, a channel, a gate region, a gate oxide layer and at least two source regions; the gate region is arranged above the gate oxide layer, the gate oxide layer is arranged above the channel, the channel and all the source regions are arranged above the drift region respectively, and the channel is between the two source regions.
[0007] Further technical solutions are that the doping concentration of the channel ranges from 1E15 to 1E20.
[0008] Further technical solutions are that the thickness of the gate oxide layer ranges from 30nm to 75nm.
[0009] Further technical solutions are that the thickness of the drift region ranges from 0.3um to 1.0um.
[0010] Further technical solutions are that the utility model further comprises a semiconductor substrate, and the semiconductor substrate is arranged below the drift region.
[0011] Further, the technical scheme is that the MOSFET chip structure further comprises a drain, which is arranged below the semiconductor substrate.
[0012] Further, the technical scheme is that the proportion of the total area of the terminal region to the single chip area of the MOSFET chip is 15%, and the proportion of the total area of the active region to the single chip area of the MOSFET chip is 85%.
[0013] In another aspect, the utility model also provides a MOSFET chip for optical MOSFET relay, including the MOSFET chip structure as any one of the above embodiment.
[0014] Compared with the prior art, the technical effects that the utility model embodiment can achieve include:
[0015] Under the condition of the certain chip area, the terminal structure area is compressed, the active region area is expanded, and the on-resistance is reduced. DETAILED DESCRIPTION
[0016] In order to more clearly illustrate the technical scheme in the embodiment of the utility model, the drawings needed in the embodiment description will be briefly introduced, and obviously, the drawings in the following description are some embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained without creative labor.
[0017] Fig. 1 A MOSFET chip structure structure schematic view is provided for the embodiment of the utility model.
[0018] Fig. 2 Another MOSFET chip structure structure schematic view is provided for the embodiment of the utility model. DETAILED DESCRIPTION
[0019] The technical scheme in the embodiment will be clearly and completely described below in combination with the drawings in the embodiment of the utility model, and similar components in the drawings are represented by similar component numbers. Obviously, the following described embodiments are only some embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the utility model.
[0020] It should be understood that, when used in the specification and the appended claims, the terms "include" and "contain" indicate the existence of the described features, whole, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, whole, steps, operations, elements, components and / or their sets.
[0021] It should also be understood that the terminology used in this specification of embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the present invention. As used in this specification of embodiments of the present invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0022] See Figs. 1-2 This utility model provides a MOSFET chip structure. The MOSFET chip structure includes an active region and a termination region; the termination region surrounds the active region; the total area of the termination region accounts for 15%-30% of the area of a single MOSFET chip; the total area of the active region accounts for 70%-85% of the area of a single MOSFET chip. Specific descriptions of each component are as follows:
[0023] In this embodiment, the terminal structure area is compressed, the active area area is enlarged, and the on-resistance is reduced. Viewed from above, the MOSFET chip structure shows the terminal area surrounding the active area. The total area of the terminal area accounts for 15%-30% of the area of a single MOSFET chip; the total area of the active area accounts for 70%-85% of the area of a single MOSFET chip. The on-resistance R of the MOSFET is determined by the source region resistance R0. S Channel resistance R JFET Semiconductor substrate resistance R SUB Drift region resistance R DR p-based resistance R CH Composed of series, where R = R S +R JFET +R SUB +R DR +R CH .
[0024] See also Figs. 1-2 In this embodiment, the active region includes a drift region, a channel, a gate region, a gate oxide layer, and at least two source regions; the gate region is disposed above the gate oxide layer, the gate oxide layer is disposed above the channel, the channel and all the source regions are respectively disposed above the drift region, and the channel is between the two source regions.
[0025] Specifically, the doping type of the source region is the opposite of that of the drift region.
[0026] Furthermore, the doping concentration of the channel ranges from 1E15 to 1E20.
[0027] Specifically, the higher the doping concentration of the channel, the lower the channel resistance. Therefore, by increasing the doping concentration of the channel, the resistance R can be reduced.JFET , and thus the on-resistance is reduced.
[0028] Further, the thickness of the gate oxide layer is in the range of 30nm-75nm.
[0029] Specifically, by applying a voltage on the gate, the charge distribution of the semiconductor surface under the gate oxide layer can be changed, thus forming or eliminating the conductive channel, and thus controlling the current flow between the source and the drain. The thinned gate oxide thickness can improve the efficiency of the device, making the work efficiency of applying a voltage on the gate higher. In an embodiment, the thickness of the gate oxide layer is 50nm.
[0030] Further, the thickness of the drift region is in the range of 0.3um-1.0um.
[0031] Specifically, the smaller the thickness of the drift region, the smaller the resistance of the drift region, and the on-resistance R of the MOSFET is composed in series of the source region resistance R S , the channel resistance R JFET , the semiconductor substrate resistance R SUB , the drift region resistance R DR , and the p-substrate resistance R CH , where R=R S +R JFET +R SUB +R DR +R CH . In an embodiment, the thickness of the drift region is 0.5um.
[0032] Further, a semiconductor substrate is further included, which is arranged below the drift region.
[0033] Specifically, the semiconductor substrate is the basic material in the process of manufacturing semiconductor devices, which is usually a piece of specially treated single crystal material sheet, such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), etc. In this embodiment, the doping type of the source region is the same as that of the semiconductor substrate.
[0034] Further, a drain is further included, which is arranged below the semiconductor substrate.
[0035] Specifically, the drain in the MOSFET functions as the output end of the current, i.e. the current flows from the source to the drain through the channel.
[0036] Further, the proportion of the total area of the termination region to the single chip area of the MOSFET chip is 15%, and the proportion of the total area of the active region to the single chip area of the MOSFET chip is 85%.
[0037] Specifically, the MOSFET chip structure has an optimal conduction path when the active area proportion is 85% and the terminal area proportion is 15% in the MOSFET chip structure viewed from above, and the on-resistance can be reduced.
[0038] The utility model embodiment further provides a MOSFET chip for optical MOSFET relay, including the MOSFET chip structure as any one of the above embodiments.
[0039] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.
[0040] In the description of the utility model, it is understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the utility model.
[0041] In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the utility model, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0042] In the utility model, unless otherwise specifically defined and limited, the terms "installation", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be connected, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the communication or interaction relationship between two elements. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0043] In the present application, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can include the first and second features directly contacting, or the first and second features not directly contacting but contacting through another feature between them. Moreover, the first feature "on", "above" and "on top of" the second feature includes the first feature directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "underneath" the second feature includes the first feature directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.
[0044] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present application.
[0045] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, these modifications and variations of the present application are intended to be included within the scope of the claims of the present application and their equivalents. Therefore, the present application is intended to include these modifications and variations.
[0046] The above is a specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A MOSFET chip structure, characterized in that, Includes active area and terminal area; The terminal area surrounds the active area; The total area of the terminal area accounts for 15%-30% of the area of a single MOSFET chip; The ratio of the total area of the active region to the area of a single MOSFET chip is between 70% and 85%. The active region includes a drift region, a channel, a gate region, a gate oxide layer, and at least two source regions; the gate region is disposed above the gate oxide layer, the gate oxide layer is disposed above the channel, the channel and all the source regions are respectively disposed above the drift region, and the channel is between the two source regions.
2. The MOSFET chip structure according to claim 1, characterized in that, The thickness of the gate oxide layer ranges from 30 nm to 75 nm.
3. The MOSFET chip structure according to claim 1, characterized in that, The thickness of the drift region ranges from 0.3 μm to 1.0 μm.
4. The MOSFET chip structure according to claim 1, characterized in that, It also includes a semiconductor substrate disposed below the drift region.
5. The MOSFET chip structure according to claim 4, characterized in that, It also includes a drain electrode, which is disposed below the semiconductor substrate.
6. The MOSFET chip structure according to claim 1, characterized in that, The total area of the terminal region accounts for 15% of the area of a single MOSFET chip, and the total area of the active region accounts for 85% of the area of a single MOSFET chip.
7. A MOSFET chip for use in an optical MOSFET relay, characterized in that, Including the MOSFET chip structure as described in any one of claims 1-6.