Low-internal-resistance MOS packaging structure

Abstract

The utility model discloses a low-internal-resistance MOS packaging structure, and belongs to the field of integrated circuits, the low-internal-resistance MOS packaging structure comprises a substrate and an MOS chip, the top of the substrate is symmetrically and fixedly provided with four contact electrodes, the top of the substrate is symmetrically provided with four jacks, the outer side of the MOS chip is symmetrically and fixedly provided with four pins, the inner wall of the substrate is slidably connected with a raised line in an inserted mode, and the raised line is connected with the contact electrodes in an inserted mode. A conduction plate is fixedly installed at the bottom of the protruding strip, two heat dissipation plates are installed at the bottom of the conduction plate, and fixing plates are installed on the outer sides of the two heat dissipation plates. By arranging the substrate, the contact electrode and the MOS chip, current flows to the substrate from the MOS chip through the contact electrode, due to the low resistance characteristic of the contact electrode, energy loss is reduced, the contact resistance of the MOS chip structure is remarkably reduced, and the current bearing capacity is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a low-internal-resistance MOS packaging structure. BACKGROUND

[0002] With the development of electronic devices towards high power and high efficiency, the current carrying capacity and internal resistance of semiconductor devices become key performance indicators. At present, MOS (Metal Oxide Semiconductor) devices are widely used in power electronics due to their fast switching speed and low power consumption.

[0003] However, the traditional MOS packaging structure has the problem of high internal resistance under high current conditions, which leads to serious device heating and efficiency reduction, limiting its further development in high power applications. CONTENT OF THE INVENTION

[0004] In view of the shortcomings of the prior art, the present application provides a low-internal-resistance MOS packaging structure, which overcomes the shortcomings of the prior art and aims to solve the problems in the background art.

[0005] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows: a low-internal-resistance MOS packaging structure, comprising a substrate and a MOS chip, the top of the substrate is symmetrically fixedly installed with four contact electrodes, the top of the substrate is symmetrically provided with four insertion holes, the outer side of the MOS chip is symmetrically fixedly installed with four pins, the inner wall of the substrate is slidably inserted with a protrusion, the bottom of the protrusion is fixedly installed with a conductive plate, the bottom of the conductive plate is installed with two heat sinks, and the outer side of the two heat sinks is installed with a fixed plate.

[0006] As a preferred embodiment, the bottom of the four pins is inserted into the inner wall of the four insertion holes, and the outer wall of the four pins is fitted with the outer wall of the contact electrode.

[0007] By adopting the above technical scheme, the pins can be stably installed and welded on the inner wall of the insertion hole and fixedly connected with the contact electrode, so that the MOS chip can be stably installed on the top of the substrate.

[0008] As a preferred embodiment, the inner wall of the substrate is symmetrically provided with two insertion grooves adapted to the protrusion, and the protrusion is inserted into the inner wall of the insertion groove.

[0009] By adopting the above technical scheme, the substrate and the conductive plate can be stably connected, ensuring that they will not be easily detached after installation.

[0010] As a preferred embodiment, the outer side of the fixed plate is symmetrically fixedly installed with four soldering lugs, and the inner wall of the four soldering lugs is provided with a soldering hole, and the inner wall of the soldering hole is soldered with a soldering paste.

[0011] By adopting the technical scheme, the fixing plate can be stably installed at the bottom of the conducting plate, so that the fixing plate cannot be easily separated and the tin paste cannot protrude outward, thereby ensuring the appearance beauty.

[0012] As a preferred embodiment, the fixing plate is a galvanized stainless steel plate.

[0013] By adopting the technical scheme, the fixing plate cannot be easily rusted, thereby ensuring the durability.

[0014] As a preferred embodiment, the top of the conducting plate is tightly attached to the bottom of the substrate, and the conducting plate is made of copper.

[0015] By adopting the technical scheme, the heat of the substrate and the MOS chip can be completely adsorbed, thereby achieving the heat dissipation effect.

[0016] The beneficial effects of the present application are as follows:

[0017] The low-internal-resistance MOS packaging structure is provided with a substrate, a contact electrode and a MOS chip, so that the current flows from the MOS chip to the substrate through the contact electrode. Due to the low-resistance characteristic of the contact electrode, the energy loss is reduced, the contact resistance of the MOS chip structure is significantly reduced, and the current carrying capacity is improved.

[0018] The low-internal-resistance MOS packaging structure effectively disperses the generated heat through the fixing plate, thereby ensuring the stable operation of the system. DETAILED DESCRIPTION

[0019] Figure 1 The figure is a schematic diagram of the overall structure of the present application;

[0020] Figure 2 The figure is a schematic diagram of the expanded structure of the present application;

[0021] Figure 3 The figure is a schematic diagram of the cross-sectional structure of the substrate of the present application;

[0022] Figure 4 The figure is a schematic diagram of the cross-sectional structure of the conducting plate of the present application.

[0023] In the figure, 1 is a substrate, 2 is a contact electrode, 3 is a hole, 4 is a MOS chip, 5 is a pin, 6 is a protruding strip, 7 is a conducting plate, 8 is a heat dissipation plate, 9 is a fixing plate, 10 is a solder ear, and 11 is a solder hole. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0025] Referring to Figures 1-4 A low-resistance MOS packaging structure, comprising a substrate 1 and a MOS chip 4, four contact electrodes 2 are symmetrically and fixedly installed on the top of the substrate 1, four insertion holes 3 are symmetrically and formed on the top of the substrate 1, four pins 5 are symmetrically and fixedly installed on the outer side of the MOS chip 4, a convex strip 6 is slidably inserted into the inner wall of the substrate 1, a conductive plate 7 is fixedly installed on the bottom of the convex strip 6, two heat dissipation plates 8 are installed on the bottom of the conductive plate 7, and a fixed plate 9 is installed on the outer side of the two heat dissipation plates 8.

[0026] Referring to Figure 1 - Figure 3 The bottom of the four pins 5 is inserted into the inner wall of the four insertion holes 3, and the outer wall of the four pins 5 is in close contact with the outer wall of the contact electrodes 2, so that the pins 5 can be stably installed and welded on the inner wall of the insertion holes 3 and fixedly connected with the contact electrodes 2, thereby stably installing the MOS chip 4 on the top of the substrate 1.

[0027] Referring to Figure 3 The inner wall of the substrate 1 is symmetrically formed with two insertion grooves adapted to the convex strip 6, and the convex strip 6 is inserted into the inner wall of the insertion grooves, so that the substrate 1 and the conductive plate 7 can be stably connected, and the substrate 1 will not be easily detached after installation.

[0028] Referring to Figure 4 The outer side of the fixed plate 9 is symmetrically and fixedly installed with four soldering lugs 10, and the inner wall of each of the four soldering lugs 10 is formed with a soldering hole 11, and the inner wall of the soldering hole 11 is soldered with solder paste, so that the fixed plate 9 can be stably installed on the bottom of the conductive plate 7, and the solder paste will not be easily detached and will not protrude on the outside, and the appearance will be beautiful.

[0029] Referring to Figure 4 The fixed plate 9 is a galvanized stainless steel plate, so that the fixed plate 9 will not be easily rusted, and the durability is ensured.

[0030] Referring to Figure 3 and Figure 4 The top of the conductive plate 7 is in close contact with the bottom of the substrate 1, and the conductive plate 7 is made of copper material, so that the heat of the substrate 1 and the MOS chip 4 can be completely absorbed, and the heat dissipation effect is achieved.

[0031] Working principle: when using the device, first take MOS chip 4 and insert pin 5 into the inner wall of socket 3, and the outer wall is attached to the outside of contact electrode 2, then the substrate 1 and pin 5 can be welded and connected, at the same time, the convex strip 6 on the top of the conducting plate 7 can be inserted into the inner wall of the insertion slot, so that the substrate 1 and the conducting plate 7 can be stably connected, which can ensure that it will not be easily separated after installation, at the same time, two heat sinks 8 can be installed on the bottom of the substrate 1, and the fixed plate 9 can be covered on the outside of the two heat sinks 8, and the solder paste can be soldered to the inner wall of the soldering lug 10, which can position the fixed plate 9 and ensure that the heat sink 8 can be stably arranged in the middle position of the conducting plate 7 and the fixed plate 9.

[0032] In the description of the present application, it should be pointed out that the terms "upper", "lower", "inner", "outer", "front end", "rear end", "two ends", "one end", "the other end" and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, therefore it cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0033] In the description of the present application, it should be pointed out that, unless otherwise specified and limited, the terms "installation", "provided with", "connection" and the like should be understood broadly, for example, "connection" can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through intermediate medium, can be the communication between two elements. For ordinary skilled persons in the art, the specific meaning of the above terms in the present application can be understood according to the specific situation.

[0034] The present application has been described above in combination with specific embodiments, but those skilled in the art should understand that these descriptions are exemplary and not a limitation on the scope of protection of the present application. Those skilled in the art can make various modifications and changes to the present application according to the spirit and principles of the present application, and these modifications and changes are also within the scope of the present application.

Claims

1. A low-internal-resistance MOS package structure comprising a substrate (1) and a MOS chip (4), characterized in that, The top of the substrate (1) is symmetrically fixed with four contact electrodes (2), the top of the substrate (1) is symmetrically provided with four insertion holes (3), the outer side of the MOS chip (4) is symmetrically fixed with four pins (5), the inner wall of the substrate (1) is slidably inserted with a convex strip (6), the bottom of the convex strip (6) is fixed with a conducting plate (7), the bottom of the conducting plate (7) is provided with two heat dissipation plates (8), and the outer side of the two heat dissipation plates (8) is provided with a fixed plate (9).

2. The low-internal-resistance MOS package structure according to claim 1, wherein, The bottom of the four pins (5) is inserted into the inner wall of the four insertion holes (3), and the outer wall of the four pins (5) is in close contact with the outer wall of the contact electrode (2).

3. The low-impedance MOS package structure of claim 1, wherein, The inner wall of the substrate (1) is symmetrically provided with two insertion grooves matched with the convex strip (6), and the convex strip (6) is inserted into the inner wall of the insertion groove.

4. The low-impedance MOS package structure of claim 1, wherein, The outer side of the fixed plate (9) is symmetrically fixed with four solder ears (10), and the inner wall of the four solder ears (10) is provided with a solder hole (11), and the inner wall of the solder hole (11) is soldered with solder paste.

5. The low-impedance MOS package structure of claim 1, wherein, The fixed plate (9) is a galvanized stainless steel plate.

6. The low-impedance MOS package structure of claim 1, wherein, The top of the conducting plate (7) is in close contact with the bottom of the substrate (1), and the conducting plate (7) is made of copper.

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