Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure. The semiconductor structure comprises a first semiconductor tube core, a second semiconductor tube core and an insulating encapsulation body, wherein the second semiconductor tube core is arranged below the first semiconductor tube core and is jointed to the first semiconductor tube core; the insulating encapsulation body is arranged above the second semiconductor tube core; the first semiconductor die includes a semiconductor substrate and an interconnect structure under the semiconductor substrate. A maximum lateral size of the semiconductor substrate of the first semiconductor die is smaller than a maximum lateral size of the second semiconductor die. An insulating encapsulation at least laterally surrounds the semiconductor substrate of the first semiconductor die, thereby providing a semiconductor structure with reduced stress and improved bond integrity.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor structures, and more particularly, to semiconductor structures including bonded dies of different lateral sizes. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to advances in technology, which have resulted in an increase in the complexity of semiconductor devices and processes used to manufacture them. This increase in complexity has led to a steady decrease in minimum feature sizes, which allows more components to be integrated into a given area. As a result, the industry has moved toward smaller and more complex devices. The industry continues to seek improved mechanisms for forming semiconductor structures with improved electrical performance. SUMMARY

[0003] Embodiments of the present application provide a semiconductor structure including a first semiconductor die, a second semiconductor die under and bonded to the first semiconductor die, and an insulative encapsulation disposed over the second semiconductor die, the first semiconductor die including a semiconductor substrate and an interconnect structure under the semiconductor substrate, a maximum lateral size of the semiconductor substrate of the first semiconductor die being less than a maximum lateral size of the second semiconductor die, the insulative encapsulation at least laterally surrounding the semiconductor substrate of the first semiconductor die.

[0004] Embodiments of the present application provide a semiconductor structure including a first semiconductor die, a second semiconductor die under and bonded to the first semiconductor die, and an insulative encapsulation disposed over the second semiconductor die, the first semiconductor die including a functional region, a seal ring region surrounding the functional region, and a peripheral region surrounding the seal ring region, the peripheral region of the first semiconductor die being in physical contact with the insulative encapsulation and including sidewalls that are substantially aligned with sidewalls of the second semiconductor die.

[0005] Based on the foregoing, embodiments of the present application provide a semiconductor structure that removes a portion of a first semiconductor die prior to forming an insulative encapsulation, the portion corresponding to a non-functional (or peripheral) region of a bonded structure. This can help reduce the risk of delamination propagation during insulative encapsulation formation. According to some embodiments, a portion of a bonded structure having an unbonded region is removed prior to forming an insulative encapsulation. In this manner, the possibility of delamination propagation is eliminated. Semiconductor structures with reduced defects, improved reliability, and improved yield can be realized. Accordingly, various embodiments provide semiconductor structures with reduced stress and improved bonding integrity.

[0006] In order to make the above features and advantages of the embodiments of the present application more apparent, the following embodiments are described in detail, and the accompanying drawings are referred to, and the detailed description is given as follows. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1A A schematic cross-sectional view of a first semiconductor die is shown, in accordance with some embodiments.

[0008] FIG. 1B A schematic cross-sectional view of a semiconductor wafer is shown, in accordance with some embodiments.

[0009] FIGS. 2A-2F Schematic cross-sectional views of intermediate steps during a process of forming an integrated circuit package including a semiconductor structure, in accordance with some embodiments, are shown.

[0010] FIG. 3A And FIG. 3B A schematic cross-sectional view of a variant of a semiconductor structure, in accordance with some embodiments, is shown.

[0011] FIGS. 4A-4C Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure, in accordance with some embodiments, are shown.

[0012] FIG. 5A A schematic cross-sectional view of a first semiconductor die is shown, in accordance with some embodiments.

[0013] FIGS. 5B-5E Schematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure, in accordance with some embodiments, are shown.

[0014] FIG. 6 A schematic cross-sectional view of a semiconductor structure, in accordance with some embodiments, is shown.

[0015] BRIEF DESCRIPTION OF DRAWINGS

[0016] 10A, 10B, 10C, 10D, 10E, 10F: semiconductor structure; 20: packaging substrate; 30: IC package; 101, 101', 101", 201, 301, 301': first level; 102: second level; 110, 110', 110", 110'-1, 110'-2, 210, 210', 210": first semiconductor die; 110A: functional region; 110F, 111a, 121a, 1200F: front side; 110G', 110G'-1, 110G'-2: ledge portion; 110P, 210P: peripheral region; 110PL, LG1, LG1', LY1, LZ1: lateral dimension; 110P': remaining peripheral region; 110S: seal ring region; 110W: continuous sidewall; 110X, 210X, 3321, 3321': first portion; 110Y, 110Y', 210Y, 210Y', 3322: second portion; 110YW, 110YW', 110YW', 113W', 114W', 120W, 132W, 232W, 1131V', 1151W: singulated sidewall; 110Z, 210Z: third portion; 111, 111-1, 111': first semiconductor substrate; 111V', 111W, 1131W, 1131W', 1131W", 1141W: sidewall; 111b, 121b: backside; 112: first device; 113, 113', 113'-1, 113", 113"-1: first interconnect structure; 114: first bonding structure; 115: seal ring; 120, 120': second semiconductor die; 120R: recess; 121: second semiconductor substrate; 121W, 123W1, 150W: outer sidewall; 123, 123': second interconnect structure; 123V1, 123V2, 124V1, 124V2: inner sidewall; 124, 124': second bonding structure; 125: via / TSV; 125a: first end; 125b: second end; 132, 232, 232', 332, 332', 332": insulative encapsulation; 132', 132'-1: singulated insulative encapsulation; 142: conductive terminal; 150: rewire structure; 151: dielectric layer; 152: conductive pattern; 202: substrate / second level; 204: contact pad; 206: underfill; 210G1: first ledge; 210G2: second ledge; 210W: fourth portion; 232t, 332t, 1241t: top surface; 1131, 1131', 1131", 1131"-1: first dielectric layer; 1131U: upper surface / first surface / surface; 1131U', 1151U', 1231t: upper surface / surface; 1131W1: first sidewall; 1131t: second surface; 1132: first metallization pattern; 1141: first bonding dielectric layer;1141t, 1142t, 1241t, 1242t: top surface; 1142: first bonding connection; 1142D, 1242D: additional bonding connection; 1151, 1151': additional sealing ring; 1200, 1200': semiconductor wafer; 1231, 1231': second dielectric layer; 1232: second metallization pattern; 1241, 1241': second bonding dielectric layer; 1242: second bonding connection; IF10, IF10', IF20: bonding interface; LM2: maximum lateral size; LX1: lateral size / maximum lateral size; NB1: un-bonded region; SL1: scribe lane. DETAILED DESCRIPTION

[0017] The following disclosure provides different embodiments or examples for implementing various features of the present disclosure. Specific examples of structures and arrangements are presented in order to provide a thorough description of the present disclosure. Of course, these are merely examples and are in no way limiting of the scope of this disclosure. For example, in the following description, a first feature formed "on" or "above" a second feature can include embodiments where the first feature is formed directly on the second feature or where the first feature is formed indirectly on the second feature with intervening features being formed therebetween. Additionally, the present disclosure can use the same or similar reference numerals for the same or similar components or features in various examples.

[0018] Also, for ease of explanation, spatial relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Embodiments discussed herein are directed to providing various semiconductor structures and methods of forming the same. For example, a semiconductor structure is formed by bonding a first semiconductor die to a second semiconductor die and forming an insulating encapsulation over the second semiconductor die to surround the first semiconductor die. Internal stresses arise from differences in thermal expansion between the first and second semiconductor dies and the insulating encapsulation. The differences in thermal expansion are due to differences in the coefficients of thermal expansion (CTEs) of the materials between the first and second semiconductor dies and the insulating encapsulation. Additionally, the large CTE mismatch between the insulating encapsulation, the first and second semiconductor dies creates stresses in the semiconductor structure, particularly at the bonding interface of the first and second semiconductor dies. During formation of the insulating encapsulation, delamination can occur in the bonded structure or can be made worse in the bonded structure. For example, delamination propagates from a non-functional (or peripheral) region of the bonded structure to a functional (or central) region of the bonded structure, and such propagation can result in device failure.

[0020] According to some embodiments, a portion of the first semiconductor die is removed prior to forming the insulating encapsulation, the portion corresponding to a non-functional (or peripheral) region of the bonded structure. This can help reduce the risk of delamination propagation during formation of the insulating encapsulation. According to some embodiments, a portion of the bonded structure having an unbonded region is removed prior to forming the insulating encapsulation. In this way, the possibility of delamination propagation is eliminated. Semiconductor structures with reduced defects, improved reliability, and improved yield can be realized. Accordingly, various embodiments provide semiconductor structures with reduced stresses and improved bonding integrity.

[0021] FIG. 1A A schematic cross-sectional view of a first semiconductor die is shown in accordance with some embodiments. It should be noted that FIG. 1A is provided for illustrative purposes only, and according to some embodiments, the first semiconductor die can use fewer or additional components. Reference is made to FIG. 1AA first semiconductor die 110 can be provided. The first semiconductor die 110 can be formed in a wafer (not shown) that can include different die regions that are singulated in subsequent steps to form a plurality of first semiconductor dies 110. The first semiconductor die 110 can be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), a combination thereof (e.g., a system-on-a-chip (SoC) die), or the like.

[0022] In some embodiments, the first semiconductor die 110 includes a first semiconductor substrate 111, a first device 112 formed in / on the first semiconductor substrate 111, a first interconnect structure 113 formed over the first semiconductor substrate 111 and electrically coupled to the first device 112, and a first bonding structure 114 formed over the first interconnect structure 113 and electrically coupled to the first interconnect structure 113. The first semiconductor substrate 111 can be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. The first semiconductor substrate 111 can include other semiconductor materials (e.g., germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide indium phosphide), or combinations thereof. Other suitable substrates can be used, such as a multilayer substrate or a graded substrate.

[0023] The first semiconductor substrate 111 can include a front side 111a and a back side 111b opposite the front side 111a. For example, a first device 112 is formed at the front side 111a of the first semiconductor substrate 111. The first device 112 can include active devices (e.g., transistors, diodes, etc.), passive devices (e.g., capacitors, resistors, sensors, etc.), combinations thereof, or the like. While a single first device 112 is illustratively shown in the first semiconductor die 110, it should be noted that the number and type of the first devices 112 can be different from what is shown.

[0024] With continued reference to FIG. 1A The first interconnect structure 113 can be formed over the front side 111a of the first semiconductor substrate 111 and electrically coupled to the first device 112 to form an integrated circuit. The first interconnect structure 113 can include one or more first dielectric layers 1131 and first metallization patterns 1132 embedded in the first dielectric layers 1131. The material of the first dielectric layers 1131 can include oxide (e.g., silicon oxide or aluminum oxide), nitride (e.g., silicon nitride), carbide (e.g., silicon carbide), the like, or combinations thereof. The respective first metallization patterns 1132 can include conductive pads, wires, vias, combinations thereof, and / or the like. The respective first metallization patterns 1132 can be formed of a conductive material such as copper, cobalt, aluminum, gold, combinations thereof, or the like. It should be noted that the first dielectric layers 1131 and the first metallization patterns 1132 can have different configurations than what is shown.

[0025] In some embodiments, the first bonding structure 114 includes one or more first bonding dielectric layers 1141 and first bonding connections 1142 embedded in the first bonding dielectric layers 1141. The first bonding dielectric layers 1141 can be formed of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, and / or the like. The first bonding connections 1142 can be formed of a conductive material such as copper, aluminum, or the like. The respective first bonding connections 1142 can be conductive pads, vias, combinations thereof, and / or the like. In some embodiments, the first bonding connections 1142 are electrically connected to the first metallization patterns 1132 of the first interconnect structure 113. It should be noted that the first bonding dielectric layers 1141 and the first bonding connections 1142 can have different configurations / profiles than what is shown. In some embodiments, a planarization process (e.g., a chemical mechanical polish (CMP) process, a lapping process, an etching process, combinations thereof, or the like) is performed such that the top surfaces (1141t and 1142t) of the first bonding dielectric layers 1141 and the first bonding connections 1142 are substantially flush (or coplanar) within a process variation range.

[0026] With continued reference to FIG. 1AThe first semiconductor die 110 can include a functional (or active) region 110A, a seal ring region 110S surrounding the functional region 110A, and a peripheral region 110P surrounding the seal ring region 110S. For example, the seal ring region 110S is between the functional region 110A and the peripheral region 110P. In some embodiments, the peripheral region 110P is considered a street region. In some embodiments, the first device 112, the first metallization pattern 1132, and the first bond connection 1142 are within the functional region 110A. In some embodiments, the first bond dielectric layer 1141 and the first dielectric layer 1131 both extend across the functional region 110A and the seal ring region 110S and the peripheral region 110P.

[0027] In some embodiments, one or more seal rings 115 can be embedded in the first dielectric layer 1131 and within the seal ring region 110S. In some embodiments, a respective seal ring 115 is disposed around a turn of the first metallization pattern 1132 in the functional region 110A. The seal ring 115 can include a via and electrically conductive pads vertically stacked and connected together through the via, where the electrically conductive pads of the seal ring 115 can be at the same level as the electrically conductive pads of the first metallization pattern 1132, and the via of the seal ring 115 can be at the same level as the via of the first metallization pattern 1132. It is noted that the seal ring 115 can have a different configuration than shown.

[0028] In some embodiments, the first bond structure 114 includes additional bond connections 1142D embedded in the first bond dielectric layer 1141 and disposed on top of the seal ring 115 within the seal ring region 110S. The additional bond connections 1142D can be formed at the same level as the first bond connections 1142. In some embodiments, the additional bond connections 1142D are electrically and spatially isolated from the seal ring 115 by at least the first bond dielectric layer 1141. Alternatively, the additional bond connections 1142D are physically connected to the underlying seal ring 115. In some embodiments, the additional bond connections 1142D are dummy connections and electrically float in the first semiconductor die 110. For example, the presence of the additional bond connections 1142D helps to increase pattern uniformity and metal density, which facilitates subsequent bonding processes. Alternatively, the additional bond connections 1142D are omitted and no electrically conductive features are formed on top of the seal ring 115 within the seal ring region 110S.

[0029] Still referring to FIG. 1AAn additional sealing ring 1151 may be embedded in the first dielectric layer 1131 and within the peripheral region 110P. The additional sealing ring 1151 may be formed at the same level as the sealing ring 115. It should be noted that the additional sealing ring 1151 may have a different configuration than shown. In some embodiments, an additional engagement connector 1142D is distributed within the peripheral region 110P and above the additional sealing ring 1151. The additional engagement connector 1142D may be electrically and spatially isolated from the additional sealing ring 1151 at least through the first engagement dielectric layer 1141. The additional engagement connector 1142D may (or may not) be physically connected to the additional sealing ring 1151. Alternatively, the additional sealing ring 1151 and / or the additional engagement connector 1142D disposed within the peripheral region 110P may be omitted. The first semiconductor die 110 may (or may not) include any metallization pattern and / or any conductive features outside the sealing ring 115 (e.g., within the peripheral region 110P).

[0030] FIG. 1B A schematic cross-sectional view of a semiconductor wafer according to some embodiments is shown. It should be noted that... FIG. 1B For illustrative purposes only, and according to some embodiments, the semiconductor wafer may use fewer or additional components. See also... FIG. 1B A semiconductor wafer 1200 may be provided. The semiconductor wafer 1200 may include a second semiconductor substrate 121 having a front side 121a and a back side 121b, a second interconnect structure 123 formed on the front side 121a of the second semiconductor substrate 121, a second bonding structure 124 formed on the second interconnect structure 123, and a through hole 125 formed in the second semiconductor substrate 121 and extending into the second interconnect structure 123.

[0031] The second semiconductor substrate 121 may be a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, or the like. The material of the second semiconductor substrate 121 may be selected from the materials used to form the substrate. FIG. 1A The same set of candidate materials as the first semiconductor substrate 111 discussed herein. The second semiconductor substrate 121 may be doped or undoped. In some embodiments, the semiconductor wafer 1200 does not have active / passive devices, and the second semiconductor substrate 121 does not include active / passive devices formed on the front side 121a. In some embodiments, a second device (e.g., a transistor, diode, capacitor, resistor, sensor, combination thereof, and / or the like; not shown) is formed on the front side 121a of the second semiconductor substrate 121. The second interconnect structure 123 may include one or more second dielectric layers 1231 and a second metallization pattern 1232 embedded in the second dielectric layer 1231. The second dielectric layer 1231 and the second metallization pattern 1232 may be respectively connected to FIG. 1AThe first dielectric layer 1131 and the first metallization pattern 1132 are similar, and thus are not repeated here.

[0032] The second bonding structure 124 can be formed over and electrically connected to the second interconnect structure 123. For example, the second bonding structure 124 includes one or more second bonding dielectric layers 1241 and second bonding connections 1242 embedded in the second bonding dielectric layers 1241. The second bonding connections 1242 can be electrically connected to the second metallization pattern 1232. The second bonding dielectric layers 1241 and the second bonding connections 1242 can be similar to the first bonding dielectric layers 1141 and the first bonding connections 1142, respectively. FIG. 1A The first bonding dielectric layer 1141 and the first bonding connection 1142 are similar, and thus are not repeated here. In some embodiments, the second bonding structure 124 includes an additional bonding connection 1242D embedded in the second bonding dielectric layer 1241. The additional bonding connection 1242D can be formed at the same level as the second bonding connection 1242. In some embodiments, the additional bonding connection 1242D is a dummy connection and is electrically isolated from the second bonding connection 1242. The additional bonding connection 1242D can be electrically floating in the semiconductor wafer 1200. In some embodiments, the additional bonding connection 1242D is subsequently bonded to an additional bonding connection 1142D of the first semiconductor die 110. A planarization process (e.g., a CMP process, a grinding process, an etching process, a combination thereof, or the like) can optionally be performed on the second bonding structure 124 such that the top surfaces (1241t and 1242t) of the second bonding dielectric layer 1241, the second bonding connection 1242, and the additional bonding connection 1142D are substantially planar (or coplanar) within a process variation range.

[0033] The via 125 can be formed in the second semiconductor substrate 121 by depositing one or more diffusion barrier or isolation layers, depositing a seed layer, and depositing a conductive material (e.g., tungsten, titanium, aluminum, copper, any combination thereof, and / or the like) into the trench of the second semiconductor substrate 121. For example, the respective via 125 includes a first end 125a physically and electrically connected to one of the second metallization patterns 1232 and a second end 125b opposite the first end 125a, where the second end 125b can be buried in the second semiconductor substrate 121 at this stage.

[0034] FIGS. 2A-2F schematics of intermediate steps during a process of forming an integrated circuit (IC) package including a semiconductor structure, in accordance with some embodiments. Unless otherwise noted, the first semiconductor die 110 and the semiconductor wafer 1200 in these embodiments are substantially similar to those in FIGS. 1A-1BSimilar components in the illustrated embodiments are identified by like reference numerals. Details regarding the first semiconductor die 110 and the semiconductor wafer 1200 can be found in the discussion of the previous embodiments.

[0035] Referring to FIG. 2A and referring to FIGS. 1A-1B , the first semiconductor die 110 can be bonded to the semiconductor wafer 1200. While a single first semiconductor die 110 is shown, any number of first semiconductor dies 110 can be bonded to the semiconductor wafer 1200. In some embodiments, the first semiconductor die 110 and the semiconductor wafer 1200 are directly bonded in a face-to-face manner by dielectric-to-dielectric bonding and metal-to-metal bonding. For example, the front side 110F of the first semiconductor die 110 is bonded to the front side 1200F of the semiconductor wafer 1200. In some embodiments, the first bonding dielectric layer 1141 is fused to the second bonding dielectric layer 1241 by dielectric-to-dielectric bonding, and a dielectric-to-dielectric (e.g., oxide-to-oxide) bond can be formed therebetween. The first bonding connection 1142 can be directly bonded to the second bonding connection 1242 by metal-to-metal bonding, and a metal-to-metal (e.g., copper-to-copper) bond can be formed therebetween. In some embodiments, a dielectric-to-metal (e.g., oxide-to-copper; not shown separately) bond is formed at the bonding interface IF10 of the first semiconductor die 110 and the semiconductor wafer 1200. In some embodiments, the bonding interface IF10 has no solder material. The bonding interface IF10 can be substantially flat and planar within a process variation range.

[0036] In some embodiments, the bonding of the first semiconductor die 110 and the semiconductor wafer 1200 includes a pre-bonding process and an annealing process. During the pre-bonding process, a force can be applied to press the first semiconductor die 110 towards the semiconductor wafer 1200. The bonding strength of the first and second bonding dielectric layers (1141 and 1241) can be improved in the annealing process, in which the first and second bonding dielectric layers (1141 and 1241) are annealed at a high temperature. In some embodiments, after the bonding process, the first and second bonding connections (1142 and 1242) are directly connected to each other in a one-to-one manner. In some embodiments, additional bonding connections (1142D and 1242D) are directly bonded to each other in a one-to-one manner.

[0037] It should be understood that an issue affecting the electrical reliability of the bonded structure is the adhesive force between the first semiconductor die 110 and the semiconductor wafer 1200. Poor adhesion can lead to delamination. In some cases, during the bonding process, at the annealing temperature, the first and second bonding connections may expand and exert stress on the surrounding first and second bonding dielectric layers, resulting in delamination. For example, after the bonding process, an unbonded region NB1 exists at the bonding interface IF10 (e.g., corresponding to the peripheral region 110P). During subsequent processing steps (e.g.) FIG. 2C As described in the formation of the insulating encapsulation, a large CTE mismatch between the insulating encapsulation and the semiconductor die / wafer can generate stress in the resulting structure, particularly at the interface between the insulating encapsulation and the semiconductor die / wafer. Under thermal mismatch stress, the unbonded region NB1 may expand, and cracks (if present) may extend toward the functional region 110A. This could cause the first semiconductor die and the semiconductor wafer to separate, resulting in the resulting structure malfunctioning or failing. Therefore, in the fabrication of semiconductor structures, it is important to prevent delamination of the bonding interface and to prevent any cracks from extending into the functional region 110A. As described in more detail below, by partially removing the bonded structure, the bonding interface stress can be reduced during the formation of the insulating encapsulation, and the adhesion of the bonded structure can be improved.

[0038] Reference FIG. 2B And refer to FIG. 2A A portion of the first semiconductor die 110 in the peripheral region 110P can be removed by any suitable method to form a first semiconductor die 110' including a flange portion 110G. For example, photoresist (not shown) is formed on the bonded structure by spin coating, spraying, or any suitable deposition process, and the photoresist covers the back side 111b of the first semiconductor substrate 111. The photoresist is then patterned by photolithography or the like to form openings, wherein the openings in the photoresist can be accessibly exposed to a portion of the first semiconductor substrate 111 to be removed. The portion of the first semiconductor substrate 111 exposed by the openings in the photoresist can then be removed by, for example, plasma etching, laser grooving, and / or any suitable removal process. In some embodiments, not only the portion of the first semiconductor substrate 111 in the peripheral region 110P directly above the unbonded region NB1 (if present) can be removed, but also a portion of the first dielectric layer 1131 beneath the portion of the first semiconductor substrate 111 can be removed. The photoresist can then be removed.

[0039] like FIG. 2BAs shown, the first semiconductor die 110' can include a first portion 110X and a second portion 110Y connected to the first portion 110X and bonded to the semiconductor wafer 1200. The first portion 110X can be a remaining portion of the first semiconductor substrate 111' and the second portion 110Y can include the first interconnect structure 113 and the underlying first bonding structure 114. The first interconnect structure 113 and the underlying first bonding structure 114 can laterally protrude from the first semiconductor substrate 111'. The portion of the first interconnect structure 113 and the underlying first bonding structure 114 that protrude from the first semiconductor substrate 111' can be considered a flange portion 110G. An additional encapsulation ring 1151 and an additional bonding connector 1142D can be disposed in the flange portion 110G. For example, a lateral size LX1 of the first portion 110X is less than a lateral size LY1 of the second portion 110Y. The difference in lateral sizes (LY1 and LX1) can be a lateral size LG1 of the flange portion 110G. It is noted that the lateral sizes (LX1, LY1 and LG1) can vary depending on process and product requirements and do not constitute a limitation of the disclosure. In some embodiments, a sidewall 111W of the first semiconductor substrate 111' is laterally displaced from a sidewall 1131W of the first dielectric layer 1131 and a sidewall 1141W of the first bonding dielectric layer 1141, where the sidewall 1141W is substantially flush (or coplanar) with the sidewall 1131W within a process variation range. In some embodiments, an upper surface 1131U of the first dielectric layer 1131 connected to the sidewall 1131W can be exposed in an accessible manner at this stage.

[0040] Referring to FIG. 2C and referring to FIG. 2B An insulative encapsulation 132 can be formed on the semiconductor wafer 1200 to cover the first semiconductor die 110'. In some embodiments, the insulative encapsulation 132 is formed from a molding material or compound and can be formed by compression molding, transfer molding or the like. The molding material includes a polymer material and optionally a filler (not shown separately), where the filler can be silica particles or the like and the polymer material can be an epoxy resin or the like. The filler mixed in the polymer material can provide mechanical strength and heat dissipation for the insulative encapsulation 132. For example, an insulative material is formed over a top surface 1241t of the second bonding dielectric layer 1241 of the semiconductor wafer 1200 and the first semiconductor die 110' can be buried or covered by the insulative material. The insulative material can then be cured to form the insulative encapsulation 132.

[0041] A planarization process (e.g., CMP, grinding, etching, a combination thereof, or the like) is optionally performed to planarize the insulative encapsulation 132. The planarization process can or can not remove the insulative encapsulation 132 on the backside 111b of the first semiconductor substrate 111'. In some embodiments, the backside 111b of the first semiconductor die 110' is exposed in a touchable manner by the planarized insulative encapsulation 132, and surfaces (e.g., 111b and 132t) of the first semiconductor die 110' and the insulative encapsulation 132 are substantially flush (or coplanar) within a process variation range. In some embodiments, the insulative encapsulation 132 laterally covers the first and second portions (110X and 110Y) of the first semiconductor die 110'. The insulative encapsulation 132 can be in physical contact with the sidewall 111W of the first semiconductor substrate 111', the upper surface 1131U and sidewall 1131W of the first dielectric layer 1131, and the sidewall 1141W of the first bonding dielectric layer 1141. By partially removing the first semiconductor die 110 to form the first semiconductor die 110' having the ledge portion 110G, the bonding interface stress, particularly in the peripheral region 110P of the first semiconductor die 110, can be reduced during the formation of the insulative encapsulation 132. In this way, even if there are unbonded regions (e.g., NB1) and / or cracks in the bonded structure, the stress in the bonded structure can be mitigated during the formation of the insulative encapsulation 132, thereby preventing the occurrence of delamination / cracking, preventing the delamination / cracking from becoming more severe, and / or preventing the delamination / cracking from extending to the functional region 110A. FIG. 2A In some embodiments, the insulative encapsulation 132 is formed after the first semiconductor die 110' is bonded to the second semiconductor die 121'. In some embodiments, the insulative encapsulation 132 is formed after the first semiconductor die 110' is bonded to the second semiconductor die 121' and the backside 121b of the second semiconductor die 121' is thinned. In some embodiments, the insulative encapsulation 132 is formed after the first semiconductor die 110' is bonded to the second semiconductor die 121' and the backside 121b of the second semiconductor die 121' is thinned, and the first semiconductor die 110' is partially removed to form the first semiconductor die 110' having the ledge portion 110G.

[0042] With continued reference to FIG. 2C and FIG. 2B A thinning process (e.g., grinding, CMP, etching, a combination thereof, or the like) can be performed on the backside of the semiconductor wafer 1200. For example, the backside 121b of the second semiconductor substrate 121 is thinned until at least a portion of the second end 125b of the via 125 is exposed in a touchable manner. In some embodiments, the thinning process is performed after the insulative encapsulation 132 is formed. Since the via 125 penetrates through the second semiconductor substrate 121, the via 125 can be considered as a through-substrate via (TSV) 125.

[0043] With reference to FIG. 2D and with reference to FIG. 2CThe plurality of electrically conductive terminals 142 can be formed over the backside 121b of the second semiconductor substrate 121 and electrically connected to the TSVs 125. The electrically conductive terminals 142 can be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connections, solder balls, metal pillars, micro bumps, bumps formed of electroless nickel-electroless palladium-immersion gold (ENEPIG), or the like. The electrically conductive terminals 142 can include an electrically conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the electrically conductive terminals 142 are formed of a solder material and a reflow process is performed on the solder material to form the desired bump shape. In some embodiments, a respective electrically conductive terminal 142 includes a pillar portion (e.g., a copper pillar) having substantially vertical sidewalls and a cap portion formed on the pillar portion, where the cap portion has a bump profile.

[0044] In some embodiments, the redistribution structure 150 is formed on the backside 121b of the second semiconductor substrate 121 and the second ends 125b of the TSVs 125 prior to forming the electrically conductive terminals 142. For example, the redistribution structure 150 includes one or more dielectric layers 151 and electrically conductive patterns (or redistribution lines) 152 formed in the dielectric layers 151 and electrically connected to the TSVs 125. The dielectric layers 151 can be formed of any suitable dielectric material, such as polybenzoxazole (PBO), polyimide, benzocyclobuten (BCB), combinations thereof, or the like. The electrically conductive patterns 152 can include electrically conductive pads, vias, wires, combinations thereof, or the like, and can be formed of any suitable electrically conductive material, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. In some embodiments, the electrically conductive patterns 152 include under bump metallization (UBM) pads, and the electrically conductive terminals 142 are formed on the UBM pads. Alternatively, the redistribution lines of the redistribution structure 150 are omitted. In this case, UBM pads are formed directly on the second ends 125b of the TSVs 125, and the electrically conductive terminals 142 are formed on the UBM pads to electrically couple to the TSVs 125.

[0045] Referring to FIG. 2E and referring to FIG. 2DOptionally, a monomerization process can be performed by dicing along a scribe line SL1 to form individual semiconductor structures 10A. For example, semiconductor structure 10A includes a first layer 101 stacked on a second layer 102, wherein the first layer 101 includes a first semiconductor die 110' and an insulating encapsulation 132 covering the first semiconductor die 110', and the second layer 102 includes a second semiconductor die 120 formed by monomerization of semiconductor wafer 1200, a redistribution structure 150 beneath the second semiconductor die 120, and conductive terminals 142 electrically coupled to the second semiconductor die 120 via the redistribution structure 150. In some embodiments, the second semiconductor die 120 is considered an intermediary. In some embodiments, the scribe line SL1 passes perpendicularly through the periphery of the first semiconductor die 110' (e.g., flange portion 110G or second portion 110Y). For example, after the monomerization process, at least the edge of the flange portion 110G is removed to form the flange portion 110G'. During the monomerization process, a portion of the insulating encapsulation 132 laterally surrounding the second portion 110Y of the first semiconductor die 110' can be removed, and after the monomerization process, the remaining insulating encapsulation 132 laterally surrounding the first portion 110X of the first semiconductor die 110' can be retained. After the monomerization process, the maximum lateral size LX1 of the first semiconductor substrate 111' of the first semiconductor die 110' is less than the maximum lateral size LM2 of the second semiconductor die 120. The maximum lateral size of the first interconnect structure 113 may be substantially equal to the maximum lateral size LM2 of the second semiconductor die 120.

[0046] like FIG. 2E As shown, the monomerized insulating encapsulation 132' may have monomerized sidewalls 132W, which are substantially flush (or coplanar) with the monomerized sidewalls 110YW of the second portion 110Y of the first semiconductor die 110' and the monomerized sidewalls 120W of the second semiconductor die 120 within the range of process variations. For example, the monomerized sidewalls 110YW of the second portion 110Y of the first semiconductor die 110' include the monomerized sidewalls 113W' of the first interconnect structure 113 and the monomerized sidewalls 114W' of the first bonding structure 114. The position of the scribe line SL1 can be adjusted according to process and product requirements. For example, the scribe line SL1 passes only through the insulating encapsulation 132 and the underlying semiconductor wafer 1200, but not through the first semiconductor die 110'. In this configuration, the first and second portions (110X and 110Y) of the first semiconductor die 110' remain laterally covered by a monomerized insulating encapsulation. In an alternative embodiment, the scribe line SL1 extends through the flange portion 110G and, as will be discussed later... FIG. 3BThe additional seal ring 1151 described in the flange portion 110G is singulated.

[0047] Referring FIG. 2F and referring FIG. 2E Semiconductor structure 10A is optionally mounted on a package substrate 20 using electrically conductive terminals 142 to form an integrated circuit (IC) package 30. Package substrate 20 can include a substrate 202 that can be made of a semiconductor material of silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon carbide germanium, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, and the like can also be used. Substrate 202 can be an SOI substrate. Alternatively, substrate 202 includes an insulating core (not shown separately), such as a fiberglass reinforced resin core (e.g., FR4), a BT resin core, or includes a printed circuit board (PCB) material or film. A build-up film (e.g., Ajinomoto build-up film or other laminate material; not shown separately) can be used for substrate 202. Substrate 202 can include active and / or passive devices (not shown) to produce the functional requirements of the system design.

[0048] The package substrate 20 can include contact pads 204 formed in / on the substrate 202. The conductive terminals 142 can be reflowed to attach the semiconductor structure 10A to the contact pads 204 of the package substrate 20. After coupling the conductive terminals 142 to the contact pads 204, the semiconductor structure 10A can be electrically coupled to the package substrate 20. In some embodiments, the IC package 30 includes an underfill 206 formed in a gap between the semiconductor structure 10A and the package substrate 20. The underfill 206 can laterally surround the conductive terminals 142 for protection. The underfill 206 can be formed by a capillary flow process after attaching the semiconductor structure 10A, or can be formed by an appropriate deposition method prior to attaching the semiconductor structure 10A. The underfill 206 can be a continuous material extending from the gap between the package substrate 20 and the semiconductor structure 10A. In some embodiments, the underfill 206 extends upward to be in physical contact with the singulated sidewall 120W of the second semiconductor die 120. Depending on the amount of underfill 206 applied, in some embodiments, the underfill 206 extends upward to be in physical contact with the singulated sidewall 110YW of the first semiconductor die 110’. The perimeter of the interface IF10 can be surrounded by the underfill 206. In some other embodiments, the underfill 206 extends upward to be in physical contact with the singulated sidewall 132W of the singulated insulative encapsulation 132’. The above examples are provided for illustrative purposes only, and in other embodiments, the IC package 30 can include fewer or additional components.

[0049] FIG. 3A and FIG. 3B schematic cross-sectional views of variants of semiconductor structures in accordance with some embodiments are shown. Unless otherwise noted, the materials and methods of formation of the components in these embodiments are substantially the same as in the previously described embodiments. FIG. 2E like components are indicated by like reference numerals in the illustrated embodiments. FIGS. 3A-3B Details of the illustrated components can be found in the discussion of the previous embodiments.

[0050] Referring to FIG. 3A and referring to FIG. 2E , except that the first semiconductor die 110’-1 of the first tier 101’ includes a third portion 110Z interposed vertically between the first portion 110X and the second portion 110Y’ and the additional sealing ring 1151 in the second portion 110Y’ is in direct contact with the singulated insulative encapsulation 132’-1, FIG. 3A the semiconductor structure 10B shown is substantially the same as FIG. 2EThe illustrated semiconductor structure 10A is similar. The third portion 110Z can have a lateral size substantially equal to that of the first portion 110X and less than that of the second portion 110Y’. For example, the third portion 110Z is part of the first interconnect structure 113’ and the second portion 110Y’ includes the remaining part of the first interconnect structure 113’ and the underlying first bonding structure 114. The second portion 110Y’ can laterally protrude from the third portion 110Z and the protruding portion can be considered a flange portion 110G’-1. An additional sealing ring 1151 can be disposed in the second portion 110Y’ and the flange portion 110G’-1.

[0051] In some embodiments, as FIG. 2B described during the process of partially removing the first semiconductor die 110, the portion of the first interconnect structure 113 directly underneath the portion of the first semiconductor substrate 111 in the peripheral region 110P (labeled in FIG. 2A ) is also removed until at least a portion of the additional sealing ring 1151 is exposed in a touchable manner by the first dielectric layer 1131’. During the removal process, the additional sealing ring 1151 can act as a stop layer. In some embodiments, the upper surface 1131U’ of the first dielectric layer 1131’ and the upper surface 1151U’ of the additional sealing ring 1151 are substantially flush (or coplanar) within process variation. In some embodiments, the upper surface 1151U’ of the additional sealing ring 1151 protrudes slightly from the upper surface 1131U’ of the first dielectric layer 1131’. The sidewall 1131W’ of the first dielectric layer 1131’ connected to the upper surface 1131U’ can be substantially flush (or coplanar) with the sidewall 111W of the first semiconductor substrate 111’. The sidewall 1131W’ of the first dielectric layer 1131’ can be considered a sidewall of the third portion 110Z. The monolithic sidewall 110YW of the second portion 110Y’ can be laterally displaced from the sidewall 1131W’ of the third portion 110Z.

[0052] As FIG. 3AAs shown, the first tier 101'of the semiconductor structure 10B can include a monolithically encapsulated insulative enclosure 132'-1 extending along sidewalls (111W and 1131W') of the first portion 110X and the third portion 110Z. The monolithically encapsulated insulative enclosure 132'-1 can be in physical contact with an upper surface 1131U' of the first dielectric layer 1131'and an upper surface 1151U' of the additional sealing ring 1151. After the monolithication process, monolithized sidewalls 132W of the monolithically encapsulated insulative enclosure 132'-1 can be substantially flush (or coplanar) with monolithized sidewalls 110YW of the second portion 110Y' and monolithized sidewalls 120W of the second semiconductor die 120. The semiconductor structure 10B can be mounted on a package substrate 20 (see FIG. 2F ) using electrically conductive terminals 142, to form an IC package.

[0053] Referring to FIG. 3B and to FIG. 2E , in addition to the second portion 110Y of the first semiconductor die 110'-2 can have monolithized sidewalls 110YW' including monolithized sidewalls 1151W of the additional sealing ring 1151 ', FIG. 3B The semiconductor structure 10C shown is similar to the semiconductor structure 10A shown in FIG. 2E . For example, a scribe lane SL1 (marked in FIG. 2D ) passes through the additional sealing ring 1151 in the flange portion 110G of the first semiconductor die 110'. In this case, during the monolithication process, a cutting tool (e.g., a blade or the like) can cut through the insulative enclosure 132, the first dielectric layer 1131, the additional sealing ring 1151, and the first bond structure 114, thereby forming the first tier 101 ". In some embodiments, the scribe lane SL1 also passes through the additional bond connections (1142D and 1242D) directly below the monolithized additional sealing ring 1151 in the flange portion 110G. In this case, monolithized sidewalls of the additional bond connections (1142D and 1242D) can be exposed at the outer sidewall of the semiconductor structure 10C. As an alternative, no additional bond connections (1142D and 1242D) are monolithized. Thus, FIG. 3B the monolithized bond connections (1142D and 1242D) in

[0054] After the singulation process, the singulated sidewalls 110YW’ of the second portion 110Y of the first semiconductor die 110’-2 can include singulated sidewalls 1131W” of the first dielectric layer 1131, singulated sidewalls 1151W of the additional sealing rings 1151’, and singulated sidewalls 114W’ of the first bonding structure 114, which are substantially flush (or coplanar) with each other within process variations. The singulated sidewalls 110YW’ of the second portion 110Y of the first semiconductor die 110’-2 can be substantially flush (or coplanar) with the singulated sidewalls 132W of the singulated insulating encapsulation 132’ and the singulated sidewalls 120W of the second semiconductor die 120 within process variations. The semiconductor structure 10C is optionally mounted on a package substrate 20 using the conductive terminals 142 (see FIG. 2F ), to form an IC package.

[0055] It is to be understood that the singulated sidewalls of the semiconductor structure can have a different configuration than shown, depending on the location of the scribe lane SL1 (marked in FIG. 2D ). For example, the lateral size LG1’ of the ledge portion 110G’-2 is non-zero. In some embodiments, the lateral size LG1’ is greater than 1 pm. Other values are also possible. In some embodiments, the scribe lane SL1 (marked in FIG. 2D ) passes through both the conductive landing pad and the via of the respective additional sealing ring 1151. As FIG. 3B shown, the singulated sidewalls 1151W of the respective additional sealing ring 1151’ can thus include sidewalls of the conductive landing pad and sidewalls of the via, which are substantially flush (or coplanar) with each other within process variations. In some other embodiments, the scribe lane SL1 (marked in FIG. 2D ) passes through the conductive landing pad of the respective additional sealing ring 1151, but not through the via of the respective additional sealing ring 1151. In this case, the singulated sidewalls 1151W of the respective additional sealing ring 1151’ can include sidewalls of the conductive landing pad, and the sidewalls of the conductive landing pad of the additional sealing ring 1151’ and the segmented sidewalls of the first dielectric layer 1131 are arranged vertically and alternately. In alternative embodiments, the scribe lane SL1 (marked in FIG. 2D ) passes through the first dielectric layer 1131, and the additional sealing ring 1151 is outside the scribe lane SL1. In this case, the additional sealing ring 1151 is completely removed during the singulation process. Thus, the additional sealing rings 1151’ are circumscribed by dashed boxes in FIG. 3B to indicate that they can (or can not) be present in the ledge portion of the first semiconductor die 110’-2.

[0056] FIGS. 4A-4Cschematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure are shown. Unless otherwise noted, the materials and methods of forming the components in these embodiments are substantially the same as in the embodiments shown in FIGS. 2A to 2E the previous embodiments. Details regarding the formation processes and materials of the components shown in FIGS. 4A-4C the previous embodiments can be found in the discussion of the previous embodiments.

[0057] Referring to FIG. 4A and to FIGS. 2A-2B , the first semiconductor die 110 can be bonded to the semiconductor wafer 1200 as described in FIG. 2A . After the bonding process, a portion of the bonded structure can be removed by any appropriate method, such as plasma etching, laser dicing, combinations thereof, other patterning processes, or the like. For example, a peripheral region 110P of the first semiconductor die 110 is partially (or entirely) removed to form a first semiconductor die 110” having a continuous sidewall 110W. The continuous sidewall 110W can include sidewalls 111V of the first semiconductor substrate 111, sidewalls 1131V of the first dielectric layer 1131, and sidewalls 1141V of the first bonding structure 114. For example, the sidewalls (111V, 1131V, and 1141V) are substantially flush (or coplanar) with each other within a process variation range.

[0058] In some embodiments, a portion of the first semiconductor die 110 corresponding to the unbonded region NB1 (if present, labeled in FIG. 2A ) is removed. In some embodiments, the first semiconductor substrate 111, the first interconnect structure 113 underneath the first semiconductor substrate 111, and the first bonding structure 114 underneath the first interconnect structure 113 within the peripheral region 110P are partially (or entirely) removed. In some embodiments, the additional sealing ring 1151 disposed in the peripheral region 110P and the additional bonding connector 1142D (if present) directly underneath the additional sealing ring 1151 are also removed. Alternatively, the additional sealing ring 1151 and / or the additional bonding connector 1142D within the peripheral region 110P can be partially removed. In this case, sidewalls of the additional sealing ring 1151 and / or sidewalls of the additional bonding connector 1142D can be exposed at the outer sidewall of the first semiconductor die 110. For example, the peripheral region 110P of the first semiconductor die 110 is partially removed, and the lateral size 110PL of the remaining peripheral region 110P’ is non-zero. For example, the lateral size 110PL of the remaining peripheral region 110P’ is greater than 1 pm. Other values are also possible.

[0059] Continuing to refer to FIG. 4Asemiconductor wafer 1200' with a recess 120R. In a top view (not shown), the recess 120R can be a dead loop around the first semiconductor die 110". The depth of the recess 120R can vary depending on the process and product requirements, as long as the un-bonded region NB1 (labeled in FIG. 2A ) of the bonded structure is removed. The width of the recess 120R can correspond to the width of the removed portion of the first semiconductor die 110. By removing the un-bonded region NB1 (labeled in FIG. 2A ) in the first semiconductor die and the semiconductor wafer, the remaining portion of the bonding interface IF10' can remain well bonded. For example, the bottom most portion of the recess 120R reaches the interface of the second bonding structure 124' and the second interconnect structure 123' or can extend into the second interconnect structure 123'. In the illustrated embodiment, the recess 120R is defined by the inner sidewalls (124V1 and 124V2) of the second bonding dielectric layer 1241' of the second bonding structure 124', the inner sidewalls (123V1 and 123V2) of the second dielectric layer 1231' of the second interconnect structure 123', and the upper surface 1231t of the second dielectric layer 1231'. In other embodiments where the bottom of the recess 120R reaches the second bonding structure without extending into the second interconnect structure, the recess 120R is defined by the inner sidewalls (124V1, 124V2, 123V1, and 123V2) and the upper surface of the second bonding dielectric layer. In some embodiments, the inner sidewalls (124V1 and 123V1) are substantially flush (or coplanar) with the continuous sidewall 110W of the first semiconductor die 110".

[0060] Referring to FIG. 4B and referring to FIG. 4A and FIGS. 2C-2D , an insulating encapsulation 232 can be formed on the semiconductor wafer 1200' to cover the first semiconductor die 110". The material and formation method of the insulating encapsulation 232 can be the same as described in FIG. 2CThe insulative encapsulation 132 described in the background is similar, and thus not repeated here. The insulative encapsulation 232 can extend along the continuous sidewall 110W of the first semiconductor die 110” and fill the recess 120R of the semiconductor wafer 1200’. For example, the insulative encapsulation 232 is in physical contact with the second dielectric layer 1231’ that defines the recess 120R and the inner sidewalls (124V1, 124V2, 123V1, and 123V2) of the second dielectric layer 1231’ and the upper surface 1231t. A planarization process (e.g., CMP, grinding, etching, a combination thereof, or the like) can be optionally performed to planarize the insulative encapsulation 232 and the first semiconductor die 110. In some embodiments, the backside 111b of the first semiconductor die 110” and the top surface 232t of the insulative encapsulation 232 are substantially flush (or coplanar) within a process variation range. Since the un-bonded region NB1 (labeled in FIG. 2A the background) is removed prior to forming the insulative encapsulation 232, there is no delamination / cracking in the remaining bonding interface IF10’. In this way, the possibility of delamination / cracking propagation caused by the stress induced during the formation of the insulative encapsulation 232 can be reduced or eliminated.

[0061] In some embodiments, a thinning process (e.g., grinding, CMP, etching, a combination thereof, or the like) is performed on the backside of the semiconductor wafer 1200’ until at least a portion of the second end 125b of the TSV 125 is exposed in a touchable manner. The thinning process can be similar to the processes described in the background, and thus not repeated here. In some embodiments, the redistribution structure 150 and the conductive terminal 142 are formed on the backside of the semiconductor wafer 1200’ and the second end 125b of the TSV 125 in sequence. Details of the redistribution structure 150 and the conductive terminal 142 have been described in the background, and thus not repeated here. In alternative embodiments, the redistribution structure 150 is replaced by a UBM pad to directly couple the conductive terminal 142 to the TSV 125. FIG. 2C FIG. 2D

[0062] Referring to FIG. 4C and referring to FIG. 4B and FIGS. 2E-2F ​​The singulation process is optionally performed by cutting along the scribe lane SL1 to form individual semiconductor structures 10D. In some embodiments, the scribe lane SL1 passes perpendicularly through the recess 120R of the semiconductor wafer 1200', and a cutting tool (e.g., a saw blade, a knife blade, or the like) can travel through the insulative encapsulation 232 and the semiconductor wafer 1200'. For example, the resulting semiconductor structure 10D includes a first tier 201 stacked on a second tier 202, where the first tier 201 includes a first semiconductor die 110" and an insulative encapsulation 232' laterally covering the first semiconductor die 110", and the second tier 202 includes a second semiconductor die 120' formed by singulating the semiconductor wafer 1200', a redistribution structure 150 under the second semiconductor die 120', and a conductive terminal 142 electrically coupled to the second semiconductor die 120' through the redistribution structure 150. After the singulation process, a maximum lateral size LX1 of the first semiconductor substrate 111 is less than a maximum lateral size LM2 of the second semiconductor die 120. The maximum lateral sizes of the first interconnect structure 113, the first bonding structure 114, and the second bonding structure 124 can be substantially equal to the maximum lateral size LX1 of the first semiconductor substrate 111. The insulative encapsulation 232' can extend perpendicularly into the second tier 202 and beyond the bonding interface IF10'. For example, the insulative encapsulation 232' extends along the continuous sidewall 110W of the first semiconductor die 110" and the inner sidewalls (124V1 and 123V1) of the second bonding structure 124' and the second interconnect structure 123'.

[0063] In some embodiments, the singulated sidewall 232W of the insulative encapsulation 232' is substantially flush (or coplanar) with the singulated sidewall of the second semiconductor die 120'. In embodiments where the scribe lane SL1 passes perpendicularly through the recess 120R of the semiconductor wafer 1200', the singulated sidewall of the second semiconductor die 120' includes the outer sidewall 123W1 of the second interconnect structure 123', the outer sidewall 121W of the second semiconductor substrate 121, and the outer sidewall 150W of the redistribution structure 150 (if present). In FIG. 4B The location of the scribe lane SL1 as labeled in FIG. 12 can be adjusted according to process and product requirements. In alternative embodiments, the scribe lane SL1 passes perpendicularly through a region other than the recess 120R, so that the recess 120R filled by the insulative encapsulation 232 can remain in the resulting semiconductor structure after the singulation process. The semiconductor structure 10D is optionally mounted on a package substrate 20 (see FIG. 13) using the conductive terminal 142 to form an IC package. FIG. 2F

[0064] FIG. 5A A schematic cross-sectional view of a first semiconductor die is shown in accordance with some embodiments. It should be noted that​FIG. 5A are provided for illustrative purposes only, and according to some embodiments, the first semiconductor die can use fewer or additional components. Unless otherwise noted, FIG. 5A the first semiconductor die in FIG. 1A the first semiconductor die described in FIG. 5A Details of the first semiconductor die shown can be found in the discussion of the preceding embodiments.

[0065] Referring to FIG. 5A and referring to FIG. 1A , the first semiconductor die 210 can be similar to the first semiconductor die 110 described in FIG. 1A except that the first semiconductor die 210 includes a first ledge 210G1 and a second ledge 210G2 disposed in the peripheral region 210P. The first semiconductor die 210 can have a stepped sidewall. For example, the first semiconductor die 210 is formed in a wafer (not shown) that can include different die regions that are singulated in subsequent steps to form a plurality of first semiconductor dies 210. To perform the singulation process for forming the first semiconductor die 210, a shallow recess can be formed in a scribe lane region of the semiconductor wafer by etching or other appropriate recessing process, thereby forming a sidewall 1141W of the first dielectric layer 1141. If the shallow recess is deep enough to reach the first interconnect structure 113", then a first sidewall 1131W1 of the first dielectric layer 1131" and a first surface 1131U of the first dielectric layer 1131" connected to the first sidewall 1131W1 are also formed. Next, a slotting process (e.g., laser slotting, plasma cutting, or the like) can be performed on the semiconductor wafer and through the shallow recess, thereby forming a groove connected to the recess. For example, the groove extends through the first dielectric layer 1131", and a second ledge 210G2 having a second sidewall 1131V of the first dielectric layer 1131" is formed. In some embodiments, the slotting process stops until the front side 111a of the first semiconductor substrate 111 is exposed in a touchable manner. Subsequently, a dicing process can be performed on the semiconductor wafer to completely separate the die regions from one another to form individual first semiconductor dies 210. The dicing process can be performed through the shallow recess and the underlying groove in the scribe lane region, and a first ledge 210G1 having a sidewall 111V of the first semiconductor substrate 111 is formed.

[0066] The above-described steps for forming the first semiconductor die 210 are merely examples, and other suitable methods can be used to form the first semiconductor die 210 with a stepped sidewall profile. The lateral size (e.g., width) of the first and second flanges (210G1 and 210G2) can vary and can depend on the width of the groove formed by the grooving process and the blade used to perform the dicing process. The lateral size of the first and second flanges (210G1 and 210G2) is not limiting in this disclosure. Due to process differences in the recessing / grooving / dicing processes, the sidewalls / surfaces of different regions of the first semiconductor die 210 can have different roughness. For example, the sidewalls / surfaces (e.g., 1131W, 1131U, 1131V, and 111a) formed via recessing / grooving are smoother than the sidewall 111V formed via dicing. In some embodiments, the surface roughness of the sidewalls / surfaces (e.g., 1131W, 1131U, 1131V, and 111a) is less than the surface roughness of the sidewall 111V.

[0067] FIGS. 5B-5E schematic cross-sectional views of intermediate steps during a process of forming a semiconductor structure in accordance with some embodiments are shown. Unless otherwise noted, the materials and methods of formation of the components in these embodiments are substantially the same as those described in FIGS. 2A to 2E the previous embodiments. Details regarding the formation processes and materials of the components shown in FIGS. 5B-5E may be found in the discussion of the previous embodiments.

[0068] Referring to FIG. 5B and referring to FIG. 5A and FIG. 2A , the first semiconductor die 210 can be bonded to the semiconductor wafer 1200. The bonding process of the first semiconductor die 210 and the semiconductor wafer 1200 can be similar to the processes described in FIG. 2A and thus will not be repeated here. For example, the first bonding structure 114 of the first semiconductor die 210 can be bonded to the second bonding structure 124 of the semiconductor wafer 1200, and the bonding interface IF20 of the first semiconductor die 210 and the semiconductor wafer 1200 can be substantially flat and planar.

[0069] Referring to FIG. 5C and referring to FIG. 5B and FIG. 2BA portion of the first semiconductor die 210 in the peripheral region 210P can be removed by any suitable method to form a first semiconductor die 210'. For example, a photoresist (not shown) is formed on the bonded structure by spin coating, spray coating, or any suitable deposition process and covers the backside of the first semiconductor substrate 111, which is then patterned by photolithography or the like to form openings where the photoresist exposes a portion of the first semiconductor substrate 111 to be removed in an accessible manner. Next, the portion of the first semiconductor substrate 111 exposed by the openings of the photoresist can be removed by, for example, etching or any suitable removal process. Subsequently, the photoresist can be removed. In some embodiments, only the portion of the first semiconductor substrate 111 in the peripheral region 210P is removed to expose the second surface 1131t of the first dielectric layer 1131" opposite the first surface 1131u in an accessible manner. In alternative embodiments, not only the portion of the first semiconductor substrate 111 in the peripheral region 210P is removed, but also a portion of the first dielectric layer 1131 directly underneath the portion of the first semiconductor substrate 111 in the peripheral region 210P, as will be described later in connection with FIG. 2B. FIG. 6 as described.

[0070] As FIG. 5C shown, the first semiconductor die 210' can include a first portion 210X, a second portion 210Y underneath the first portion 210X, and a third portion 210Z underneath the second portion 210Y and bonded to the semiconductor wafer 1200. For example, the first portion 210X is the remaining first semiconductor substrate 111-1, the second portion 210Y is a portion of the first interconnect structure 113", and the third portion 210Z includes the remaining portion of the first interconnect structure 113" and the underlying first bonding structure 114. In some embodiments, the second portion 210Y protrudes laterally from the first portion 210X and the third portion 210Z, and the third portion 210Z is wider than the first portion 210X. For example, a lateral size LY1 of the second portion 210Y is greater than a lateral size LZ1 of the third portion 210Z, and the lateral size LZ1 of the third portion 210Z is greater than a lateral size LX1 of the first portion 210X. Sidewalls 111V' of the first portion 210X can be laterally displaced from sidewalls 1131V of the second portion 210Y, and the sidewalls (111V' and 1131V) can be laterally displaced from sidewalls (1131W and 1141W) of the third portion 210Z.

[0071] Referring FIG. 5D and referring FIG. 5C and FIGS. 2C-2DAn insulating encapsulation 332 can be formed on the semiconductor wafer 1200 to cover the first semiconductor die 210'. The material and formation method of the insulating encapsulation 332 can be compared with... FIG. 2C The insulating encapsulation 132 described herein is similar and will not be repeated here. Optionally, planarization processes (e.g., CMP, polishing, etching, combinations thereof, or the like) may be performed to planarize the insulating encapsulation 332. In some embodiments, the back side 111b of the first semiconductor substrate 111-1 and the top surface 332t of the insulating encapsulation 332 are substantially flush (or coplanar) within a range of process variations. The insulating encapsulation 332 may have multiple portions of varying widths corresponding to the first / second / third portions of the first semiconductor die 210'. The insulating encapsulation 332 may extend along the stepped sidewalls of the first semiconductor die 210'. For example, the insulating encapsulation 332 is in physical contact with the sidewall 111V' of the first semiconductor substrate 111-1, the first and second surfaces (1131U and 1131t) and first and second sidewalls (1131W and 1131V) of the first dielectric layer 1131”, and the sidewall 1141W of the first bonding structure 114.

[0072] In some embodiments, a thinning process (e.g., polishing, CMP, etching, a combination thereof, or the like) is performed on the back side of the semiconductor wafer 1200 until at least a portion of the second end 125b of the TSV 125 is exposed in a tangible manner. The thinning process may be combined with... FIG. 2C The processes described are similar and will not be repeated here. In some embodiments, the redistribution structure 150 and the conductive terminal 142 are sequentially formed on the back side of the semiconductor wafer 1200 and on the second end 125b of the TSV 125. Details of the redistribution structure 150 and the conductive terminal 142 have been described in [the following text is missing from the original] FIG. 2D As described herein, and will not be repeated here. In an alternative embodiment, the redistribution structure 150 is replaced by a UBM pad to directly couple the conductive terminal 142 to the TSV 125.

[0073] Reference FIG. 5E And refer to FIG. 5D and FIGS. 2E-2F Optionally, a monomerization process can be performed by slicing along a scribe line SL1 to form individual semiconductor structures 10E. In some embodiments, the scribe line SL1 passes perpendicularly through the periphery of the first semiconductor die 210'. In this case, after the monomerization process, at least the periphery of the second portion 210Y of the first semiconductor die 210' can be removed. During the monomerization process, said portion of the insulating encapsulation 332 laterally surrounding the second portion 210Y of the first semiconductor die 210' can be removed, and after the monomerization process, the remaining insulating encapsulation 332 laterally surrounding the first portion 210X and the third portion 210Z of the first semiconductor die 210' can be retained.FIG. 5D The location of the scribe lane SL1 as marked in FIG. 10 can be adjusted according to process and product requirements. In some other embodiments, the scribe lane SL1 only goes through the insulating encapsulation 332 and the underlying semiconductor wafer 1200, without going through the first semiconductor die 210’, thus after the singulation process, the first / second / third portions (210X / 210Y / 210Z) of the first semiconductor die 210’ remain covered by the insulating encapsulation 332. In alternative embodiments, the scribe lane SL1 goes through the additional sealing ring 1151 vertically, thus during the singulation process, the additional sealing ring 1151 is cut, as FIG. 3B described and shown.

[0074] In some embodiments, the semiconductor structure 10E includes a first tier 301 stacked on the second tier 102, where the first tier 301 includes a first semiconductor die 210’ and an insulating encapsulation 332’ laterally covering the first semiconductor die 210’, and the second tier 102 includes a second semiconductor die 120 formed by singulating the semiconductor wafer 1200, a redistribution structure 150 under the second semiconductor die 120, and a conductive terminal 142 electrically coupled to the second semiconductor die 120 through the redistribution structure 150. After the singulation process, a maximum lateral size LX1 of the first semiconductor substrate 111-1 of the first semiconductor die 210’ is less than a maximum lateral size LM2 of the second semiconductor die 120. A maximum lateral size of the first interconnect structure 113” can be substantially equal to the maximum lateral size LM2 of the second semiconductor die 120. The insulating encapsulation 332’ can include a first portion 3321 laterally covering a first portion 210X of the first semiconductor die 210’ and a second portion 3322 laterally covering a third portion 210Z of the first semiconductor die 210’. The first and second portions 3321 and 3322 of the insulating encapsulation 332’ can be vertically separated from each other by the second portion 210Y of the first semiconductor die 210’. The singulated sidewalls (3321V and 3322V) of the first and second portions (3321 and 3322) of the insulating encapsulation 332’ can be substantially flush (or coplanar) with the singulated sidewall 1131V’ of the second portion 210Y of the first semiconductor die 210’ and the singulated sidewall 120W of the second semiconductor die 120 within a process variation range. The semiconductor structure 10E is optionally mounted on a package substrate 20 (see FIG. 2F ) using the conductive terminal 142 to form an IC package.

[0075] FIG. 6 schematic cross-sectional views of semiconductor structures are shown in accordance with some embodiments. Unless otherwise noted, the materials and methods of forming the components in these embodiments are substantially as described and shown in FIG. 5E andFIG. 3A Like elements in the illustrated embodiments are identified by like reference numerals. FIG. 6 Details of the illustrated components can be found in the discussion of the preceding embodiments.

[0076] Referring to FIG. 6 and referring to FIG. 5E and FIG. 3A except that the first semiconductor die 210” of the first tier 301’ includes a fourth portion 210W that is vertically interposed between the first portion 210X and the second portion 210Y’, and the additional sealing ring 1151 is in direct contact with the insulative encapsulation 332” in the second portion 210Y’, FIG. 6 The semiconductor structure 10F illustrated is similar to FIG. 5E The semiconductor structure 10E illustrated. The fourth portion 210W of the first semiconductor die 210” can have a lateral size that is substantially equal to that of the first portion 210X and less than that of the second portion 210Y’. For example, the fourth portion 210W is part of the first interconnect structure 113”-1, and the second portion 210Y’ includes the remaining part of the first interconnect structure 113’-1. The second portion 210Y’ can laterally protrude from the fourth portion 210W. The additional sealing ring 1151 can be disposed in the second portion 210Y’.

[0077] The process of forming the first semiconductor die 210” can be similar FIG. 3A to the process described. For example, during the process of partially removing the first semiconductor die 210 as described in FIG. 5C the first semiconductor die 210X is also removed, as well as the portion of the first interconnect structure 113”-1 that is in the peripheral region 210P (labeled in FIG. 5BA portion of the first interconnect structure 113" under the portion of the first semiconductor substrate 111 in the middle is removed until at least a portion of the additional sealing ring 1151 is exposed in a touchable manner by the first dielectric layer 1131"-1. The additional sealing ring 1151 can act as a stopper layer during the removal process. In some embodiments, the upper surface 1131U' of the first dielectric layer 1131"-1 and the upper surface 1151U' of the additional sealing ring 1151 are substantially flush (or coplanar) within a process variation range. In some embodiments, the upper surface 1151U' of the additional sealing ring 1151 protrudes from the upper surface 1131U' of the first dielectric layer 1131"-1. The sidewall 1131W' of the first dielectric layer 1131"-1 connected to the upper surface 1131U' can be substantially flush (or coplanar) with the sidewall 111V' of the first semiconductor substrate 111-1. The first portion 3321' of the insulative encapsulation 332" can extend along the sidewalls (111V' and 1131W') of the first portion 210X and the fourth portion 210W. The first portion 3321' of the insulative encapsulation 332" can be in physical contact with the upper surface 1131U' of the first dielectric layer 1131"-1 and the upper surface 1151U' of the additional sealing ring 1151. The semiconductor structure 10F is mounted on a package substrate 20 (see FIG. 2F ), with electrically conductive terminals 142, to form an IC package.

[0078] Embodiments can have one or a combination of the following features and / or advantages. By removing a portion of the bonded structure corresponding to the unbonded region in the bonded structure prior to forming the insulative encapsulation, the risk of delamination propagation in the bonded structure during formation of the insulative encapsulation can be reduced or eliminated. For example, the step of removing the portion of the bonded structure includes removing a peripheral portion of the first semiconductor die. This can help reduce stress applied to the first semiconductor die during formation of the insulative encapsulation and can improve adhesion of the first semiconductor die and the semiconductor wafer. In some embodiments, a portion of the semiconductor wafer directly bonded to the peripheral portion of the first semiconductor die is also removed to ensure that the unbonded region is not present in the bonded structure prior to formation of the insulative encapsulation. In some embodiments, the first semiconductor die includes one or more flanges that can provide a stepped profile that can be adhered to the second semiconductor die by the insulative encapsulation to reduce delamination defects in the bonded structure. Thus, a semiconductor structure with reduced defects, improved reliability, and improved yield can be realized.

[0079] Other features and processes can also be included. For example, test structures can be incorporated to facilitate verification testing of 3D packages or 3DIC devices. Test structures can for example include test pads formed on a redistribution layer or substrate that allow for testing of 3D packages or 3DICs, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0080] According to some embodiments, a semiconductor structure includes a first semiconductor die, a second semiconductor die underneath and bonded to the first semiconductor die, and an insulating encapsulation disposed over the second semiconductor die. The first semiconductor die includes a semiconductor substrate and an interconnect structure underneath the semiconductor substrate. A maximum lateral size of the semiconductor substrate of the first semiconductor die is less than a maximum lateral size of the second semiconductor die. The insulating encapsulation at least laterally surrounds the semiconductor substrate of the first semiconductor die.

[0081] In some embodiments, the first semiconductor die includes a sidewall of the interconnect structure and a sidewall of the semiconductor substrate laterally displaced from the sidewall of the interconnect structure. In some embodiments, the insulative encapsulant extends along the sidewall of the semiconductor substrate and lands on an upper surface of the interconnect structure connected to the sidewall of the interconnect structure. In some embodiments, the upper surface of the interconnect structure connected to the sidewall of the interconnect structure includes a surface of a conductive feature in direct contact with the insulative encapsulant. In some embodiments, the first semiconductor die further includes a bonding structure under the interconnect structure and bonded to the second semiconductor die, wherein the insulative encapsulant is vertically spaced apart from the second semiconductor die by the interconnect structure and the bonding structure. In some embodiments, the first semiconductor die further includes a first bonding structure having a first sidewall, the second semiconductor die includes a second bonding structure bonded to the first bonding structure and having a second sidewall, and the insulative encapsulant extends along the first sidewall and the second sidewall. In some embodiments, the second semiconductor die further includes a semiconductor substrate under the second bonding structure, and an outer sidewall of the insulative encapsulant is substantially aligned with a sidewall of the semiconductor substrate of the second semiconductor die. In some embodiments, the insulative encapsulant includes a first portion extending along a first sidewall of the first semiconductor die and a second portion extending along a second sidewall of the first semiconductor die laterally displaced from the first sidewall of the first semiconductor die. In some embodiments, outer sidewalls of the first portion and the second portion of the insulative encapsulant are substantially aligned with at least a portion of an outer sidewall of the interconnect structure of the first semiconductor die. In some embodiments, the first portion and the second portion of the insulative encapsulant are vertically separated from each other by a peripheral region of the first semiconductor die. In some embodiments, a bonding interface of the first semiconductor die and the second semiconductor die is free of solder material.

[0082] According to some embodiments, a semiconductor structure includes a first semiconductor die, a second semiconductor die under the first semiconductor die and bonded to the first semiconductor die, and an insulative encapsulant disposed over the second semiconductor die. The first semiconductor die includes a functional region, a seal ring region surrounding the functional region, and a peripheral region surrounding the seal ring region. The peripheral region of the first semiconductor die is in physical contact with the insulative encapsulant and includes a sidewall substantially aligned with a sidewall of the second semiconductor die.

[0083] In some embodiments, the sidewalls of the peripheral region of the first semiconductor die are substantially aligned with outer sidewalls of the insulative encapsulation, and an upper surface of the peripheral region connected to the sidewalls of the peripheral region is in physical contact with the insulative encapsulation. In some embodiments, the first semiconductor die further includes a conductive feature disposed in the peripheral region, and a surface of the conductive feature is in physical contact with the insulative encapsulation. In some embodiments, the second semiconductor die includes a semiconductor substrate and a bonding structure over the semiconductor substrate and bonded to the first semiconductor die, and the sidewalls of the peripheral region of the first semiconductor die are substantially aligned with sidewalls of the bonding structure, the sidewalls of the bonding structure being laterally displaced from sidewalls of the semiconductor substrate. In some embodiments, the insulative encapsulation includes a first portion and a second portion vertically separated from each other by the peripheral region of the first semiconductor die. In some embodiments, the first portion of the insulative encapsulation is wider than the second portion of the insulative encapsulation.

[0084] According to some embodiments, a method of manufacturing a semiconductor structure includes performing a bonding process to bond a first semiconductor die to a second semiconductor die, wherein after the bonding process, a first sidewall of the first semiconductor die is substantially flush with a second sidewall of the second semiconductor die; and forming an insulative encapsulation over the second semiconductor die to laterally surround the first semiconductor die.

[0085] In some embodiments, the method of manufacturing further includes, after the bonding process and before forming the insulative encapsulation, partially removing the first semiconductor die to form the first semiconductor die including the first sidewall and a third sidewall laterally displaced from the first sidewall; and performing a singulation process on the insulative encapsulation, the first semiconductor die, and the second semiconductor die, wherein after the singulation process, the first sidewall of the first semiconductor die is substantially flush with the second sidewall of the second semiconductor die. In some embodiments, the method of manufacturing further includes, after the bonding process and before forming the insulative encapsulation, partially removing a peripheral region of the first semiconductor die and a portion of the second semiconductor die underneath the peripheral region of the first semiconductor die to form a recess on the second semiconductor die; and forming the insulative encapsulation on the second semiconductor die to laterally cover the first semiconductor die and fill the recess.

[0086] Finally, it should be noted that: the above examples are used to illustrate the technical solutions of the embodiments of the present application, but not limited to them; although the embodiments of the present application are described in detail with reference to the foregoing examples, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized by, Comprising: a first semiconductor die including a semiconductor substrate and an interconnect structure under the semiconductor substrate; a second semiconductor die under and bonded to the first semiconductor die, wherein a maximum lateral size of the semiconductor substrate of the first semiconductor die is less than a maximum lateral size of the second semiconductor die; and an insulative encapsulation disposed over the second semiconductor die and laterally around the semiconductor substrate of the first semiconductor die. wherein the first semiconductor die includes a sidewall of the interconnect structure and a sidewall of the semiconductor substrate laterally displaced from the sidewall of the interconnect structure.

2. The semiconductor structure of claim 1, wherein, wherein the first semiconductor die further includes:

3. The semiconductor structure of claim 1, wherein, a bonding structure under the interconnect structure and bonded to the second semiconductor die, wherein the insulative encapsulation is vertically spaced from the second semiconductor die by the interconnect structure and the bonding structure. wherein:

4. The semiconductor structure of claim 1, wherein, the first semiconductor die further includes a first bonding structure having a first sidewall, the second semiconductor die includes a second bonding structure bonded to the first bonding structure and having a second sidewall, and the insulative encapsulation extends along the first sidewall and the second sidewall. wherein the insulative encapsulation includes:

5. The semiconductor structure of claim 1, wherein, a first portion extending along a first sidewall of the first semiconductor die; and a second portion extending along a second sidewall of the first semiconductor die laterally displaced from the first sidewall of the first semiconductor die. wherein outer sidewalls of the first portion and the second portion of the insulative encapsulation are substantially aligned with at least a portion of an outer sidewall of the interconnect structure of the first semiconductor die.

6. The semiconductor structure of claim 5, wherein, Comprising:

7. A semiconductor structure, characterized by a first semiconductor die including a functional region, a seal ring region around the functional region, and a peripheral region around the seal ring region; a second semiconductor die under and bonded to the first semiconductor die; and an insulative encapsulation disposed over the second semiconductor die, wherein the peripheral region of the first semiconductor die is in physical contact with the insulative encapsulation and includes a sidewall substantially aligned with a sidewall of the second semiconductor die. wherein the sidewall of the peripheral region of the first semiconductor die is substantially aligned with an outer sidewall of the insulative encapsulation, and an upper surface of the peripheral region connected to the sidewall of the peripheral region is in physical contact with the insulative encapsulation.

8. The semiconductor structure of claim 7, wherein, wherein the first semiconductor die further includes a conductive feature disposed in the peripheral region, and a surface of the conductive feature is in physical contact with the insulative encapsulation.

9. The semiconductor structure of claim 7, wherein, wherein:

10. The semiconductor structure of claim 7, wherein, the second semiconductor die includes a semiconductor substrate and a bonding structure over the semiconductor substrate and bonded to the first semiconductor die, and the sidewall of the peripheral region of the first semiconductor die is substantially aligned with a sidewall of the bonding structure, the sidewall of the bonding structure laterally displaced from a sidewall of the semiconductor substrate. ​

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