Pavement feature vector extraction device based on cross-correlation time difference analysis

Abstract

The utility model discloses a pavement feature vector extraction device based on cross-correlation time difference analysis. The pavement feature vector extraction device comprises a signal input interface, a signal conditioning circuit, a cross-correlation circuit, a sampling circuit, a discrimination circuit and a control circuit. According to the device, a dual-channel signal conditioning framework input by dual sensors is adopted, a special cross-correlation time difference analysis hardware circuit is integrated, and a closed-loop control adaptive parameter adjustment and peak triggering dual-channel synchronous sampling circuit is matched, so that core time difference characteristics of vibration signals at different spatial positions can be accurately captured; according to the method, the signal anti-interference performance and the parameter signal-to-noise ratio are remarkably improved, multi-section cross-scene data acquisition requirements are met, high-quality refined feature data are provided for subsequent big data analysis, and the data cleaning and processing cost is effectively reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to traffic infrastructure state perception and big data analysis field, concretely is a kind of road surface feature vector extraction device based on cross-correlation time difference analysis. BACKGROUND

[0002] With the continuous improvement of traffic infrastructure management system, big data analysis technology has been widely applied in the whole life cycle monitoring and maintenance decision of pavement. The collection and feature extraction of pavement vibration signal are the core links for providing basic data for subsequent big data modeling, performance evaluation and disease early warning. The performance of the collection equipment directly determines the quality of the data, and then affects the reliability of the big data analysis result and the scientificity of the maintenance strategy. At present, the industry generally obtains pavement state data by deploying vibration sensor hardware equipment, and gradually forms a complete application chain of "hardware collection-feature extraction-big data analysis-maintenance decision".

[0003] However, the existing pavement vibration signal feature extraction device is difficult to adapt to the demand of high-quality, multi-dimensional basic data for big data analysis, and there are many technical bottlenecks at the hardware level: first, the traditional device adopts a single sensor hardware architecture to collect signals, which is easily disturbed by external factors such as vehicle driving noise, environmental vibration, etc. The signal-to-noise ratio of the extracted feature parameters is low, which leads to a significant increase in the cost of data cleaning in the subsequent big data processing process, and the analysis accuracy is also significantly limited. Second, the existing device lacks a special cross-correlation time difference analysis hardware circuit, and cannot accurately capture the time difference characteristics of the signals collected by sensors at different spatial positions. This feature is a key indicator of core state parameters such as road flatness and compaction, and it is difficult to meet the demand of big data analysis for fine and targeted feature data. Third, the signal conditioning and sampling circuit of many devices has limited self-adaptive adjustment capability, and the gain, filtering and other parameters of the hardware circuit are often preset according to experience, or the adjustment range and flexibility are insufficient, which cannot be dynamically adjusted according to the vibration signal frequency and amplitude difference of different road sections (such as expressways and urban trunk roads), leading to poor universality of the collected data, and it is difficult to support cross-scenario big data fusion analysis.

[0004] Therefore, a feature extraction device is needed that can accurately extract the cross-correlation time difference characteristics of pavement vibration signals through hardware architecture optimization, has strong anti-interference capability, and adapts to the demand of big data analysis, to realize efficient collection of high-quality pavement feature data, and provide reliable hardware data source support for big data-driven pavement management and maintenance work. UTILITY MODEL CONTENT

[0005] The utility model discloses a purpose at overcoming prior art's insufficient, provide a kind of road surface feature vector extraction device based on cross-correlation time difference analysis, including signal input interface, signal conditioning circuit, cross-correlation circuit, sampling circuit, discriminant circuit and control circuit;The output end of the signal input interface is connected to the input end of the signal conditioning circuit;The first output end and the second output end of the signal conditioning circuit are connected to the first input end and the second input end of the cross-correlation circuit respectively;The output end of the cross-correlation circuit is connected to the input end of the sampling circuit;The first sampling output end and the second sampling output end of the sampling circuit are connected to the first signal input end and the second signal input end of the discriminant circuit respectively;The device further includes first feature output port and second feature output port, and the first feature output end and the second feature output end of the discriminant circuit are connected to the first feature output port and the second feature output port respectively;The pulse output end of the sampling circuit is connected to the enable end of the discriminant circuit;The flag output end of the discriminant circuit is connected to the input end of the control circuit;

[0006] The first control output end group of the control circuit includes two output ends, and is connected to the two control ends of the cross-correlation circuit respectively;The second control output end of the control circuit is connected to the gain control end of the signal conditioning circuit;The flyback detection input end of the control circuit is connected to the flyback synchronization signal output end of the cross-correlation circuit.

[0007] Preferably, the signal conditioning circuit includes first channel and second channel;The first channel includes first charge amplifier, first voltage-controlled gain amplifier and first band-pass filter;The output end of the first charge amplifier is connected to the input end of the first voltage-controlled gain amplifier, and the output end of the first voltage-controlled gain amplifier is connected to the input end of the first band-pass filter;The second channel includes second charge amplifier, second voltage-controlled gain amplifier and second band-pass filter;The output end of the second charge amplifier is connected to the input end of the second voltage-controlled gain amplifier, and the output end of the second voltage-controlled gain amplifier is connected to the input end of the second band-pass filter;The gain control end of the first voltage-controlled gain amplifier and the gain control end of the second voltage-controlled gain amplifier are connected, and the common connection end is the gain control end of the signal conditioning circuit;The output end of the first band-pass filter is the first output end of the signal conditioning circuit;The output end of the second band-pass filter is the second output end of the signal conditioning circuit.

[0008] Preferably, the cross-correlation circuit comprises, in sequence, an analog voltage-controlled delay chip, an analog multiplier chip, a low-pass filter, and a scanning voltage generation circuit; a signal input end of the analog voltage-controlled delay chip is connected to a second output end of the signal conditioning circuit; a delay control end of the analog voltage-controlled delay chip is connected to an output end of the scanning voltage generation circuit; a first input end of the analog multiplier chip is connected to a first output end of the signal conditioning circuit; a second input end of the analog multiplier chip is connected to a signal output end of the analog voltage-controlled delay chip; an input end of the low-pass filter is connected to a product output end of the analog multiplier chip; and an output end of the low-pass filter is an output end of the cross-correlation circuit.

[0009] Preferably, the scanning voltage generation circuit comprises a first voltage-controlled oscillator, a second voltage-controlled oscillator, a multipath analog switch chip, and an integral operator; address control ends of the multipath analog switch chip are connected to a first control output end group of the control circuit; an output end of the first voltage-controlled oscillator and an output end of the second voltage-controlled oscillator are respectively connected to two input ends of the multipath analog switch chip; a common output end of the multipath analog switch chip is connected to an input end of the integral operator; an output end of the integral operator is an output end of the scanning voltage generation circuit, and is connected to a delay control end of the analog voltage-controlled delay chip, and serves as a flyback synchronization signal output end of the cross-correlation circuit.

[0010] Preferably, the sampling circuit comprises a first voltage comparator, a peak value holder, and a double-channel sampling and holding chip; a same-phase input end of the first voltage comparator is connected to a signal input end of the peak value holder, and the connection end is an input end of the sampling circuit; a peak value output end of the peak value holder is connected to an opposite-phase input end of the first voltage comparator; a reset control end of the peak value holder is connected to an output end of the first voltage comparator; the output end of the first voltage comparator is a pulse output end of the sampling circuit, and is connected to a sampling trigger end of the double-channel sampling and holding chip; a first-channel input end of the double-channel sampling and holding chip is connected to an output end of the cross-correlation circuit; a first-channel output end of the double-channel sampling and holding chip is a first sampling output end of the sampling circuit; a second-channel input end of the double-channel sampling and holding chip is connected to a delay control end of the analog voltage-controlled delay chip; and a second-channel output end of the double-channel sampling and holding chip is a second sampling output end of the sampling circuit.

[0011] Preferably, the inverting input of the first voltage comparator is connected to the peak output of the peak hold via a dynamic bias circuit; the dynamic bias circuit includes a sample-and-hold circuit, a single-pole double-throw analog switch chip, a voltage divider network, and a reference voltage source; the input of the sample-and-hold circuit is connected to the peak output of the peak hold; the output of the sample-and-hold circuit and the output of the reference voltage source are connected to a first node via the voltage divider network; the first node is connected to the inverting input of the first voltage comparator; the common terminal of the single-pole double-throw analog switch chip is connected to the logic control terminal of the sample-and-hold circuit, its first selection terminal is connected to a fixed level, and its second selection terminal is connected to the output of the first voltage comparator; the control terminal of the single-pole double-throw analog switch chip is connected to the bias mode switching terminal of the control circuit.

[0012] Preferably, the discrimination circuit includes a second voltage comparator, a third voltage comparator, an AND gate logic chip, and a dual-output analog switch chip;

[0013] The non-inverting input of the second voltage comparator (U16A) is connected to the first sampling output of the sampling circuit, and its inverting input is connected to the first reference voltage source.

[0014] The non-inverting input of the third voltage comparator is connected to the second sampling output of the sampling circuit, and its inverting input is connected to the second reference voltage source.

[0015] The output terminals of the second and third voltage comparators are respectively connected to the two input terminals of the AND gate logic chip; the output terminal of the AND gate logic chip is the flag output terminal of the discrimination circuit and is connected to the enable terminal of the dual-output analog switch chip; the two input terminals of the dual-output analog switch chip are respectively connected to the non-inverting input terminal of the second and third voltage comparators; the two output terminals of the dual-output analog switch chip are the first feature output terminal and the second feature output terminal of the discrimination circuit.

[0016] The beneficial effects of this utility model are: 1. By adopting a dual-sensor signal acquisition and cross-correlation hardware architecture, the anti-interference capability of road vibration signals is significantly improved, the signal-to-noise ratio of characteristic parameters is effectively increased, and the data cleaning cost of subsequent big data processing is reduced;

[0017] 2. By using the cross-correlation hardware circuit and peak-triggered synchronous sampling circuit in the analog domain, the time difference characteristics and signal strength characteristics that are strongly correlated with the road surface condition are directly and in real time, forming a standardized feature vector that can be directly used by the subsequent system. This improves the quality from the data source and reduces the data cleaning and preprocessing burden of the backend big data processing.

[0018] 3. It has the ability to adaptively adjust signal conditioning and sampling parameters, which can adapt to the differences in vibration signals of different road sections, improve the universality of collected data, and support cross-scenario big data fusion analysis. Attached Figure Description

[0019] Figure 1 This is a system architecture diagram of a road feature vector extraction device based on cross-correlation time difference analysis;

[0020] Figure 2 This is a circuit structure diagram of a specific embodiment of the signal conditioning circuit in this utility model;

[0021] Figure 3 This is a circuit structure diagram of one specific embodiment of the cross-correlation circuit in this utility model;

[0022] Figure 4 This is a circuit structure diagram of one specific embodiment of the sampling circuit in this utility model;

[0023] Figure 5 This is a circuit structure diagram of one specific embodiment of the discrimination circuit in this utility model.

[0024] Figure Labels

[0025] In the signal conditioning circuit, RfA is the current-limiting resistor (first channel), CfA is the feedback capacitor (first channel), RdcA is the DC feedback resistor (first channel), R1A_hp is the first high-pass resistor (first channel), R2A_hp is the second high-pass resistor (first channel), C1A_hp is the first high-pass capacitor (first channel), R1A_lp is the first low-pass resistor (first channel), R2A_lp is the second low-pass resistor (first channel), and C1A_lp is the first low-pass capacitor (first channel).

[0026] RfB is the current-limiting resistor (second channel), CfB is the feedback capacitor (second channel), RdcB is the DC feedback resistor (second channel), R1B_hp is the first high-pass resistor (second channel), R2B_hp is the second high-pass resistor (second channel), C1B_hp is the first high-pass capacitor (second channel), R1B_lp is the first low-pass resistor (second channel), R2B_lp is the second low-pass resistor (second channel), and C1B_lp is the first low-pass capacitor (second channel).

[0027] Rin_int is the integrating input resistor, R1 is the first bias resistor, R2 is the second bias resistor, R5 is the clamping resistor, R6 is the integrating bias resistor, Cf_int is the integrating capacitor, U1 is the microcontroller, U2A is the first precision operational amplifier, U2B is the second precision operational amplifier, U3A is the first voltage-controlled gain amplifier, U3B is the second voltage-controlled gain amplifier, U4A is the first bandpass filter, U4A_1 is the first high-pass operational amplifier, U4A_2 is the first low-pass operational amplifier, U4B is the second bandpass filter, U4B_1 is the second high-pass operational amplifier, U4B_2 is the second low-pass operational amplifier, U5 is the analog voltage-controlled delay chip, U6 is the analog multiplier chip, U7 is the low-pass filter, and U8A is the first voltage-controlled delay chip. The oscillator is as follows: U8B is the second voltage-controlled oscillator; U9 is a multi-channel analog switch chip; U10A is an integrator; U11A is the first voltage comparator; U12 is a peak hold circuit; U13 is a dual-channel sample-and-hold chip; U14 is a sample-and-hold circuit; U15 is a single-pole double-throw analog switch chip; U16A is the second voltage comparator; U16B is the third voltage comparator; U17 is an AND gate logic chip; U18 is a dual-output analog switch chip; U19 is the first reference voltage chip; U20 is the second reference voltage chip; U21 is the third reference voltage chip; D1 is a Zener diode; W1 is the first precision potentiometer; W2 is the second precision potentiometer; GND_A is analog ground; and GND_D is digital ground. Detailed Implementation

[0028] The technical solution of this utility model is described in further detail below with reference to the accompanying drawings, but the scope of protection of this utility model is not limited to the following description.

[0029] The features and performance of this utility model will be further described in detail below with reference to embodiments.

[0030] Example 1

[0031] like Figure 1As shown, a road feature vector extraction device based on cross-correlation time difference analysis includes a signal input interface, a signal conditioning circuit, a cross-correlation circuit, a sampling circuit, a discrimination circuit, and a control circuit. The output terminal of the signal input interface is connected to the input terminal of the signal conditioning circuit. The first and second output terminals of the signal conditioning circuit are respectively connected to the first and second input terminals of the cross-correlation circuit. The output terminal of the cross-correlation circuit is connected to the input terminal of the sampling circuit. The first and second sampling output terminals of the sampling circuit are respectively connected to the first and second signal input terminals of the discrimination circuit. The device also includes a first feature output port and a second feature output port. The first and second feature output terminals of the discrimination circuit are respectively connected to the first and second feature output ports. The pulse output terminal of the sampling circuit is connected to the enable terminal of the discrimination circuit. The flag output terminal of the discrimination circuit is connected to the input terminal of the control circuit.

[0032] The first control output terminal group of the control circuit includes two output terminals, which are respectively connected to the two control terminals of the cross-correlation circuit; the second control output terminal of the control circuit is connected to the gain control terminal of the signal conditioning circuit; and the flyback detection input terminal of the control circuit is connected to the flyback synchronization signal output terminal of the cross-correlation circuit.

[0033] The signal input interface is defined as a first input port and a second input port, such as Figure 2 As shown, the signal pin of the first input port is connected to the input node IN_A of the first channel of the signal conditioning circuit, and its reference ground pin is connected to analog ground (GND_A) for connecting to the first road vibration sensor. The signal pin of the second input port is connected to the input node IN_B of the second channel of the signal conditioning circuit, and its reference ground pin is also connected to analog ground (GND_A) for connecting to the second road vibration sensor.

[0034] Specifically, the control circuit is implemented by a microcontroller U1, such as an STM32H743. One of its input pins (e.g., PC13) is connected to the flag output pin of the discrimination circuit; one of its ADC input pins (e.g., PC2) serves as a retrace detection input pin, connected to the retrace synchronization signal output of the cross-correlation circuit. In the specific implementation, this retrace synchronization signal output is a detectable delay control voltage node V_CTRL. The microcontroller U1 continuously samples this voltage node through its internal analog-to-digital converter. When the sampled value reaches a preset threshold (corresponding to V_CTRL voltage approaching the clamping voltage, such as 2.9V), the scan is considered complete, and retracement must be initiated. Two of its GPIO pins (e.g., PB0 and PC1) serve as the first control output group, connected to the address control pin of the multi-channel analog switch chip U9 in the cross-correlation circuit; one of its DAC output pins (e.g., PA4) serves as the second control output pin, connected to the gain control terminal of the signal conditioning circuit. U1 is powered by a +3.3V digital power supply, and its digital ground (GND_D) pin is connected to the system's digital ground.

[0035] Furthermore, the first and second feature output ports are specifically implemented as two sets of standard analog voltage output interfaces, such as terminal blocks or SMA connectors. The two output pins of the dual-output analog switch chip (U18) of the discrimination circuit are directly connected to the signal pins of the first and second feature output ports respectively via traces on the circuit board. When the discrimination circuit determines that a feature is valid, U18 is turned on, and the two feature voltages (cross-correlation amplitude and time delay control voltage) are synchronously output to the corresponding feature output ports, which can be acquired by an external data logger or analog-to-digital converter, thereby completing the hardware extraction and output of the road feature vector.

[0036] The device requires an external power supply of ±12V, ±5V, and +3.3V DC operating voltages to power the analog and digital circuits, respectively. To achieve good anti-interference performance, the grounding terminals of all analog circuits should be connected to analog ground (GND_A), and the grounding terminals of all digital circuits should be connected to digital ground (GND_D). The analog ground (GND_A) and digital ground (GND_D) should be connected at a single point near the power input via a 0Ω resistor or ferrite bead.

[0037] All electronic components in the signal input interface, signal conditioning circuit, cross-correlation circuit, sampling circuit, discrimination circuit, and control circuit described in this embodiment can be integrated and electrically connected on a single printed circuit board to form an independent hardware testing device.

[0038] The overall workflow of the device described in this embodiment is as follows: Two spatially fixed road vibration sensors send the collected vibration signals to the device through signal input interfaces. The signals are first pre-processed by a signal conditioning circuit, including amplification and filtering, to improve the signal-to-noise ratio and limit the frequency band. The two processed signals are then sent to a cross-correlation circuit. One signal is subjected to a variable delay regulated by a controlled voltage and then multiplied with the other signal using an analog multiplication operation. The product is then low-pass filtered to output a cross-correlation signal reflecting the change in the similarity between the two signals over time. This cross-correlation output signal enters a sampling circuit, which detects the occurrence of cross-correlation peaks in real time. When a valid peak is detected, the sampling circuit not only outputs a trigger pulse but also simultaneously acquires and maintains the current cross-correlation amplitude (first feature) and generates the delay control voltage value corresponding to the peak (second feature). These two feature values ​​are sent to a discrimination circuit, which compares them with a preset threshold. If both exceed the threshold, it is determined to be a valid road feature event, and a flag signal is output. Simultaneously, the two feature values ​​are routed to the feature output terminal of the device. During this hardware coordination process, the microcontroller U1 monitors the level of its input pin (PC13) in real time. When it detects that the characteristic valid flag signal output by the discrimination circuit goes high, U1 immediately sets the output level of its first control output group (PB0, PC1) to logic '00' and holds it for a predetermined time. This operation switches the multiplexed analog switch chip (U9) in the cross-correlation circuit to its internal ground channel, causing the input of the integrator (U10A) to return to zero, thereby quickly resetting the delay control voltage node V_CTRL to a low level, thus resetting the scan voltage.

[0039] This embodiment constructs a complete system architecture for a road feature vector extraction device based on cross-correlation time-of-flight analysis, clarifying the hardware framework and interconnections consisting of signal input, conditioning, cross-correlation calculation, peak detection and sampling, discrimination, and a central control circuit. It lays the foundation for the entire device's functionality and emphasizes the power supply and grounding isolation design for analog and digital circuits.

[0040] Example 2

[0041] This embodiment provides a specific implementation of a signal conditioning circuit based on Embodiment 1.

[0042] like Figure 2 As shown, the signal conditioning circuit includes a symmetrical first channel (corresponding to input node IN_A) and a second channel (corresponding to input node IN_B).

[0043] The first channel includes a charge amplifier, a first voltage-controlled gain amplifier U3A, and a first bandpass filter U4A connected in sequence.

[0044] The charge amplifier for the first channel is built using a first precision operational amplifier U2A (e.g., OPA2188); the charge amplifier for the second channel is built using a second precision operational amplifier U2B (e.g., OPA2188), with completely symmetrical circuit topology and device parameters to the first channel. The power supply pins of U2A / U2B are connected to +12V_A, -12V_A, and analog ground (GND_A). Taking the first channel as an example: the output is connected to the inverting input of U2A through a current-limiting resistor RfA (e.g., 100MΩ); a feedback capacitor CfA (e.g., 100pF) is connected in parallel between the inverting input and output of U2A, and a DC feedback resistor RdcA (e.g., 1GΩ) is connected in parallel across CfA. The non-inverting input of U2A is directly connected to analog ground (GND_A). Its output is connected to the input of the first voltage-controlled gain amplifier U3A.

[0045] The gain control terminal of the first voltage-controlled gain amplifier U3A (such as AD8337) is shared with the corresponding gain control terminal of U3B in the second channel, forming the gain control terminal, which is connected to the DAC output pin (PA4) of the microcontroller U1. The power supply pins of U3A are connected to +12V_A, -12V_A, and analog ground (GND_A). The output terminal of U3A is connected to the input terminal of the first bandpass filter.

[0046] The first bandpass filter is a fourth-order Butterworth type with a passband of 1Hz to 1kHz, implemented by cascading two operational amplifiers (U4A_1, U4A_2, optional OPA2188):

[0047] U4A_1 (High-pass stage, 1Hz cutoff): Configured as a Saleen-Kai high-pass filter. The output of U3A is connected to its inverting input via a first high-pass resistor R1A_hp (1MΩ), and a first high-pass capacitor C1A_hp (0.16uF) is connected between the inverting input and the output. Its non-inverting input is connected to analog ground (GND_A) via a second high-pass resistor R2A_hp (1MΩ). The power supply pins of U4A_1 are connected to +12V_A, -12V_A, and analog ground (GND_A).

[0048] U4A_2 (low-pass stage, cutoff frequency 1kHz): configured as a Saleen-Kai low-pass filter. The output of U4A_1 is connected to its inverting input via a first low-pass resistor R1A_lp (1.6kΩ), and a first low-pass capacitor C1A_lp (0.1uF) is connected between the inverting input and the output. Its non-inverting input is connected to analog ground (GND_A) via a second low-pass resistor R2A_lp (1.6kΩ). The power supply pins of U4A_2 are connected to +12V_A, -12V_A, and analog ground (GND_A). The output of U4A_2 is the first output terminal OUT_A of the signal conditioning circuit.

[0049] The second channel circuit is completely symmetrical to the first channel, such as... Figure 2 As shown.

[0050] The first and second channels of the signal conditioning circuit operate in parallel. Taking the first channel as an example, the weak charge signal from the piezoelectric sensor first enters the charge amplifier composed of the first precision operational amplifier U2A. This circuit converts the high-impedance charge signal into a low-impedance voltage signal and performs preliminary amplification. Subsequently, the voltage signal is sent to the voltage-controlled gain amplifier U3A, whose amplification factor is linearly controlled by the analog voltage output from the DAC pin of the microcontroller U1, thereby realizing programmable gain adjustment to adapt to input signals of different amplitudes. Finally, the signal passes through a fourth-order Butterworth bandpass filter composed of cascaded U4A_1 and U4A_2. This filter strictly limits the frequency band of the signal (1Hz-1kHz), which covers the spectrum of mainstream road vibration signals caused by vehicles passing by. It can effectively suppress low-frequency environmental sway and high-frequency electrical noise, effectively suppress out-of-band noise and interference, and provide a clean and frequency-consistent signal for subsequent cross-correlation analysis. The operation of the second channel is completely symmetrical with that of the first channel, ensuring that the amplitude and phase characteristics of the two signal conditioning are consistent.

[0051] This embodiment details a specific circuit implementation of a signal conditioning circuit. Its core lies in using a charge amplifier to process the sensor signal, followed by cascading a voltage-controlled gain amplifier and a bandpass filter. This design achieves high-impedance conversion, programmable amplification, and rigorous bandpass filtering, ensuring that the two signals required for subsequent cross-correlation processing have sufficient amplitude, a good signal-to-noise ratio, and consistent bandwidth characteristics. It is a key front-end circuit for improving the measurement accuracy and adaptability of the entire device.

[0052] Example 3

[0053] This embodiment provides a specific implementation of a cross-correlation circuit based on embodiment 1.

[0054] like Figure 3 As shown, the cross-correlation circuit includes an analog voltage control delay chip U5, an analog multiplier chip U6, a low-pass filter U7, and a scanning voltage generation circuit.

[0055] The second output terminal OUT_B of the signal conditioning circuit is connected to the signal input pin (IN) of the analog voltage control delay chip U5 (e.g., AD8344). The power supply pin of U5 is connected to +5V_A and analog ground (GND_A). The first output terminal OUT_A of the signal conditioning circuit is connected to the first input pair pin X1 (X2 pin grounded) of the analog multiplier chip U6 (e.g., AD835). The signal output pin (OUT) of the analog voltage control delay chip U5 is connected to the second input pair pin Y1 (Y2 pin grounded) of the analog multiplier chip U6. The power supply pin of U6 is connected to +12V_A, -12V_A, and analog ground (GND_A). The product output pin (OUT) of the analog multiplier chip U6 is connected to the input pin (IN) of the low-pass filter U7 (e.g., LTC1562-2). The power supply pin of U7 is connected to +5V_A and -5V_A. The output pin (OUT) of U7 is the output terminal U7_OUT of the cross-correlation circuit.

[0056] In the scanning voltage generation circuit, the control pins (VCO) of the first voltage-controlled oscillator U8A and the second voltage-controlled oscillator U8B (which can be LM566) are connected to +5V_A and analog ground (GND_A) respectively through a 10kΩ precision potentiometer (W1 / W2). The frequencies of the two oscillation signals can be manually set by adjusting the potentiometers to adapt to different frequency bands of road vibration signals. The output pins of the first voltage-controlled oscillator U8A and the second voltage-controlled oscillator U8B are connected to the two input pins S1 and S2 of the multi-channel analog switch chip U9 (such as ADG704). The unused input pins S3 and S4 of U9 are directly connected to analog ground (GND_A). The power supply pins of U9 are connected to +5V_A and analog ground (GND_A). The address control pins A0 and A1 of the multi-channel analog switch chip U9 are connected to the first control output pins (PB0, PC1) of the microcontroller U1, and its common output pin COM is connected to the inverting input of the integrator U10A. The integrator U10A is composed of an operational amplifier (such as OPA2188). Its inverting input is connected to the COM pin of U9 through an integrating input resistor Rin_int (10kΩ), and its output is connected through an integrating capacitor Cf_int (1nF). Its non-inverting input is connected to analog ground (GND_A) through a 10kΩ integrating bias resistor R6. A 10kΩ clamping resistor R5 is connected in series between its output and the +3.3V_A power supply. Simultaneously, the output is connected to the cathode of a 3.0V unidirectional Zener diode D1 (such as BZT52C3V0), and the anode of this Zener diode D1 is connected to analog ground (GND_A). This circuit clamps the output voltage from 0V to approximately 3.2V, ensuring that the delay control voltage supplied to the analog voltage control delay chip U5 strictly conforms to its 0V to +3V input voltage range, while preventing integrator saturation. The power supply pins of U10A are connected to +12V_A, -12V_A, and analog ground (GND_A). The output of the integrator U10A is defined as the delay control voltage node V_CTRL. This node is connected to the delay control terminal of the analog voltage control delay chip (U5) as its control voltage. This node voltage is the scan voltage generated by the scan voltage generation circuit and serves as a monitoring point for the internal operating status of the system.

[0057] During the scanning phase, microcontroller U1 controls the multiplexer analog switch chip U9 to select either the first voltage-controlled oscillator U8A or the second voltage-controlled oscillator U8B. The V_CTRL voltage rises linearly under integration. This rising voltage signal is simultaneously output through the flyback synchronization signal output terminal (i.e., the V_CTRL node) of the cross-correlation circuit, allowing microcontroller U1 to perform closed-loop monitoring. Microcontroller U1 acquires this voltage in real time through its flyback detection input pin (PC2). When the V_CTRL voltage rises to near the clamping voltage (approximately 3.0V, i.e., the breakdown threshold of Zener diode D1), microcontroller U1 determines that the current scanning cycle has ended. It then changes the address state of the multiplexer analog switch chip U9 through its first control output group (PB0, PC1) (e.g., switching from selecting the voltage-controlled oscillator to its internal ground channel), causing the input of the integrator U10A to become zero, and its output voltage V_CTRL to quickly reset to a low level (approximately 0V), thus completing one scan-flyback cycle. Afterwards, U1 can switch the address of U9 again to start the next round of delayed scanning. This method, in which the microcontroller U1 actively monitors the V_CTRL voltage and controls its periodic reset, constitutes the system's inherent scan-reverse synchronization mechanism, enabling the cross-correlation circuit to continuously and stably search for the time difference characteristics between signals.

[0058] The core function of the cross-correlation circuit is to calculate the cross-correlation function of the two input signals. The first signal output from the signal conditioning circuit is directly sent to one input terminal (X1) of the analog multiplier U6. The second signal is first sent to the analog voltage-controlled delay chip U5. U5 applies a controllable time delay to the signal according to the voltage value on its delay control pin (V_CTRL). The delayed signal is then sent to the other input terminal (Y1) of the multiplier U6. U6 multiplies the two signals, and its output is smoothed by the low-pass filter U7 to obtain an approximate cross-correlation value of the two signals under a certain delay. To scan for the cross-correlation peak, the circuit integrates a scanning voltage generation circuit: the microcontroller U1 controls the multi-channel analog switch U9 through the GPIO pin to select the input of different frequency oscillation signals generated by the first voltage-controlled oscillator U8A or the second voltage-controlled oscillator U8B. This scanning signal is integrated by the integrator U10A to generate a continuously changing ramp voltage, which serves as the delay control voltage of U5, thus enabling the signal delay to scan linearly with time. The clamping circuit ensures that the scanning voltage is within the safe operating range of U5.

[0059] This embodiment provides a specific implementation of a cross-correlation circuit, illustrating the implementation method of the cross-correlation circuit based on analog multipliers and voltage-controlled delay technology, as well as the delayed scanning voltage generation circuit designed for peak searching. This scheme utilizes analog circuits to achieve real-time cross-correlation operations and flexibly adapts to road vibration signals of different frequency bands through a programmable scanning signal source, providing a hardware foundation for accurately extracting the time difference (corresponding to the delayed control voltage) between two signals.

[0060] Example 4

[0061] This embodiment provides a specific implementation of the sampling circuit based on embodiment 3.

[0062] like Figure 4 As shown, the sampling circuit includes a first voltage comparator U11A, a peak hold circuit U12, and a dual-channel sample-and-hold chip U13 (such as AD783).

[0063] The output terminal U7_OUT of the cross-correlation circuit is simultaneously connected to the non-inverting input terminal of the first voltage comparator U11A (such as ADCMP572) and the signal input terminal of the peak hold circuit U12 (such as AD585). The power supply pin of U12 is connected to +5V_A, -5V_A and analog ground (GND_A).

[0064] The peak output of peak hold U12 is connected to the input of the dynamic bias circuit, and the output of the dynamic bias circuit (i.e., node A) is connected to the inverting input of the first voltage comparator U11A; simultaneously, its reset control terminal (RST) is directly connected to the output of the first voltage comparator U11A. This connection forms the core closed loop: when the cross-correlation output signal exceeds the currently held peak value, the voltage comparator flips and outputs a high-level pulse. This pulse, while triggering sampling, resets the peak hold, causing it to begin tracking a new, higher signal level.

[0065] The dynamic bias circuit provides a switchable bias voltage to the inverting input of the comparator. It includes a sample-and-hold circuit U14, a single-pole double-throw analog switch chip U15, first bias resistors R1 (10kΩ) and R2 (40kΩ), and a reference voltage source VREF. The third reference voltage chip U21 provides the reference voltage source VREF. It uses a precision reference voltage chip (such as REF5025) and outputs a 2.5V precision DC voltage. Its power supply pin is connected to +5V_A, and its ground pin is connected to analog ground (GND_A).

[0066] The peak output of peak hold U12 is connected to the input pin IN of sample-and-hold U14 (such as LF398). The output pin (OUT) of U14 is connected to one end of the first bias resistor R1. The other end of R1 and one end of R2 are connected to node A, and the other end of R2 is connected to the output of the reference source VREF. Node A is connected to the inverting input of the first voltage comparator U11A.

[0067] The logic control pin LCH of sample-and-hold circuit U14 is connected to the common pin COM of single-pole double-throw analog switch chip U15. The two select pins S1 and S2 of U15 are connected to a fixed low level (e.g., GND_A) and the output of the first voltage comparator U11A, respectively. The control pin (IN) of U15 is connected to a GPIO pin (e.g., PB2) of microcontroller U1 to receive the bias mode switching signal.

[0068] When U15 switches to S1 (ground), the control pin LCH of U14 is fixed low, and U14 remains in "tracking" mode, its output following the output of the peak hold. When U15 switches to S2 (connected to the output of U11A), the control logic of U14 is synchronized with signal detection: during a high-level pulse output by U11A (valid signal detected), the LCH pin of U14 is high, entering "hold" mode and latching the current peak voltage; when U11A outputs a low level, the LCH pin is low, returning to "tracking" mode and following the output of the peak hold. The reference voltage VREF is used to set an initial or minimum comparison threshold. Optionally, a delay circuit can be added between the output of the first voltage comparator U11A and the reset control terminal of the peak hold (U12) to ensure the priority and stability of the sampling trigger signal.

[0069] The power supply pins of U11A are connected to +5V_A and analog ground (GND_A). Its output is connected to the sampling trigger pin HOLD of the dual-channel sample-and-hold chip U13. The sampling trigger pin HOLD is active high, and a high-level pulse output from U11A can effectively trigger it. The first channel input pin CH1_IN of U13 is connected to the output U7_OUT of the cross-correlation circuit, and the second channel input pin CH2_IN of U13 is connected to the delay control voltage node V_CTRL, so that when the sampling trigger pin HOLD is triggered, the delay control voltage value at that moment is synchronously sampled and held as the second characteristic quantity. The power supply pins V+ and V- of U13 are connected to +5V_A and -5V_A, respectively, and the ground pin is connected to analog ground (GND_A), conforming to its datasheet's dual power supply requirements. The first channel output pin CH1_OUT of U13 is the first sampling output of the sampling circuit, and the second channel output pin CH2_OUT is the second sampling output.

[0070] It should be noted that there is a timing relationship between the high-level pulse output by the first voltage comparator U11A, the reset action of the peak hold circuit U12, and the capture action of the dual-channel sample-and-hold chip U13, which is determined by the characteristics of the devices themselves and ensures the reliable operation of the system:

[0071] Sampling and capture priority and instantaneous completion: The sample / hold switching of the dual-channel sample-and-hold chip U13 is triggered by the rising edge of the level on its HOLD pin. This action is a high-speed switching control with an extremely short setup time (typically in the nanosecond range). Once triggered, the output of U13 will instantly hold the voltage values ​​on its input pins CH1_IN and CH2_IN at the moment of triggering.

[0072] The peak hold reset is a relatively slow process: the reset operation of the peak hold U12 is the discharge process of its internal holding capacitor. There is a short delay on the order of microseconds from the time the reset signal is received until the voltage at its output terminal drops significantly.

[0073] Reliable timing guarantee: Based on the aforementioned device characteristics, when the cross-correlation signal exceeds the dynamic threshold, the high-level pulse edge output by the first voltage comparator U11A will first trigger and latch data to U13 within a very short time. Then, the output of the peak hold U12 will begin to slowly decrease under the action of its reset signal. This natural timing, formed by physical characteristics, ensures that the sampling circuit captures the stable, undisturbed amplitude of the cross-correlation signal and the delay control voltage value at the moment of peak detection trigger. The reset function of the peak hold U12 primarily serves to prepare for detecting the next potentially higher peak after the current valid peak value has been sampled, without affecting the accuracy of the current sampling.

[0074] The sampling circuit is responsible for detecting the peak value of the cross-correlation output signal and simultaneously sampling key data. The cross-correlation signal is simultaneously input to the non-inverting input of the first voltage comparator U11A and the input of the peak hold circuit U12. The peak hold circuit U12 tracks and holds the historical peak value of the input signal in real time. Its output is processed by the dynamic bias circuit (composed of U14, U15, R1, R2, and VREF) to provide a dynamic threshold for the inverting input of U11A. When the instantaneous value of the cross-correlation signal exceeds this dynamic threshold, the output of U11A jumps to a high-level pulse. This pulse has a dual function: first, it serves as a sampling trigger signal, sent to the HOLD pin of the dual-channel sample-and-hold chip U13, so that it simultaneously acquires and holds the current cross-correlation signal amplitude (CH1_IN input) and generates the delay control voltage value corresponding to the peak value (CH2_IN input); second, it feeds back to the reset terminal (RST) of the peak hold circuit U12, clearing it and starting to track the next possible higher peak value. U15 in the dynamic bias circuit is controlled by a microcontroller and can switch between different operating modes to change the threshold generation strategy.

[0075] This embodiment provides an implementation of a sampling circuit, and a specific circuit structure for peak detection and synchronous sampling. It employs a combination of peak hold and dynamic threshold comparison to reliably detect cross-correlation peak values, and utilizes the detection pulse to synchronously trigger the sampling and holding of two signals, ensuring the strict temporal correspondence between the extracted "cross-correlation amplitude" and "delay control voltage" features, providing accurate data pairs for subsequent discrimination.

[0076] Example 5

[0077] This embodiment provides a specific implementation of the discrimination circuit based on embodiment 1.

[0078] like Figure 5 As shown, the discrimination circuit includes a second voltage comparator U16A, a third voltage comparator U16B, an AND gate logic chip U17, and a dual-output analog switch chip U18.

[0079] The first sampling output terminal of the sampling circuit is connected to the non-inverting input terminal of the second voltage comparator U16A (e.g., ADCMP572), and its inverting input terminal is connected to the first reference voltage VREF1 (2.5V) generated by the first reference voltage chip U19 (e.g., REF5025). The power supply pin of U19 is connected to +5V_A, and the ground pin is connected to GND_A. The second sampling output terminal of the sampling circuit is connected to the non-inverting input terminal of the third voltage comparator U16B, and its inverting input terminal is connected to the second reference voltage VREF2 (3.0V) generated by the second reference voltage chip U20 (e.g., REF5030). The power supply pin of U20 is connected to +5V_A, and the ground pin is connected to GND_A. The power supply pins of U16A and U16B are connected to +5V_A and analog ground (GND_A).

[0080] The outputs of the second voltage comparator U16A and the third voltage comparator U16B are each connected to the two inputs of the AND gate logic chip U17 (such as SN74LVC1G08) through a level-shifting resistor divider network. Each divider network consists of a 1kΩ resistor (near the comparator output) and a 2kΩ resistor (near the AND gate input) connected in series. The other end of the 2kΩ resistor is connected to digital ground (GND_D), which is used to convert the 5V analog comparator output level to a digital level of approximately 3.33V to match the 3.3V power supply requirement of the AND gate logic chip U17. The power supply pin of U17 is connected to +3.3V_D and digital ground (GND_D). The output of AND gate logic chip U17 is connected to the enable pin (EN) of dual-output analog switch chip U18 (such as ADG884). This enable pin is active high and its input level range is compatible with 3.3V~5V. It can directly receive the 3.3V high-level signal output by AND gate logic chip U17. This enable pin is also connected to U1 (PC13) as the flag output pin of the discrimination circuit.

[0081] The two input pins of the dual-output analog switch chip U18 are connected to the non-inverting inputs of the second voltage comparator U16A and the third voltage comparator U16B, respectively. The power supply pins of U18 are connected to +5V_A and analog ground (GND_A). The two output pins of U18 are the first characteristic output and the second characteristic output of the discrimination circuit, respectively.

[0082] The discrimination circuit performs threshold discrimination and output control on the two feature quantities sent from the sampling circuit. The first sampled output (cross-correlation amplitude) is compared with the first reference voltage VREF1 in U16A. If the amplitude exceeds VREF1, U16A outputs a high level. The second sampled output (delay control voltage) is compared with the second reference voltage VREF2 in U16B. If the voltage exceeds VREF2, U16B outputs a high level. After level conversion, the results of these two comparisons are sent to AND gate U17 for logical AND operation. AND gate U17 outputs a high-level valid flag signal only when both feature quantities simultaneously exceed their respective preset thresholds. This flag signal serves as the feature valid flag output for the entire device and also enables the dual-channel analog switch U18. When enabled, U18 routes the two feature voltages from the sampling circuit (i.e., the non-inverting input voltages of U16A and U16B) to the first and second feature output pins of the device, respectively, completing the final output of the valid feature vector.

[0083] This embodiment provides a specific implementation circuit for feature discrimination and output interface. Two independent comparators are used to perform threshold judgments on the cross-correlation amplitude and time delay voltage, and AND gate logic is used to ensure that a valid road feature event is only determined when both conditions are met. This dual discrimination mechanism improves the system's anti-interference capability and reliability. Simultaneously, an analog switch is used to only conduct the output when the flag is valid, achieving controlled output of feature data.

[0084] The above description is merely a preferred embodiment of this utility model. It should be understood that this utility model is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this utility model should be protected within the scope of the appended claims.

Claims

1. A road surface feature vector extraction device based on cross-correlation time difference analysis, characterized by, The device comprises a signal input interface, a signal conditioning circuit, a cross-correlation circuit, a sampling circuit, a discrimination circuit and a control circuit. An output end of the signal input interface is connected to an input end of the signal conditioning circuit; first and second output ends of the signal conditioning circuit are connected to first and second input ends of the cross-correlation circuit respectively; an output end of the cross-correlation circuit is connected to an input end of the sampling circuit; first and second sampling output ends of the sampling circuit are connected to first and second signal input ends of the discrimination circuit respectively; the device further comprises first and second characteristic output ports, and first and second characteristic output ends of the discrimination circuit are connected to the first and second characteristic output ports respectively; A pulse output end of the sampling circuit is connected to an enable end of the discrimination circuit; a flag output end of the discrimination circuit is connected to an input end of the control circuit; A first control output end group of the control circuit comprises two output ends connected to two control ends of the cross-correlation circuit respectively; a second control output end of the control circuit is connected to a gain control end of the signal conditioning circuit; a flyback detection input end of the control circuit is connected to a flyback synchronization signal output end of the cross-correlation circuit.

2. The road surface feature vector extraction device based on cross-correlation time difference analysis according to claim 1, characterized by, The signal conditioning circuit comprises a first channel and a second channel; The first channel comprises a first charge amplifier, a first voltage-controlled gain amplifier (U3A) and a first band-pass filter; an output end of the first charge amplifier is connected to an input end of the first voltage-controlled gain amplifier (U3A), and an output end of the first voltage-controlled gain amplifier (U3A) is connected to an input end of the first band-pass filter; The second channel comprises a second charge amplifier, a second voltage-controlled gain amplifier (U3B) and a second band-pass filter; an output end of the second charge amplifier is connected to an input end of the second voltage-controlled gain amplifier (U3B), and an output end of the second voltage-controlled gain amplifier (U3B) is connected to an input end of the second band-pass filter; A gain control end of the first voltage-controlled gain amplifier (U3A) is connected to a gain control end of the second voltage-controlled gain amplifier (U3B), and the connection end is a gain control end of the signal conditioning circuit; An output end of the first band-pass filter is a first output end of the signal conditioning circuit, and an output end of the second band-pass filter is a second output end of the signal conditioning circuit.

3. The road surface feature vector extraction device based on cross-correlation time difference analysis according to claim 1, characterized by, The cross-correlation circuit comprises an analog voltage-controlled delay chip (U5), an analog multiplier chip (U6), a low-pass filter (U7) and a scanning voltage generation circuit connected in sequence. The signal input end of the analog voltage control delay chip (U5) is connected to the second output end of the signal conditioning circuit; the delay control end of the analog voltage control delay chip (U5) is connected to the output end of the scanning voltage generation circuit; the first input end of the analog multiplier chip (U6) is connected to the first output end of the signal conditioning circuit; the second input end of the analog multiplier chip (U6) is connected to the signal output end of the analog voltage control delay chip (U5); the input end of the low-pass filter (U7) is connected to the product output end of the analog multiplier chip (U6); and the output end of the low-pass filter (U7) is the output end of the cross-correlation circuit.

4. The road surface feature vector extraction device based on cross-correlation time difference analysis according to claim 3, characterized by, The scanning voltage generation circuit comprises a first voltage-controlled oscillator (U8A), a second voltage-controlled oscillator (U8B), a multi-path analog switch chip (U9), and an integral operator (U10A); the address control end of the multi-path analog switch chip (U9) is connected to the first control output end group of the control circuit; the output end of the first voltage-controlled oscillator (U8A) and the output end of the second voltage-controlled oscillator (U8B) are respectively connected to two input ends of the multi-path analog switch chip (U9); the common output end of the multi-path analog switch chip (U9) is connected to the input end of the integral operator (U10A); the output end of the integral operator (U10A) is the output end of the scanning voltage generation circuit, and is connected to the delay control end of the analog voltage control delay chip (U5), and serves as the flyback synchronization signal output end of the cross-correlation circuit.

5. The road surface feature vector extraction device based on cross-correlation time difference analysis according to claim 4, characterized by, The sampling circuit comprises a first voltage comparator (U11A), a peak value holder (U12), and a double-channel sampling and holding chip (U13); The non-inverting input end of the first voltage comparator (U11A) is connected to the signal input end of the peak value holder (U12), and the common connection end is the input end of the sampling circuit; The peak value output end of the peak value holder (U12) is connected to the inverting input end of the first voltage comparator (U11A); The reset control end of the peak value holder (U12) is connected to the output end of the first voltage comparator (U11A); The output end of the first voltage comparator (U11A) is the pulse output end of the sampling circuit, and is connected to the sampling trigger end of the double-channel sampling and holding chip (U13); The first channel input end of the double-channel sampling and holding chip (U13) is connected to the output end of the cross-correlation circuit; and the first channel output end of the double-channel sampling and holding chip (U13) is the first sampling output end of the sampling circuit. The second channel input end of the double-channel sampling and holding chip (U13) is connected to the delay control end of the analog voltage control delay chip (U5); and the second channel output end of the double-channel sampling and holding chip (U13) is the second sampling output end of the sampling circuit.

6. The road surface feature vector extraction device based on cross-correlation time difference analysis according to claim 5, characterized by, The inverting input terminal of the first voltage comparator (U11A) is connected to the peak output terminal of the peak holder (U12) through a dynamic bias circuit; the dynamic bias circuit comprises a sample holder, a single-pole double-throw analog switch chip, a voltage dividing resistor network and a reference voltage source; The input terminal of the sample holder (U14) is connected to the peak output terminal of the peak holder (U12); the output terminal of the sample holder (U14) and the output terminal of the reference voltage source are connected to a first node through the voltage dividing resistor network; the first node is connected to the inverting input terminal of the first voltage comparator (U11A); the common terminal of the single-pole double-throw analog switch chip (U15) is connected to the logic control terminal of the sample holder (U14), the first selection terminal is connected to a fixed level, and the second selection terminal is connected to the output terminal of the first voltage comparator (U11A); the control terminal of the single-pole double-throw analog switch chip (U15) is connected to the bias mode switching terminal of the control circuit.

7. The road surface feature vector extraction device based on cross-correlation time difference analysis according to claim 5, characterized by, The discrimination circuit comprises a second voltage comparator (U16A), a third voltage comparator (U16B), an AND gate logic chip (U17) and a dual-path output analog switch chip (U18); The non-inverting input terminal of the second voltage comparator (U16A) is connected to the first sample output terminal of the sampling circuit, and the inverting input terminal is connected to a first reference voltage source (U19); The non-inverting input terminal of the third voltage comparator (U16B) is connected to the second sample output terminal of the sampling circuit, and the inverting input terminal is connected to a second reference voltage source (U20); The output terminals of the second voltage comparator (U16A) and the third voltage comparator (U16B) are respectively connected to the two input terminals of the AND gate logic chip (U17); The output terminal of the AND gate logic chip (U17) is the flag output terminal of the discrimination circuit and is connected to the enable terminal of the dual-path output analog switch chip (U18); The two input terminals of the dual-path output analog switch chip (U18) are respectively connected to the non-inverting input terminal of the second voltage comparator (U16A) and the non-inverting input terminal of the third voltage comparator (U16B); the two output terminals of the dual-path output analog switch chip (U18) are respectively the first characteristic output terminal and the second characteristic output terminal of the discrimination circuit.

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