Solar cell

Abstract

The utility model discloses a solar cell. The solar cell comprises a substrate and a passivation layer, the substrate comprises a first plate surface, a second plate surface and a plurality of side surfaces, the first plate surface and the second plate surface are opposite to each other, the side surfaces are connected with the first plate surface and the second plate surface, the first plate surface is provided with a plurality of first electrode structures and a plurality of second electrode structures, and the roughness of the first side surface in the side surfaces is smaller than that of the second plate surface; the passivation layer comprises a first passivation part and a second passivation part, the first passivation part covers the first side surface and is in direct contact with the first side surface, and the second passivation part covers the part, close to the first side surface, of the second plate surface and the part, close to the first side surface, of the first plate surface; in the direction perpendicular to the first side face and away from the first side face, the thickness of the part, covering the first plate face, of the second passivation part is gradually reduced, and / or the thickness of the part, covering the second plate face, of the second passivation part is gradually reduced. The edge passivation effect of the solar cell is better, and an assembly formed by the solar cell has higher efficiency.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a solar cell. Background Technology

[0002] With the development of the photovoltaic industry, the conversion efficiency of crystalline silicon solar cells is continuously improving, gradually approaching its theoretical limit. To further increase the light-receiving area of ​​the cells, high-efficiency cells are trending towards a shift from double-sided contact to back-contact (BC) technology. Unobstructed front-side electrodes in solar cells can lead to a 2%-3% increase in short-circuit current (Isc). From the perspective of surface passivation technology, BC cells can be further divided into TBC cells based on tunneling oxide passivation contact (TOPCon) technology, HBC cells based on heterojunction (HJT) technology, and HPBC cells based on hybrid passivation technologies (Al-BSF, PERC, TOPCon, HJT, etc.). Among these, TBC cells offer higher cost-effectiveness and have greater industrialization potential. Utility Model Content

[0003] At least one embodiment of this disclosure provides a solar cell, which includes a substrate and a passivation layer. The substrate includes a first plate surface and a second plate surface disposed opposite to each other, and a plurality of side surfaces connecting the first plate surface and the second plate surface. The first plate surface is provided with a plurality of first electrode structures and a plurality of second electrode structures. The plurality of side surfaces include a first side surface, the roughness of which is less than that of the second plate surface. The passivation layer includes a first passivation portion and a second passivation portion. The first passivation portion covers the first side surface and is in direct contact with it. The second passivation portion covers the portion of the second plate surface near the first side surface and the portion of the first plate surface near the first side surface.

[0004] For example, in a solar cell provided in at least one embodiment of this disclosure, the thickness of the portion of the second passivation portion covering the first plate surface gradually decreases in a direction perpendicular to and away from the first side surface, and / or the thickness of the portion of the second passivation portion covering the second plate surface gradually decreases.

[0005] For example, in a solar cell provided in at least one embodiment of this disclosure, the plurality of sides further includes a second side, the roughness of the first side is less than the roughness of the second side, and the roughness of the second side is substantially the same as the roughness of the second plate surface.

[0006] For example, in at least one embodiment of the solar cell provided in this disclosure, the first side is a surface formed by a machining process, and the second plate surface is a surface formed by a texturing process.

[0007] For example, in a solar cell provided in at least one embodiment of this disclosure, the second plate surface includes a first micromorphology with a plurality of protrusions, and the first side surface does not include the first micromorphology.

[0008] For example, in a solar cell provided in at least one embodiment of this disclosure, all of the plurality of sides except the first side include the first micromorphology.

[0009] For example, in at least one embodiment of the solar cell provided in this disclosure, the roughness Ra of the first side surface is less than 1 micrometer, and the roughness of the second plate surface is greater than 1 micrometer.

[0010] For example, in a solar cell provided in at least one embodiment of this disclosure, the first plate surface has a plurality of alternating first doped regions and a plurality of second doped regions. Each of the plurality of first doped regions includes a first tunneling oxide layer disposed on the first plate surface and a first doped layer disposed on the side of the first tunneling oxide layer away from the first plate surface. Each of the plurality of second doped regions includes a second tunneling oxide layer disposed on the first plate surface and a second doped layer disposed on the side of the second tunneling oxide layer away from the first plate surface. A plurality of first electrode structures are respectively disposed in the plurality of first doped regions and are electrically connected to the first doped layers in the plurality of first doped regions. A plurality of second electrode structures are respectively disposed in the plurality of second doped regions and are electrically connected to the second doped layers in the plurality of second doped regions.

[0011] For example, at least one embodiment of the solar cell provided in this disclosure further includes: an insulating layer, including a first insulating portion and a second insulating portion, wherein the first insulating portion covers the first plate surface, the second insulating portion covers the second plate surface and the other sides of the plurality of sides besides the first side, the first insulating portion is disposed on the side of the first doped layer and the second doped layer away from the first plate surface, the plurality of first electrode structures are electrically connected to the corresponding first doped layer through vias in the first insulating portion, and the plurality of second electrode structures are electrically connected to the corresponding second doped layer through vias in the first insulating portion.

[0012] For example, in a solar cell provided in at least one embodiment of this disclosure, the surface of the second insulating portion away from the substrate is a first surface, and the first surface includes a first micromorphology with a plurality of protrusions.

[0013] For example, in at least one embodiment of the solar cell provided in this disclosure, the second plate surface and the other side surfaces are in direct contact with the second insulating portion.

[0014] For example, in a solar cell provided in at least one embodiment of this disclosure, on the first plate surface and the second plate surface, the second passivation portion covers the side of the insulating layer away from the substrate.

[0015] For example, in a solar cell provided in at least one embodiment of this disclosure, on the first side, the surface of the first passivated portion away from the substrate is a second surface, and the roughness of the second surface is less than the roughness of the first surface.

[0016] For example, at least one embodiment of the solar cell provided in this disclosure further includes: a plurality of first busbar electrodes and a plurality of second busbar electrodes, wherein the plurality of first electrode structures are electrically connected to the plurality of first busbar electrodes respectively, the plurality of second electrode structures are electrically connected to the plurality of second busbar electrodes respectively, and on the first plate surface, the second passivation portion is spaced apart from the plurality of first busbar electrodes and the plurality of second busbar electrodes.

[0017] For example, in a solar cell provided in at least one embodiment of this disclosure, the insulating layer includes a first insulating layer and a second insulating layer located on the side of the first insulating layer away from the substrate. The first insulating layer includes aluminum oxide, and the second insulating layer includes one or more of silicon nitride, silicon oxynitride, and silicon oxide. The passivation layer includes one or more of silicon or aluminum oxide, nitride, and carbide.

[0018] At least one embodiment of this disclosure provides a method for preparing a solar cell, comprising: forming a solar cell mother plate, and performing a cutting process on the solar cell mother plate to form a plurality of solar cell sub-plates, wherein each of the plurality of solar cell sub-plates includes a substrate, wherein the substrate includes a first plate surface and a second plate surface disposed opposite to each other and a plurality of side surfaces connecting the first plate surface and the second plate surface, a plurality of first electrode structures and a plurality of second electrode structures are formed on the first plate surface, and the plurality of side surfaces includes a first side surface, which is a side surface formed by the cutting process, and the roughness of the first side surface is less than the roughness of the second plate surface; Multiple solar cell sub-plates are stacked and their first sides are aligned. A passivation layer is formed on the first sides of the multiple solar cell sub-plates to form multiple solar cells. The passivation layer extends into the gap between two adjacent solar cell sub-plates to form on the portion of the first plate surface near the first side and / or the portion of the second plate surface near the first side. In a direction perpendicular to and away from the first side, the thickness of the passivation layer covering the portion of the first plate surface gradually decreases, and / or the thickness of the passivation layer covering the portion of the second plate surface gradually decreases.

[0019] For example, in at least one embodiment of the present disclosure, the method for forming a battery cell motherboard includes: forming a plurality of first doped regions and a plurality of second doped regions on a first surface of the substrate motherboard by a patterning process and a texturing process. Each of the plurality of first doped regions includes a first tunneling oxide layer formed on the first surface and a first doped layer formed on the side of the first tunneling oxide layer away from the first surface. Each of the plurality of second doped regions includes a second tunneling oxide layer formed on the first surface and a second doped layer formed on the side of the second tunneling oxide layer away from the first surface. The second surface and the plurality of side surfaces of the substrate motherboard are formed by the texturing process to have a first micromorphology including a plurality of protrusions.

[0020] For example, in the preparation method provided in at least one embodiment of this disclosure, forming a battery cell mother plate further includes: forming an insulating layer on a first plate surface, a second plate surface, and a plurality of side surfaces of the substrate mother plate, wherein on the first plate surface, the insulating layer is formed on the side of the first doped layer and the second doped layer away from the first plate surface.

[0021] For example, in the fabrication method provided in at least one embodiment of this disclosure, forming a battery cell motherboard further includes: forming an electrode structure layer on a first surface of the substrate motherboard on the side of the insulating layer away from the substrate motherboard, wherein the electrode structure layer includes the plurality of first electrode structures, the plurality of second electrode structures, and the plurality of first bus electrodes and the plurality of second bus electrodes, the plurality of first electrode structures being electrically connected to a corresponding first doped layer through vias in the insulating layer, the plurality of second electrode structures being electrically connected to a corresponding second doped layer through vias in the insulating layer, the plurality of first electrode structures being electrically connected to the plurality of first bus electrodes, and the plurality of second electrode structures being electrically connected to the plurality of second bus electrodes.

[0022] For example, in the preparation method provided in at least one embodiment of this disclosure, the cutting process is performed after the electrode structure layer is formed. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1 This is a partial cross-sectional schematic diagram of a solar cell provided in at least one embodiment of the present disclosure;

[0025] Figure 2This is a partial structural schematic diagram of a solar cell provided in at least one embodiment of the present disclosure;

[0026] Figure 3 A partial cross-sectional schematic diagram of the insulating layer of a solar cell provided in at least one embodiment of this disclosure; and

[0027] Figures 4-14 This is a schematic diagram illustrating the fabrication process of a solar cell provided in at least one embodiment of the present disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0030] The inventors of this disclosure discovered in their research that, for modules formed from solar cells, modules formed from half-cell solar cells have a greater power advantage than modules formed from whole-cell solar cells because half-cell solar cells can significantly reduce resistance loss. However, the process of cutting the solar cell in half introduces problems such as laser damage and loss of passivation layer. Even with non-destructive cutting techniques, some power loss still occurs in the module, and this loss is particularly noticeable for high-efficiency cells.

[0031] For example, in some embodiments, the edge of a half-cell solar cell is a textured surface formed by a texturing process. This surface is relatively rough and has a higher defect density. Especially when the impurity distribution at the edge of the silicon wafer is relatively complex, the textured surface structure is not conducive to edge passivation. Therefore, it does not significantly improve the fill factor (FF) of the cell and is not conducive to improving the cell efficiency.

[0032] At least one embodiment of this disclosure provides a solar cell, which includes a substrate and a passivation layer. The substrate includes a first plate surface and a second plate surface disposed opposite to each other, and a plurality of side surfaces connecting the first plate surface and the second plate surface. The first plate surface is provided with a plurality of first electrode structures and a plurality of second electrode structures. The plurality of side surfaces include a first side surface, the roughness of which is less than that of the second plate surface. The passivation layer includes a first passivation portion and a second passivation portion. The first passivation portion covers the first side surface and is in direct contact with it. The second passivation portion covers the portion of the second plate surface near the first side surface and the portion of the first plate surface near the first side surface. In a direction perpendicular to the first side surface and away from the first side surface, the thickness of the portion of the second passivation portion covering the first plate surface gradually decreases, and / or the thickness of the portion of the second passivation portion covering the second plate surface gradually decreases.

[0033] In the solar cell provided in this embodiment, the first side is smoother, which makes it easier to fabricate the edge passivation layer and achieve a better edge passivation effect. In addition, the module formed by the solar cell has higher efficiency, i.e., higher CTM (Cell to Module), thereby improving the performance of the module.

[0034] This disclosure provides at least one embodiment of a method for fabricating a solar cell, comprising: forming a solar cell mother plate; and performing a cutting process on the solar cell mother plate to form a plurality of solar cell sub-plates, wherein each of the plurality of solar cell sub-plates includes a substrate, the substrate includes a first plate surface and a second plate surface disposed opposite to each other and a plurality of side surfaces connecting the first plate surface and the second plate surface, a plurality of first electrode structures and a plurality of second electrode structures are formed on the first plate surface, and the plurality of side surfaces include a first side surface, which is a side surface formed by the cutting process described above, and the roughness of the first side surface is less than the roughness of the second plate surface; stacking the plurality of solar cell sub-plates and aligning the first side surfaces of the plurality of solar cell sub-plates, forming a passivation layer on the first side surfaces of the plurality of solar cell sub-plates, thereby forming a plurality of solar cells, wherein the passivation layer enters the gap between two adjacent plurality of solar cell sub-plates to form a portion of the first plate surface near the first side surface and / or a portion of the second plate surface near the first side surface, and in a direction perpendicular to and away from the first side surface, the thickness of the portion of the passivation layer covering the first plate surface gradually decreases, and / or the thickness of the portion of the passivation layer covering the second plate surface gradually decreases.

[0035] In the method for preparing solar cells provided in this disclosure, after the structure of the entire solar cell is fabricated, the entire solar cell is cut to form multiple sub-panels. The first side of the multiple sub-panels formed in this way is smoother, which is beneficial to the subsequent fabrication of the edge passivation layer and ensures a better edge passivation effect. In addition, compared with the cutting process during the formation of the entire solar cell structure, since the number of sub-panels doubles after the cutting process, it means that more equipment is needed to match the production capacity before the cutting process. The preparation method provided in this disclosure does not require an additional amount of preparation equipment for multiple sub-panels. For example, it only needs to match the doubled number of solar cells in the subsequent processes of depositing the passivation layer and conducting a second performance test on multiple solar cells. No additional equipment is needed in other processes, thereby simplifying the preparation process to the greatest extent and not having too much impact on the current production conditions and production capacity, which is more economical.

[0036] The solar cell and its preparation method disclosed herein are illustrated below through several specific embodiments.

[0037] This disclosure provides at least one embodiment of a solar cell. Figure 1 A cross-sectional schematic diagram of the solar cell is shown, as follows. Figure 1 As shown, the solar cell includes a substrate 110, which includes a first plate surface 111 and a second plate surface 112 disposed opposite to each other, and a plurality of side surfaces connecting the first plate surface 111 and the second plate surface 112. The first plate surface 111 is provided with a plurality of first electrode structures E1 and a plurality of second electrode structures E2. The plurality of side surfaces include a first side surface 113, the roughness of which is less than that of the second plate surface 112.

[0038] For example, in some embodiments, such as Figure 1 As shown, the multiple sides also include a second side 114. The roughness of the first side 113 is less than that of the second side 114. The roughness of the second side 114 is basically the same as that of the second plate surface 112.

[0039] For example, in some examples, the roughness of the other sides (including the second side 114) of the multiple sides, other than the first side 113, is substantially the same as that of the second plate surface 112.

[0040] For example, the first side 113 is a surface formed by a machining process, such as a cutting process, such as a laser cutting process, directly or indirectly, so that the surface is relatively smooth, that is, the roughness is small; the second plate surface 112 is a surface formed by a texturing process, or, in some examples, the second plate surface 112 and other sides such as the second side 114 are surfaces formed by a texturing process, so that the surface is relatively rough, that is, the roughness is greater than the roughness of the surface formed by the above-mentioned machining process.

[0041] For example, the surface directly formed by the above-mentioned cutting process can be a surface formed by cutting itself, while the surface indirectly formed can be a surface formed by the material's own fracture after cutting. These surfaces are all smooth surfaces formed directly or indirectly by machining processes, and their surface roughness is smaller.

[0042] In the solar cell provided in this embodiment, the first side is smoother / smoother than the second side and other sides. Compared with the surface formed by texturing process, the first side has fewer defects and is more conducive to the production of edge passivation layer, ensuring better edge passivation effect. In addition, the cell can have a higher fill factor (FF), and the formed module has higher efficiency, that is, a higher CTM (Cell to Module), thereby improving the performance of the formed module.

[0043] For example, in some embodiments, such as Figure 1 As shown, the second plate surface 112 includes a first micromorphology with multiple protrusions, for example, a first micromorphology with multiple pyramidal protrusions, where the cross-section of the multiple pyramidal protrusions is... Figure 1 The diagram shows multiple triangles. As a result, the second surface 112 has a larger roughness. For example, the first side surface 113 does not include the first micromorphology, that is, the morphology of the first side surface 113 is different from that of the second surface 112, and the first side surface 113 is smoother than the second surface 112.

[0044] For example, in some embodiments, all sides other than the first side 113 (including the second side 114) of the plurality of sides include the first micromorphology. For example, the sides including the first micromorphology are formed by a texturing process during the preparation process, for example, by the same texturing process as the second plate surface 112.

[0045] For example, in some embodiments, the roughness Ra of the first side surface 113 is less than 1 micrometer, and the roughness of the second plate surface 112 is greater than 1 micrometer, for example, greater than 2 micrometers, for example, between 2 and 3 micrometers. In this case, the first side surface 113 has fewer surface defects, which is beneficial for the fabrication of the edge passivation layer and improves the passivation effect.

[0046] For example, in some embodiments, such as Figure 1 As shown, the solar cell also includes a passivation layer 130, which includes a first passivation portion 131 and a second passivation portion 132. The first passivation portion 131 covers the first side 113 and is in direct contact with it; the second passivation portion 132 covers the portion of the second plate surface 112 near the first side 113 and the portion of the first plate surface 111 near the first side 113. That is, the passivation layer 130 is not only formed on the first side 113, but also on the portion of the second plate surface 112 near the first side 113 and the portion of the first plate surface 111 near the first side 113, thereby achieving an all-round edge passivation effect and avoiding defects such as passivation layer defects at the boundary between the first side 113 and other sides or the second plate surface. In addition, since the first side 113 has fewer surface defects, the passivation layer 130 can better bond with the first side 113 to improve the edge passivation effect.

[0047] For example, in some embodiments, in a direction perpendicular to and away from the first side surface 113, that is, along Figure 1 In the horizontal direction to the left, the thickness of the passivation layer 130 (second passivation portion 132) covering the portion of the first plate surface 111 gradually decreases; or, the thickness of the passivation layer 130 (second passivation portion 132) covering the portion of the second plate surface 112 gradually decreases; or, the thickness of the passivation layer 130 (second passivation portion 132) covering the portion of the first plate surface 111 gradually decreases, and the thickness of the passivation layer 130 (second passivation portion 132) covering the portion of the second plate surface 112 gradually decreases. Embodiments of this disclosure describe the passivation layer 130 in... Figure 1 The length of the extension in the horizontal direction to the left is not limited.

[0048] For example, Figure 2 A partial structural schematic diagram of a solar cell provided in at least one embodiment of this disclosure is shown, such as... Figure 2 As shown, in this example, in the direction perpendicular to and away from the first side 113, that is, along Figure 2 In the horizontal direction to the left, the thickness of the passivation layer 130 (second passivation portion 132) covering the portion of the first plate surface 111 gradually decreases, and the thickness of the passivation layer 130 (second passivation portion 132) covering the portion of the second plate surface 112 also gradually decreases. For example, on the second plate surface 112 of the substrate 110, the passivation layer 130 can extend across multiple protrusions, while on the first plate surface 111 of the substrate 110, the passivation layer 130 does not extend to the location of the first electrode structure E1 or the second electrode structure E2.

[0049] For example, such as Figure 2As shown, on the first side 113 of the substrate 110, the surface of the first passivation portion 131 of the passivation layer 130 is smoother and directly contacts the first side 113, and the first passivation portion 131 is tightly bonded to the first side 113; on the second plate surface 112, the second passivation portion 132 of the passivation layer 130 has a surface morphology that is substantially the same as that of the second plate surface 112, for example, including a micromorphology with multiple protrusions.

[0050] For example, in some embodiments, such as Figure 1 As shown, the first plate surface 111 has a plurality of alternating first doped regions A and a plurality of second doped regions B. Each first doped region A includes a first tunneling oxide layer 11 disposed on the first plate surface 111 and a first doped layer 12 disposed on the side of the first tunneling oxide layer 11 away from the first plate surface 111. A plurality of first electrode structures E1 are respectively disposed in the plurality of first doped regions A and are respectively electrically connected to the first doped layer 12 in the plurality of first doped regions A.

[0051] For example, such as Figure 1 As shown, each second doped region B includes a second tunneling oxide layer 21 disposed on the first plate surface 111 and a second doped layer 22 disposed on the side of the second tunneling oxide layer 21 away from the first plate surface 111. Multiple second electrode structures E2 are respectively disposed in multiple second doped regions B and are electrically connected to the second doped layer 22 in multiple second doped regions B.

[0052] For example, in some embodiments, one of the first electrode structure E1 and the second electrode structure E2 is a positive electrode structure and the other is a negative electrode structure; for example, the first electrode structure E1 is a positive electrode structure and the second electrode structure E2 is a negative electrode structure, or, in other embodiments, the first electrode structure E1 may be a negative electrode structure and the second electrode structure E2 may be a positive electrode structure.

[0053] For example, when the first electrode structure E1 is a positive electrode structure and the second electrode structure E2 is a negative electrode structure, in the first doped region A, the material of the first tunneling oxide layer 11 can be silicon dioxide, the first doped layer 12 can be boron-doped polycrystalline silicon, and the material of the first electrode structure E1 can be a metal electrode, such as silver, aluminum, copper, or other metal materials or alloy materials; in the second doped region B, the material of the second tunneling oxide layer 21 can be silicon dioxide, the second doped layer 22 can be phosphorus-doped polycrystalline silicon, and the material of the second electrode structure E2 can be a metal electrode, such as silver, aluminum, copper, or other metal materials or alloy materials. For example, when the first electrode structure E1 is a negative electrode structure and the second electrode structure E2 is a positive electrode structure, the structure and materials of the first doped region A and the second doped region B can refer to the above example, and will not be repeated here.

[0054] For example, in some embodiments, such as Figure 1 As shown, the solar cell also includes an insulating layer 140, which includes a first insulating portion 141 and a second insulating portion 142. The first insulating portion 141 covers the first plate surface 111, and the second insulating portion 142 covers the second plate surface 112 and other sides 114 of a plurality of sides excluding the first side 113. On the first plate surface 111, the first insulating portion 141 is disposed on the side of the first doped layer 12 and the second doped layer 22 away from the first plate surface 111. A plurality of first electrode structures E1 are electrically connected to the corresponding first doped layer 12 through vias in the first insulating portion 141, and a plurality of second electrode structures E2 are electrically connected to the corresponding second doped layer 22 through vias in the first insulating portion 141. For example, the substrate 110 is in direct contact with the second insulating portion 142 on the second plate surface 112 and the other sides mentioned above.

[0055] For example, such as Figure 1 As shown, the surface of the second insulating portion 142 away from the substrate 110 is the first surface 142A. The first surface 142A has a surface morphology that is substantially the same as that of the second plate surface 112 and the other side surfaces mentioned above, for example, including a micromorphology with multiple protrusions.

[0056] For example, in some embodiments, on the first plate surface 111 and the second plate surface 112, the second passivation portion 132 covers the side of the insulating layer 140 away from the substrate 110. Thus, during the fabrication process, the passivation layer 130 is formed later than the insulating layer 140, and the passivation layer 130 and the insulating layer 140 are structures formed by two independent processes with a clear interface between them.

[0057] For example, in some embodiments, on the first side 113, the surface of the first passivation portion 131 away from the substrate 110 is a second surface 131A, and the roughness of the second surface 131A is less than that of the first surface 142A. For example, the surface morphology of the first surface 142A is substantially the same as that of the first side 111, but its surface morphology is smoother.

[0058] For example, in some embodiments, such as Figure 2 As shown and in the following references Figure 13The solar cell also includes multiple first busbars G1 and multiple second busbars G2. Multiple first electrode structures E1 are electrically connected to the multiple first busbars G1, and multiple second electrode structures E2 are electrically connected to the multiple second busbars G2. On the first plate surface 111, a second passivation portion 132 is spaced apart from the multiple first busbars G1 and the multiple second busbars G2, meaning the second passivation portion 132 does not extend to the locations where the multiple first busbars G1 and the multiple second busbars G2 are located. Therefore, the second passivation portion 132 will not affect the structure and function of the multiple first busbars G1 and the multiple second busbars G2, and there is no risk of affecting the welding of the multiple first busbars G1 and the multiple second busbars G2 during the manufacturing process.

[0059] For example, multiple first bus electrodes G1 and multiple second bus electrodes G2 are spaced apart, meaning there is no electrical connection between them; similarly, multiple first electrode structures E1 and multiple second electrode structures E2 are spaced apart, meaning there is no electrical connection between them.

[0060] For example, in some embodiments, the insulating layer 140 may include multiple insulator layers, which may be formed using inorganic materials. For example, see reference... Figure 3 The insulating layer 140 may include a first insulating layer 140A and a second insulating layer 140B located on the side of the first insulating layer 140A away from the substrate 110. The material of the first insulating layer 140A may be alumina or other suitable insulating material. The first insulating layer 140A may include one or more insulator layers, for example, alumina or other suitable insulating material as the main material. The second insulating layer 140B may include one or more of silicon nitride, silicon oxynitride, and silicon oxide, for example, one or more insulator layers formed from one or more of silicon nitride, silicon oxynitride, and silicon oxide. For example, the number and thickness of the plurality of insulator layers included in the first insulating portion 141 located on the first plate surface 111 may not be exactly the same as the number and thickness of the plurality of insulator layers included in the second insulating portion 142 located on the second plate surface 112.

[0061] For example, the number of insulator layers in the first insulating portion 141 located on the first plate surface 111, including the first insulating layer 140A, can be the same as the number of insulator layers in the second insulating portion 142 located on the second plate surface 112, but the total thickness of the insulator layers in the first insulating portion 141 located on the first plate surface 111 is greater than the total thickness of the insulator layers in the second insulating portion 142 located on the second plate surface 112; for example, the number of insulator layers in the first insulating portion 141 located on the first plate surface 111, including the second insulating layer 140B, can be greater than the number of insulator layers in the second insulating portion 142 located on the second plate surface 112, and the total thickness of the insulator layers in the first insulating portion 141 located on the first plate surface 111 is greater than the total thickness of the insulator layers in the second insulating portion 142 located on the second plate surface 112.

[0062] For example, the insulation layer structure (e.g., quantity and thickness) at different positions of the insulation layer 140 can be set according to different needs. The above is just an example, and the embodiments disclosed herein are not limited thereto.

[0063] For example, the material of the passivation layer 130 can be an inorganic insulating material, such as one or more of oxides, nitrides, or carbides of silicon (Si), aluminum (Al), etc., and the thickness of the first passivation portion 131 can be 20nm-150nm, for example 20nm-100nm, such as 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, etc. In the direction perpendicular to and away from the first side surface 113, that is, along... Figure 1 and Figure 2 In the horizontal direction to the left, the thickness of the second passivation portion 132 decreases from 20nm-100nm to 0.

[0064] For example, in the above embodiment, the first side 113 is described as a smooth surface. In other embodiments, the solar cell may also include multiple smooth sides, such as multiple sides formed by mechanical processing. These sides may have a structure that is substantially the same as the first side 113 and achieve substantially the same effect.

[0065] For example, in other embodiments, the plurality of sides also includes a third side and a fourth side ( Figure 1(not shown in the diagram) The third side can also be a smooth surface, or the fourth side can also be a smooth surface, or both the third and fourth sides can be smooth surfaces; for example, in some embodiments, the second side 114 can also be a smooth surface. The above-mentioned passivation layer 130 can be provided on the smooth surface, and can achieve the same technical effect as the first side 113. The embodiments disclosed herein will not be described in detail.

[0066] This disclosure provides at least one embodiment of a method for fabricating a solar cell, the method comprising: forming a solar cell mother plate, and performing a cutting process on the solar cell mother plate to form a plurality of solar cell sub-plates; each solar cell sub-plate includes a substrate 110, the substrate 110 including a first plate surface 111 and a second plate surface 112 disposed opposite to each other and a plurality of side surfaces connecting the first plate surface 111 and the second plate surface 112, the first plate surface 111 having a plurality of first electrode structures E1 and a plurality of second electrode structures E2 formed thereon, the plurality of side surfaces including a first side surface 113, the first side surface 113 being a side surface formed by the cutting process described above, the roughness of the first side surface 113 being less than the roughness of the second plate surface 112; the plurality of side surfaces are then cut into multiple solar cells. Multiple solar cell panels are stacked and their first sides 113 are aligned. A passivation layer 130 is formed on the first sides 113 of the multiple solar cell panels to form multiple solar cells. The passivation layer 130 enters the gap between two adjacent solar cell panels to form on the portion of the first panel 111 near the first side 113 and / or the portion of the second panel 112 near the first side 113. In a direction perpendicular to and away from the first side 113, the thickness of the passivation layer 130 covering the portion of the first panel 111 gradually decreases, and / or the thickness of the passivation layer 130 covering the portion of the second panel 112 gradually decreases.

[0067] For example, Figures 4-14 A schematic diagram of the fabrication process of a solar cell provided in at least one embodiment of this disclosure is shown below. Figures 4-14 The present disclosure provides a detailed description of the method for preparing solar cells according to the embodiments.

[0068] For example, in some embodiments, such as Figures 4-11 As shown, forming the solar cell motherboard includes the following steps.

[0069] First, such as Figure 4As shown, a substrate mother plate 0110 is provided, which can be a silicon-based substrate such as a silicon wafer. For example, the substrate mother plate 0110 can be polished to form a clean and regular surface. For example, the polishing solution is a mixed solution of alkali (such as KOH, NaOH, etc.) and polishing additives, wherein the alkali concentration is about 5%-10%, and the temperature range is 60°C-100°C, such as 70°C, 80°C, or 90°C.

[0070] For example, such as Figure 5 As shown, at least a first tunneling oxide layer 011 and a polycrystalline silicon material layer 012 are formed on the first plate surface (lower plate surface in the figure) of the substrate mother plate 0110. Then, the polycrystalline silicon material layer 012 is doped, for example, by boron doping, so that the polycrystalline silicon material layer 012 is formed as a boron-doped polycrystalline silicon layer, and borosilicate glass (BSG) 012A is formed on the surface of the polycrystalline silicon material layer 012.

[0071] For example, the thickness of the first tunneling oxide layer 011 ranges from 1 nm to 3 nm, such as 1.5 nm, 2.0 nm, or 2.5 nm; the thickness of the polycrystalline silicon layer 012 ranges from 200 nm to 400 nm, such as 250 nm, 300 nm, or 350 nm; and the thickness of the borosilicate glass (BSG) 012A ranges from 30 nm to 70 nm, such as 40 nm, 50 nm, or 60 nm. For example, the first tunneling oxide layer 011 can be prepared by thermal oxidation, and the polycrystalline silicon layer 012 can be prepared by low-pressure chemical vapor deposition (LPCVD) with the introduction of silane. The oxidation and LPCVD temperatures range from 550°C to 650°C. Boron doping can be carried out by thermal diffusion, with the entire diffusion process performed in multiple steps, accompanied by the introduction of gases such as nitrogen, air, and boron trichloride (BCl3) in different proportions. The process temperature range is 850°C to 1000°C.

[0072] For example, the above process can involve stacking two battery cell motherboards with their back sides (first panel) facing outwards and their front sides (second panel) facing inwards (double-insertion configuration). There is a gap between the two battery cell motherboards. In this case, if... Figure 5 As shown, the first tunneling oxide material layer 011 and the polycrystalline silicon material layer 012 will form a wraparound at the edge, thereby forming multiple sides of the substrate mother plate 0110 and the second plate surface (the upper plate surface in the figure).

[0073] For example, such as Figure 6As shown, multiple first doped regions A and multiple second doped regions B are formed on the first surface of the substrate 0110 using a patterning process. For example, the patterning process forms multiple grooves on the first surface of the substrate 0110, and the multiple second doped regions B are located in the multiple grooves, thereby dividing the multiple first doped regions A and multiple second doped regions B. For example, the patterning process includes a combination of laser ablation and alkaline etching. A laser is used to ablate borosilicate glass (BSG) 012A according to a specific pattern (corresponding to the second doped region B), followed by wet etching to remove the ablated BSG and the underlying silicon, with an etching depth of 2μm-5μm. The etching solution is a mixed solution of alkali (such as KOH, NaOH, etc.) and SiO2 protective additive, with an alkali concentration of 10%-20%.

[0074] After that, as Figure 7 As shown, at least a second tunneling oxide layer 021 and a polycrystalline silicon material layer 022 are formed on the first surface of the substrate mother plate 0110. The polycrystalline silicon material layer 022 is then doped, for example, with phosphorus, to form a phosphorus-doped polycrystalline silicon layer. Furthermore, a phosphorus silicate glass (PSG) 022A is formed on the surface of the polycrystalline silicon material layer 012. The thickness of the second tunneling oxide layer 021 ranges from 1 nm to 3 nm, for example, 1.5 nm, 2.0 nm, or 2.5 nm; the thickness of the polycrystalline silicon layer 022 ranges from 100 nm to 300 nm, for example, 250 nm, 300 nm, or 350 nm; and the thickness of the phosphorus silicate glass (PSG) 022A ranges from 20 nm to 60 nm, for example, 30 nm, 40 nm, or 50 nm. For example, the second tunneling oxide material layer 021 can be prepared by thermal oxidation, and the polycrystalline silicon material layer 022 can be prepared by low-pressure chemical vapor deposition (LPCVD) with the introduction of silane. The temperature range of oxidation and LPCVD is 550-650°C. Phosphorus doping is carried out by thermal diffusion. The entire diffusion process is carried out in multiple steps, with nitrogen, air, phosphorus oxychloride (POCl3) and other gases introduced in different proportions. The process temperature range is 850°C-950°C.

[0075] For example, because the above process involves stacking two battery cell motherboards with their backs facing outwards and their fronts facing inwards (double-insertion setup), gaps exist between the cells, such as... Figure 7 As shown, the second tunneling oxide layer 021 and the polysilicon layer 022 are formed around the edges, thereby forming multiple sides of the substrate mother plate 0110 and the second plate surface (the upper plate surface in the figure). Polysilicon deposition and phosphorus diffusion cover all surfaces of the back groove. For example, the second tunneling oxide layer 021 and the polysilicon layer 022 are also formed on the sidewalls of the grooves of the multiple second doped regions B, which are not shown in the figure.

[0076] For example, after the above process, a high-temperature annealing process can be performed to crystallize the polycrystalline silicon material layer 022. The annealing temperature is 900°C-1000°C. For example, if the tunneling oxide layer and the doped polycrystalline silicon layer are formed by LPCVD heating diffusion in the manner described above, the high-temperature annealing step can be combined with the LPCVD heating diffusion step.

[0077] For example, such as Figure 7 and Figure 8 As shown, the phosphorosilicate glass (PSG) 022A in multiple first doped regions A undergoes surface treatment, such as laser treatment, and the phosphorosilicate glass (PSG) 022A at the edges of multiple second doped regions B (e.g., defined as isolation regions C) undergoes surface treatment, such as laser treatment, to form laser-treated phosphorosilicate glass (PSG) 022B on the surfaces of the isolation regions C of the first doped regions A and the second doped regions B. Figure 8 As shown, laser-treated phosphosilicate glass (PSG) 022B is easier to remove by etching.

[0078] For example, such as Figure 9 As shown, a texturing process is performed on the substrate motherboard 0110 and some structures formed thereon. For example, before the texturing process, refer to... Figure 8 The tunneling oxide layers 011 and 021, polycrystalline silicon layers 012 and 022, as well as the BSG and PSG layers, located on the second plate surface and multiple sides can be removed by passing the second plate surface downward through a chain-type wet process in a mixed solution of nitric acid, hydrofluoric acid and sulfuric acid, which is also known as removing the winding film layers.

[0079] Subsequently, the phosphorus silicate glass (PSG) 022B, phosphorus-doped polycrystalline silicon 022, and the second tunneling oxide layer 021, which have undergone a second laser treatment, can be removed from the first plate surface in a wet process. Borosilicate glass (BSG) 012A and the untreated phosphorus silicate glass (PSG) 022A serve as protective layers, ensuring that the untreated borosilicate glass (BSG) 012A and the untreated phosphorus silicate glass (PSG) 022A, along with their internal films, are not removed. Simultaneously, a pyramidal textured surface is formed on the front side (second plate surface). The texturing solution is a mixed solution of alkali (such as KOH, NaOH, etc.), texturing additives, and SiO2 protective additives, with an alkali concentration of 2%-5% and a temperature range of 60°C-100°C.

[0080] Finally, in a wet process equipment, hydrofluoric acid is used to remove borosilicate glass (BSG) 012A and untreated phosphosilicate glass (PSG) 022A, forming a structure as shown in the image. Figure 9 The structure shown.

[0081] Therefore, as Figure 9 As shown, through the above process, the side surface and the second surface of the substrate mother plate 0110 are textured surfaces formed by the texturing process. That is, the second surface 112 and multiple side surfaces of the substrate mother plate 0110 are formed by the texturing process to form a first micromorphology including multiple protrusions.

[0082] For example, such as Figure 9 As shown, through the above patterning process and texturing process, a plurality of first doped regions A and a plurality of second doped regions B are formed on the first plate surface 111 of the substrate mother plate 0110. Each of the plurality of first doped regions A includes a first tunneling oxide layer 11 formed on the first plate surface 111 and a first doped layer 12 formed on the side of the first tunneling oxide layer 11 away from the first plate surface 111. Each of the plurality of second doped regions B includes a second tunneling oxide layer 21 formed on the first plate surface 111 and a second doped layer 22 formed on the side of the second tunneling oxide layer 21 away from the first plate surface 111.

[0083] For example, such as Figure 10 As shown, an insulating layer 140 is formed on the first surface, the second surface, and multiple sides of the substrate mother plate 0110 using processes such as deposition. On the first surface, the insulating layer 140 is formed on the side away from the first surface 111 of the first doped layer 12 and the second doped layer 22.

[0084] For example, insulating layer 140 may include multiple insulator layers, for example, in forming Figure 3 When the insulating layer 140 is shown, a first insulating layer 140A with aluminum oxide as the main material can be formed by atomic layer deposition (ALD) or other methods. The first insulating layer 140A may include one or more insulator layers. On the side of the first insulating layer 140A away from the substrate 110, a second insulating layer 140B can be formed by deposition, such as physical vapor deposition (PECVD). The second insulating layer 140B may be one or more insulator layers formed by one or more of silicon nitride, silicon oxynitride and silicon oxide. When multiple insulator layers are formed, the multiple insulator layers can be formed sequentially.

[0085] For example, the number of layers and thickness of the first insulating layer 140A and the second insulating layer 140B formed on the first and second plates can be the same or different. For clarity, Figure 10 The insulating layer 140 is shown as a single layer.

[0086] For example, such as Figure 11As shown, on the first plate surface 111 of the substrate mother plate 0110, on the side of the insulating layer 140 away from the substrate mother plate 0110, an electrode structure layer is formed, for example, by screen printing, sintering or other processes. The electrode structure layer includes a plurality of first electrode structures E1, a plurality of second electrode structures E2, a plurality of first bus electrodes G1 and a plurality of second bus electrodes G2 (described later). The plurality of first electrode structures E1 are electrically connected to the corresponding first doped layer 12 through vias sintered in the insulating layer 140, and the plurality of second electrode structures E2 are electrically connected to the corresponding second doped layer 22 through vias sintered in the insulating layer 140. The plurality of first electrode structures E1 are electrically connected to the plurality of first bus electrodes G1, and the plurality of second electrode structures E2 are electrically connected to the plurality of second bus electrodes G2.

[0087] For example, the multiple first electrode structures E1 and multiple second electrode structures E2 can also be referred to as sub-gates / fine gates, and the multiple first bus electrodes G1 and multiple second bus electrodes G2 can also be referred to as main gates, serving to collect fine gate current and connect to the welding electrode. For example, the extending directions of the multiple first bus electrodes G1 and multiple second bus electrodes G2 are perpendicular to the extending directions of the multiple first electrode structures E1 and multiple second electrode structures E2.

[0088] For example, multiple first bus electrodes G1 and multiple second bus electrodes G2, along with multiple first electrode structures E1 and multiple second electrode structures E2, can be printed simultaneously or in stages. The pastes used can be the same or different, and the specific choice can be made according to the requirements.

[0089] For example, after the electrode structure layer is formed, the main structure of the entire solar cell is formed. At this time, the cell can be tested for the first time. After the first performance test is completed, the cell motherboard 0110 is cut.

[0090] For example, after the electrode structure layer is formed, such as Figure 12 As shown, the battery cell motherboard 0110 is cut using a process such as laser cutting to form multiple battery sub-boards 10. This cutting process forms the first side surface 113 of the substrate 110 of the multiple battery sub-boards 10. Since the first side surface 113 is formed by the cutting process, the first side surface 113 is smoother than the other sides and the second board surface 112.

[0091] For example, Figure 13 The diagram shows a planar schematic of the process of cutting the solar cell motherboard 0110 to form multiple solar cell daughterboards. Figure 12 It can be seen as Figure 13 A schematic diagram of the cross-section along line XX. (See diagram below.) Figure 13As shown, multiple first bus electrodes G1 and multiple second bus electrodes G2 are formed on multiple battery sub-boards. Each first bus electrode G1 is connected to multiple first electrode structures E1, and each second bus electrode G2 is connected to multiple second electrode structures E2.

[0092] For example, after forming multiple battery sub-panels 10, the multiple battery sub-panels 10 can be stacked. Figure 14 A schematic diagram showing a multi-layered arrangement of battery sub-panels is shown, such as... Figure 14 As shown, multiple solar cell sub-plates 10 are aligned and arranged with their first side surfaces 113 aligned. Then, a passivation layer 130 is formed on the first side surfaces 113 of the multiple solar cell sub-plates 10. For example, the passivation layer 130 is formed by deposition, sputtering or other processes, thereby forming multiple solar cells.

[0093] For example, during the preparation process, such as Figure 14 As shown, hundreds to thousands (e.g., 400-2000) of battery sub-panels 10 can be neatly stacked with their first side surfaces 113 facing the same direction. One or more of the following materials—oxides, nitrides, or carbides of silicon (Si), aluminum (Al), etc.—are deposited simultaneously on the first side surfaces 113 of these battery sub-panels 10 using atomic layer deposition, vapor phase deposition, or other methods. The deposition temperature is 200 degrees Celsius, and the deposition thickness is 20 nm to 150 nm, for example, 20 nm to 100 nm, to form a passivation layer 130 on the first side surfaces 113 of the hundreds to thousands of battery sub-panels 10. The passivation layer 130 can repair cutting damage to the first side surfaces 113, such as laser damage and passivation film defects, thereby achieving a better passivation effect.

[0094] For example, during the formation of the passivation layer 130, the passivation layer 130 can enter the gap between two adjacent battery sub-plates 10 to form a portion of the first plate surface 111 near the first side surface 113 and a portion of the second plate surface 112 near the first side surface 113, which is the aforementioned second passivation portion 132.

[0095] For example, refer to Figure 1 and Figure 2 In the direction perpendicular to and away from the first side surface 113, that is, along Figure 1 and Figure 2 In the horizontal direction to the left, the thickness of the passivation layer 130 covering the portion of the first plate surface 111 gradually decreases; or, the thickness of the passivation layer 130 covering the portion of the second plate surface 112 gradually decreases; or, the thickness of the passivation layer 130 covering the portion of the first plate surface 111 gradually decreases, and the thickness of the passivation layer 130 covering the portion of the second plate surface 112 gradually decreases.

[0096] For example, after multiple solar cells are formed, a second cell performance test can be performed, such as testing, sorting / grading multiple solar cells. This process can improve the concentration of the cell sub-panel's electrical performance, thereby further improving the module's CTM (Complete Technology Metric).

[0097] For example, the above preparation method is introduced using a one-time cutting process to cut the entire solar cell in half. In other embodiments, the entire solar cell can also be cut multiple times or a one-time cutting process to form patterned cutting lines, thereby forming a solar cell with multiple smooth sides. In this case, a passivation layer 130 can be deposited on each of these smooth sides. Please refer to the above embodiments for details, which will not be repeated here.

[0098] Therefore, the preparation method provided in this embodiment is also applicable to the preparation of shingled cells and modules with three, four, or five sections. In this case, the side surfaces formed by cutting have the same structure and technical effects as the first side surface.

[0099] In summary, in the method for preparing the solar cell provided in this embodiment, after the entire solar cell structure is fabricated, the entire solar cell is cut to form multiple sub-plates. The first sides of these multiple sub-plates are smoother, which facilitates the subsequent fabrication of the edge passivation layer and ensures a better edge passivation effect, thus improving the fill factor (FF). Furthermore, compared to performing the cutting process during the formation of the entire solar cell structure, for example, compared to... Figure 4 After the process or Figure 8 After the initial cutting process, the number of battery panels doubles, meaning more equipment is needed to match the production capacity before cutting. Figure 4 After the process or Figure 8 The preparation process following the cutting process has disadvantages in terms of equipment investment; the preparation process provided by the present disclosure only requires matching the number of solar cells to double in the process of depositing the passivation layer and the second performance test of multiple solar cells. No additional equipment is required for other processes. Therefore, it will not increase the amount of preparation equipment and processes for multiple solar cells, thereby simplifying the preparation process to the greatest extent and not having too much impact on the current production conditions and capacity, making it more economical.

[0100] The following points also need to be explained:

[0101] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0102] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It is understood that when an element is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0103] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0104] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A solar cell, characterized by, The substrate includes a first plate surface and a second plate surface arranged opposite to each other, and a plurality of side surfaces connecting the first plate surface and the second plate surface, The first plate surface is provided with a plurality of first electrode structures and a plurality of second electrode structures, The plurality of side surfaces includes a first side surface, and a roughness of the first side surface is less than a roughness of the second plate surface; The passivation layer includes: a first passivation portion covering the first side surface and being in direct contact with the first side surface, and a second passivation portion covering a portion of the second plate surface close to the first side surface and a portion of the first plate surface close to the first side surface.

2. The solar cell according to claim 1, wherein In a direction perpendicular to the first side surface and away from the first side surface, a thickness of the portion of the first plate surface covered by the second passivation portion gradually decreases, and / or a thickness of the portion of the second plate surface covered by the second passivation portion gradually decreases.

3. The solar cell of claim 1, wherein, The plurality of side surfaces further includes a second side surface, The roughness of the first side surface is less than the roughness of the second side surface, The roughness of the second side surface is substantially the same as the roughness of the second plate surface.

4. The solar cell as claimed in any one of claims 1 to 3, wherein The first side surface is a surface formed by a mechanical processing process, and the second plate surface is a surface formed by a texturing process.

5. The solar cell as claimed in any one of claims 1 to 3, wherein The second plate surface includes a first micro-topography having a plurality of protrusions, The first side surface does not include the first micro-topography.

6. The solar cell of claim 5, wherein, The plurality of side surfaces other than the first side surface includes the first micro-topography.

7. The solar cell as claimed in any one of claims 1 to 3, wherein The roughness Ra of the first side surface is less than 1 micron, and the roughness of the second plate surface is greater than 1 micron.

8. The solar cell of claim 1, wherein, The first plate surface has a plurality of first doped regions and a plurality of second doped regions arranged alternately, Each of the plurality of first doped regions includes a first tunnel oxide layer arranged on the first plate surface and a first doped layer arranged on a side of the first tunnel oxide layer away from the first plate surface, Each of the plurality of second doped regions includes a second tunnel oxide layer arranged on the first plate surface and a second doped layer arranged on a side of the second tunnel oxide layer away from the first plate surface, The plurality of first electrode structures are respectively arranged in the plurality of first doped regions and are respectively electrically connected with the first doped layers in the plurality of first doped regions, The plurality of second electrode structures are respectively arranged in the plurality of second doped regions and are respectively electrically connected with the second doped layers in the plurality of second doped regions.

9. The solar cell of claim 8, wherein, Further comprising: an insulating layer including a first insulating portion and a second insulating portion, The first insulating portion covers the first plate surface, and the second insulating portion covers the second plate surface and the plurality of side surfaces other than the first side surface, The first insulating portion is arranged on a side of the first doped layer and the second doped layer away from the first plate surface, the plurality of first electrode structures are respectively electrically connected with the corresponding first doped layers through vias in the first insulating portion, and the plurality of second electrode structures are respectively electrically connected with the corresponding second doped layers through vias in the first insulating portion.

10. The solar cell of claim 9, wherein, A surface of the second insulating portion distal to the substrate is a first surface, the first surface including a first microtopography having a plurality of protrusions.

11. The solar cell of claim 9, wherein, The second plate surface and the other side surface are in direct contact with the second insulating portion.

12. The solar cell of claim 10, wherein, On the first plate surface and the second plate surface, the second passivation portion covers a side of the insulating layer distal to the substrate.

13. The solar cell of claim 12, wherein, On the first side surface, a surface of the first passivation portion distal to the substrate is a second surface, the second surface having a roughness less than a roughness of the first surface.

14. The solar cell of claim 12, wherein, Further comprising: a plurality of first bus electrodes, wherein the plurality of first electrode structures are respectively electrically connected to the plurality of first bus electrodes, and a plurality of second bus electrodes, wherein the plurality of second electrode structures are respectively electrically connected to the plurality of second bus electrodes, On the first plate surface, the second passivation portion is disposed apart from the plurality of first bus electrodes and the plurality of second bus electrodes.

15. The solar cell of claim 9, wherein, The insulating layer includes a first insulating layer and a second insulating layer on a side of the first insulating layer distal to the substrate, a material of the first insulating layer being aluminum oxide, and a material of the second insulating layer being silicon nitride, silicon oxynitride, or silicon oxide.

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