Data acquisition instrument with hardware triggering function

Abstract

The utility model provides a data acquisition instrument with a hardware triggering function. The data acquisition instrument comprises an analog signal chain; the FPGA controller is electrically connected with the analog signal chain; the microcontroller is electrically connected with the FPGA controller; the isolation assembly is electrically connected with the FPGA controller; the digital potentiometer is electrically connected with the FPGA controller and the microcontroller respectively; and the protection assembly is electrically connected with the isolation assembly. According to the utility model, an external digital trigger signal / analog trigger signal is isolated through the protection assembly and the isolation assembly, so that the reliability of data is improved, and the waste of storage space and computing resources due to a large amount of low-value or unconcerned data is avoided; the FPGA controller synchronously triggers an external digital trigger signal / analog trigger signal by starting an analog signal chain, and the isolation assembly dynamically configures the digital potentiometer through the microcontroller, so that the digital potentiometer can adapt to different types and models, and further can meet scenes with high real-time performance.

Description

Technical Field

[0001] This utility model relates to the field of structural safety monitoring technology, and in particular to a data acquisition instrument with hardware triggering function. Background Technology

[0002] In modern data acquisition technology, data acquisition instruments are widely used in engineering testing, medical monitoring, environmental monitoring, industrial automation, and many other fields. Triggered acquisition functionality is particularly important for these applications, primarily due to: ① Real-time requirements: Many application scenarios require immediate data acquisition when specific events occur. For example, in medical monitoring, a patient's physiological signals (such as electrocardiograms) need to be recorded rapidly when heart rate abnormalities occur, allowing doctors to analyze and intervene promptly. Triggered acquisition ensures that the data acquisition instrument activates at critical moments, capturing important data and meeting real-time monitoring needs. ② Effectiveness of signal capture: In high-frequency or rapidly changing signals, relying on continuous data acquisition may lead to the generation of a large amount of useless data, resulting in the loss of instantaneous information about critical events. Through a triggering mechanism, the data acquisition instrument can activate only when the signal of interest occurs, thereby improving the effectiveness and accuracy of the data. ③ Improved resource efficiency: Triggered data acquisition effectively reduces the burden of data storage and post-processing. When data is acquired only when specific events occur, the amount of data recorded can be significantly reduced, alleviating the burden on data storage and processing systems and improving the efficiency of data analysis. ④ Synchronous data acquisition between multiple devices: In complex monitoring systems, multiple data acquisition devices are often required to collect sensor data simultaneously. Triggering mechanisms can ensure synchronous sampling between different data acquisition devices.

[0003] In current technologies, data acquisition instruments typically rely on software control to trigger the data acquisition process. This approach has several significant problems. Software-triggered modes depend on the acquisition device continuously sampling signals. When the signal exceeds a software-defined threshold, a set length of samples is saved and transmitted. This leads to several issues:

[0004] First, the equipment and software need to store the sampled data in real time, which will collect a large amount of data that is of low value or irrelevant, wasting storage space and computing resources, resulting in low resource utilization.

[0005] Second, software triggering requires the execution of judgment logic, which leads to a long time delay and cannot meet the needs of scenarios with high real-time requirements. Utility Model Content

[0006] Therefore, the purpose of this utility model is to provide a data acquisition device with hardware triggering function to solve the shortcomings of the prior art.

[0007] This utility model provides a data acquisition device with hardware triggering function, including:

[0008] Analog signal chain;

[0009] The FPGA controller is electrically connected to the analog signal chain;

[0010] The microcontroller is electrically connected to the FPGA controller;

[0011] An isolation component is electrically connected to the FPGA controller;

[0012] A digital potentiometer is electrically connected to the FPGA controller and the microcontroller, respectively.

[0013] The protection component is electrically connected to the isolation component;

[0014] The external digital trigger signal / analog trigger signal is sequentially input to the FPGA controller through the protection component and the isolation component, and the FPGA controller synchronously triggers the external digital trigger signal / analog trigger signal by starting the analog signal chain. The isolation component dynamically configures the digital potentiometer through the microcontroller to adapt to different types of models.

[0015] Compared with the prior art, the beneficial effects of this utility model are: by isolating external digital trigger signals / analog trigger signals through protection components and isolation components, the reliability of data is improved, thereby avoiding a large amount of low-value or irrelevant data, which wastes storage space and computing resources. The FPGA controller synchronously triggers external digital trigger signals / analog trigger signals by starting the analog signal chain, and the isolation component dynamically configures the digital potentiometer through the microcontroller, thereby adapting to different types of models and meeting the needs of scenarios with high real-time requirements.

[0016] Furthermore, the analog signal chain includes an analog-to-digital converter.

[0017] Furthermore, the analog signal chain can be a static signal chain or a dynamic signal chain.

[0018] Furthermore, the isolation component includes an isolation power supply, a digital isolator, and a voltage isolation comparator. The isolation power supply is electrically connected to the digital isolator and the voltage isolation comparator, respectively. The digital isolator is electrically connected to the FPGA controller, and the voltage isolation comparator is electrically connected to the FPGA controller.

[0019] Furthermore, the FPGA controller receives external digital trigger signals and analog trigger signals from the digital isolator / voltage isolation comparator, and forwards the external digital trigger signals and analog trigger signals through the digital isolator.

[0020] Furthermore, the protection component includes a digital output interface protection circuit, a digital input interface protection circuit, and an analog input interface protection circuit, all of which are electrically connected to the isolation component.

[0021] Furthermore, both the digital output interface protection circuit and the digital input interface protection circuit are protected against line surges using self-resetting fuses RT1-RT4 and TVS diodes D1-D4.

[0022] Furthermore, the analog input interface protection circuit consists of a TVS diode D5, a decoupling resistor R48, and a gas discharge diode G1, forming a two-stage surge protection circuit for surge protection of the analog signal line. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a data acquisition device with hardware triggering function in an embodiment of this utility model;

[0024] Figure 2 This is a schematic diagram of the analog signal triggering circuit in an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of the digital signal triggering circuit and isolated power supply in an embodiment of this utility model.

[0026] Explanation of key component symbols:

[0027] 1. Analog signal chain; 2. FPGA controller; 3. Microcontroller;

[0028] 40. Isolation components; 4. Isolation power supplies; 5. Digital isolators; 6. Voltage isolation comparators;

[0029] 7. Digital potentiometer;

[0030] 80. Protection components; 8. Digital output interface protection circuit; 9. Digital input interface protection circuit; 10. Analog input interface protection circuit.

[0031] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this utility model. Detailed Implementation

[0032] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of this utility model are shown in the drawings. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this utility model will be more thorough and complete.

[0033] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] Please see Figure 1 The image shows a data acquisition device with hardware triggering function in an embodiment of this utility model, including an analog signal chain 1, an FPGA controller 2, a microcontroller 3, an isolation component 40, a digital potentiometer 7, and a protection component 80.

[0036] The FPGA controller 2 is electrically connected to the analog signal chain 1, the microcontroller 3 is electrically connected to the FPGA controller 2, the isolation component 40 is electrically connected to the FPGA controller 2, the digital potentiometer 7 is electrically connected to the FPGA controller 2 and the microcontroller 3 respectively, and the protection component 80 is electrically connected to the isolation component 40. The microcontroller 3 configures the FPGA controller 2 to work in hardware trigger mode, configures the working mode and sampling rate of the analog-to-digital converter in the analog signal chain 1 through the FPGA controller 2, and implements programmable analog trigger signal threshold settings by configuring the digital potentiometer 7. The external digital trigger signal / analog trigger signal is sequentially input to the FPGA controller 2 through the protection component 80 and the isolation component 40, and the FPGA controller 2 synchronously triggers the external digital trigger signal / analog trigger signal by starting the analog signal chain 1. The isolation component 40 dynamically configures the digital potentiometer 7 through the microcontroller 3 to adapt to different types of models.

[0037] Specifically, in this embodiment, the isolation component 40 includes an isolation power supply 4, a digital isolator 5, and a voltage isolation comparator 6. The FPGA controller 2 receives external digital and analog trigger signals from the digital isolator 5 or the voltage isolation comparator 6, and forwards the trigger signals to the next-level acquisition device through the digital isolator 5. The isolation power supply 4 is electrically connected to the digital isolator 5 and the voltage isolation comparator 6, respectively. The digital isolator 5 is electrically connected to the FPGA controller 2, and the voltage isolation comparator 6 is electrically connected to the FPGA controller 2. The FPGA controller 2 receives external digital and analog trigger signals from the digital isolator 5 / the voltage isolation comparator 6, and forwards the external digital and analog trigger signals through the digital isolator 5. The protection component 80 includes a digital output interface protection circuit 8, a digital input interface protection circuit 9, and an analog input interface protection circuit 10, all of which are electrically connected to the isolation component 40.

[0038] It should be noted that the digital output interface protection circuit 8 and the digital input interface protection circuit 9 are both electrically connected to the digital isolator 5, and the analog input interface protection circuit 10 is electrically connected to the voltage isolation comparator 6.

[0039] It should be explained that the analog signal chain 1 includes an analog-to-digital converter. For example, in a multi-channel synchronous dynamic data acquisition instrument, the first-stage amplification can be a programmable amplifier, with different gains configured for large and small signals to achieve the highest signal-to-noise ratio measurement. The filter section can use a 4th to 6th order Butterworth active low-pass filter with an SK circuit topology, used as an anti-aliasing filter. The analog-to-digital converter can be a 16-bit or 24-bit converter with an independent core for each channel, or a converter with a sample-and-hold circuit, depending on the requirements of the monitoring object.

[0040] It's worth noting that analog signal chain 1: This part is divided into the signal processing front-end (signal amplification) of the data acquisition instrument, as well as the signal conditioning (filtering and level conversion) and signal sampling (analog-to-digital converter) sections. Generally, analog signal chains fall into two main categories: ① Static signal chains: These measure static physical quantities, such as slowly changing environmental parameters (temperature, pressure, etc.). Because static signal chains have low requirements for data sampling rate and synchronization, multi-channel solutions for this type of static signal chain typically use analog switches or signal relays for expansion. Only one signal chain is needed, and the data is finally sampled by an analog-to-digital converter before being transmitted to a microcontroller, etc. ② Dynamic signal chains: These measure dynamic physical quantities, such as structural vibrations (acceleration, velocity, etc.). Because dynamic signals generally require a higher sampling rate and synchronous sampling, multi-channel dynamic signal chain solutions use independent signal chain processing for each channel, with each channel using an independent analog-to-digital converter for data conversion, and finally transmitting the data to an FPGA or other high-speed interface controller.

[0041] FPGA Controller 2: Primarily used for logic control and data reading of the analog-to-digital converter, and may also perform some preset FIR digital filters, low sampling rate sampling, and other algorithm functions internally. Simultaneously, its external trigger monitoring I / O port responds promptly to external digital or analog trigger signals based on the data acquisition instrument's operating mode, initiating analog-to-digital converter sampling to achieve synchronous trigger sampling. The sampled data is then filtered, packaged according to protocol, and sent to microcontroller 3.

[0042] It is worth noting that FPGA controller 2 is primarily responsible for handling the logic response to external hardware trigger signals, including analog and digital trigger signals, as well as hardware trigger signals and clock signals forwarded to the next-level device. It also processes the sampled data output from the analog-to-digital converter on analog signal chain 1, performing digital filtering and protocol packaging before sending the data to microcontroller 3. External hardware trigger signals can be in the form of level triggering, edge triggering, etc. When the acquisition device is configured in external trigger mode, the internal logic of FPGA controller 2 will prioritize responding to external trigger signals. Once the trigger signal is recognized by FPGA controller 2, it immediately starts sampling the analog-to-digital converter in analog signal chain 1, thus responding to the external trigger signal. When responding to external trigger signals, FPGA controller 2 not only initiates its own trigger sampling but can also forward the trigger signal to the next-level device through a digital isolator, achieving synchronous trigger sampling across multiple devices. For example, when a digital or analog trigger signal is valid, FPGA controller 2 can forward the trigger signal again through digital isolator 5.

[0043] Microcontroller 3: Primarily responsible for configuring the FPGA and the operating modes of the analog-to-digital converter (ADC). This includes configuring the FPGA to operate in real-time sampling mode, timed sampling mode, software trigger mode, and external hardware trigger mode. It also configures the ADC's sampling rate and operating mode via the FPGA. Additionally, it configures the digital potentiometer via the IIC bus to set the analog trigger signal threshold, specifically... Figure 2 As shown.

[0044] It's worth noting that microcontroller 3 is responsible for configuring the resistance value of the digital potentiometer to dynamically adjust the threshold of the analog trigger signal, as well as configuring the FPGA operating parameters and the analog-to-digital converter operating parameters via the FPGA. It reads the data packets sent by the FPGA and sends them to the host via the communication interface.

[0045] Isolated power supply 4: Specifically as follows Figure 3 As shown, the VCC power supply of U12 is the system power supply of the data acquisition instrument, and ISO_V is the output voltage of the isolation power supply, which is used to provide the isolation side power supply for U13 (digital isolator 5) and U14 (voltage isolation comparator), as detailed below. Figure 2 and Figure 3 As shown.

[0046] It is worth noting that the isolation power supply 4 is mainly responsible for providing power to the isolation devices of the digital isolator 5 and the voltage isolation comparator 6. The isolation design improves the reliability of the acquisition system. Isolation prevents electrostatic discharge, leakage current, short circuits, and equipment failures, ensuring safety. It also isolates external surge energy and cuts off ground loop interference, thereby improving signal transmission quality.

[0047] Digital Isolator 5: such as Figure 3 As shown, DTrig_RX is a digital trigger signal provided by an external digital sensor or device, such as a temperature switch, Hall effect switch, or a digital trigger signal output from a higher-level data acquisition unit. The DTrig_RX signal is sent to the FPGA controller via U13 (digital isolator 5). The DTrig_TX signal is the DTrig_RX signal relayed internally within the FPGA, used to provide a trigger signal to the next-level acquisition device. Furthermore, the source of DTrig_TX is not limited to the DTrig_RX digital trigger signal; it can also come from analog trigger signals, such as… Figure 2 The analog trigger signal input to J11.

[0048] It is worth noting that digital isolator 5 is responsible for isolating external digital trigger signals and digital clock signals. Simultaneously, FPGA controller 2 acquires the external digital trigger signals and digital clock signals, and then sends these two signals to the next-level acquisition device through digital isolator 5 for synchronous hardware trigger sampling between multiple devices. The digital isolator does not change the logic level of the external digital signal; it only handles isolation and transmission. That is, when the external digital level changes from '1' to '0' or from '0' to '1', it can generate an edge-triggered level signal or a level-triggered signal.

[0049] Voltage isolation comparator 6: see Figure 2 U14 is a voltage isolation comparator 6, used via its IN pin to detect signals output from external analog sensors, such as voltage-output sensors (e.g., vibration sensors), current-output sensors (after passing through an external current-to-voltage converter), or analog trigger signals from a previous-stage data acquisition unit. This signal is compared to the threshold voltage of U14's REF pin. When the voltage of the input analog trigger signal Ui is higher than REF, the output signal ATRIG_IN of U14 changes, triggering the FPGA to start sampling. The LATCH pin is used to capture abnormal events within a specific time period when continuous detection mode is not available; this mode is used in some special scenarios. R47 and C80 are used as RC filters for external analog signals.

[0050] It is worth noting that the voltage isolation comparator 6 is used to isolate external analog trigger signals. At the same time, the comparison voltage VREF of the voltage isolation comparator 6 can be dynamically configured by configuring the digital potentiometer through the microcontroller 3. When the level value Vi of the external analog signal is greater than VREF, the output of the voltage isolation comparator 6 changes from low level to high level or from high level to low level, generating a trigger signal and sending it to the FPGA controller 2.

[0051] Digital potentiometer 7: See Figure 2 U15 is a digital potentiometer 7, which connects to the microcontroller via the IIC bus and receives configuration information from the microcontroller 3. The REF pin of U14 can provide 100uA of current. The resistance configuration range of the U15 digital potentiometer is 1K to 10K ohms, so the threshold voltage Vc range is 0.1V to 1V.

[0052] It is worth noting that the digital potentiometer 7 is used to adjust the reference voltage of the voltage isolation comparator, which is the comparison threshold of the analog trigger signal, for triggering judgment of signals with different amplitudes. The digital potentiometer 7 is connected to the microcontroller 3 via a digital bus. The microcontroller 3 sets the resistance value Rc of the digital potentiometer according to the required threshold voltage value. The REF pin of the voltage isolation comparator 6 is connected to an internal current source, which outputs a fixed current value I. The threshold voltage Vc = Rc * I. The digital potentiometer enables programmable analog signal threshold setting.

[0053] Digital output interface protection circuit 8, digital input interface protection circuit 9: see Figure 3 R42, R43, R44, and R45 are resistance matching resistors. Resetting fuses RT1-RT4 and TVS diodes D1-D4 are used for line surge protection.

[0054] It is worth noting that the digital output interface protection circuit 8 protects the digital trigger signals and digital clock signals forwarded by the digital isolator 5 from this device. Since these signals need to be connected to the next device via external signal lines, certain electrostatic discharge and surge protection measures are required. Similarly, the digital input interface protection circuit 9 protects the external digital trigger signals and digital clock signals input to the digital isolator 5.

[0055] Analog input interface protection circuit 10: See Figure 2 The TVS diode D5, decoupling resistor R48, and gas discharge diode G1 form a two-stage surge protection circuit for surge protection of analog signal lines.

[0056] It is worth noting that the analog input interface protection circuit 10 protects the voltage isolation comparator from damage caused by static electricity and surges generated on the external analog trigger signal line.

[0057] In summary, the data acquisition instrument with hardware triggering function in the above embodiments of this utility model improves data reliability by isolating external digital trigger signals / analog trigger signals through protection component 80 and isolation component 40, thereby avoiding the waste of storage space and computing resources by a large amount of low-value or irrelevant data. The FPGA controller 2 synchronously triggers external digital trigger signals / analog trigger signals by starting analog signal chain 1, and the isolation component 40 dynamically configures digital potentiometers through microcontroller 3, thereby adapting to different types of models and meeting the needs of scenarios with high real-time requirements.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0059] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A data acquisition instrument with hardware triggering function, characterized in that, The application relates to a digital-analog signal conversion device. The device comprises an analog signal chain, an FPGA controller connected with the analog signal chain, a microcontroller connected with the FPGA controller, an isolation component connected with the FPGA controller, a digital potentiometer connected with the FPGA controller and the microcontroller respectively, a protection component connected with the isolation component, wherein an external digital trigger signal / analogue trigger signal is input to the FPGA controller through the protection component and the isolation component in sequence, and the FPGA controller is triggered by starting the analog signal chain to synchronize the external digital trigger signal / analogue trigger signal, and the isolation component is dynamically configured to the digital potentiometer through the microcontroller to adapt to different types of models. An analog-to-digital converter is arranged in the analog signal chain. The analog signal chain is a static signal chain or a dynamic signal chain. The isolation component comprises an isolated power supply, a digital isolator and a voltage isolation comparator, the isolated power supply is connected with the digital isolator and the voltage isolation comparator respectively, the digital isolator is connected with the FPGA controller, and the voltage isolation comparator is connected with the FPGA controller. The FPGA controller receives the external digital trigger signal and the analogue trigger signal of the digital isolator and the voltage isolation comparator, and forwards the external digital trigger signal and the analogue trigger signal through the digital isolator. The protection component comprises a digital output interface protection circuit, a digital input interface protection circuit and an analogue input interface protection circuit, and the digital output interface protection circuit, the digital input interface protection circuit and the analogue input interface protection circuit are connected with the isolation component. The digital output interface protection circuit and the digital input interface protection circuit are both subjected to line surge protection through self-recovery fuses RT1-RT4 and TVS tubes D1-D4.

2. The data acquisition instrument with hardware triggering capability of claim 1, wherein, The analogue input interface protection circuit is subjected to secondary surge protection through a TVS tube D5, a decoupling resistor R48 and a gas discharge tube G1 for surge protection of an analogue signal line.

3. The data acquisition instrument with hardware triggering capability of claim 1, wherein, ​ 4. The data acquisition instrument with hardware triggering capability of claim 1, wherein, ​ 5. The data acquisition instrument with hardware triggering capability of claim 4, wherein, ​ 6. The data acquisition instrument with hardware triggering capability of claim 1, wherein, ​ 7. The data acquisition instrument with hardware triggering capability of claim 6, wherein, ​ 8. The data acquisition instrument with hardware triggering capability of claim 6, wherein, ​

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