Battery management system, chip, battery device and electric device

Abstract

The utility model discloses a battery management system, a chip, a battery device and a power utilization device. The battery management system comprises a filter circuit, wherein the input end of the filter circuit is coupled with the LIN bus; the filter circuit is configured to receive a communication message of the LIN bus and process the width of an interference signal in the communication message into the maximum clock period. According to the embodiment of the invention, the anti-interference capability of LIN bus communication can be improved.

Description

Technical Field

[0001] This application relates to the field of battery management technology, and in particular to a battery management system and chip, battery device and power consumption device. Background Technology

[0002] LIN (Local Interconnect Network) bus is widely used in vehicle control due to its low cost, providing communication between components such as windows, seats, windshield wipers, and air conditioning systems. These components need to have a low-power mode, meaning they enter a sleep state when not in operation and resume normal operation upon receiving a specific wake-up signal.

[0003] However, automotive electronics requirements mandate that onboard electronic devices undergo rigorous electromagnetic compatibility (EMC) testing, including Bulk Current Injection (BCI) testing. BCI interference can couple high-frequency common-mode currents onto the LIN bus. LIN bus devices in related technologies typically incorporate resistor-capacitor (RC) filters and transient voltage suppressor (TVS) diodes on the board-level system to enhance their anti-interference capabilities. However, for persistent low-frequency interference signals, the RC filter circuit cannot increase the filtering time constant to ensure the normal waveform of the communication signal; and for interference signals with amplitudes lower than the TVS clamping voltage, the suppression effect is very limited.

[0004] Continuous low-frequency interference signals can not only mix into normal waveforms and disrupt normal communication, but may also be incorrectly identified as communication messages by LIN bus devices, preventing devices that are supposed to enter hibernation from doing so, or causing devices in hibernation to be abnormally woken up or unable to be woken up. Utility Model Content

[0005] This application provides a battery management system and chip, a battery device and a power-consuming device, which can improve the anti-interference capability of LIN bus communication.

[0006] In a first aspect, this application provides a battery management system, including a filter circuit, the input of which is coupled to a LIN bus; the filter circuit is configured to receive communication messages from the LIN bus and process the width of interference signals in the communication messages to a maximum of one clock cycle.

[0007] According to the battery management system provided in the embodiments of this application, possible random transient glitches can be "standardized" into a synchronous pulse with a width of at most one clock cycle. By limiting the maximum width of the interference signal, it is easier for subsequent simple circuits to identify and filter it, thereby greatly reducing its impact on system functions and improving the anti-interference capability of LIN bus communication. This solves the problem that devices that should enter hibernation cannot enter hibernation normally, and devices in hibernation are abnormally woken up or cannot be woken up.

[0008] In one possible implementation of the first aspect, the filter circuit includes an OR gate and a plurality of D flip-flops, the clock terminals of the plurality of D flip-flops being coupled to the same clock signal line, the input terminal of the first-stage D flip-flop being coupled to a LIN bus, and the output terminal of the preceding-stage D flip-flop being coupled to the input terminal of the following-stage D flip-flop, the plurality of input terminals of the OR gate being coupled to the output terminals of the plurality of D flip-flops respectively, and the output terminal of the OR gate being the output terminal of the filter circuit.

[0009] According to the battery management system provided in the embodiments of this application, the filtering circuit includes multiple parallel D flip-flops, and the signals output by the multiple D flip-flops are finally output through an OR gate, which can unify and "standardize" possible random short-term glitches into a synchronous pulse with a width of at most one clock cycle. By limiting the maximum width of the interference signal, it is easier for the subsequent circuits of the filtering circuit to identify and filter it, thereby greatly reducing its impact on the system function and improving the anti-interference capability of LIN bus communication.

[0010] In one possible implementation of the first aspect, the filter circuit includes three D flip-flops and a first OR gate and a second OR gate; the two inputs of the first OR gate are respectively coupled to the outputs of the first-stage D flip-flops and the second-stage D flip-flops, the two inputs of the second OR gate are respectively coupled to the outputs of the third-stage D flip-flops and the first OR gate, and the output of the second OR gate is the output of the filter circuit.

[0011] In this embodiment, multiple D flip-flops are selected in parallel, which can simultaneously ensure both filtering effect and fast response speed, guaranteeing that the subsequent circuits of the filtering circuit can successfully receive the correct signal and thus perform the corresponding processing actions.

[0012] In one possible implementation of the first aspect, the battery management system further includes a receiver, and the filtering circuit includes a first filtering circuit, the input of which is coupled to a LIN bus via the receiver, the receiver being configured to receive sleep messages on the LIN bus and output them to the first filtering circuit.

[0013] In this embodiment, a first filtering circuit is provided after the receiver. The information received by the receiver from the LIN bus includes sleep messages. The first filtering circuit can filter out low-frequency interference signals in the sleep messages, which can effectively improve the stability of the signal and ensure the normal sleep of the LIN bus device during BCI interference.

[0014] In one possible implementation of the first aspect, the battery management system further includes a wake-up monitoring circuit, and the filtering circuit includes a second filtering circuit. The input of the second filtering circuit is coupled to the LIN bus through the wake-up monitoring circuit. The wake-up monitoring circuit is configured to monitor the wake-up signal on the LIN bus and output it to the second filtering circuit.

[0015] In this embodiment, a second filtering circuit is set after the wake-up monitoring circuit. The information received by the wake-up monitoring circuit from the LIN bus includes the wake-up signal. The second filtering circuit can filter out low-frequency interference signals in the wake-up signal, which can effectively improve the stability of the signal and ensure the normal wake-up of the LIN bus device in the event of BCI interference.

[0016] In one possible implementation of the first aspect, the filtering circuit includes a first filtering circuit and a second filtering circuit, the first filtering circuit being coupled to a first clock signal line, the second filtering circuit being coupled to a second clock signal line, and the clock signals of the first clock signal line and the second clock signal line having different frequencies.

[0017] Since the first and second filter circuits are used in different locations, and the pulse widths of the interference signals that the first and second filter circuits need to filter out are different, the filtering requirements of the two filter circuits can be flexibly met by setting the frequency of the clock signal connected to the two filter circuits to be different.

[0018] In one possible implementation of the first aspect, the signal accessed by the first filter circuit includes a sleep message, the signal accessed by the second filter circuit includes a wake-up signal, and the frequency of the clock signal of the first clock signal line is greater than the frequency of the clock signal of the second clock signal line.

[0019] Compared to a valid sleep message, a valid wake-up signal typically has a larger pulse width. Therefore, the period of the clock signal connected to the second filter circuit should be configured to be longer as needed to filter out interference signals that last for a longer period of time in the wake-up signal.

[0020] In one possible implementation of the first aspect, the receiver includes a first comparator, a first input terminal of the first comparator being coupled to a LIN bus via a first resistor, a second input terminal of the first comparator being coupled to a first reference voltage terminal, and an output terminal of the first comparator being coupled to the input terminal of a first filter circuit.

[0021] In this embodiment, the first resistor serves as a voltage divider resistor to protect subsequent devices from damage; the first comparator can convert analog voltage signals into digital voltage signals, which can then be recognized and processed by the MCU.

[0022] In one possible implementation of the first aspect, the battery management system further includes a second resistor and a third resistor connected in series between the battery and a ground terminal, wherein the series connection point of the second resistor and the third resistor is the first reference voltage terminal.

[0023] In this embodiment, the reference voltage required by the first comparator can be obtained by dividing the battery voltage using the second and third resistors, without the need for an additional voltage source as a reference voltage source, thus simplifying the circuit structure.

[0024] In one possible implementation of the first aspect, the wake-up monitoring circuit includes a follower and a second comparator;

[0025] The input of the follower is coupled to the LIN bus, the output of the follower is coupled to the first input of the second comparator, the second input of the second comparator is coupled to the second reference voltage, and the output of the second comparator is coupled to the input of the second filter circuit.

[0026] In this embodiment, the follower conditions and buffers the signals of the LIN bus; the second comparator can convert the analog voltage signal into a digital voltage signal, so that it can be recognized and processed by the MCU.

[0027] Based on the same technical concept, in a second aspect, embodiments of this application provide a battery device, including a battery and a battery management system as described in any embodiment of the first aspect.

[0028] Based on the same technical concept, in a third aspect, embodiments of this application provide an electrical device including a battery pack as described in the second aspect embodiment.

[0029] Based on the same technical concept, in a fourth aspect, embodiments of this application provide a battery management chip, including a filter circuit, the input of which is coupled to a LIN bus; the filter circuit is configured to receive communication messages from the LIN bus and process the width of interference signals in the communication messages to a maximum of one clock cycle.

[0030] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0031] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic diagram of the structure of a battery management system according to an embodiment of this application;

[0033] Figure 2 This is a schematic diagram of another battery management system according to an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the structure of another battery management system according to an embodiment of this application;

[0035] Figure 4 This is a timing diagram of a LIN communication message according to an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of the structure of another battery management system according to an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the structure of another battery management system according to an embodiment of this application;

[0038] Figure 7 A schematic diagram of the structure of a battery device provided in an embodiment of this application;

[0039] Figure 8 This is a schematic diagram of the structure of an electrical device provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy.

[0042] In this document, the terms “coupled,” “connected,” and “linked” are used to refer to a direct or indirect connection between two objects. For example, when describing a first object coupled to a second object, the first object is considered to be coupled to the second object even if it is not in direct physical contact with the second object, but is indirectly in contact with the second object through a conductor and / or other objects. The term “circuit” is widely used and intended to include hardware implementations of both electronic components and conductors that, when connected and configured, enable the performance of the functions described in this application, without being limited to the type of electronic circuit.

[0043] This application provides a battery management system (BMS) for implementing at least one of the following functions for individual battery cells: state monitoring, state analysis, charge / discharge control, safety protection, thermal management, high-voltage power distribution, and information management. In addition, the BMS can also implement the functions of a controller in an electrical device, such as a vehicle control unit (VCU) or a motor control unit (MCU), etc., and this application does not impose any limitations on this.

[0044] It should be noted that the battery management system in this application can be integrated as a controller into the battery device, such as into the battery pack or energy storage box.

[0045] The battery management system in this application can also be integrated as a controller into electrical devices, such as in a vehicle or vehicle chassis.

[0046] The battery management system in this application can also be integrated into the charging device as a controller, such as into the charging device or the battery swapping device.

[0047] The battery management system in this application can also be deployed as control software on a server. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms, such as vehicle networking cloud, APP backend, etc.

[0048] like Figure 1The battery management system provided in this application embodiment includes a filter circuit 10. The input terminal of the filter circuit 10 is coupled to a LIN bus, and the clock terminal of the filter circuit 10 is coupled to a clock signal line CLK. The filter circuit 10 is configured to receive communication messages from the LIN bus, process the interference signals in the communication messages into pulses with a maximum width of one clock cycle, and output them.

[0049] LIN bus is a low-speed serial communication standard based on a single-wire master-slave architecture, tailored for low-cost automotive applications. Through simplified protocols and hardware, it economically and efficiently controls a large number of simple electronic devices and is an indispensable underlying component of modern automotive layered network architectures.

[0050] For example, the filter circuit 10 and the LIN bus can be coupled through other circuits, such as a receiver or a wake-up monitoring circuit.

[0051] The filter circuit 10 receives communication messages from the LIN bus, including but not limited to sleep messages or wake-up signals, so that the device can go into sleep or wake up normally.

[0052] The LIN bus operates in a noisy automotive electrical environment, and the actual waveform of the signals on the LIN bus may contain glitches. The filter circuit 10 has the function of filtering out possible random and short-lived glitches, ensuring that a short-lived glitch (interference signal) can only last for a maximum of one clock cycle, thus preventing the interference signal from lasting for a sufficiently long time.

[0053] According to the battery management system provided in the embodiments of this application, possible random transient glitches can be "standardized" into a synchronous pulse with a width of at most one clock cycle. By limiting the maximum width of the interference signal, it is easier for subsequent simple circuits to identify and filter it, thereby greatly reducing its impact on system functions and improving the anti-interference capability of LIN bus communication. This solves the problem that devices that should enter hibernation cannot enter hibernation normally, and devices in hibernation are abnormally woken up or cannot be woken up.

[0054] In other words, the filter circuit 10 provided in this application is an anti-interference design that balances cost and effectiveness by adopting the strategy of "allowing passage but limiting harm".

[0055] In some embodiments, such as Figure 2As shown, the filter circuit 10 includes an OR gate 11 and multiple D flip-flops 12. The clock terminals of the multiple D flip-flops 12 are coupled to the same clock signal line CLK. The input terminal D of the first-stage D flip-flop 121 is coupled to the LIN bus, and the output terminal Q of the previous stage D flip-flop is coupled to the input terminal D of the next stage D flip-flop. The multiple input terminals of the OR gate 11 are respectively coupled to the output terminals Q of the multiple D flip-flops. The output terminal of the OR gate is the output terminal OUT of the filter circuit.

[0056] A D flip-flop is a basic digital logic unit circuit that is edge-triggered or level-triggered and has data storage and synchronization control functions. Its core function is to "capture" the current value of the data input terminal D and store it in its output terminal Q when the valid edge (or level) of the clock signal arrives, and maintain this state until the next valid clock event arrives.

[0057] An OR gate is a basic logic gate circuit whose core function is to perform a logical "OR" operation. Its rule is: when any one or more inputs are logical "true" (usually represented as a high level 1), the output is "true" (1); the output is "false" (0) only when all inputs are logical "false" (low level 0).

[0058] It should be noted that, Figure 2 Taking the filter circuit 10 as an example, which includes 3 D flip-flops 12, this is not intended to limit this application. The number of D flip-flops included in the filter circuit 10 can also be 2, 4, 5 or other values. Figure 2 Taking the filter circuit 10 as an example, which includes 2 OR gates 11, this is not intended to limit this application. For example, the filter circuit 10 may include one OR gate, and the number of input terminals of the OR gate is equal to the number of D flip-flops in the filter circuit; or, for example, the number of OR gates in the filter circuit is less than the number of D flip-flops, and the final output logic can conform to OUT=Q1 OR Q2 OR ……Qn, where Q1, Q2……Qn represent the signals output by the first-stage D flip-flops to the nth-stage D flip-flops, respectively.

[0059] Multiple D flip-flops receive the clock signal from the same clock signal line CLK and are asynchronously input to the LIN bus. The output signals of these multiple D flip-flops are ultimately output through an OR gate, forming a simplified "majority voter." This allows a brief glitch (interference signal) to likely only affect one of the D flip-flops (such as the first-stage D flip-flop), preventing the glitch from being applied long enough and being filtered out by subsequent D flip-flops. A real, stable signal change will subsequently affect all D flip-flops.

[0060] The following example, using a filter circuit 10 comprising three D flip-flops 12, illustrates how the filter circuit 10 can filter out transient positive glitches (logic "1" glitch):

[0061] Initial state: The first-stage D flip-flop 121 receives a logic "0" signal, Q1=Q2=Q3=0.

[0062] Glitches and Sampling: When a brief positive glitch occurs, assuming that at the rising edge of a clock signal, only the first-stage D flip-flop 121 captures the glitch (output Q1 becomes logic "1"), while the second-stage D flip-flop 122 and the third-stage D flip-flop 123 capture logic "0" due to slight timing differences; at this time, the state is: Q1=1, Q2=0, Q3=0; the output changes to: OUT=(1 OR 0) OR 0 =1, and the positive glitch causes the output to go high.

[0063] Glitches disappear and recover: In the next clock cycle, the glitches have already disappeared, and the input signal of the filter circuit recovers to a stable "0"; at the next rising edge of the clock, the first-stage D flip-flop 121 samples to 0, and Q1 changes from 1 back to 0; the second-stage D flip-flop 122 and the third-stage D flip-flop 123 also sample to 0, so Q2 and Q3 remain 0; at this time, the state is: Q1=0, Q2=0, Q3=0; the output changes: OUT=(0 OR 0) OR 0 = 0, and the output returns to a low level.

[0064] In summary, this brief spike generates a positive pulse with a width of only one clock cycle at the final output terminal OUT. A true, stable transition from 0 to 1 will cause the output terminal OUT to output a stable high level that lasts for at least three clock cycles (theoretically, it will continue indefinitely). Therefore, for the subsequent circuitry (such as the microcontroller unit MCU) following the filter circuit 10, distinguishing between a single-clock-cycle pulse and a stable high level is very easy. For example, if the subsequent circuitry is a state machine that requires multiple consecutive high-level cycles to be effective, then this single-cycle pulse can be easily filtered out.

[0065] The filter circuit 10 provided in this application includes multiple parallel D flip-flops, which can "normalize" possible random transient glitches into synchronous pulses with a width of at most one clock cycle. By limiting the maximum width of the interference signal, it makes it easier for subsequent simple circuits to identify and filter, thereby greatly reducing its impact on system function. In other words, the filter circuit 10 provided in this application is an anti-interference design that achieves a balance between cost and effectiveness with a strategy of "allowing passage but limiting harm".

[0066] Specifically, Table 1 shows that filter circuit 10 can improve anti-interference capability and allow valid signals to pass:

[0067] Table 1

[0068]

[0069] According to the battery management system provided in the embodiments of this application, the filter includes multiple parallel D flip-flops, and the signals output by the multiple D flip-flops are finally output through an OR gate. This can "standardize" any possible random and transient glitches into a synchronous pulse with a width of at most one clock cycle. By limiting the maximum width of the interference pulse, it is easier for the subsequent circuits of the filter to identify and filter it, thereby greatly reducing its impact on the system function and improving the anti-interference capability of LIN bus communication.

[0070] In some embodiments, such as Figure 2 As shown, the filter circuit 10 includes three D flip-flops 12 and a first OR gate 111 and a second OR gate 112; the three D flip-flops 12 are respectively a first-stage D flip-flop 121, a second-stage D flip-flop 122 and a third-stage D flip-flop 123.

[0071] The two inputs of the first OR gate 111 are coupled to the outputs of the first-stage D flip-flop 121 and the second-stage D flip-flop 122, respectively. The two inputs of the second OR gate 112 are coupled to the outputs of the third-stage D flip-flop 123 and the first OR gate 111, respectively. The output of the second OR gate 112 is the output OUT of the filter circuit.

[0072] Generally, the more parallel D flip-flops there are, the better the filtering effect on interference signals. However, each stage of D flip-flops introduces a clock cycle delay, so N stages of D flip-flops introduce N clock cycles of delay. Therefore, the more D flip-flops there are, the lower the pass rate of the effective signal, which in turn reduces the success rate of communication.

[0073] In this embodiment, three D flip-flops are used in parallel, which can simultaneously ensure both filtering effect and fast response speed, guaranteeing that the subsequent circuits of the filtering circuit can successfully receive the correct signal and then perform the corresponding processing actions.

[0074] Of course, the number of D flip-flops and / or the frequency of the clock signal in the filter circuit 10 can be adjusted according to the baud rate of the communication signal. For example, when the baud rate of the communication signal is low, the time width of the interference signal that can be filtered out can be increased, for example, by increasing the number of D flip-flops or decreasing the frequency of the clock signal, to increase the filtering time.

[0075] In some embodiments, such as Figure 3 As shown, the battery management system also includes a receiver 20, and the filtering circuit includes a first filtering circuit 101. The input terminal of the first filtering circuit 101 is coupled to the LIN bus through the receiver 20. The receiver 20 is configured to receive sleep messages on the LIN bus and output them to the first filtering circuit 101.

[0076] The output terminal OUT of the first filter circuit 101 is coupled to the first port LIN-RX, which can be coupled to a microcontroller unit (MCU). The receiver 20 converts LIN bus communication messages into digital logic signals that can be directly obtained by other components and transmits them through the first port LIN-RX, including sleep messages.

[0077] The hibernation of LIN bus devices is achieved by monitoring the arrival or timeout of hibernation messages on the LIN bus, primarily handled by receiver 20. During BCI testing, interference signals may cause hibernation message reception failures, preventing the LIN bus device from actively entering hibernation. Furthermore, continuous interference can disrupt the LIN bus's silent state, causing the LIN bus device to mistakenly believe that communication messages are present, leading to a continuous reset of the timeout counter and ultimately causing hibernation failure.

[0078] For example, such as Figure 4 As shown, a complete LIN protocol frame includes a header, a response, and several response spaces. The header includes a break field, a synchronization byte field, and an ID field, while the response includes data (Data1~DataN) and a checksum.

[0079] The hibernation message is the same as the normal message, but it has a defined special ID or data segment identifier. When the controller receives the message, it will switch from the normal state to the hibernation state.

[0080] For LIN communication with a baud rate of 19200, the duration of a data byte's level is 50us. The premise of filtering is that the real data should not be lost. Therefore, 10us is a relatively balanced value.

[0081] The RC filter circuit on the same layer of the board-level system can only handle most high-frequency signals with pulse widths less than 1µs. However, it is usually unable to handle low-frequency interference signals (such as interference signals with pulse widths of 1-10µs) in sleep messages. During BCI interference testing, signal fluctuations are very large. In this embodiment, a first filter circuit 101 is added after the receiver 20, which can filter out low-frequency interference signals with pulse widths of 10µs and below, effectively improving signal stability and reducing the number of lost messages.

[0082] Please refer to the reference. Figure 2 and Figure 3The first filter circuit 101 includes multiple parallel D flip-flops, and the signals output by the three D flip-flops are ultimately output via an OR gate. Taking the first filter circuit 101 as an example, which includes three D flip-flops 12, the D flip-flops can hold the input signal from the previous clock edge. When three consecutive input signals are all logic "0", the output signals Q1, Q2, and Q3 are output as logic "0" after passing through the OR gate, generating a valid signal (logic "0"). By controlling the externally input clock signal, the time for the first filter circuit 101 to obtain a valid signal can be controlled within 10µs, thereby filtering out low-frequency interference signals shorter than 10µs.

[0083] For example, when a low-frequency interference signal of less than 5µs is present, the detection result is "0" at the first clock edge. After being input to the first filter circuit 101, the output signal Q1 of the first-stage D flip-flop 121 in the first filter circuit 101 remains "0". At the next clock edge, the detection result is "1", causing the output signal Q1 of the first-stage D flip-flop 121 in the first filter circuit 101 to change to "1". The output signals Q2 of the second-stage D flip-flop 122 and Q3 of the third-stage D flip-flop 123 remain "0". Since Q1 is "1", the final output after entering the OR gate is "1". At this time, the subsequent circuits of the first filter circuit 101 can confirm that there is no valid signal input and will not reset the timeout count. Therefore, the first filter circuit 101 can effectively filter out low-frequency interference signals.

[0084] Only when a low-level signal with a pulse width greater than 10us is present will the three clock edge detection results remain "0", and the final output of the first filter circuit 101 will be "0". At this time, the subsequent circuits of the first filter circuit 101 confirm that there is a valid signal input, ensuring the normal sleep of the LIN bus device during BCI interference.

[0085] The operation of the first filter circuit 101 will not affect the signal waveform of the LIN bus, and the filtering effect of the first filter circuit can be adjusted as needed. For example, the first filter circuit 101 includes three parallel D flip-flops. When a signal is acknowledged, the shortest duration needs to be greater than two clock cycles. For example, the frequency of the clock signal connected to the first filter circuit 101 can be 200kHz, and the filtering time is 10us (i.e., 2*5us), thereby filtering out low-frequency interference signals less than 10us.

[0086] In this embodiment, a first filtering circuit 101 is provided after the receiver 20. The information received by the receiver 20 from the LIN bus includes sleep messages. The first filtering circuit 101 can filter out low-frequency interference signals in the sleep messages, which can effectively improve the stability of the signal and ensure the normal sleep of the LIN bus device during BCI interference.

[0087] In some embodiments, such as Figure 5 As shown, the battery management system also includes a wake-up monitoring circuit 30 and a filtering circuit including a second filtering circuit 102. The input terminal of the second filtering circuit 102 is coupled to the LIN bus through the wake-up monitoring circuit 30. The wake-up monitoring circuit 30 is configured to monitor the wake-up signal on the LIN bus and output it to the second filtering circuit 102.

[0088] The output terminal OUT of the second filter circuit 102 is coupled to the second port LIN-WAKE, which can be coupled to a microcontroller unit (MCU). The wake-up monitoring circuit 30 converts the LIN bus communication message into a digital logic signal that can be directly obtained by other components and transmits it through the second port LIN-WAKE, including a wake-up signal.

[0089] The first port LIN-RX and the second port LIN-WAKE can be coupled to different pins of the MCU.

[0090] The LIN bus device is woken up by monitoring a valid wake-up signal on the LIN bus. The wake-up signal is detected by the wake-up monitoring circuit 30. After detecting a valid wake-up signal, the wake-up monitoring circuit 30 notifies other components through the second port LIN-WAKE.

[0091] The wake-up signal is a logic "0" (dominant) level lasting more than 150µs, followed by a logic "1" (recessive) level lasting more than 4.5ms. The dominant level is low, and the recessive level is high. The LIN bus is in a recessive state when silent.

[0092] During BCI interference testing, the signal on the LIN bus fluctuated significantly, making it impossible for the signal on the LIN bus to remain silent. The inventors discovered that the typical interference signal frequency in BCI interference testing is between 150kHz and 80MHz. Therefore, using a 20µs digital filter can effectively filter out this waveform without affecting the normal detection of the wake-up signal.

[0093] The RC filter circuit on the same layer of the board-level system can only process most high-frequency signals with pulse widths less than 1µs. However, it is usually unable to handle low-frequency interference signals (such as interference signals with pulse widths of 20µs or less) in the wake-up signal. In this embodiment, a second filter circuit 102 is added after the wake-up monitoring circuit 30, which can filter out low-frequency interference signals with pulse widths of 20µs or less without affecting the normal detection of the wake-up signal.

[0094] Please refer to the reference. Figure 2 and Figure 5The second filter circuit 102 includes multiple parallel D flip-flops, and the signals output by the three D flip-flops are ultimately output via an OR gate. Taking the second filter circuit 102 as an example, which includes three D flip-flops 12, during BCI interference testing, in order to ensure that a continuous 4.5ms logic "1" level is detected normally, the second filter circuit 102 is added after the wake-up monitoring circuit 30. After a normal logic "0" (dominant) level is detected, the second filter circuit 102 begins to wait for a logic "1" (recessive) level that lasts longer than 4.5ms. Due to the presence of BCI interference, there is a high probability of logic "0" interference, which may cause the LIN bus device to fail to wake up normally. For example, if the frequency of the clock signal connected to the second filter circuit 102 is set to 50kHz, interference signals lasting less than 20µs can be filtered out, thus reducing the possibility of wake-up failure in actual applications.

[0095] In this embodiment, a second filtering circuit 102 is provided after the wake-up monitoring circuit 30. The information received by the wake-up monitoring circuit 30 from the LIN bus includes a wake-up signal. The second filtering circuit 102 can filter out low-frequency interference signals in the wake-up signal, which can effectively improve the stability of the signal and ensure the normal wake-up of the LIN bus device in the event of BCI interference.

[0096] It should be noted that in the above embodiments, the receiver 20, the wake-up monitoring circuit 30, the first filter circuit 101, and the second filter circuit 102 only process the signal to ensure the integrity of the signal and filter out interference signals, so that the subsequent circuits of the filter circuit can successfully receive the correct signal and then perform corresponding processing actions.

[0097] In some embodiments, please refer to the reference Figure 3 and Figure 5 The filtering circuit includes a first filtering circuit 101 and a second filtering circuit 102. The first filtering circuit 101 is coupled to the first clock signal line CLK1, and the second filtering circuit 102 is coupled to the second clock signal line CLK2. The clock signals of the first clock signal line and the second clock signal line have different frequencies.

[0098] The number of D flip-flops included in the first filter circuit 101 and the second filter circuit 102 can be the same. Since the first filter circuit 101 and the second filter circuit 102 are used in different positions, and the pulse widths of the interference signals that the first filter circuit 101 and the second filter circuit 102 need to filter are different, the filtering requirements of the two filter circuits can be flexibly met by setting the frequency of the clock signal connected to the two filter circuits to be different.

[0099] In some embodiments, the signal received by the first filter circuit 101 includes a sleep message, the signal received by the second filter circuit 102 includes a wake-up signal, and the frequency of the clock signal of the first clock signal line CKL1 is greater than the frequency of the clock signal of the second clock signal line CLK2.

[0100] The lower the frequency of the clock signal, the longer the period of the clock signal, and the wider the pulse width of the interference signals that can be filtered out.

[0101] Compared to a valid sleep message, a valid wake-up signal typically has a larger pulse width. Therefore, the period of the clock signal connected to the second filter circuit 102 should be configured to be longer as needed to filter out interference signals that last for a longer period of time in the wake-up signal.

[0102] In some embodiments, such as Figure 6 As shown, the receiver 20 includes a first comparator 21. The first input terminal of the first comparator 21 is coupled to the LIN bus through a first resistor R1. The second input terminal of the first comparator 21 is coupled to the first reference voltage terminal Vref1. The output terminal of the first comparator 21 is coupled to the input terminal of the first filter circuit 101. The output terminal of the first filter circuit 101 is coupled to the first port LIN-RX.

[0103] The LIN bus operates in a noisy automotive electrical environment, and the actual waveform of the signals on the LIN bus may contain glitches, with a voltage range from 0V to the battery voltage (typically 12V). Since the 12V voltage source on the LIN bus is higher than the MCU's withstand voltage (3.3V or 5V), direct connection would damage the chip. Therefore, a resistor divider network is first used to proportionally reduce the 12V signal to a level that the MCU's I / O ports can safely handle (e.g., converting 12V to 3.3V).

[0104] The signal after being divided by the first resistor R1 is an analog waveform, and the boundaries between its high and low levels may not be clear. At this point, the first comparator 21 starts to work.

[0105] The first comparator 21 requires a reference voltage, and the voltage at the first reference voltage terminal Vref1 can be set to a value between logic "0" and logic "1". For example, for a system with a target voltage of 3.3V, the voltage at the first reference voltage terminal Vref1 can be set to 1.65V.

[0106] If the LIN bus input voltage is higher than the voltage of the first reference voltage terminal Vref1, the first comparator 21 outputs a high level (e.g., 3.3V), representing logic '1' or 'recessive' (recessive bit).

[0107] If the LIN bus input voltage is lower than the voltage of the first reference voltage terminal Vref1, the first comparator 21 outputs a low level (e.g., 0V), representing logic '0' or 'dominant'.

[0108] The output of the first comparator 21 is a clean, steep digital signal (square wave) whose level fully conforms to the MCU's digital I / O standard.

[0109] The digital signal is first sent to the first filter circuit 101, and then sent by the first filter circuit 101 to the RX pin of the MCU's serial communication interface (such as UART), where the MCU performs subsequent byte parsing, verification and frame processing.

[0110] In this embodiment, the first resistor R1 serves as a voltage divider resistor to protect subsequent devices from damage; the first comparator 21 can convert analog voltage signals into digital voltage signals, which can then be recognized and processed by the MCU.

[0111] In some embodiments, such as Figure 6 As shown, the battery management system also includes a second resistor R2 and a third resistor R3, which are connected in series between the battery VBAT and the ground terminal GND. The series connection point of the second resistor R2 and the third resistor R3 is the first reference voltage terminal Vref1.

[0112] For example, the battery VBAT is also coupled to the LIN bus via diode D1 and a fourth resistor R4. Additionally, the battery VBAT can also serve as a power supply for the receiver 20 and the wake-up monitoring circuit 30.

[0113] For example, if the battery VBAT is a 12V battery, by adjusting the second resistor R2 and the third resistor R3, the voltage of the first reference voltage terminal Vref1 can be made to the target voltage.

[0114] In this embodiment, the reference voltage required by the first comparator can be obtained by dividing the battery voltage using the second and third resistors, without the need for an additional voltage source as a reference voltage source, thus simplifying the circuit structure.

[0115] In some embodiments, such as Figure 6 As shown, the wake-up monitoring circuit 30 includes a follower 31 and a second comparator 32. The input of the follower 31 is coupled to the LIN bus, and the output of the follower 31 is coupled to the first input of the second comparator 32. The second input of the second comparator 32 is coupled to the second reference voltage terminal Vref2, and the output of the second comparator 32 is coupled to the input of the second filter circuit 102. The output of the second filter circuit 102 is coupled to the second port LIN-WAKE.

[0116] For example, a resistor can be used to divide the battery voltage VBAT to obtain the second reference voltage terminal Vref2, which will not be elaborated here.

[0117] In sleep mode, the LIN bus is pulled up to the battery VBAT voltage (usually 12V) by the master node's pull-up resistor (such as the fourth resistor R4), which is a recessive level (logic 1).

[0118] The wake-up process is achieved by any node (master or slave) pulling the LIN bus low to ground (GND), generating a dominant level (logic 0). This dominant level needs to be maintained for a certain period of time to be considered a valid wake-up signal.

[0119] To monitor voltage changes on the LIN bus, a voltage divider is first needed to reduce the voltage to a level that the internal circuitry of the chip can handle (e.g., 3.3V). The divided signal may then need to drive multiple subsequent circuits. Here, voltage follower 31 can be a voltage follower, which performs the voltage divider process. Voltage followers have the characteristics of high input impedance and low output impedance. Their high input impedance prevents a load effect on the precise voltage divider network, ensuring the accuracy of the voltage division ratio; their low output impedance allows them to powerfully drive multiple subsequent circuits without interfering with each other.

[0120] Therefore, at this stage, the voltage follower 31 outputs a "conditioned" but still analog voltage signal that faithfully reflects the changes in the LIN bus voltage.

[0121] The analog voltage signal conditioned by the follower 31 is sent to a second comparator 32 dedicated to wake-up. The second comparator 32 compares the analog voltage signal output by the follower 31 with the voltage of the second reference voltage terminal Vref2 (also known as the wake-up reference voltage Vwake).

[0122] The voltage of the second reference voltage terminal Vref2 can be set at a threshold that can clearly distinguish the "recessive" (high level) and "dominant" (low level) states of the bus.

[0123] If the LIN bus voltage is higher than the voltage at the second reference voltage terminal Vref2, the second comparator 32 outputs a high level (e.g., 3.3V), representing logic '1' or 'recessive' (recessive bit). In this case, the LIN bus is in a recessive state and does not need to be woken up.

[0124] If the LIN bus voltage is lower than the voltage of the second reference voltage terminal Vref2, the second comparator 32 outputs a low level (e.g., 0V), representing logic '0' or 'dominant' (dominant bit). The LIN bus is pulled low and is in a dominant state, which may trigger a wake-up.

[0125] Interference signals on the LIN bus may also generate brief dominant levels. In this embodiment, the wake-up monitoring circuit 30 is followed by a second filter circuit 102. The second filter circuit 102 will only confirm a valid wake-up request after detecting a dominant level for a sufficiently long duration. The second filter circuit 102 outputs the identified valid wake-up signal to the second port LIN-WAKE, which is then connected to an external interrupt pin or a general purpose input / output port of the MCU.

[0126] In this embodiment, the follower conditions and buffers the signals of the LIN bus; the second comparator 32 can convert the analog voltage signal into a digital voltage signal, so that it can be recognized and processed by the MCU.

[0127] For example, such as Figure 6 As shown, the battery management system also includes a LIN bus controller 40 and a transmitter 50. The LIN bus controller 40 is coupled to a third port LIN-TX and the transmitter 50 for controlling the transmitter 50. The LIN bus controller 40 is also coupled to a receiver 20 for controlling the receiver 20.

[0128] Transmitter 50 includes driver 51 and switch 52, with driver 51 controlling the state of switch 52. Controller 40 and transmitter 50 convert data from the third port LIN-TX into messages conforming to LIN bus communication.

[0129] This application does not limit the specific structure of the LIN bus controller 40 and the transmitter 50.

[0130] Based on the same technical concept, embodiments of this application also provide a battery device. For example... Figure 7 As shown, the battery device 1000 provided in this application embodiment includes a battery 200 and a battery management system 100 as described in any of the above embodiments.

[0131] It is understood that the battery pack has the beneficial effects of the battery management system provided in the embodiments of this application. For details, please refer to the specific descriptions of the battery management system in the above embodiments. This embodiment will not repeat them here.

[0132] In this application, the battery device includes at least one battery cell and a battery management system. The connection method between multiple battery cells can be any method conventional in the art, such as series connection, parallel connection, or a hybrid connection that includes all of these connection methods. Hybrid connection refers to the series and parallel connection of multiple batteries, and there is no particular limitation on this.

[0133] Based on the same technical concept, this application also provides an electrical device. For example... Figure 8As shown, the power-consuming device 2000 provided in this application embodiment includes the battery device 1000 as described in any of the above embodiments.

[0134] It is understood that the electrical device has the beneficial effects of the battery pack provided in the embodiments of this application. For details, please refer to the specific description of the battery pack in the above embodiments. This embodiment will not repeat the description here.

[0135] In this application, the electrical device includes a battery device and an electrical load. The electrical device can be, but is not limited to, power equipment (such as electric vehicles, electric cars, electric boats, spacecraft), electronic equipment (such as mobile phones, tablets, laptops, bionic machines, digital cameras, electric toys, etc.), wearable devices (such as watches, bracelets, VR glasses, etc.), energy storage power stations, etc.

[0136] Based on the same technical concept, this application also provides a battery management chip, including a filter circuit. The input terminal of the filter circuit is coupled to a LIN bus, and the clock terminal of the filter circuit is coupled to a clock signal line. The filter circuit is configured to receive communication messages from the LIN bus, process the interference signals in the communication messages into pulses with a maximum width of one clock cycle, and output them.

[0137] The battery management chip provided in the embodiments of this application can "standardize" possible random short-term glitches into a synchronous pulse with a width of at most one clock cycle. By limiting the maximum width of the interference signal, it is made easier for subsequent simple circuits to identify and filter it, thereby greatly reducing its impact on system functions and improving the anti-interference capability of LIN bus communication. This solves the problem that devices that should enter sleep mode cannot enter sleep mode normally, and devices in sleep mode are abnormally woken up or cannot be woken up.

[0138] It should be noted that in the above embodiments, the resistor is presented as a single resistor. In other embodiments, the resistor may also be an integrated combination of series, parallel, or mixed resistors. Similarly, in the above embodiments, the capacitor is presented as a single capacitor. In other embodiments, the capacitor may also be an integrated combination of series, parallel, or mixed capacitors. The specific parameters of each device can be set according to actual needs, and this application does not limit this.

[0139] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0140] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A battery management system, characterized in that, It includes a filter circuit, the input of which is coupled to a LIN bus, and the clock terminal of which is coupled to a clock signal line. The filtering circuit is configured to receive communication messages from the LIN bus and process the width of interference signals in the communication messages to a maximum of one clock cycle.

2. The battery management system according to claim 1, characterized in that, The filtering circuit includes an OR gate and multiple D flip-flops. The clock terminals of the multiple D flip-flops are coupled to the same clock signal line. The input terminal of the first-stage D flip-flop is coupled to the LIN bus, and the output terminal of the previous-stage D flip-flop is coupled to the input terminal of the next-stage D flip-flop. The multiple input terminals of the OR gate are respectively coupled to the output terminals of the multiple D flip-flops. The output terminal of the OR gate is the output terminal of the filtering circuit.

3. The battery management system according to claim 2, characterized in that, The filter circuit includes three D flip-flops, a first OR gate, and a second OR gate; The two inputs of the first OR gate are coupled to the outputs of the first-stage D flip-flop and the second-stage D flip-flop, respectively. The two inputs of the second OR gate are coupled to the outputs of the third-stage D flip-flop and the first OR gate, respectively. The output of the second OR gate is the output of the filter circuit.

4. The battery management system according to any one of claims 1-3, characterized in that, The battery management system further includes a receiver, and the filtering circuit includes a first filtering circuit. The input of the first filtering circuit is coupled to the LIN bus through the receiver. The receiver is configured to receive sleep messages on the LIN bus and output them to the first filtering circuit.

5. The battery management system according to any one of claims 1-3, characterized in that, The battery management system further includes a wake-up monitoring circuit, and the filtering circuit includes a second filtering circuit. The input terminal of the second filtering circuit is coupled to the LIN bus through the wake-up monitoring circuit. The wake-up monitoring circuit is configured to monitor the wake-up signal on the LIN bus and output it to the second filtering circuit.

6. The battery management system according to any one of claims 1-3, characterized in that, The filtering circuit includes a first filtering circuit and a second filtering circuit. The first filtering circuit is coupled to a first clock signal line, and the second filtering circuit is coupled to a second clock signal line. The clock signals of the first clock signal line and the second clock signal line have different frequencies.

7. The battery management system according to claim 6, characterized in that, The signals input to the first filtering circuit include sleep messages, and the signals input to the second filtering circuit include wake-up signals. The frequency of the clock signal on the first clock signal line is greater than the frequency of the clock signal on the second clock signal line.

8. The battery management system according to claim 4, characterized in that, The receiver includes a first comparator, a first input terminal of which is coupled to the LIN bus via a first resistor, a second input terminal of which is coupled to a first reference voltage terminal, and an output terminal of which is coupled to the input terminal of the first filter circuit.

9. The battery management system according to claim 8, characterized in that, The battery management system further includes a second resistor and a third resistor, which are connected in series between the battery and the ground terminal, and the series connection point of the second resistor and the third resistor is the first reference voltage terminal.

10. The battery management system according to claim 5, characterized in that, The wake-up monitoring circuit includes a follower and a second comparator; The input terminal of the follower is coupled to the LIN bus, the output terminal of the follower is coupled to the first input terminal of the second comparator, the second input terminal of the second comparator is coupled to the second reference voltage terminal, and the output terminal of the second comparator is coupled to the input terminal of the second filter circuit.

11. A battery management chip, characterized in that, Includes a filter circuit, the input of which is coupled to a LIN bus; The filtering circuit is configured to receive communication messages from the LIN bus, process the interference signals in the communication messages into pulses with a maximum width of one clock cycle, and output them.

12. A battery device, characterized in that, Includes a battery and a battery management system as claimed in any one of claims 1 to 10.

13. An electrical appliance, characterized in that, Includes the battery device as described in claim 12.

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