Integrated circuit
By setting a via offset detection test unit on the integrated circuit, the problem of not being able to detect via offset in the DRAM manufacturing process in the prior art is solved, realizing real-time monitoring in the manufacturing process and improving product yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2026-04-07
AI Technical Summary
Existing technology cannot detect via offset during DRAM manufacturing, leading to reduced product yield.
A test unit for via offset detection is set on the integrated circuit. By detecting whether there is an offset between two adjacent conductor layers, the via offset can be detected during the manufacturing process.
It improves the monitoring capabilities in the DRAM manufacturing process, enabling timely handling of via misalignment issues, increasing product yield, and enhancing the accuracy and precision of judgment.
Smart Images
Figure CN224098137U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit technology, and relates to integrated circuits and their via offset detection technology, specifically an integrated circuit. Background Technology
[0002] DRAM is short for Dynamic Random Access Memory. It is formed by stacking multiple conductor layers. Through-holes are set between two adjacent conductor layers, and then metal is filled into the through-holes to form metal lines. The conductor layers are interconnected in the vertical direction through the metal lines, thereby enabling power supply and data exchange between the conductor layers.
[0003] During DRAM manufacturing, vias must not connect with two adjacent conductor layers, otherwise it will affect the functionality of the DRAM product. However, in actual manufacturing, vias often shift to one side. When a via shifts to one side, it may cause two adjacent conductor layers to connect, leading to a decrease in the reliability of the DRAM product. When the via shift is severe, it can also directly affect the yield of the DRAM product.
[0004] Existing technologies typically employ physical failure analysis (PFA) methods to detect via misalignment. These methods include ultrasonic microscopy, X-ray detection, focused ion beam microscopy, and probe detection. However, PFA methods can only detect via misalignment after DRAM product manufacturing is complete; they cannot detect via misalignment during the DRAM manufacturing process. This results in a detection lag. If via misalignment occurs and cannot be detected and addressed promptly during DRAM manufacturing, it significantly impacts the yield of the DRAM product. Utility Model Content
[0005] In view of the above-described background technology, the detection of via offset in the prior art is lagging and cannot be performed during the DRAM manufacturing process, which has a technical problem that affects the yield of DRAM products. In order to address this technical problem, this utility model proposes an integrated circuit.
[0006] This invention involves setting a test unit on an integrated circuit for via offset detection. The test unit detects whether there is an offset between two adjacent conductor layers, thereby determining whether the two adjacent conductor layers are connected. This enables the detection of via offset during DRAM manufacturing, improving the monitoring capability of the DRAM manufacturing process. At the same time, it allows processing personnel to promptly handle via offset problems based on the via offset detection results, thereby improving the yield of DRAM products.
[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0008] This utility model discloses an integrated circuit, wherein a test unit for through-hole offset detection is provided on the integrated circuit;
[0009] The test unit includes at least one set of conductor groups stacked sequentially from top to bottom. Each set of conductor groups includes two adjacent conductor layers and a through hole between the two adjacent conductor layers. When the through hole is offset, the through hole connects the two adjacent conductor layers; when the through hole is not offset, the two adjacent conductor layers are not connected through the through hole.
[0010] Further specifying, the test unit includes at least two sets of conductor groups stacked sequentially from top to bottom and a through hole disposed between two adjacent sets of conductor groups, wherein the two adjacent sets of conductor groups are connected in series or in parallel through the through hole.
[0011] Further defined, the two adjacent conductor layers include a first upper conductor layer and a first lower conductor layer, the first lower conductor layer includes a first lower conductor and a second lower conductor, and the through hole provided between the two adjacent conductor layers includes a first through hole, the first through hole being provided between the first upper conductor layer and the first lower conductor layer;
[0012] When the first via is offset, the first via connects the first upper conductor layer and the first lower conductor, or the first via connects the first upper conductor layer and the second lower conductor.
[0013] Further specified, the two adjacent conductor layers also include a second upper conductor layer and a second lower conductor layer, the second lower conductor layer includes a third lower conductor and a fourth lower conductor, and the through hole provided between the two adjacent conductor layers also includes a second through hole;
[0014] When the second via is offset, the second via connects the second upper conductor layer and the third lower conductor, or the second via connects the second upper conductor layer and the fourth lower conductor.
[0015] Further specifying, the first spacing is different from the second spacing. The first spacing refers to the spacing between the first through hole and the first lower conductor, or the spacing between the first through hole and the second lower conductor; the second spacing refers to the spacing between the second through hole and the third lower conductor, or the spacing between the second through hole and the fourth lower conductor.
[0016] Further specifying, the offset of the first through hole is determined based on the first spacing, and the offset of the second through hole is determined based on the second spacing. The formula for calculating the offset is as follows:
[0017] S0 = (ba) / 2
[0018] In the formula, S0 is the offset of the first through hole or the offset of the second through hole, in μm; b is the distance between the first lower conductor and the second lower conductor, which is the sum of twice the first distance and the radial dimension of the first through hole, or the distance between the third lower conductor and the fourth lower conductor, which is the sum of twice the second distance and the radial dimension of the second through hole, in μm; a is the radial dimension of the first through hole or the radial dimension of the second through hole, in μm.
[0019] Furthermore, the resistance values of the first lower conductor, the second lower conductor, the third lower conductor, and the fourth lower conductor are all different.
[0020] Further specified, the projected area of the first upper conductor layer can completely cover the projected area of the detection area, and the detection area includes at least the area between the first lower conductor and the second lower conductor;
[0021] The projected area of the second upper conductor layer can completely cover the projected area of the detection area, and the detection area also includes at least the area between the third and fourth lower conductors.
[0022] Further specified, the resistance values of the first lower conductor and the second lower conductor differ by at least one order of magnitude; the resistance values of the third lower conductor and the fourth lower conductor differ by at least one order of magnitude.
[0023] Further specifying, when two adjacent sets of conductors are connected in series through a via, both sets of conductors are provided with test pins; when two adjacent sets of conductors are connected in parallel through a via, the overlapping portion of the two sets of conductors is provided with test pins.
[0024] Compared with the prior art, the beneficial effects of this utility model are as follows:
[0025] 1. This utility model relates to an integrated circuit, which has a test unit for via offset detection on the integrated circuit. The test unit detects whether there is an offset between two adjacent conductor layers, thereby determining whether the two adjacent conductor layers are connected. This enables the detection of via offset during DRAM manufacturing, improves the monitoring capability of DRAM manufacturing, and facilitates the processing personnel to deal with via offset problems in a timely manner based on the via offset detection results, thereby improving the yield of DRAM products.
[0026] 2. In this utility model, the resistance values of the first lower conductor, the second lower conductor, the third lower conductor, and the fourth lower conductor are all different. The offset direction of the through hole can be determined based on the detected resistance value. At the same time, the offset amount of the through hole can be determined based on the distance between the first lower conductor and the second lower conductor and the radial dimension of the through hole, which facilitates a more accurate judgment of the through hole offset.
[0027] 3. In this utility model, the resistance values between the first lower conductor and the second lower conductor differ by at least one order of magnitude, and the resistance values between the third lower conductor and the fourth lower conductor differ by at least one order of magnitude. This can avoid misjudgment caused by the resistance values between the first lower conductor and the second lower conductor, as well as between the third lower conductor and the fourth lower conductor, being too small, thereby improving the accuracy of the judgment. Attached Figure Description
[0028] Figure 1 This is a front view of the conductor group;
[0029] Figure 2 Top view of the conductor group Figure 1 ;
[0030] Figure 3 Top view of the conductor group Figure 2 ;
[0031] Figure 4 Top view of the conductor group Figure 3 ;
[0032] Figure 5 Left view of the conductor group;
[0033] Figure 6 A top view of multiple conductor groups being tested in parallel;
[0034] Figure 7 A top view of multiple conductor groups being tested in series;
[0035] Figure 8 This is a schematic diagram showing how the offset of the first through hole is determined by the first spacing.
[0036] Figure 9 This is a schematic diagram illustrating the application of the integrated circuit of this invention in single-step photolithography size detection.
[0037] In the figure, 100 - first upper conductor layer, 200 - first via, 300 - first lower conductor layer, 301 - first lower conductor, 302 - second lower conductor, 400 - photolithography area. Detailed Implementation
[0038] To make the technical solution of this utility model clearer, the technical solution of this utility model will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Therefore, the following detailed description of the embodiments of this utility model provided in the accompanying drawings is not intended to limit the scope of protection, but merely to represent selected embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0039] This invention provides an integrated circuit with a test unit for via offset detection. The test unit includes at least one set of conductor groups stacked sequentially from top to bottom. Each conductor group includes two adjacent conductor layers and a via between them. When the via is offset, it connects the two adjacent conductor layers; when the via is not offset, the two adjacent conductor layers are not connected through the via. Specifically, during integrated circuit manufacturing, a test pin is provided on one of the two adjacent conductor layers. The resistance of the conductor layer is tested through the test pin. If a specific resistance is detected on the conductor layer, the via is offset, making the two adjacent conductor layers conductive; if the resistance is infinite, the via is not offset, and the two adjacent conductor layers are not conductive.
[0040] This invention can set the test pins in different directions to detect the offset of the through hole in the horizontal and vertical directions, including the offset direction and the offset amount in the corresponding direction.
[0041] This invention uses a test unit to detect whether there is an offset between two adjacent conductor layers, thereby determining whether the two adjacent conductor layers are connected. This enables the detection of via offset during DRAM manufacturing, improving the monitoring capabilities of the DRAM manufacturing process. At the same time, it allows processing personnel to promptly address via offset issues based on the detection results, thereby improving the yield of DRAM products.
[0042] In this invention, the test unit includes at least two sets of conductor groups stacked sequentially from top to bottom, and a through hole disposed between two adjacent sets of conductor groups. The adjacent sets of conductor groups are connected in series or in parallel through the through hole. See also Figure 6 In the case of two adjacent conductor groups connected in parallel, test pins are placed in the overlapping area of the two adjacent conductor groups. This reduces the number of test pins required and enables the detection of via misalignment between adjacent conductor groups. See also Figure 7 In the case of two adjacent conductor groups connected in series, test pins are provided on both conductor groups to detect the via offset between adjacent conductor groups. When there are multiple conductor groups, test pins can be provided only on the top conductor group. By detecting the resistance value corresponding to the top conductor group, the via offset can be determined. However, the resistance values of multiple conductor layers in the same conductor group corresponding to the same test pin should be different. Preferably, the resistance values of multiple conductor layers in the same conductor group corresponding to the same test pin should differ by at least one order of magnitude to reduce the error in judging the offset.
[0043] See Figure 1 , Figure 2 , Figure 3 and Figure 5 In this invention, two adjacent conductor layers include a first upper conductor layer 100 and a first lower conductor layer 300. The first lower conductor layer 300 includes a first lower conductor 301 and a second lower conductor 302. A through-hole is provided between the two adjacent conductor layers, including a first through-hole 200. The first through-hole 200 is located between the first upper conductor layer 100 and the first lower conductor layer 300. A test pin is located on the first upper conductor layer 100. By detecting the resistance value of the first upper conductor layer 100, the offset of the first through-hole 200 can be determined. When the first through-hole 200 is offset, the first through-hole 200 connects the first upper conductor layer 100 and the first lower conductor 301, or the first through-hole 200 connects the first upper conductor layer 100 and the second lower conductor 302. At this time, a specific resistance value can be detected on the first upper conductor layer 100. When the first through-hole 200 is not offset, the resistance value on the first upper conductor layer 100 is infinite.
[0044] In this invention, two adjacent conductor layers further include a second upper conductor layer and a second lower conductor layer. The second lower conductor layer includes a third lower conductor and a fourth lower conductor. The via between the two adjacent conductor layers also includes a second via. The test pin is disposed on the second upper conductor layer. By detecting the resistance value of the second upper conductor layer, the offset of the second via can be determined. When the second via is offset, the second via connects the second upper conductor layer and the third lower conductor, or the second via connects the second upper conductor layer and the fourth lower conductor. In this case, a specific resistance value can be detected on the second upper conductor layer. When the second via is not offset, the resistance value on the second upper conductor layer is infinite.
[0045] In this invention, the spacing between the first through hole 200 and the first lower conductor 301, and the spacing between the first through hole 200 and the second lower conductor 302, are both first spacings. The top end of the first through hole 200 is connected to the first upper conductor layer 100. When the first through hole 200 is not offset, it is located within the first spacing and is not connected to the first lower conductor 301 or the second lower conductor 302. When the first through hole 200 is offset, it shifts towards the side closer to the first lower conductor 301 or the side closer to the second lower conductor 302, so that the first through hole 200 is connected to the first lower conductor 301 or the second lower conductor 302. Therefore, the offset of the first through hole 200 can be determined by detecting the resistance value on the first upper conductor layer 100.
[0046] In this invention, the spacing between the second through hole and the third lower conductor, and the spacing between the second through hole and the fourth lower conductor, are both second spacings. The top of the second through hole is connected to the second upper conductor layer. When the second through hole is not offset, the bottom of the second through hole is located within the second spacing and is not connected to the third or fourth lower conductor. When the second through hole is offset, it shifts towards the side closer to the third or fourth lower conductor, so that the second through hole is connected to the third or fourth lower conductor. Therefore, the offset of the second through hole can be determined by detecting the resistance value on the second upper conductor layer.
[0047] In this invention, preferably, the first spacing and the second spacing are different, which can improve the accuracy of the offset detection result judgment.
[0048] See Figure 4 This invention can determine the offset of the first through hole 200 based on the first spacing and the offset of the second through hole based on the second spacing. Specifically, the formula for calculating the offset is as follows:
[0049] S0 = (ba) / 2
[0050] In the formula, S0 is the offset of the first through hole 200 or the offset of the second through hole, in μm; b is the distance between the first lower conductor 301 and the second lower conductor 302, which is the sum of twice the first distance and the radial dimension of the first through hole 200, or the distance between the third lower conductor and the fourth lower conductor, which is the sum of twice the second distance and the radial dimension of the second through hole, in μm; a is the radial dimension of the first through hole 200 or the radial dimension of the second through hole, in μm.
[0051] See Figure 8 A detailed schematic diagram showing the determination of the offset of the first through hole through the first spacing is shown in Table 1, and the detection results are shown in Table 1.
[0052] Table 1: Offset Detection Results of the First Through Hole
[0053]
[0054]
[0055] Depend on Figure 8 As can be determined from Table 1, the first through hole 200 is offset upwards, and the offset amount is between 3 and 4 μm.
[0056] In this invention, the resistance values of the first lower conductor 301, the second lower conductor 302, the third lower conductor, and the fourth lower conductor are all different. Preferably, the difference between the resistance values of the first lower conductor 301 and the second lower conductor 302 is at least one order of magnitude, and the difference between the resistance values of the third lower conductor and the fourth lower conductor is at least one order of magnitude. The larger the difference, the more accurate the judgment of the offset of the first through-hole 200 and the second through-hole through the detection results, and the lower the judgment error caused by the small difference. The different resistance values of the first lower conductor 301, the second lower conductor 302, the third lower conductor, and the fourth lower conductor can be achieved by different materials, different ion implantation concentrations, and different wiring methods (line length, line width), etc.
[0057] In this invention, the projected area of the first upper conductor layer 100 can completely cover the projected area of the detection area. The detection area includes at least the area between the first lower conductor 301 and the second lower conductor 302, to ensure that when the first through hole 200 is offset, the top of the first through hole 200 can still make full contact with the first upper conductor layer 100, thereby passing through the first upper conductor layer 100 for detection. The projected area of the second upper conductor layer can completely cover the projected area of the detection area, and the detection area also includes at least the area between the third lower conductor and the fourth lower conductor, to ensure that when the second through hole is offset, the top of the second through hole can still make full contact with the second upper conductor layer, thereby passing through the second upper conductor layer for detection.
[0058] The present invention relates to a method for detecting via offset of integrated circuits, the method comprising the following steps:
[0059] The resistance of the conductor group is measured; if the resistance is infinite, it is determined that the via is not offset; otherwise, it is determined that the via is offset.
[0060] The presence of through-hole offset includes both the first through-hole 200 and the second through-hole offset; the absence of through-hole offset includes both the first through-hole 200 and the second through-hole offset.
[0061] The first through hole 200 is offset as follows: when the resistance of the first upper conductor layer 100 is a first preset value, the first through hole 200 is offset in the direction of the first lower conductor 301, and the offset distance is a first distance; when the resistance of the first upper conductor layer 100 is a second preset value, the first through hole 200 is offset in the direction of the second lower conductor 302, and the offset distance is a first distance.
[0062] The first through-hole 200 has no offset if the resistance of the first upper conductor layer 100 is infinite.
[0063] The second via can be offset as follows: when the resistance of the second upper conductor layer is a third preset value, the second via is offset towards the third lower conductor by a distance equal to the second distance; when the resistance of the second upper conductor layer is a fourth preset value, the second via is offset towards the fourth lower conductor by a distance equal to the second distance.
[0064] The second via does not have any offset if the resistance of the second upper conductor layer is infinite.
[0065] See Figure 9 The via offset detection method for integrated circuits according to this invention can detect the photolithographic size of a 400-degree photolithographic region. Figure 9 By placing test pins at all four corners of a photolithographic region 400, the displacement of the four corners of the photolithographic region can be determined. Figure 9 The outward expansion indicates that the illumination of the entire photolithography area 400 has expanded, and the exposure area is larger than expected. Therefore, by placing the test units for via offset detection of this invention at the four corners of the photolithography area 400, the illumination level of the corresponding layer of the photolithography area 400 can be detected, thereby realizing the detection of common anomalies such as translation, magnification, reduction, or rotation.
[0066] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
Claims
1. An integrated circuit, characterized in that, The integrated circuit is provided with a test unit for via offset detection; The test unit includes at least one set of conductor groups stacked sequentially from top to bottom. Each set of conductor groups includes two adjacent conductor layers and a through hole between the two adjacent conductor layers. When the through hole is offset, the through hole connects the two adjacent conductor layers; when the through hole is not offset, the two adjacent conductor layers are not connected through the through hole.
2. The integrated circuit according to claim 1, characterized in that, The test unit includes at least two sets of conductor groups stacked sequentially from top to bottom and a through hole disposed between two adjacent sets of conductor groups, wherein the two adjacent sets of conductor groups are connected in series or in parallel through the through hole.
3. The integrated circuit according to claim 1 or 2, characterized in that, The two adjacent conductor layers include a first upper conductor layer (100) and a first lower conductor layer (300). The first lower conductor layer (300) includes a first lower conductor (301) and a second lower conductor (302). The through hole provided between the two adjacent conductor layers includes a first through hole (200). The first through hole (200) is provided between the first upper conductor layer (100) and the first lower conductor layer (300). When the first via (200) is offset, the first via (200) connects the first upper conductor layer (100) and the first lower conductor (301), or the first via (200) connects the first upper conductor layer (100) and the second lower conductor (302).
4. The integrated circuit according to claim 3, characterized in that, The two adjacent conductor layers also include a second upper conductor layer and a second lower conductor layer. The second lower conductor layer includes a third lower conductor and a fourth lower conductor. The through-hole provided between the two adjacent conductor layers also includes a second through-hole. When the second via is offset, the second via connects the second upper conductor layer and the third lower conductor, or the second via connects the second upper conductor layer and the fourth lower conductor.
5. The integrated circuit according to claim 4, characterized in that, The first spacing is different from the second spacing. The first spacing refers to the spacing between the first through hole (200) and the first lower conductor (301), or the spacing between the first through hole (200) and the second lower conductor (302); the second spacing refers to the spacing between the second through hole and the third lower conductor, or the spacing between the second through hole and the fourth lower conductor.
6. The integrated circuit according to claim 5, characterized in that, The offset of the first through hole (200) is determined based on the first spacing, and the offset of the second through hole is determined based on the second spacing. The formula for calculating the offset is as follows: S0 = (ba) / 2 In the formula, S0 is the offset of the first through hole (200) or the offset of the second through hole, in μm; b is the distance between the first lower conductor (301) and the second lower conductor (302), which is the sum of twice the first distance and the radial dimension of the first through hole (200), or the distance between the third lower conductor and the fourth lower conductor, which is the sum of twice the second distance and the radial dimension of the second through hole, in μm; a is the radial dimension of the first through hole (200) or the radial dimension of the second through hole, in μm.
7. The integrated circuit according to claim 5, characterized in that, The resistance values of the first lower conductor (301), the second lower conductor (302), the third lower conductor, and the fourth lower conductor are all different.
8. The integrated circuit according to claim 7, characterized in that, The projected area of the first upper conductor layer (100) can completely cover the projected area of the detection area, and the detection area includes at least the area between the first lower conductor (301) and the second lower conductor (302); The projected area of the second upper conductor layer can completely cover the projected area of the detection area, and the detection area also includes at least the area between the third and fourth lower conductors.
9. The integrated circuit according to claim 7, characterized in that, The resistance of the first lower conductor (301) and the resistance of the second lower conductor (302) differ by at least one order of magnitude; the resistance of the third lower conductor and the resistance of the fourth lower conductor differ by at least one order of magnitude.
10. The integrated circuit according to claim 2, characterized in that, When two adjacent sets of conductors are connected in series through a via, test pins are provided on both sets of conductors; when two adjacent sets of conductors are connected in parallel through a via, test pins are provided on the overlapping portion of the two sets of conductors.