Two-contact electronic cigarette system
By adding a decoding circuit to the two-contact electronic cigarette system, the problem that the host chip could not recognize the uplink data of the slave chip was solved, and the accurate recognition of the master control chip was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2026-04-10
AI Technical Summary
In a two-contact electronic cigarette system, the host chip cannot recognize the uplink data sent by the slave chip.
A decoding circuit is added to the two-contact electronic cigarette system. The slave anti-counterfeiting chip is connected through two contacts. The decoding circuit receives and decodes the uplink data sent by the slave anti-counterfeiting chip, enabling the main control chip to identify it.
This technology enables the main control chip to accurately identify the uplink data of the slave anti-counterfeiting chip, thus solving the problem of identification difficulties.
Smart Images
Figure CN224098792U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic technology field, more specifically, relate to a two contact electronic cigarette system. BACKGROUND
[0002] Figure 1 It is the block diagram of three contact electronic cigarette system, and the electronic cigarette holder and electronic cigarette cartridge are connected through three contacts, wherein, contact 1 and contact 2 transmit energy and information to realize the interaction of master chip and slave anti-fake chip, and contact 3 realizes the switch of heating wire.
[0003] Figure 2 It is the block diagram of two contact electronic cigarette system, and the electronic cigarette holder and electronic cigarette cartridge are connected through two contacts, and energy and information are transmitted through the two contacts, and the heating wire and slave chip in cartridge are parallelly connected.
[0004] Among them, the master chip sends data to the slave chip, which is downlink data, and the slave chip returns data to the master chip, which is uplink data.
[0005] Figure 3 It is the uplink data waveform schematic diagram of three contact electronic cigarette system and two contact electronic cigarette system respectively. Figure 3 V1, V2 and V3 shown in the figure represent the voltage amplitude of contact 2 at different time, and V1 is the voltage amplitude of contact 1 at different time. Figure 3 It can be seen that, in three contact electronic cigarette system, V1 voltage is close to 0V level, and V2 voltage is close to power supply voltage, which can be directly recognized as low level and high level by master chip without processing.
[0006] From three contact electronic cigarette system to two contact electronic cigarette system, the slave chip and heating wire are parallelly connected in two contact electronic cigarette system, and the resistance of heating wire is as small as about 1 ohm, which causes that the slave returns data 0 in uplink data and cannot be pulled down to close to 0V voltage like three contact scheme, V3 voltage is greater than 0V voltage, and V3 voltage is only slightly smaller than V2 voltage, so V3 voltage cannot be directly recognized as low level, and then the master chip cannot recognize the uplink data sent by slave. SUMMARY
[0007] The utility model provides a two contact electronic cigarette system in view of the technical problem existing in prior art, solves the problem that master cannot recognize the uplink data sent by slave.
[0008] The utility model provides a two contact electronic cigarette system, including electronic cigarette holder and electronic cigarette cartridge, the electronic cigarette holder includes master control chip, decoding circuit and first PMOS switch, and the electronic cigarette cartridge includes slave anti-fake chip;
[0009] The VCC pin of the master control chip is connected with the positive electrode of the battery, the C1 pin of the master control chip is connected with the KX pin of the decoding circuit, the C2 pin of the master control chip is connected with the DOUT pin of the decoding circuit, the K0 pin of the decoding circuit is connected with the gate of the first PMOS switch, the source of the first PMOS switch is connected with the positive electrode of the battery, the drain of the first PMOS switch is connected with the DIN pin of the decoding circuit, the GND pin of the decoding circuit is connected with the INOUT2 pin of the slave anti-fake chip through a first contact, the DIN pin of the decoding circuit is connected with the INOUT1 pin of the slave anti-fake chip through a second contact, and a heating wire is connected between the INOUT1 pin and the INOUT2 pin of the slave anti-fake chip.
[0010] The decoding circuit receives uplink data sent by the slave anti-fake chip to the master control chip through the second contact, and decodes the uplink data into signal data recognizable by the master control chip.
[0011] On the basis of the above technical scheme, the utility model still can make improvement as follows.
[0012] Optionally, the decoding circuit comprises a timing generation circuit, a comparator, a first switch S1 and a second switch S2, the input end of the timing generation circuit is connected with the C1 pin of the master control chip through a KX pin, the output signal K0 of the timing generation circuit is connected with the gate of the PMOS switch, the positive input VP pin of the comparator is connected with the DIN pin of the decoding circuit through the first switch S1, the DIN pin is grounded through a resistor R1 and a resistor R2, the negative input VN pin of the comparator is connected between the resistor R1 and the resistor R2 through the second switch S2, the output signal K1 of the timing generation circuit is connected with the first switch S1, and the output signal K2 of the timing generation circuit is connected with the second switch S2.
[0013] The positive input VP pin of the comparator is also grounded through a capacitor C1, and the negative input VN pin of the comparator is grounded through a capacitor C2.
[0014] Optionally, the timing generation circuit comprises a first timing generation sub-circuit and a second timing generation sub-circuit, the first timing generation sub-circuit comprises a plurality of series-connected inverters, the first timing generation sub-circuit outputs K0 signal and K2 signal through a plurality of series-connected inverters and a plurality of NAND gates.
[0015] The second timing generation sub-circuit comprises a plurality of series-connected inverters, and the second timing generation sub-circuit outputs signal K1 through the plurality of inverters.
[0016] Optionally, the first timing generation sub-circuit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate and a second NAND gate, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter are connected in series, an input end of the first inverter is connected to a KX pin of the decoding circuit, an output end of the fifth inverter is connected to one input end of the first NAND gate, the other input end of the first NAND gate is connected to the input end of the first inverter, an output end of the first NAND gate is connected to one input end of the second NAND gate, the other input end of the second NAND gate is connected to the input end of the first inverter, the output end of the first NAND gate outputs a signal K2, and an output end of the second NAND gate outputs a signal K0.
[0017] Optionally, the first switch S1 is a second PMOS switch, a drain of the second PMOS switch is connected to a positive input VP pin of the comparator, a source of the second PMOS switch is connected to a DIN pin of the decoding circuit, and a gate of the second PMOS switch is connected to a signal K1.
[0018] The second switch S2 is a third PMOS switch, a drain of the third PMOS switch is connected to a negative input VN pin of the comparator, a source of the third PMOS switch is connected to a common end of the resistor R1 and the resistor R2, and a gate of the third PMOS switch is connected to a signal K2.
[0019] The two-contact electronic cigarette system provided by the utility model increases the decoding circuit in the traditional two-contact electronic cigarette, the decoding circuit is connected to the slave anti-fake chip through two contacts, the decoding circuit receives uplink data sent by the slave anti-fake chip to the master control chip through the second contact, decodes the uplink data into signal data that can be recognized by the master control chip, and the utility model increases the decoding circuit in the two-contact electronic cigarette system, can decode uplink data sent by the slave anti-fake chip to the master control chip, and makes the master control chip accurately recognize the uplink data of the slave anti-fake chip. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 It is a circuit principle diagram of an existing three-contact electronic cigarette system;
[0021] Figure 2 It is a circuit principle diagram of an existing two-contact electronic cigarette system;
[0022] Figure 3 It is an uplink data waveform schematic diagram of an existing three-contact electronic cigarette system and two-contact electronic cigarette system;
[0023] Figure 4A circuit principle diagram of a two-contact electronic cigarette system is provided for an embodiment of the utility model.
[0024] Figure 5 A decoding circuit principle diagram of an embodiment of the utility model is provided.
[0025] Figure 6 A decoding circuit principle diagram of an embodiment of the utility model is provided.
[0026] Figure 7 A timing control waveform and a decoding waveform schematic diagram of the two-contact electronic cigarette system of the embodiment of the utility model are provided. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model. In addition, the technical features in each embodiment or single embodiment provided by the utility model can be combined with each other at will to form a feasible technical scheme, and this combination is not restricted by the order of steps and / or structure mode, but must be based on the realization by those skilled in the art, when the combination of technical schemes appears contradictory or cannot be realized, it should be considered that the combination of technical schemes does not exist, and is not within the protection scope required by the utility model.
[0028] Referring to Figure 4 , a circuit principle diagram of a two-contact electronic cigarette system of an embodiment of the utility model is provided, the two-contact electronic cigarette system comprises an electronic cigarette rod and an electronic cigarette cartridge, the electronic cigarette rod comprises a master control chip, a decoding circuit and a first PMOS switch (PMOS0), the electronic cigarette cartridge comprises a slave anti-fake chip.
[0029] The VCC pin of the master control chip is connected with the positive pole of the battery, the C1 pin of the master control chip is connected with the KX pin of the decoding circuit, the C2 pin of the master control chip is connected with the DOUT pin of the decoding circuit, the K0 pin of the decoding circuit is connected with the gate of the first PMOS switch, the source of the first PMOS switch is connected with the positive pole of the battery, the drain of the first PMOS switch is connected with the DIN pin of the decoding circuit, the GND pin of the decoding circuit is connected with the INOUT2 pin of the slave anti-fake chip through a first contact, the DIN pin of the decoding circuit is connected with the INOUT1 pin of the slave anti-fake chip through a second contact, and a heating wire is connected between the INOUT1 pin and the INOUT2 pin of the slave anti-fake chip.
[0030] The decoding circuit receives uplink data sent by the slave anti-fake chip to the master control chip through the second contact, and decodes the uplink data into signal data recognizable by the master control chip.
[0031] Referring to Figure 5 In an embodiment of the utility model, decoding circuit includes time sequence generation circuit, comparator, first switch S1 and second switch S2, the input of time sequence generation circuit is connected with C1 pin of master control chip through KX pin, the output signal K0 of time sequence generation circuit is connected with the gate of PMOS switch, the positive input VP pin of comparator is connected with DIN pin of decoding circuit through first switch S1, DIN pin is connected with ground through resistance R1 and resistance R2, the negative input VN pin of comparator is connected between resistance R1 and resistance R2 through second switch S2, the output signal K1 of time sequence generation circuit is connected with first switch S1, the output signal K2 of time sequence generation circuit is connected with second switch S2, the positive input VP pin of comparator is also connected with ground through capacitor C1, and the negative input VN pin of comparator is connected with ground through capacitor C2.
[0032] Wherein, first switch S1 switch is always closed, and the positive input VP of comparator=DIN signal.Second switch S2 is controlled by K2 signal, and capacitor C2 is charged once before each period, and after charging, the second S2 switch is disconnected, and because VN point has no load, VN can always keep equal to VR, VR=DIN / (R1+R2)*R2, and it is guaranteed that V3 voltage<VR voltage<V2 voltage, and in V3 voltage time period, because VP<VR, the output end DOUT of comparator outputs low level, and the decoded low level is transmitted to the master control chip.
[0033] Referring to Figure 6The timing generation circuit comprises a first timing generation sub-circuit and a second timing generation sub-circuit, the first timing generation sub-circuit comprises a plurality of inverters connected in series, the first timing generation sub-circuit outputs a K0 signal and a K2 signal through the plurality of inverters connected in series and a plurality of NAND gates, respectively; and the second timing generation sub-circuit comprises a plurality of inverters connected in series, and the second timing generation sub-circuit outputs a K1 signal through the plurality of inverters.
[0034] In one embodiment of the utility model, the first timing generation sub-circuit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate and a second NAND gate, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter are connected in series, an input end of the first inverter is connected with a KX pin of the decoding circuit, an output end of the fifth inverter is connected with one input end of the first NAND gate, the other input end of the first NAND gate is connected with the input end of the first inverter, an output end of the first NAND gate is connected with one input end of the second NAND gate, the other input end of the second NAND gate is connected with the input end of the first inverter, the output end of the first NAND gate outputs a signal K2, and the output end of the second NAND gate shows a signal K0.
[0035] In one embodiment of the utility model, the first switch S1 is a second PMOS (PMOS1) switch, a drain of the second PMOS switch is connected with a positive input VP pin of the comparator, a source of the second PMOS switch is connected with a DIN pin of the decoding circuit, and a gate of the second PMOS switch is connected with a signal K1.
[0036] The second switch S2 is a third PMOS (PMOS2) switch, a drain of the third PMOS switch is connected with a negative input VN pin of the comparator, a source of the third PMOS switch is connected with a common end of the resistor R1 and the resistor R2, and a gate of the third PMOS switch is connected with a signal K2.
[0037] In one embodiment of the utility model, Figure 7 The timing control waveform and the decoding waveform schematic diagram of the two-contact electronic cigarette system provided by the utility model are shown, KX, K0, K1 and K2 are all logic signals, the second PMOS switch is always open, the signal K1 is always 0, the third PMOS switch is opened when the signal K2 is 0, VR charges the capacitor C2, the capacitor C2 is charged once in each period, VR=VN is maintained, and the selection of R1 and R2 needs to ensure that V3 voltage < VR voltage < V2 voltage.
[0038] The utility model provides a kind of in traditional two contact electronic cigarette's cigarette holder increases decoding circuit, decoding circuit is connected slave anti-fake chip by two contacts, decoding circuit receives the uplink data that slave anti-fake chip sends to master control chip by second contact to master control chip, uplink data is decoded into signal data that the described master control chip can identify.
[0039] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.
[0040] Although the preferred embodiments of the utility model have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the utility model.
[0041] Obviously, those skilled in the art can make various modifications and variations to the utility model without departing from the spirit and scope of the utility model. Thus, if these modifications and variations of the utility model fall within the scope of the claims of the utility model and their equivalents, the utility model also intends to include these modifications and variations.
Claims
1. A two-contact electronic cigarette system, characterized in that, The electronic cigarette cartridge comprises a master control chip, a decoding circuit and a first PMOS switch, and the electronic cigarette cartridge comprises a slave anti-fake chip; The VCC pin of the master control chip is connected with the positive electrode of the battery, the C1 pin of the master control chip is connected with the KX pin of the decoding circuit, the C2 pin of the master control chip is connected with the DOUT pin of the decoding circuit, the K0 pin of the decoding circuit is connected with the gate of the first PMOS switch, the source of the first PMOS switch is connected with the positive electrode of the battery, the drain of the first PMOS switch is connected with the DIN pin of the decoding circuit, the GND pin of the decoding circuit is connected with the INOUT2 pin of the slave anti-fake chip through a first contact, the DIN pin of the decoding circuit is connected with the INOUT1 pin of the slave anti-fake chip through a second contact, and a heating wire is connected between the INOUT1 pin and the INOUT2 pin of the slave anti-fake chip. The decoding circuit receives uplink data sent by the slave anti-fake chip to the master control chip through the second contact, and decodes the uplink data into signal data recognizable by the master control chip.
2. A two-contact electronic cigarette system according to claim 1, characterised in that, The decoding circuit comprises a timing generation circuit, a comparator, a first switch S1 and a second switch S2, the input end of the timing generation circuit is connected with the C1 pin of the master control chip through the KX pin, the output signal K0 of the timing generation circuit is connected with the gate of the PMOS switch, the positive input VP pin of the comparator is connected with the DIN pin of the decoding circuit through the first switch S1, the DIN pin is grounded through a resistor R1 and a resistor R2, the negative input VN pin of the comparator is connected between the resistor R1 and the resistor R2 through the second switch S2, the output signal K1 of the timing generation circuit is connected with the first switch S1, and the output signal K2 of the timing generation circuit is connected with the second switch S2. The positive input VP pin of the comparator is also grounded through a capacitor C1, and the negative input VN pin of the comparator is grounded through a capacitor C2.
3. A two-contact electronic cigarette system according to claim 2, characterised in that, The timing generation circuit comprises a first timing generation sub-circuit and a second timing generation sub-circuit, the first timing generation sub-circuit comprises a plurality of serial inverters, the first timing generation sub-circuit outputs K0 signal and K2 signal through a plurality of serial inverters and a plurality of NAND gates, The second timing generation sub-circuit comprises a plurality of serial inverters, and the second timing generation sub-circuit outputs signal K1 through the plurality of inverters.
4. A two-contact electronic cigarette system according to claim 3, characterised in that, The first timing generation sub-circuit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate and a second NAND gate, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter are connected in series, an input end of the first inverter is connected to a KX pin of the decoding circuit, an output end of the fifth inverter is connected to one input end of the first NAND gate, another input end of the first NAND gate is connected to the input end of the first inverter, an output end of the first NAND gate is connected to one input end of the second NAND gate, another input end of the second NAND gate is connected to the input end of the first inverter, the output end of the first NAND gate outputs a signal K2, and an output end of the second NAND gate outputs a signal K0.
5. The two-contact electronic cigarette system of claim 2, wherein, The first switch S1 is a second PMOS switch, a drain of the second PMOS switch is connected to a positive input VP pin of the comparator, a source of the second PMOS switch is connected to a DIN pin of the decoding circuit, and a gate of the second PMOS switch is connected to a signal K1. The second switch S2 is a third PMOS switch, a drain of the third PMOS switch is connected to a negative input VN pin of the comparator, a source of the third PMOS switch is connected to a common end of the resistor R1 and the resistor R2, and a gate of the third PMOS switch is connected to a signal K2.