Negative pressure discharge circuit and power supply circuit

Abstract

In the negative voltage discharge circuit and the power supply circuit provided by the invention, a first output end of a logic circuit is connected with a grid electrode of a second MOS tube, a source electrode of the second MOS tube is connected with a VDD, and a drain electrode of the second MOS tube is connected with a grid electrode of a first MOS tube; the source electrode of the first MOS tube is grounded, and the drain electrode of the first MOS tube is used for being connected with a negative voltage discharge connecting end; the grid electrode of the third MOS tube is connected with the first output end of the non-overlapping circuit, and the source electrode of the third MOS tube is connected with the VDD; the drain electrode of the fourth MOS tube is connected with the drain electrode of the third MOS tube, the source electrode of the fourth MOS tube is grounded, and the third MOS tube and the fourth MOS tube are conducted based on the output of the non-overlapping circuit; one end of the first capacitor is connected in series between the drain electrode of the fourth MOS tube and the drain electrode of the third MOS tube, and the other end of the first capacitor is connected in series between the grid electrode of the first MOS tube and the drain electrode of the second MOS tube. And the discharging speed of the negative-voltage power supply circuit during power failure can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a negative voltage discharge circuit and a power supply circuit. BACKGROUND

[0002] Figure 1 A commonly used power supply circuit is shown in FIG. 1. The working voltage P OUT of the load circuit 02 is less than 0. As shown in FIG. 1, the output end of the DC-DC converter 01 is connected to the load circuit 02, and the DC-DC converter 01 is used to convert a voltage into the working voltage of the load circuit 02. The voltage can be the working voltage VDD of the DC-DC converter 01, or the input voltage P VIN input to the DC-DC converter 01. Figure 1

[0003] When the power supply circuit needs to stop working, VDD or P VIN is usually powered off. After the DC-DC converter 01 loses power, the DC-DC converter 01 will stop working, and thus the load circuit 02 stops working. Since the working voltage P OUT of the load circuit 02 is less than 0, the current of the load circuit 02 cannot flow back to VDD or P VIN, so that the falling speed of the working voltage P OUT is relatively slow. Figure 2 As shown in FIG. 2, the time for VDD to fall to 0V is T1, and the time for the working voltage P OUT to fall to 0V is T2, T2 is greater than T1. Ideally, the time for the working voltage P OUT to fall to 0V should be close to equal to the time for VDD to fall to 0V. If the time for the working voltage P OUT to fall to 0V is greater than the time for VDD to fall to 0V, it can cause the load circuit 02 to be abnormal, causing damage to devices in the load circuit 02 or causing poor user experience, etc. Figure 1 As shown in FIG. 2, the time for VDD to fall to 0V is T1, and the time for the working voltage P OUT to fall to 0V is T2, T2 is greater than T1. Ideally, the time for the working voltage P OUT to fall to 0V should be close to equal to the time for VDD to fall to 0V. If the time for the working voltage P OUT to fall to 0V is greater than the time for VDD to fall to 0V, it can cause the load circuit 02 to be abnormal, causing damage to devices in the load circuit 02 or causing poor user experience, etc. Figure 2 The utility model relates to a power supply circuit working voltage falling time sequence diagram. As shown in FIG. 2, the time for VDD to fall to 0V is T1, and the time for the working voltage P OUT to fall to 0V is T2, T2 is greater than T1. Ideally, the time for the working voltage P OUT to fall to 0V should be close to equal to the time for VDD to fall to 0V. If the time for the working voltage P OUT to fall to 0V is greater than the time for VDD to fall to 0V, it can cause the load circuit 02 to be abnormal, causing damage to devices in the load circuit 02 or causing poor user experience, etc. The utility model relates to a power supply circuit working voltage falling time sequence diagram. As shown in FIG. 2, the time for VDD to fall to 0V is T1, and the time for the working voltage P OUT to fall to 0V is T2, T2 is greater than T1. Ideally, the time for the working voltage P OUT to fall to 0V should be close to equal to the time for VDD to fall to 0V. If the time for the working voltage P OUT to fall to 0V is greater than the time for VDD to fall to 0V, it can cause the load circuit 02 to be abnormal, causing damage to devices in the load circuit 02 or causing poor user experience, etc. The utility model relates to a power supply circuit working voltage falling time sequence diagram. As shown in FIG. 2, the time for VDD to fall to 0V is T1, and the time for the working voltage P OUT to fall to 0V is T2, T2 is greater than T1. Ideally, the time for the working voltage P OUT to fall to 0V should be close to equal to the time for VDD to fall to 0V. If the time for the working voltage P OUT to fall to 0V is greater than the time for VDD to fall to 0V, it can cause the load circuit 02 to be abnormal, causing damage to devices in the load circuit 02 or causing poor user experience, etc.

[0004] Some embodiments provide a negative voltage discharge circuit and a power supply circuit to facilitate improving the discharge speed when the negative voltage power supply circuit is powered off.

[0005] Some embodiments provide a negative voltage discharge circuit, comprising:

[0006] A logic circuit, a first input end of the logic circuit is used to input a first control signal, and the logic circuit is used to logically process the first control signal;

[0007] A non-overlapping circuit, an input end of the non-overlapping circuit is connected to a second output end of the logic circuit;

[0008] A second MOS transistor, a gate of the second MOS transistor being connected to a second output of the logic circuit, a source of the second MOS transistor being connected to VDD;

[0009] A first MOS transistor, a gate of the first MOS transistor being connected to a drain of the second MOS transistor, a source of the first MOS transistor being grounded, a drain of the first MOS transistor being used for connecting a negative voltage discharge connection end; the first MOS transistor being turned on based on the first control signal processed by the logic circuit when VDD is powered off;

[0010] A third MOS transistor, a gate of the third MOS transistor being connected to a first output of the non-overlapping circuit, a source of the third MOS transistor being connected to VDD; the third MOS transistor being turned on based on an output of the first output of the non-overlapping circuit;

[0011] A fourth MOS transistor, a gate of the fourth MOS transistor being connected to a second output of the non-overlapping circuit, a drain of the fourth MOS transistor being connected to a drain of the third MOS transistor, a source of the fourth MOS transistor being grounded; the fourth MOS transistor being turned on based on an output of the second output of the non-overlapping circuit;

[0012] A first capacitor, one end of the first capacitor being connected in series between the drain of the fourth MOS transistor and the drain of the third MOS transistor, and the other end of the first capacitor being connected in series between the gate of the first MOS transistor and the drain of the second MOS transistor.

[0013] One of the above technical solutions has the following advantages or beneficial effects: the signal transmitted to the gate of the second MOS transistor is processed by the logic circuit, and the signal transmitted to the non-overlapping circuit is processed by the logic circuit, so that when the system is powered off, the negative voltage discharge circuit can still work. When VDD is not powered off, the second MOS transistor is turned on, the non-overlapping circuit turns on the third MOS transistor and turns off the fourth MOS transistor based on the logic circuit, so that the first capacitor is charged to pull up the voltage at the gate of the first MOS transistor, so that the first MOS transistor is in an off state, and the negative voltage discharge connection end is disconnected from the negative voltage discharge end. When VDD is powered off, the second MOS transistor is turned off based on the first control signal processed by the logic circuit, the non-overlapping circuit turns on the fourth MOS transistor, the voltage at one end of the first capacitor is pulled down to low, and the voltage at the other end of the first capacitor is pulled down to negative voltage, so that the first MOS transistor is turned on, and the negative voltage discharge connection end is connected to the negative voltage discharge end, so that the charge in the load circuit can flow into the ground through the negative voltage discharge circuit to accelerate the discharge of the load circuit after the power is off. Moreover, after VDD is dropped to 0V, the first MOS transistor is still in the on state, and the charge of the negative voltage discharge connection end continues to flow into the ground to continue the discharge of the charge in the load circuit. In this way, the discharge speed of the negative voltage supply circuit when the power is off is improved.

[0014] Some embodiments provide a negative voltage discharge circuit, the logic circuit further comprises a second signal input end, the logic circuit comprises a first inverter, a second inverter and a NAND gate;

[0015] The input end of the first inverter serves as a first signal input end, the output end of the first inverter is connected to the input end of the second inverter; the output end of the second inverter is connected to the first input end of the NAND gate, the second input end of the NAND gate serves as a second signal input end, and the output end of the NAND gate serves as a second output end; the gate of the second MOS tube is connected between the first inverter and the second inverter.

[0016] Another technical solution in the above technical solution has the following advantages or beneficial effects: the first control signal is transmitted to the first input end of the NAND gate after being processed twice by the first inverter and the second inverter. The NAND gate can perform logic judgment based on the signals input from the first input end and the second input end, and transmit the result to the non-overlapping circuit. When the second input end of the NAND gate is connected to the output end of the delay circuit, a certain time buffer is provided by using the delay circuit, which helps to adjust the timing of the signal and ensure the stability and reliability of the entire logic circuit. The logic circuit not only can realize effective processing of the input signal, but also can improve the working efficiency and stability of the entire negative voltage discharge circuit.

[0017] Some embodiments provide a negative voltage discharge circuit, further comprising a delay circuit;

[0018] The delay circuit comprises an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a second capacitor and a third capacitor;

[0019] The eleventh inverter, the twelfth inverter, the thirteenth inverter and the fourteenth inverter are connected in sequence; one end of the second capacitor is connected between the eleventh inverter and the twelfth inverter, and the other end of the second capacitor is grounded; one end of the third capacitor is connected between the twelfth inverter and the thirteenth inverter, and the other end of the third capacitor is grounded.

[0020] Another technical solution in the above technical solution has the following advantages or beneficial effects: when the second control input end receives a high-level signal, the eleventh inverter inverts it to a low-level signal and outputs it to the twelfth inverter. The twelfth inverter inverts the low-level signal to a high-level signal and outputs it to the thirteenth inverter. Similarly, the thirteenth inverter and the fourteenth inverter invert the signal in turn, and finally the fourteenth inverter outputs a low-level signal opposite to the initial high-level signal to the second signal input end of the logic circuit. The second capacitor and the third capacitor have a delay effect, and delay the transmission speed of the signal through the charging and discharging process, thereby realizing the delay function. After receiving the second control signal, the delay circuit can have a certain time delay to perform subsequent operations, so that after the system is powered off, the negative voltage discharge circuit can continue to operate, which is beneficial to the stable operation and accurate control of the negative voltage discharge circuit.

[0021] Some embodiments provide a negative voltage discharge circuit, the non-overlapping circuit comprising an OR gate, a fourth inverter, a fifth inverter, an AND gate, a sixth inverter and a seventh inverter;

[0022] The first input end of the OR gate serves as the input end of the non-overlapping circuit, the output end of the OR gate is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter serves as the first output end of the non-overlapping circuit;

[0023] The first input end of the AND gate is connected to the first input end of the OR gate, the output end of the AND gate is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter serves as the second output end of the non-overlapping circuit;

[0024] The second input end of the OR gate is connected to the output end of the seventh inverter, and the second input end of the AND gate is connected to the output end of the fifth inverter.

[0025] The other technical solution in the above technical solution has the following advantages or beneficial effects: when the input end receives a high-level signal, the OR gate outputs a high-level signal to the fourth inverter, the fourth inverter inverts it into a low-level signal and transmits it to the fifth inverter, the fifth inverter inverts it again, and outputs a high-level signal as the signal of the first output end of the non-overlapping circuit. At the same time, the AND gate outputs a low-level signal to the sixth inverter, the sixth inverter inverts it into a high-level signal and transmits it to the seventh inverter, the seventh inverter inverts it again, and outputs a low-level signal as the signal of the second output end of the non-overlapping circuit. At this time, the first output end is high-level, and the second output end is low-level, realizing non-overlapping output. When the fifth inverter outputs a high-level signal, the high-level signal output by the fifth inverter is transmitted to the AND gate through the second input end of the AND gate, and the AND gate logically processes the high-level signal input by the first input end and the high-level signal input by the first input end, and the seventh inverter outputs a high-level signal as the signal of the second output end of the non-overlapping circuit. When the input end receives a low-level signal, the output state of the OR gate will depend on the state of the second input end, that is, the second output end of the seventh inverter. If the second output end is low-level, the OR gate outputs a low-level signal, and after being inverted by the fourth inverter and the fifth inverter, the first output end will be low-level. At the same time, the AND gate outputs a low-level signal because at least one of the two input ends is low-level, and after being inverted by the sixth inverter and the seventh inverter, the second output end remains low-level. In this way, the third MOS tube and the fourth MOS tube are prevented from being turned on at the same time through the non-overlapping circuit.

[0026] Some embodiments provide a negative voltage discharge circuit, further comprising a voltage limiting circuit; the voltage limiting circuit comprises a fifth MOS tube, the drain of the fifth MOS tube is grounded, and the gate of the fifth MOS tube and the source of the fifth MOS tube are both connected between the drain of the second MOS tube and the gate of the first MOS tube.

[0027] The other technical solution in the above technical solution has the following advantages or beneficial effects: the negative voltage discharge circuit comprises a fifth MOS tube, the drain of the fifth MOS tube is grounded, and the gate of the fifth MOS tube and the source of the fifth MOS tube are both connected between the drain of the second MOS tube and the gate of the first MOS tube. In this way, the negative voltage discharge circuit controls the maximum value of the gate voltage of the first MOS tube by using the fifth MOS tube, so that the voltage of the gate and the source of the fifth MOS tube is in the negative voltage region, and the negative voltage discharge circuit can be used for negative voltage discharge.

[0028] Some embodiments provide a negative voltage discharge circuit, further comprising a first resistor and a second resistor;

[0029] One end of the first resistor is connected to the drain of the first MOS tube, and the other end of the first resistor is connected to the negative voltage discharge connection end;

[0030] One end of the second resistor is connected to the drain of the second MOS tube, and the other end of the second resistor is connected to the gate of the first MOS tube.

[0031] Another technical solution in the above technical solution has the following advantages or beneficial effects: the first resistor is connected in series between the drain of the first MOS tube and the negative voltage discharge connection end, the current size of the negative voltage discharge circuit is controlled through the first resistor, and then the discharge speed of the negative voltage discharge is controlled. The second resistor is connected in series between the drain of the second MOS tube and the gate of the first MOS tube, so that current limiting is facilitated when the second MOS tube is turned on, and the use reliability of the negative voltage discharge circuit is facilitated.

[0032] Some embodiments provide a negative voltage discharge circuit, the non-overlapping circuit comprising an eighth inverter, a ninth inverter, a tenth inverter, a first PMOS tube, a first NMOS tube, a second NMOS tube, a second PMOS tube, a third PMOS tube and a third NMOS tube.

[0033] The input end of the eighth inverter serves as the input end of the non-overlapping circuit; the output end of the eighth inverter is connected to the gate of the first PMOS tube, the second, further comprising a delay circuit, the logic circuit further comprising a second signal input end; the delay circuit comprises a first buffer, a second buffer, a third buffer and a fourth buffer connected in sequence; the input end of the first buffer serves as the second control input end of the negative voltage discharge circuit, the output end of the fourth buffer is connected to the gate of the second NMOS tube, the third PMOS tube and the third NMOS tube; the source of the first PMOS tube is connected to VDD, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is grounded, and the first output end of the non-overlapping circuit is connected between the drain of the first PMOS tube and the drain of the first NMOS tube;

[0034] The source of the second PMOS tube is connected to VDD, the drain of the second PMOS tube is connected to the source of the third PMOS tube, the drain of the third PMOS tube and the drain of the third NMOS tube, the source of the third NMOS tube is grounded, and the second output end of the non-overlapping circuit is connected between the drain of the third PMOS tube and the drain of the third NMOS tube;

[0035] The input end of the ninth inverter is connected to the second output end of the non-overlapping circuit, and the output end of the ninth inverter is connected to the gate of the first NMOS tube; the input end of the tenth inverter is connected to the first output end of the non-overlapping circuit, and the output end of the tenth inverter is connected to the gate of the third PMOS tube.

[0036] Another one of the above technical solutions has the following advantages or beneficial effects: when the input end is high, the eighth inverter outputs low, making the first PMOS conductive and the first NMOS non-conductive, at this time, the first output end is high, and at the same time, the second NMOS is conductive, but since the first NMOS is non-conductive, it does not affect the level state of the first output end. The ninth inverter input end is low, and the ninth inverter output high makes the first NMOS remain in a non-conductive state. When the tenth inverter receives the high level signal of the first output end, the tenth inverter outputs low to the gate of the third PMOS, making the third PMOS cut off, and the third NMOS is in a cut-off state since the gate is directly connected to the output of the eighth inverter, making the second output end remain low. Conversely, when the input end is low, the states of various devices are opposite, realizing non-overlapping output. In this way, the third MOS and the fourth MOS are prevented from being conductive at the same time through the non-overlapping circuit.

[0037] Some embodiments provide a negative voltage discharge circuit, further comprising a voltage limiting circuit; the voltage limiting circuit comprises a diode, the anode of the diode is connected to the gate of the first MOS, and the cathode of the diode is grounded.

[0038] Another one of the above technical solutions has the following advantages or beneficial effects: the negative voltage discharge circuit includes a diode, the anode of the diode is connected to the gate of the first MOS, and the cathode of the diode is grounded. In this way, the negative voltage discharge circuit uses the diode to control the maximum value of the gate voltage of the first MOS, so that the gate of the first MOS can be maintained at a state lower than 0V, and the negative voltage discharge circuit can be used for negative voltage discharge.

[0039] Some embodiments provide a power supply circuit, comprising:

[0040] A DC-DC converter, the output end is used to connect a load circuit, so that the DC-DC converter provides operating voltage for the load circuit, and the operating voltage is less than 0;

[0041] A negative voltage discharge circuit, the negative voltage discharge connection end of the negative voltage discharge circuit is connected between the DC-DC converter and the load circuit, and the negative voltage discharge end of the negative voltage discharge circuit is grounded; wherein the negative voltage discharge circuit is the negative voltage discharge circuit provided in the above embodiments, the drain of the first MOS in the negative voltage discharge circuit is used as the negative voltage discharge connection end, and the source of the first MOS is used as the negative voltage discharge end.

[0042] Another technical solution in the above technical solution has the following advantages or beneficial effects: the power supply circuit includes a negative voltage discharge circuit, a negative voltage discharge connection end of the negative voltage discharge circuit is connected between the DC-DC converter and the load circuit, and a negative voltage discharge end of the negative voltage discharge circuit is grounded. When the power supply circuit is powered off, the negative voltage discharge connection end is conducted with the negative voltage discharge end, so that the charge in the load circuit flows into the ground through the negative voltage discharge circuit, thereby realizing that the charge in the load circuit quickly flows into the ground when the power supply circuit is powered off, and facilitating to improve the discharge speed when the negative voltage power supply circuit is powered off. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0044] Figure 1 A commonly used power supply circuit;

[0045] Figure 2 A Figure 1 Timing diagram of working voltage drop of power supply circuit;

[0046] Figure 3 Structure diagram of a power supply circuit according to some embodiments;

[0047] Figure 4 Structure diagram of a negative voltage discharge circuit according to some embodiments;

[0048] Figure 5 Structure diagram of another negative voltage discharge circuit according to some embodiments;

[0049] Figure 6A Structure diagram of a logic circuit according to some embodiments;

[0050] Figure 6B Structure diagram of another logic circuit according to some embodiments;

[0051] Figure 7A Structure diagram of a non-overlapping circuit according to some embodiments;

[0052] Figure 7B A Figure 7A Timing diagram of non-overlapping circuit;

[0053] Figure 7C Structure diagram of another non-overlapping circuit according to some embodiments;

[0054] Figure 8A This is a structural diagram of a voltage limiting circuit according to some embodiments;

[0055] Figure 8B This is a structural diagram of another voltage limiting circuit according to some embodiments;

[0056] Figure 9A This is a structural diagram of a delay circuit according to some embodiments;

[0057] Figure 9B for Figure 9A Waveform delay diagram of a medium-delay circuit;

[0058] Figure 9C This is a structural diagram of another delay circuit according to some embodiments;

[0059] Figure 10 This is a timing diagram of a negative voltage discharge circuit according to some embodiments. Detailed Implementation

[0060] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0061] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," or "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0062] Figure 3 This is a structural diagram of a power supply circuit according to some embodiments. For example... Figure 3As shown, in some embodiments, the power supply circuit includes a DC-DC converter 100, a load circuit 200 and a negative voltage discharge circuit 300. An output terminal of the DC-DC converter 100 is connected to a power input terminal of the load circuit 200, and the DC-DC converter 100 is configured to provide a working voltage for the load circuit 200, and the working voltage is a negative voltage. A negative voltage discharge connection terminal VDISCH of the negative voltage discharge circuit 300 is connected between the DC-DC converter 100 and the load circuit 200, and a negative voltage discharge terminal of the negative voltage discharge circuit 300 is connected to ground.

[0063] When the power supply circuit is powered off, the negative voltage discharge connection terminal VDISCH of the negative voltage discharge circuit 300 and the negative voltage discharge terminal of the negative voltage discharge circuit 300 are turned on, and the charges in the load circuit 200 can quickly flow to the ground through the negative voltage discharge circuit 300, so as to accelerate the discharge of the load circuit 200.

[0064] In some embodiments, the negative voltage discharge circuit 300 can include a first control input terminal CKT, and the first control input terminal CKT is configured to input a first control signal to the negative voltage discharge circuit 300. The first control signal can be used to control the negative voltage discharge connection terminal VDISCH and the negative voltage discharge terminal of the negative voltage discharge circuit 300 to be turned on. For example, the first control signal can be a high level signal, such as 1.

[0065] In some embodiments, the DC-DC converter 100 has an under-voltage latch function or an under-voltage protection function, etc. When the VDD of the DC-DC converter 100 drops to a preset value or below, the signal output terminal of the DC-DC converter 100 outputs an under-voltage latch signal or an under-voltage protection signal, etc. The under-voltage latch signal or the under-voltage protection signal can be a high level, such as 1. For example, when the VDD of the DC-DC converter 100 drops to 60% of the working voltage, the signal output terminal of the DC-DC converter 100 outputs an under-voltage latch signal or an under-voltage protection signal, etc.

[0066] In some embodiments, the first control input terminal CKT of the negative voltage discharge circuit 300 can be connected to the signal output terminal of the DC-DC converter 100. The first control signal can be an under-voltage latch signal or an under-voltage protection signal, etc.

[0067] In some embodiments, the negative voltage discharge circuit 300 can include a second control input terminal DISCH, and the second control input terminal DISCH is configured to input a second control signal to the negative voltage discharge circuit 300. The second control signal can be used to control the negative voltage discharge circuit 300 to start.

[0068] In some embodiments, the second control signal can be a high level signal, such as 1. When the second control input DISCH receives the high level signal, the negative voltage discharge circuit 300 is activated to perform the discharge operation on the load circuit 200. After the discharge operation is completed, the negative voltage discharge circuit 300 can be automatically stopped and wait for the next activation signal.

[0069] Figure 4 FIG. 1 is a schematic diagram of a negative voltage discharge circuit according to some embodiments. As shown in FIG. 1, in some embodiments, the negative voltage discharge circuit 300 can include a logic circuit 310. The logic circuit 310 can include a first signal input, which is a first control input CKT of the logic circuit 310. The logic circuit 310 includes a first output and a second output. Figure 4

[0070] In some embodiments, the logic circuit 310 can include a second signal input, which can be connected to VDD.

[0071] In some embodiments, the negative voltage discharge circuit 300 can include a first MOS transistor 301. The gate of the first MOS transistor 301 is connected to the first output of the logic circuit 310 and the second output of the logic circuit 310. The source of the first MOS transistor 301 is connected to ground. The drain of the first MOS transistor 301 is connected to a negative voltage discharge connection VDISCH. Exemplarily, the source of the first MOS transistor 301 can be used as a negative voltage discharge end of the negative voltage discharge circuit, and the drain of the first MOS transistor 301 can be used as a negative voltage discharge connection end of the negative voltage discharge circuit. The drain of the first MOS transistor 301 can be a PMOS transistor, such as LD-PMOS. When the first MOS transistor 301 is turned on, the negative voltage discharge connection end VDISCH will be connected to ground.

[0072] In some embodiments, the negative voltage discharge circuit 300 can include a first resistor 302. One end of the first resistor 302 is connected to the drain of the first MOS transistor 301, and the other end of the first resistor 302 is connected to the negative voltage discharge connection end VDISCH, so that the first resistor 302 is connected in series between the drain of the first MOS transistor 301 and the negative voltage discharge connection end VDISCH. When the first MOS transistor 301 is turned on, the charge of the negative voltage discharge connection end VDISCH flows into the ground through the first resistor 302. By adjusting the resistance value of the first resistor 302, the size of the discharge current can be adjusted, and thus the discharge speed of the negative voltage discharge can be adjusted.

[0073] ​In some embodiments, the negative voltage discharge circuit 300 can include a second MOS transistor 303. The gate of the second MOS transistor 303 is connected to the first output of the logic circuit 310, the source of the second MOS transistor 303 is connected to VDD, and the drain of the second MOS transistor 303 is connected to the gate of the first MOS transistor 301. The second MOS transistor 303 can be a PMOS transistor, such as an LD-PMOS. When VDD is powered off, the second MOS transistor 303 is turned off.

[0074] In some embodiments, the negative voltage discharge circuit 300 can include a second resistor 304. One end of the second resistor 304 is connected to the drain of the second MOS transistor 303, and the other end of the second resistor 304 is connected to the gate of the first MOS transistor 301, such that the second resistor 304 is connected in series between the drain of the second MOS transistor 303 and the gate of the first MOS transistor 301. The second resistor 304 can be used for current limiting.

[0075] In some embodiments, the negative voltage discharge circuit 300 can include a non-overlap circuit 320. The non-overlap circuit 320 includes an input IN, a first output OUTP, and a second output OUTN. When the second output of the logic circuit 310 inputs a signal to the non-overlap circuit 320, the non-overlap circuit 320 outputs two signals through the first output OUTP and the second output OUTN based on the received signal, and the start time and the end time of the output of the two signals are different.

[0076] In some embodiments, the negative voltage discharge circuit 300 can include a third MOS transistor 305. The gate of the third MOS transistor 305 is connected to the first output OUTP of the non-overlap circuit 320, the source of the third MOS transistor 305 is connected to VDD, and the drain of the third MOS transistor 305 is connected to the gate of the first MOS transistor 301. The third MOS transistor 305 can be turned on based on the signal output by the first output OUTP.

[0077] In some embodiments, the negative voltage discharge circuit 300 can include a fourth MOS transistor 306. The gate of the fourth MOS transistor 306 is connected to the second output OUTN of the non-overlap circuit 320, the source of the fourth MOS transistor 306 is connected to ground, and the drain of the fourth MOS transistor 306 is connected to the gate of the first MOS transistor 301. The fourth MOS transistor 306 can be turned on based on the signal output by the second output OUTN.

[0078] In some embodiments, the third MOS transistor 305 can be a PMOS transistor, and the fourth MOS transistor 306 can be an NMOS transistor. The third MOS transistor 305 and the fourth MOS transistor 306 can be prevented from being turned on at the same time by the non-overlap circuit 320.

[0079] In some embodiments, the negative voltage discharge circuit 300 can include a first capacitor 307. One end of the first capacitor 307 is connected to the drain of the third MOS 305 and the drain of the fourth MOS 306, and the other end of the first capacitor 307 is connected to the gate of the first MOS 301. Exemplarily, the other end of the first capacitor 307 is connected between the other end of the second resistor 304 and the gate of the first MOS 301.

[0080] In some embodiments, when the input IN of the non-overlapping circuit 320 receives a signal, the first output OUTP outputs a first signal, and the second output OUTN outputs a second signal, the first signal is output earlier than the second signal. The third MOS 305 is turned on based on the first signal, and the fourth MOS 306 is turned on based on the second signal. When the third MOS 305 is turned on, VDD charges the first capacitor 307; when the fourth MOS 306 is turned on, the charge on the first capacitor 307 flows to the ground, so that the first capacitor 307 is discharged.

[0081] In some embodiments, the negative voltage discharge circuit 300 can include a voltage limiting circuit 330. The input of the voltage limiting circuit 330 is connected to the ground, and the output of the voltage limiting circuit 330 is connected to the gate of the first MOS 301, and the voltage limiting circuit 330 is used to control the maximum value of the gate voltage of the first MOS 301. Exemplarily, the maximum value of the gate voltage of the first MOS 301 is denoted as VG_M1_MAX, and the minimum value of the gate voltage of the first MOS 301 is denoted as VG_M1_MIN, VG_M1_MIN = VG_M1_MAX - VDD. Therefore, the voltage limiting circuit 330 can determine the gate voltage when the first MOS 301 is turned on.

[0082] Figure 5 A structural diagram of another negative voltage discharge circuit according to some embodiments. As shown in Figure 5 In some embodiments, the negative voltage discharge circuit 300 can include a delay circuit 340. The input of the delay circuit 340 is used as the second control input DISCH, and the output of the delay circuit 340 can be connected to the second signal input of the logic circuit 310. The delay circuit 340 can delay the time when the second control signal is transmitted to the second signal input of the logic circuit 310.

[0083] Figure 6A A structural diagram of a logic circuit according to some embodiments. As shown in Figure 6AAs shown, in some embodiments, the logic circuit 310 can include a first inverter 311, a second inverter 312, and a third inverter 313, the second inverter 312 being connected in series between the first inverter 311 and the third inverter 313. The input end of the first inverter 311 serves as a first control input end CKT, the gate of the second MOS tube 303 is connected between the first inverter 311 and the second inverter 312, and the output end of the third inverter 313 is connected to the input end IN of the non-overlapping circuit 320.

[0084] When the first control signal is transmitted to the logic circuit 310 through the input end of the first inverter 311, the first inverter 311 first inverts the first control signal, and then transmits it to the second inverter 312. The second inverter 312 inverts the signal again, so that the signal output to the third inverter 313 is the same in phase as the original first control signal. The third inverter 313 further inverts the signal, and finally outputs the processed signal to the input end IN of the non-overlapping circuit 320. Through the design of such a logic circuit 310, the stability and accuracy of the signal can be ensured, providing a basis for the normal operation of the subsequent circuit. At the same time, the gate of the second MOS tube 303 is connected between the first inverter 311 and the second inverter 312, and the second MOS tube 303 can be turned off based on the first control signal inverted by the first inverter 311, which can effectively control the signal and enhance the flexibility and reliability of the circuit.

[0085] Figure 6B is a structural diagram of another logic circuit according to some embodiments. As shown, Figure 6B As shown, in some embodiments, the logic circuit 310 can include a first inverter 311, a second inverter 312, and a NAND gate 314. The input end of the first inverter 311 can serve as a first signal input end, the output end of the first inverter 311 is connected to the input end of the second inverter 312, the output end of the second inverter 312 is connected to the first input end of the NAND gate 314, the NAND gate 314 can be connected to VDD or the output end of the delay circuit 340, and the output end of the NAND gate 314 is connected to the input end IN of the non-overlapping circuit 320.

[0086] The first control signal is transmitted to the first input end of the NAND gate 314 after being inverted twice by the first inverter 311 and the second inverter 312. The NAND gate 314 can perform logic judgment based on the signal input from the first input end and the signal input from the second input end, and transmit the result to the non-overlapping circuit 320. When the second input end of the NAND gate 314 is connected to the output end of the delay circuit 340, a certain time buffer is provided by using the delay circuit 340, which helps to adjust the timing of the signal and ensure the stability and reliability of the entire logic circuit. The logic circuit 310 not only can effectively process the input signal, but also can improve the working efficiency and stability of the entire negative voltage discharge circuit.

[0087] Figure 7A is a structure diagram of a non-overlapping circuit according to some embodiments. As shown in Figure 7A some embodiments, the non-overlapping circuit 320 includes an OR gate 321, a fourth inverter 322, a fifth inverter 323, an AND gate 324, a sixth inverter 325, and a seventh inverter 326. A first input end of the OR gate 321 can be used as an input end IN of the non-overlapping circuit 320, a first input end of the AND gate 324 is connected to the first input end of the OR gate 321, so that the first input end of the OR gate 321 and the first input end of the AND gate 324 are respectively connected to a second output end of the logic circuit 310. An output end of the OR gate 321 is connected to an input end of the fourth inverter 322, an output end of the fourth inverter 322 is connected to an input end of the fifth inverter 323, and an output end of the fifth inverter 323 is used as a first output end OUTP of the non-overlapping circuit 320. A second input end of the AND gate 324 is connected to the output end of the fifth inverter 323, an output end of the AND gate 324 is connected to an input end of the sixth inverter 325, an output end of the sixth inverter 325 is connected to an input end of the seventh inverter 326, and an output end of the seventh inverter 326 is used as a second output end OUTN of the non-overlapping circuit 320. A second input end of the OR gate 321 is connected to the output end of the seventh inverter 326.

[0088] Figure 7B is a timing diagram of the non-overlapping circuit in Figure 7A some embodiments. The working process of the non-overlapping circuit 320 is as follows:

[0089] When the input end IN receives a high-level signal, the OR gate 321 outputs a high-level signal to the fourth inverter 322, the fourth inverter 322 inverts it into a low-level signal and transmits it to the fifth inverter 323, the fifth inverter 323 inverts it again, and outputs a high-level signal as the signal of the first output end OUTP of the non-overlapping circuit 320. At the same time, the AND gate 324 outputs a low-level signal to the sixth inverter 325, the sixth inverter 325 inverts it into a high-level signal and transmits it to the seventh inverter 326, the seventh inverter 326 inverts it again, and outputs a low-level signal as the signal of the second output end OUTN of the non-overlapping circuit 320. At this time, the first output end OUTP is high-level, and the second output end OUTN is low-level, realizing non-overlapping output. When the fifth inverter 323 outputs a high-level, the high-level signal output by the fifth inverter 323 is transmitted to the AND gate 324 through the second input end of the AND gate 324, the AND gate 324 logically processes the high-level signal input by the first input end and the high-level signal input by the first input end, and the seventh inverter 326 outputs a high-level signal and serves as the signal of the second output end OUTN of the non-overlapping circuit 320.

[0090] When the input terminal IN receives a low-level signal, the output state of OR gate 321 will depend on the state of its second input terminal, namely the second output terminal OUTN of the seventh inverter 326. If OUTN is low, OR gate 321 outputs a low-level signal. After being inverted by the fourth inverter 322 and the fifth inverter 323, the first output terminal OUTP will be low. At the same time, AND gate 324 outputs a low-level signal because at least one of its two input terminals is low. After being inverted by the sixth inverter 325 and the seventh inverter 326, the second output terminal OUTN remains low.

[0091] Thus, when the input signal IN changes from low to high, the first output OUTP immediately becomes high, while the second output OUTN only becomes high after the first output OUTP has been high for TN1 time. When the input signal IN changes from high to low, the first output OUTP only becomes low after the second output OUTN has become low. Therefore, the non-overlapping circuit 320 will not result in a situation where the second output OUTN is high and the first output OUTP is low. Furthermore, the non-overlapping circuit 320 ensures that high levels do not overlap during TN1 time and low levels do not overlap during TN2 time, with both TN1 and TN2 being greater than 0.

[0092] Figure 7C This is a structural diagram of another non-overlapping circuit according to some embodiments. For example... Figure 7CAs shown, in some embodiments, the non-overlap circuit 320 can include an eighth inverter 327, a ninth inverter 328, a tenth inverter 329, a first PMOS transistor 3211, a first NMOS transistor 3212, a second NMOS transistor 3213, a second PMOS transistor 3214, a third PMOS transistor 3215, and a third NMOS transistor 3216. An input of the eighth inverter 327 can serve as an input IN of the non-overlap circuit 320, an output of the eighth inverter 327 is connected to a gate of the first PMOS transistor 3211, a source of the first PMOS transistor 3211 is connected to VDD, a drain of the first PMOS transistor 3211 is connected to a drain of the first NMOS transistor 3212, a connection between the drain of the first PMOS transistor 3211 and the drain of the first NMOS transistor 3212 is a first output OUTP of the non-overlap circuit 320, a source of the first NMOS transistor 3212 is connected to a drain of the second NMOS transistor 3213, a gate of the second NMOS transistor 3213 is connected to the output of the eighth inverter 327, a source of the second NMOS transistor 3213 is grounded, an input of the ninth inverter 328 can be connected to a second output OUTN of the non-overlap circuit 320, an output of the ninth inverter 328 is connected to a gate of the first NMOS transistor 3212. A gate of the second PMOS transistor 3214 is connected to the output of the eighth inverter 327, a source of the second PMOS transistor 3214 is connected to VDD, a drain of the second PMOS transistor 3214 is connected to a source of the third PMOS transistor 3215, a drain of the third PMOS transistor 3215 is connected to a drain of the third NMOS transistor 3216, a source of the third NMOS transistor 3216 is grounded, a gate of the third NMOS transistor 3216 is connected to the output of the eighth inverter 327, an input of the tenth inverter 329 is connected to the first output OUTP, an output of the tenth inverter 329 is connected to a gate of the third PMOS transistor 3215, a connection between the drain of the third PMOS transistor 3215 and the drain of the third NMOS transistor 3216 is the second output OUTN of the non-overlap circuit 320.

[0093] The operation of the non-overlapping circuit 320 is as follows: When the input terminal IN is high, the eighth inverter 327 outputs a low level, causing the first PMOS transistor 3211 to turn on and the first NMOS transistor 3212 to turn off. At this time, the first output terminal OUTP is high. Simultaneously, the second NMOS transistor 3213 turns on, but since the first NMOS transistor 3212 is off, it does not affect the level state of the first output terminal OUTP. When the input terminal of the ninth inverter 328 is low, the ninth inverter 328 outputs a high level, keeping the first NMOS transistor 3212 off. When the tenth inverter 329 receives the high-level signal from the first output terminal OUTP, the tenth inverter 329 outputs a low level to the gate of the third PMOS transistor 3215, causing the third PMOS transistor 3215 to turn off. Since the gate of the third NMOS transistor 3216 is directly connected to the output of the eighth inverter 327, the third NMOS transistor 3216 is in the off state, keeping the second output terminal OUTN low. Conversely, when the input terminal IN is low, the states of each device are reversed, achieving non-overlapping output.

[0094] In this embodiment, the first NMOS transistor 3212 and the second PMOS transistor 3214 provide isolation. When the signal at the input terminal IN changes from low to high, the level of the first output terminal OUTP is not affected by the first NMOS transistor 3212 and can immediately become high. The level of the second output terminal OUTN is limited by the voltage of the second PMOS transistor 3214 and will only become high after the level of the first output terminal OUTP becomes high. When the signal at the input terminal IN changes from high to low, the level of the second output terminal OUTN can immediately become low. The first output terminal OUTP is limited by the voltage of the second PMOS transistor 3214 and will only become low after the level of the second output terminal OUTN becomes low. Therefore, there will be no situation where the second output terminal OUTN is high and the first output terminal OUTP is low. Thus, the non-overlapping circuit 320 provided in this embodiment can also achieve... Figure 7A The function of the non-overlapping circuit 320 shown.

[0095] Figure 8A This is a structural diagram of a voltage limiting circuit according to some embodiments. For example... Figure 8A As shown, in some embodiments, the voltage limiting circuit 330 may include a diode 331. The anode of diode 331 is connected to the gate of the first MOSFET 301, and the cathode of diode 331 is grounded. VG_M1_MAX is equal to the forward voltage drop of diode 331.

[0096] Figure 8B This is a structural diagram of another voltage limiting circuit according to some embodiments. For example... Figure 8AAs shown, in some embodiments, the voltage limiting circuit 330 may include a fifth MOSFET 332. The drain of the fifth MOSFET 332 is grounded, and the gate and source of the fifth MOSFET 332 are respectively connected to the gate of the first MOSFET 301. Exemplarily, the gate and source of the fifth MOSFET 332 are both connected between the other end of the second resistor 304 and the gate of the first MOSFET 301.

[0097] In some embodiments, the fifth MOSFET 332 may be an NMOS transistor. VG_M1_MAX is equal to the threshold voltage of the fifth MOSFET 332, and the voltage between the gate and source of the fifth MOSFET 332 will be in the negative voltage region.

[0098] Figure 9A This is a structural diagram of a delay circuit according to some embodiments. Figure 9A As shown, in some embodiments, the delay circuit 340 may include an eleventh inverter 341, a twelfth inverter 342, a thirteenth inverter 343, a fourteenth inverter 344, a second capacitor 345, and a third capacitor 346. The input terminal of the eleventh inverter 341 can be used as a second control input terminal DISCH. The output terminal of the eleventh inverter 341 is connected to the input terminal of the twelfth inverter 342. The output terminal of the twelfth inverter 342 is connected to the input terminal of the thirteenth inverter 343. The output terminal of the thirteenth inverter 343 is connected to the input terminal of the fourteenth inverter 344. The output terminal of the fourteenth inverter 344 is connected to the second signal input terminal of the logic circuit 310. One end of the second capacitor 345 is connected between the output terminal of the eleventh inverter 341 and the input terminal of the twelfth inverter 342, and the other end of the second capacitor 345 is grounded. One end of the third capacitor 346 is connected between the output of the twelfth inverter 342 and the input of the thirteenth inverter 343, and the other end of the third capacitor 346 is grounded.

[0099] The working principle of the delay circuit 340 is as follows: When the second control input terminal DISCH receives a high-level signal, the eleventh inverter 341 inverts it to a low-level signal and outputs it to the twelfth inverter 342. The twelfth inverter 342 then inverts this low-level signal to a high-level signal and outputs it to the thirteenth inverter 343. Similarly, the thirteenth inverter 343 and the fourteenth inverter 344 invert the signals sequentially, and finally the fourteenth inverter 344 outputs a low-level signal opposite to the initial high-level signal to the second signal input terminal of the logic circuit 310. The second capacitor 345 and the third capacitor 346 play a delay role, slowing down the signal transmission speed through the charging and discharging process, thereby realizing the delay function. After receiving the second control signal, the delay circuit 340 can perform subsequent operations with a certain time delay, so that the negative voltage discharge circuit 300 can continue to operate after the system is powered off, which is beneficial to the stable operation and precise control of the negative voltage discharge circuit 300.

[0100] Figure 9B For Figure 9A Waveform delay diagram of the delay circuit. As shown in Figure 9B , IN is the waveform of the second control signal, OUT is the waveform of the second control signal after delay processing, the rising edge delay time of the second control signal after processing by the delay circuit 340 is TD1, and the falling edge delay time is TD2.

[0101] In some embodiments, the eleventh inverter 341 and the second capacitor 345 generate a first level delay, the twelfth inverter 342 and the third capacitor 346 generate a second level delay. The larger the capacitance of the second capacitor 345 and the third capacitor 346, the longer the delay time. The thirteenth inverter 343 and the fourteenth inverter 344 can shape the output waveform, which is convenient for ensuring the signal quality and delay effect of the second signal input to the logic circuit 310.

[0102] Figure 9C For the structure diagram of another delay circuit according to some embodiments. As shown in Figure 9C , in some embodiments, the delay circuit 340 can include a first buffer 3471, a second buffer 3472, a third buffer 3473 and a fourth buffer 3474. The first buffer 3471, the second buffer 3472, the third buffer 3473 and the fourth buffer 3474 are connected in series, the input end of the first buffer 3471 can be used as the second control input end DISCH, and the output end of the fourth buffer 3474 is connected to the second signal input end of the logic circuit 310. The more the number of buffers in the delay circuit 340, the longer the delay of the delay circuit 340.

[0103] Figure 10 For the timing diagram of a negative voltage discharge circuit according to some embodiments. As shown in Figure 10As shown, in some embodiments, M1 State represents the state of the first MOS 301, OFF represents that the first MOS 301 is off, and the first resistor 302 is disconnected with the ground; ON represents that the first MOS 301 is on, and the first resistor 302 is connected with the ground, and the negative voltage discharge connection end VDISCH discharges to the ground through the first resistor 302 and the first MOS 301. At time t1, the second MOS 303 is on, and a working voltage for the load circuit 200 to work is generated. At time t2, the second control input end DISCH inputs the second control signal, and the negative voltage discharge circuit 300 is started. The third MOS 305 and the first capacitor 307 pull up the voltage at the gate of the first MOS 301, so that the first MOS 301 is off, and the second MOS 303 functions to limit the upper limit of the voltage at the gate of the first MOS 301. When power failure occurs, the first control input end CKT inputs the first control signal, and time t3 and time t4 occur almost simultaneously, but due to the function of the delay circuit 340, the second MOS 303 is off, the first control signal acts earlier than the second control signal, and the fourth MOS 306 and the third MOS 305 are off, so that the voltage at one end of the first capacitor 307 is pulled to the ground, and the voltage at the other end of the first capacitor 307 is pulled to the negative voltage, so that the first MOS 301 is on. Thereafter, even if the power voltage VDD drops to 0V, the first MOS 301 is still in the on state, and continues to flow the charge at the negative voltage discharge connection end VDISCH to the ground through the first resistor 302.

[0104] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A negative voltage discharge circuit, characterized by, The application relates to a logic circuit, which comprises: a logic circuit, a first input end of the logic circuit being used for inputting a first control signal, the logic circuit logically processing the first control signal; a non-overlapping circuit, an input end of the non-overlapping circuit being connected to a second output end of the logic circuit; a second MOS tube, a gate of the second MOS tube being connected to the second output end of the logic circuit, and a source of the second MOS tube being connected to VDD; a first MOS tube, a gate of the first MOS tube being connected to a drain of the second MOS tube, a source of the first MOS tube being grounded, and a drain of the first MOS tube being used for connecting a negative voltage discharge connection end; the first MOS tube being turned on based on the first control signal logically processed by the logic circuit when VDD is powered off; a third MOS tube, a gate of the third MOS tube being connected to a first output end of the non-overlapping circuit, and a source of the third MOS tube being connected to VDD; the third MOS tube being turned on based on the output of the first output end of the non-overlapping circuit; a fourth MOS tube, a gate of the fourth MOS tube being connected to a second output end of the non-overlapping circuit, a drain of the fourth MOS tube being connected to a drain of the third MOS tube, and a source of the fourth MOS tube being grounded; the fourth MOS tube being turned on based on the output of the second output end of the non-overlapping circuit; a first capacitor, one end of the first capacitor being connected in series between the drain of the fourth MOS tube and the drain of the third MOS tube, and the other end of the first capacitor being connected in series between the gate of the first MOS tube and the drain of the second MOS tube.

2. The negative voltage discharge circuit according to claim 1, wherein The logic circuit further comprises a second signal input end, and the logic circuit comprises a first inverter, a second inverter and a NAND gate; an input end of the first inverter being used as the first signal input end, an output end of the first inverter being connected to an input end of the second inverter, an output end of the second inverter being connected to a first input end of the NAND gate, a second input end of the NAND gate being used as the second signal input end, and an output end of the NAND gate being used as the second output end; a gate of the second MOS tube being connected between the first inverter and the second inverter.

3. The negative voltage discharge circuit according to claim 1 or 2, characterized by, Further comprising a delay circuit; the delay circuit comprising an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a second capacitor and a third capacitor; the eleventh inverter, the twelfth inverter, the thirteenth inverter and the fourteenth inverter being connected in sequence, one end of the second capacitor being connected between the eleventh inverter and the twelfth inverter, the other end of the second capacitor being grounded, one end of the third capacitor being connected between the twelfth inverter and the thirteenth inverter, and the other end of the third capacitor being grounded.

4. The negative voltage discharge circuit according to claim 1, wherein the non-overlapping circuit comprising an OR gate, a fourth inverter, a fifth inverter, an AND gate, a sixth inverter and a seventh inverter; a first input end of the OR gate being used as the input end of the non-overlapping circuit, an output end of the OR gate being connected to an input end of the fourth inverter, an output end of the fourth inverter being connected to an input end of the fifth inverter, and an output end of the fifth inverter being used as the first output end of the non-overlapping circuit; The first input end of the AND gate is connected to the first input end of the OR gate, the output end of the AND gate is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the input end of the seventh inverter, and the output end of the seventh inverter serves as the second output end of the non-overlapping circuit; The second input end of the OR gate is connected to the output end of the seventh inverter, and the second input end of the AND gate is connected to the output end of the fifth inverter.

5. The negative voltage discharge circuit according to claim 1, wherein The voltage limiting circuit further comprises a fifth MOS tube, the drain electrode of the fifth MOS tube is connected to ground, and the gate electrode and the source electrode of the fifth MOS tube are both connected between the drain electrode of the second MOS tube and the gate electrode of the first MOS tube.

6. The negative voltage discharge circuit according to claim 1, wherein The first resistor and the second resistor are further included. One end of the first resistor is connected to the drain electrode of the first MOS tube, and the other end of the first resistor is connected to the negative voltage discharge connection end. One end of the second resistor is connected to the drain electrode of the second MOS tube, and the other end of the second resistor is connected to the gate electrode of the first MOS tube.

7. The negative voltage discharge circuit according to claim 1, wherein The non-overlapping circuit comprises an eighth inverter, a ninth inverter, a tenth inverter, a first PMOS tube, a first NMOS tube, a second NMOS tube, a second PMOS tube, a third PMOS tube, and a third NMOS tube. The input end of the eighth inverter serves as the input end of the non-overlapping circuit; the output end of the eighth inverter is connected to the gate electrode of the first PMOS tube, the gate electrode of the second NMOS tube, the third PMOS tube, and the third NMOS tube; the source electrode of the first PMOS tube is connected to VDD, the drain electrode of the first PMOS tube is connected to the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected to the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected to ground, and the first output end of the non-overlapping circuit is connected between the drain electrode of the first PMOS tube and the drain electrode of the first NMOS tube; The source electrode of the second PMOS tube is connected to VDD, the drain electrode of the second PMOS tube is connected to the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the source electrode of the third NMOS tube is connected to ground, and the second output end of the non-overlapping circuit is connected between the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube; The input end of the ninth inverter is connected to the second output end of the non-overlapping circuit, and the output end of the ninth inverter is connected to the gate electrode of the first NMOS tube; The input end of the tenth inverter is connected to the first output end of the non-overlapping circuit, and the output end of the tenth inverter is connected to the gate electrode of the third PMOS tube.

8. The negative voltage discharge circuit according to claim 1, wherein The logic circuit further comprises a delay circuit and a second signal input end; the delay circuit comprises a first buffer, a second buffer, a third buffer, and a fourth buffer connected in sequence; the input end of the first buffer serves as the second control input end of the negative voltage discharge circuit, and the output end of the fourth buffer is connected to the second signal input end.

9. The negative voltage discharge circuit according to claim 1, wherein Also include voltage limiting circuit; the voltage limiting circuit includes diode, the positive pole of diode is connected the grid of first MOS tube, the negative pole of diode is grounded.

10. A power supply circuit, characterized by comprising: Comprise: DC-DC converter, output end is used for connecting load circuit, make the DC-DC converter for the load circuit provides operating voltage, operating voltage is less than 0; Negative voltage discharge circuit, the negative voltage discharge connection end of the negative voltage discharge circuit is connected between the DC-DC converter and the load circuit, the negative voltage discharge end of the negative voltage discharge circuit is grounded;Wherein, the negative voltage discharge circuit is any one of claims 1-9, the drain of the first MOS tube in the negative voltage discharge circuit is used as the negative voltage discharge connection end, and the source of the first MOS tube is used as the negative voltage discharge end.

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