Multi-channel programmable PWM drive circuit based on FPGA

Abstract

The utility model discloses a multichannel programmable PWM drive circuit based on FPGA, comprising a first decoupling capacitor, a second decoupling capacitor, an FPGA chip, a bidirectional buffer chip, and an extended PWM output chip, the input end of the FPGA chip is connected with a + 1.2 V power supply signal, a + 3.3 V power supply signal, and a clock signal, the output end of the FPGA chip and the input end of the bidirectional buffer chip are connected with the + 3.3 V power supply signal, and the output end of the bidirectional buffer chip is connected with the output end of the extended PWM output chip. The first decoupling capacitor and the second decoupling capacitor are electrically connected with the output end of the bidirectional buffer chip, and the output end of the bidirectional buffer chip and the input end of the extended PWM output chip are connected with VCC voltage signals. The parallel multi-channel PWM drive circuit based on the FPGA can solve the technical problems that when a traditional parallel multi-channel PWM drive circuit based on the FPGA is used for guaranteeing phase synchronization and frequency consistency among multiple channels, complex clock management is depended, the parallel multi-channel PWM drive circuit is easily influenced by wiring delay and clock skew, and therefore waveform distortion is easily caused.

Description

TECHNICAL FIELD

[0001] The utility model belongs to digital circuit technical field, more specifically, it relates to a kind of multi-channel programmable PWM drive circuit based on FPGA. BACKGROUND

[0002] Under the background of the deep integration of industry and intelligent manufacturing, high-precision multi-channel pulse width modulation (PWM) driving technology is undergoing a revolutionary paradigm shift. With the popularity of permanent magnet synchronous motors in industrial robot joint modules, the large-scale application of SiC / GaN wide-bandgap semiconductors in power electronic devices, and the surge in demand for nanoscale motion control in precision instruments, the traditional PWM generation architecture has revealed deep-seated structural contradictions. Traditional PWM generation schemes based on microcontrollers or dedicated chips are limited by hardware timer resources and channel expansion capabilities, making it difficult to meet the complex demands of multi-axis cooperative control, dynamic duty cycle adjustment, and high-resolution output. In particular, in industrial scenarios, the differentiated requirements of different loads for PWM frequency, phase synchronization, and dead time make the existing architecture face challenges such as insufficient channel isolation, limited timing control precision, and difficulty in dynamically reconstructing the topology.

[0003] There are three main implementation methods for existing multi-channel PWM drive circuits, including parallel multi-channel PWM drive circuits based on field programmable gate array (FPGA), PWM drive circuits based on multi-level converter topology, and multi-channel PWM drive circuits based on digital signal processing (DSP): The parallel multi-channel PWM drive circuit based on FPGA becomes an important carrier for multi-channel PWM drive with its FPGA parallel processing capability and nanosecond-level timing control accuracy. This technology designs a parameterized PWM core through a hardware description language, and each channel is independently configured with frequency, duty cycle and phase difference. Its core advantage is hard real-time, which is suitable for multi-axis motor cooperative control or high-resolution light emitting diode (LED) array regulation, and solves the channel expansion problem caused by hardware resource limitations of traditional microcontrollers; The PWM drive circuit based on multi-level converter topology realizes multi-level output through cascaded H-bridge or diode clamping topology. Taking cascaded multi-level as an example, each phase is connected by multiple power units, each unit independently generates a PWM signal, and through carrier phase shift or layer modulation strategy, an approximate sine staircase waveform is synthesized, which significantly reduces the harmonic content. This kind of technology needs to accurately coordinate the switching time of each channel to balance the voltage stress and improve system efficiency; The multi-channel PWM drive circuit based on DSP realizes multi-channel dynamic configuration through high-speed timers and interrupt service programs. This technology supports online parameter adjustment and harmonic optimization, and is widely used in variable frequency speed regulation and power active filtering. It has high flexibility.

[0004] However, the above three existing multi-channel PWM drive circuits have some defects that cannot be ignored:

[0005] First, the parallel multi-channel PWM drive circuit based on FPGA relies on complex clock management to ensure phase synchronization and frequency consistency among multiple channels, which is easily affected by wiring delay and clock offset, thus easily leading to waveform distortion;

[0006] Second, the parallel multi-channel PWM drive circuit based on FPGA needs to recompile the logic code to modify PWM parameters (such as duty cycle, frequency), and its dynamic adjustment capability is poor;

[0007] Third, the multi-level converter of the PWM drive circuit based on multi-level converter topology requires multiple switching devices and complex topology structure (such as H-bridge cascading), which leads to complex circuit design, large size and high cost;

[0008] Fourth, the DSP-based multi-channel PWM drive circuit, the DSP is limited to peripheral interface, usually only supports 8-16 channels, the number of channels is limited, and the channel expansion is poor. Utility model content

[0009] In view of the above defects or improvement needs of the prior art, the utility model provides a kind of multi-channel programmable PWM drive circuit based on FPGA, it is to solve the technical problems that the conventional parallel multi-channel PWM drive circuit based on FPGA is used in the prior art, when guaranteeing the phase synchronization and frequency consistency between multiple channels, rely on complex clock management, be susceptible to wiring delay and clock offset, thereby easily leading to waveform distortion, and its circuit needs to recompile logic code to modify PWM parameter (such as duty ratio, frequency), the technical problems of poor dynamic adjustment capability;And the technical problems that the PWM drive circuit based on multi-level converter topology is used in the prior art, not only multi-level converter needs multiple switching devices and complex topology structure (such as H bridge cascade), thereby leading to complex circuit design, bulky and high cost, and the technical problems that the multi-channel PWM drive circuit based on DSP is used in the prior art, the DSP is limited to peripheral interface, usually only supports 8-16 channels, the number of channels is limited, and the channel expansion is poor.

[0010] To achieve the above object, according to one aspect of the utility model, a kind of multi-channel programmable PWM drive circuit based on FPGA is provided, including first decoupling capacitor, second decoupling capacitor, FPGA chip, bidirectional buffer chip and expansion PWM output chip, the input end of FPGA chip is connected +1.2V power signal, +3.3V power signal and clock signal;

[0011] The output end of FPGA chip and the input end of bidirectional buffer chip are connected +3.3V power signal;

[0012] First decoupling capacitor and second decoupling capacitor are electrically connected with the output end of bidirectional buffer chip;

[0013] The output end of bidirectional buffer chip and the input end of expansion PWM output chip are connected VCC voltage signal.

[0014] Preferably, the model of FPGA chip is XC6SLX45T-2CSG324I.

[0015] Preferably, the model of bidirectional buffer chip is 74LCX16245_2.

[0016] Preferably, VCCA end in bidirectional buffer chip is grounded by first decoupling capacitor.

[0017] Preferably, VCCB end in bidirectional buffer chip is grounded by second decoupling capacitor.

[0018] Preferably, the first decoupling capacitor has a capacitance value of 0.1 microfarad.

[0019] Preferably, the second decoupling capacitor has a capacitance value of 0.1 microfarad.

[0020] Preferably, the model of the extended PWM output chip is PCA9685.

[0021] Overall, the above technical scheme conceived by the utility model compared with the prior art can achieve the following beneficial effects:

[0022] (1) The utility model discloses a clock signal and FPGA chip are directly connected, through global clock and unified time sequence control logic, ensure that the phase and frequency of multi-channel are strictly synchronous, reduce time sequence deviation, can solve the existing traditional parallel multi-channel PWM drive circuit based on FPGA when guaranteeing the phase synchronization and frequency consistency between multi-channel, rely on complex clock management, be easily affected by wiring delay and clock offset, thereby easily leading to waveform distortion.

[0023] (2) The utility model discloses that FPGA chip and bidirectional buffer chip are connected, and its bidirectional buffer chip can interact with external controller (such as MCU), support real-time parameter adjustment, need not stop reconfiguration, can solve the existing traditional parallel multi-channel PWM drive circuit based on FPGA to modify PWM parameter (such as duty ratio, frequency) and need to recompile logic code, and its dynamic adjustment ability is poor technical problem.

[0024] (3) The utility model discloses that FPGA chip generates multiple PWM signals directly through digital logic, need not multistage switching device, reduces the complexity of peripheral circuit, reduces cost, can solve the existing PWM drive circuit based on multilevel converter topology, and its multilevel converter needs multistage switching device and complex topology structure, thereby leading to the technical problem of complex circuit design, bulky and high cost.

[0025] (3) The utility model discloses that FPGA chip and bidirectional buffer chip are connected, and its parallel processing capacity supports multi-channel extension, can adapt to different level number and channel demand through increasing logic unit, need not hardware reconfiguration, can solve the technical problem that the existing PWM modulation drive circuit special DSP chip based on multilevel converter topology is difficult to meet the control demand of multilevel converter to multi-channel, high real-time, too much depends on hardware, and system expansibility is poor.

[0026] (4) The utility model discloses a FPGA chip, bidirectional buffer chip, extension PWM output chip are connected, and its FPGA chip is through the cascade with extension PWM output chip, and the multistage drive is realized to the combination bidirectional buffer chip, supports thousand level channel extension, therefore can solve the circuit of the present multichannel PWM control technology based on DSP, and the DSP of the present multichannel PWM control technology based on DSP is limited to peripheral interface, usually only supports 8-16 channels, and the channel number is limited, and the technical problem of poor channel expansibility. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is the circuit diagram of the utility model's multichannel programmable PWM drive circuit based on FPGA;

[0028] Figure 2 It is the structure schematic diagram of FPGA chip in the utility model's multichannel programmable PWM drive circuit based on FPGA;

[0029] Figure 3 It is the structure schematic diagram of bidirectional buffer chip in the utility model's multichannel programmable PWM drive circuit based on FPGA;

[0030] Figure 4 It is the structure schematic diagram of extension PWM output chip in the utility model's multichannel programmable PWM drive circuit based on FPGA. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantage of the utility model more clearly, the following is combined with the drawings and embodiment, and the utility model is further detailed. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not used to limit the utility model. In addition, the technical features involved in each embodiment of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0032] As Figure 1 The utility model discloses a multichannel programmable PWM drive circuit based on FPGA, including first decoupling capacitor 1, second decoupling capacitor 2, FPGA chip 3, bidirectional buffer chip 4 and extension PWM output chip 5.

[0033] The input end of FPGA chip 3 is connected with +1.2V power signal, +3.3V power signal and clock signal, the output end of FPGA chip 3 and the input end of bidirectional buffer chip 4 are connected with +3.3V power signal, first decoupling capacitor 1 and second decoupling capacitor 2 are electrically connected with the output end of bidirectional buffer chip 4, and the output end of bidirectional buffer chip 4 and the input end of extension PWM output chip 5 are connected with VCC voltage signal.

[0034] AsFigure 2 As shown in the figure, the FPGA chip 3 is an FPGA chip manufactured by Xilinx Company, with model number XC6SLX45T-2CSG324I.

[0035] As shown in the figure, the bidirectional buffer chip 4 is a bidirectional buffer chip manufactured by On-Semiconductor Company, with model number 74LCX16245_2. Figure 3

[0036] The VCCA end in the bidirectional buffer chip 4 is grounded through a first decoupling capacitor (C74 in the figure), and the VCCB end is grounded through a second decoupling capacitor (C75 in the figure). Figure 3 Figure 3

[0037] The capacitance value of the first decoupling capacitor 1 is 0.1 microfarad, and the capacitance value of the second decoupling capacitor 2 is 0.1 microfarad.

[0038] As shown in the figure, the expansion PWM output chip 5 is an expansion PWM output chip manufactured by Philips Semiconductor Company, with model number PCA9685. Figure 4

[0039] The working principle of the utility model is as follows:

[0040] ​​​​The +1.2V power supply signal is connected to the VCCINT pin of the FPGA chip 3 as the kernel power supply of the FPGA chip 3, the +3.3V power supply signal is connected to the VCCAUX pin of the FPGA chip 3 as the auxiliary power supply of the FPGA chip 3, the +3.3V power supply signal is connected to the VCCO_0-VCCO_3 pin of the FPGA chip 3 as the I / O power supply of the FPGA chip 3, and independent power supplies are provided for different I / O groups to ensure that the I / O signal levels are matched; at the same time, the clock signal (whose frequency is 40Hz) is connected to the FPGACLK pin of the FPGA chip 3 to drive the PWM logic inside the FPGA chip 3; then, the FPGA chip 3 generates the PWM signal and outputs the PWM signal to the FADD0-FADD15 pin of the bidirectional buffer chip 4 through the PWMEO0-PWMEO11 pin for PWM signal receiving and distribution; at the same time, the +3.3V power supply signal is connected to the VCCA and VCCB pins of the bidirectional buffer chip 4 to provide working voltage for the bidirectional buffer chip 4, and the +3.3V power supply signal connected can filter out power supply noise and stabilize the +3.3V power supply voltage after passing through the first decoupling capacitor 1 and the second decoupling capacitor 2; then, the 3.3V power supply signal is connected to the 1DIR and 2DIR pins of the bidirectional buffer chip 4, which can dynamically control the PWM signal flow direction during the process that the bidirectional buffer chip 4 receives the PWM signal; after that, the PWM signal distributed by the bidirectional buffer chip 4 is output through the ADD0-ADD15 pin of the bidirectional buffer chip 4 and then connected to the PWMEO0-PWMEO10 pin of the expansion PWM output chip 5; at the same time, the VCC voltage signal is electrically connected to the input end of the expansion PWM output chip 5 to run and power the expansion PWM output chip 5, and the PWM signal distributed by the bidirectional buffer chip 4 is connected to the external device through the expansion PWM output chip 5, realizing multi-channel PWM signal output.

[0041] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present application and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An FPGA-based multi-channel programmable PWM drive circuit, comprising a first decoupling capacitor, a second decoupling capacitor, an FPGA chip, a bidirectional buffer chip, and an extended PWM output chip, characterized in that, an input end of the FPGA chip is connected to a +1.2V power signal, a +3.3V power signal, and a clock signal; an output end of the FPGA chip and an input end of the bidirectional buffer chip are connected to the +3.3V power signal; the first decoupling capacitor and the second decoupling capacitor are electrically connected to an output end of the bidirectional buffer chip; an output end of the bidirectional buffer chip and an input end of the extended PWM output chip are connected to a VCC voltage signal.

2. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, The model of the FPGA chip is XC6SLX45T-2CSG324I.

3. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, The model of the bidirectional buffer chip is 74LCX16245_2.

4. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, A VCCA end in the bidirectional buffer chip is grounded through the first decoupling capacitor.

5. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, A VCCB end in the bidirectional buffer chip is grounded through the second decoupling capacitor.

6. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, The capacitance of the first decoupling capacitor is 0.1 microfarad.

7. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, The capacitance of the second decoupling capacitor is 0.1 microfarad.

8. The FPGA-based multi-channel programmable PWM drive circuit of claim 1, wherein, The model of the extended PWM output chip is PCA9685.

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