Series capacitor crash trigger reset circuit

Abstract

The utility model provides a serial capacitor crash trigger reset circuit which comprises an edge detection circuit, a reset trigger circuit, a reset shielding circuit, a main control unit and a power supply control unit. The adsorption voltage change of the flat plate is detected in a mode of combining edge detection and RC time delay, and resetting is triggered only when the system crashes, so that the problem that resetting is carried out every time charging in a traditional scheme is avoided; flexible starting and shielding of a reset function are realized by adopting a software control and protection circuit, and a simple and low-power-consumption circuit structure is constructed by utilizing the reset function of a charge IC; through the voltage clamping and false triggering prevention design, stable and reliable operation of the system is ensured, the problem of crash recovery of products without keys and reset holes is solved, the overall cost is reduced through the optimized circuit design, and meanwhile good user experience is provided.

Description

TECHNICAL FIELD

[0001] The utility model relates to charging management technical field especially relates to a series connection capacitor dead machine trigger reset circuit. BACKGROUND

[0002] With the wide application of tablet computers and other portable electronic devices, their reliability and stability are increasingly concerned. In actual use, due to software bugs, hardware failures and other reasons, the device may appear dead, resulting in the system unable to respond to user operation normally, seriously affecting user experience.

[0003] At present, the common system reset scheme mainly includes: (1) user manually long-presses the power key to force shutdown and restart, which is tedious and needs user intervention; (2) setting watchdog timer for system monitoring, but the watchdog may also fail in some dead conditions; (3) using external reset chip, which is high in cost and needs additional circuit space. Especially in the tablet computer with magnetic charging function, due to the increase of magnetic material at the charging interface, instantaneous power fluctuation may occur during magnetic attraction. How to utilize this power fluctuation feature to realize automatic system reset, while avoiding false triggering reset in normal working state, is a technical problem faced by the industry at present. INVENTION CONTENTS

[0004] The utility model provides a series connection capacitor dead machine trigger reset circuit, prevents false triggering reset.

[0005] The utility model discloses a hardware reset circuit of system abnormality detection, including:

[0006] The edge detection circuit is used for detecting the voltage level change of the charging power supply end VBUS and transmitting the detected edge detection signal to the reset trigger circuit.

[0007] The main control unit is used for detecting the charging state and sending the reset shielding signal to the reset shielding circuit when the system works normally.

[0008] The reset shielding circuit adjusts the detection time of the edge detection circuit according to the received reset shielding signal.

[0009] When the duration of the edge detection signal exceeds the preset time, the reset trigger circuit sends the reset trigger signal to the power control unit.

[0010] After the power control unit receives the reset trigger signal, the main control unit is controlled to reset.

[0011] Further, the edge detection circuit includes a first resistor R469 and a first capacitor C463.

[0012] One end of the first resistor R469 is connected with a charging power supply end VBUS, the other end is connected with an input end of the reset trigger circuit, and is also connected with one end of the first capacitor C463, the other end of the first capacitor C463 is grounded.

[0013] Further, the reset trigger circuit comprises a first MOS tube Q403, a second resistor R471 and a third resistor R470.

[0014] The gate of the first MOS tube Q403 is connected with the connection point of the first capacitor C463 and the first resistor R469 through the third resistor R470, the drain of the first MOS tube Q403 outputs the reset trigger signal to the master control unit through the second resistor R471, and the source of the first MOS tube Q403 is grounded.

[0015] Further, the reset shielding circuit comprises a second MOS tube Q402, a fourth resistor R474 and a fifth resistor R477.

[0016] The gate of the second MOS tube Q402 is connected with an input and output end of the master control unit through the fourth resistor R474, the source of the second MOS tube Q402 is grounded, and the drain of the second MOS tube Q402 is connected with the gate of the first MOS tube Q403; one end of the fifth resistor R477 is connected between the gate of the second MOS tube Q402 and the other end of the fourth resistor R474, and the other end of the fifth resistor R477 is grounded.

[0017] Further, the master control unit comprises an MCU.

[0018] The power supply end of the MCU is connected with a power supply output end of the power supply control unit.

[0019] The input and output end of the MCU is connected with an input end of the reset shielding circuit.

[0020] The data end and the clock end of the MCU are interconnected with the power supply control unit.

[0021] The interrupt input end of the MCU is electrically connected with an interrupt output end of the power supply control unit.

[0022] Further, the charging power supply end of the power supply control unit is electrically connected with a charging signal.

[0023] The reset signal input end of the power supply control unit is electrically connected with the reset trigger signal.

[0024] The power supply output end of the power supply control unit is connected with the power supply input end of the master control unit.

[0025] The data end and the clock end of the power control unit are connected with the master control unit respectively;

[0026] The interrupt output end of the power control unit is electrically connected with the interrupt input end of the master control unit.

[0027] Further, the power control unit is a charging management chip.

[0028] Further, the preset time is 10-15 seconds.

[0029] The utility model discloses a series connection capacitor dead machine trigger reset circuit, including edge detection circuit, reset trigger circuit, reset shielding circuit, master control unit and power control unit. Edge detection circuit detects the change of flat plate adsorption voltage through RC delay network, and reset trigger circuit judges system state according to the duration of edge detection signal;When the system is normal, the master control unit adjusts RC time constant through the reset shielding circuit dynamically, and effectively avoids false triggering;When the system is dead, the voltage characteristics when flat plate adsorption are used to trigger reset operation, and reliable recovery of the system is ensured. The circuit does not need additional key or reset hole, and can realize intelligent reset function through a small amount of discrete components, and the structure is simple, the cost is low, and the reliability is high. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is structure schematic diagram of series connection capacitor dead machine trigger reset circuit in an embodiment of the utility model;

[0031] Figure 2 It is structure schematic diagram of edge detection circuit, reset shielding circuit and reset trigger circuit in an embodiment of the utility model;

[0032] Figure 3 It is voltage waveform diagram of each node when the system is normal in an embodiment of the utility model;

[0033] Figure 4 It is voltage waveform diagram of each node under the system dead machine state in an embodiment of the utility model;

[0034] Figure 5 It is time sequence waveform diagram of each signal in the system reset process in an embodiment of the utility model. DETAILED DESCRIPTION

[0035] The utility model discloses a series connection capacitor dead machine trigger reset circuit will be described below in conjunction with the schematic diagram, wherein the preferred embodiment of the utility model is shown, should understand that the person skilled in the art can modify the utility model described herein, and still realize the advantageous effect of the utility model. Therefore, the following description should be understood as the extensive knowledge of the person skilled in the art, and not as the limitation of the utility model.

[0036] The utility model is described in more detail by way of example with reference to the drawings in the following paragraphs. The advantages and features of the utility model will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not drawn to precise scale, and are merely used to facilitate and clarify the description of the embodiments of the utility model.

[0037] Please refer to Figure 1 The embodiment discloses a series connection capacitor dead machine trigger reset circuit, including: edge detection circuit 1, main control unit, reset shielding circuit 3, power control unit and reset trigger circuit 2.

[0038] Specifically, the edge detection circuit 1 is used for detecting the level change of the charging power supply end and transmitting the detected edge detection signal to the reset trigger circuit 2; the main control unit is used for detecting the charging state and sending a reset shielding signal to the reset shielding circuit 3 when the system is working normally; the reset shielding circuit 3 adjusts the detection time of the edge detection circuit 1 according to the received reset shielding signal; when the duration of the edge detection signal exceeds the preset time, the reset trigger circuit 2 sends a reset trigger signal VDD_RST to the power control unit; after receiving the reset trigger signal VDD_RST, the power control unit controls the main control unit to reset.

[0039] In one specific embodiment, the power supply of the charging power supply end comes from an external power supply, specifically an electric signal VBUS generated by terminal equipment charging. In one specific embodiment, the electric signal VBUS can be triggered by the way of adsorbing or plugging the charger, when the tablet is adsorbed or the charger is plugged in, the power supply end level changes from 0V to 5V; when the tablet is separated or the charger is unplugged, the power supply end level changes from 5V to 0V, thereby realizing the detection of the charging state.

[0040] In the embodiment, by the cooperation of the edge detection circuit 1 and the reset shielding circuit 3, the detection time is dynamically adjusted to prevent false triggering when the system is working normally, and by using the power supply fluctuation characteristics in the charging process and combining the hierarchical judgment mechanism, the automatic recognition and reset function in the system dead state are realized, without manual operation of the user, with the characteristics of simple structure, low cost and high reliability, which significantly improves the intelligent level and user experience of the equipment.

[0041] In the embodiment, the main control unit includes an MCU.

[0042] Specifically, the power supply end is connected with a power output end of the power supply control unit; an input / output end GPIO end of the MCU is connected with an input end of the reset shielding circuit; a data end and a clock end of the MCU are interconnected with the power supply control unit; an interrupt input end of the MCU is electrically connected with an interrupt output end of the power supply control unit, and the power supply control unit sends a terminal control signal INT to the master control unit to control the master control unit to be powered off and reset.

[0043] Further, in the embodiment, the edge detection circuit 1 comprises a first resistor R469 and a first capacitor C463.

[0044] Specifically, one end of the first resistor R469 is connected with a charging power supply end; the other end is connected with an input end of the reset trigger circuit 2 and also connected with one end of the first capacitor C463, and the other end of the first capacitor C463 is grounded. When the VBUS power supply end has a level change, the change process can be detected through the charging and discharging characteristics of the RC circuit, and a detection signal is transmitted to the reset trigger circuit 2.

[0045] In the embodiment, the first capacitor C463 and the first resistor R469 constitute RC timing and edge detection, and each adsorption will generate an RC timing, that is, one reset operation.

[0046] In the embodiment, the most suitable capacitor value can be calculated according to the RC discharge equation: Ur=Us*e^(-t / RC). The threshold voltage Ur of the MOS tube, the expected reset time t, the VBUS value Us or the resistance R of the first resistor R469 are determined; for example: the preset time t is determined as 12s, the threshold voltage Ur is determined as 0.53V (the opening threshold voltage of the MOS tube), Us is determined as 5V, and the first resistor R469 is determined as 5.1M. It can be calculated that C=5.96uF, but considering voltage efficiency, VG deviation and universality (t≥12s can meet the reset requirement), the preferred value is C=10uF.

[0047] It can be understood that in the embodiment, the preset time t is selected to be between 10-15s, mainly to ensure that the system has enough judgment time to avoid false triggering in the normal charging process, and also to match the habit time of the user manually pressing the reset for a long time, and to reserve enough system dead response delay detection margin, so as to realize the optimal balance between the reliability of the system reset function and the user experience.

[0048] In the embodiment, the edge detection circuit 1 has simple structure, and only one resistor and one capacitor are needed to realize the edge detection function, so that the cost is low and the integration is easy. By reasonably selecting the RC value, the response time and the sensitivity of the circuit can be adjusted, in addition, the RC circuit has a certain filtering effect, which can filter out the high-frequency interference of the power supply end, and improve the service life of the system.

[0049] Further, in the embodiment, the reset trigger circuit 2 includes a first MOS tube Q403, a second resistor R471 and a third resistor R470.

[0050] The gate of the first MOS tube Q403 is connected with the connection point of the first capacitor C463 and the first resistor R469 through the third resistor R470, the drain of the first MOS tube Q403 outputs the reset trigger signal VDD_RST to the master control unit through the second resistor R471, and the source of the first MOS tube Q403 is grounded.

[0051] In the embodiment, the first MOS tube Q403 is used as a switching control element, the gate thereof detects the voltage change of VBUS through an RC network, the source thereof is grounded to provide a stable reference potential, and the drain thereof is connected with VDD_RST through the second resistor R471 to form a pull-up circuit; when the voltage change is detected, the first MOS tube Q403 is turned on to pull down the VDD_RST signal and trigger the reset, and the second resistor R471 not only limits the drain current but also ensures that VDD_RST can quickly recover to high level when the MOS tube is turned off. The whole circuit has simple structure, low cost and high reliability, does not need complex control logic, can realize accurate timing control by reasonably selecting the element parameters, and has good anti-interference and temperature characteristics.

[0052] Further, the reset shielding circuit 3 includes a second MOS tube Q402, a fourth resistor R474 and a fifth resistor R477.

[0053] Specifically, the gate of the second MOS tube Q402 is connected with the input and output end of the master control unit through the fourth resistor R474, the source thereof is grounded, and the drain thereof is connected with the gate of the first MOS tube Q403; one end of the fifth resistor R477 is connected between the gate of the second MOS tube Q402 and the other end of the fourth resistor R474, and the other end of the fifth resistor R477 is grounded.

[0054] In the embodiment, the second MOS Q402 is used as an enable control switch, and is connected to the main control unit through the fourth resistor R474 to realize the input of the control signal. The fifth resistor R477 is grounded to form a pull-down circuit to ensure that the second MOS Q402 is reliably turned off when there is no control signal. When the system is working normally, the MCU detects the power-on of the charging power supply end and outputs a rectangular pulse signal to make the second MOS Q402 conductive. During the high level of the rectangular pulse, the second MOS Q402 changes the original RC time constant of the first capacitor C463 after being turned on, (new RC=(R 469 / / R 470 )*C 463 , where R 469 is the resistance value of the first resistor, R 470 is the resistance value of the third resistor, and C 463 is the capacitance value of the first capacitor), so that the first capacitor C463 is quickly charged, thereby pulling down the gate voltage of the first MOS Q403 and disabling the reset signal generation. When the system crashes, the edge detection signal will continue to exceed the preset time without the reset shielding signal, and the reset trigger circuit 2 sends a reset trigger signal VDD_RST to the power supply control unit, which controls the reset of the main control unit. This design not only allows flexible control of the enablement and shielding of the reset function through software, but also has the characteristics of simple and reliable circuit structure, low power consumption, and strong anti-interference ability.

[0055] Further, in the embodiment, the pulse width of the rectangular pulse signal cannot be too long, so that a complete charging and discharging cycle can be completed within the normal adsorption time. When the panel is away, the first capacitor C463 is discharged through the parasitic diode of the second MOS Q402 and R470, and the gate voltage Vgs of the first MOS Q403 is clamped to -0.7V, remaining within the normal working range.

[0056] In a specific embodiment, the rectangular pulse width is 100ms, and those skilled in the art can select different rectangular pulse widths according to actual conditions.

[0057] Further, in the embodiment, the charging power supply end VBUS of the power supply control unit is electrically connected with the charging signal; the reset signal input end VDD_RST of the power supply control unit is electrically connected with the reset trigger signal VDD_RST; the power supply end of the power supply control unit is connected with the power supply input end of the main control unit, for providing the main control unit with a power supply voltage Vsys; and the clock end and data segment of the power supply control unit are interconnected with the main control unit.

[0058] In a specific embodiment, the power supply control unit is a Charge IC (charge management chip).

[0059] In the embodiment, the Charge IC monitors the charging state through the charging power supply end, realizes reliable system reset through the reset signal input end, provides stable power supply voltage VSYS for the master control unit through the power supply end, realizes bidirectional communication with the MCU through SCL (clock line) and SDA (data line) in I2C (integrated circuit bus), is electrically connected with the interrupt input end of the master control unit through the interrupt output end, and controls the master control unit to perform power-off reset. The design not only realizes the integration of power management, state monitoring and communication functions, but also simplifies the system reset control circuit, optimizes the system reliability and flexibility, and effectively reduces the overall cost.

[0060] Please refer to Figures 1-5 In one specific embodiment, when the above-mentioned series capacitor dead machine trigger reset circuit is adopted, the reset process of the system is as follows:

[0061] When the charger is unplugged, the voltage at the VBUS end quickly drops from 5V to 0V, and then when it is reinserted, the voltage at the VBUS end quickly rises from 0V to 5V. This voltage jump signal is coupled through the first capacitor C463 and voltage-divided and delayed through the first resistor R469, forming a trigger voltage at the gate of the first MOS tube Q403. When the gate voltage Vgs of the first MOS tube Q403 is higher than 0.53V, the first MOS tube Q403 is turned on, thereby pulling the reset trigger signal VDD_RST signal to the ground level, triggering the reset function of the power supply control unit.

[0062] If the system is in a normal state, the MCU will output a rectangular pulse signal through the input and output port after detecting the power-on of the charging power supply end VBUS through I2C, for example, outputting a 100ms rectangular pulse signal to the reset shielding circuit 3. After current limiting through the fourth resistor R474, the second MOS tube Q402 is driven to be turned on, accelerating the charging speed of the first capacitor C463. The fifth resistor R477 ensures that the second MOS tube Q402 can be reliably turned off without a control signal. When the first capacitor C463 is charged to make the gate voltage Vgs of the first MOS tube Q403 drop below its switching voltage, the second MOS tube Q402 is turned off, the reset trigger signal VDD_RST returns to high level, and the system remains in a normal working state.

[0063] In conclusion, the serial connection capacitor dead machine trigger reset circuit detects the flat plate adsorption voltage change through the edge detection and RC delay combination mode, only triggers the reset when the system is dead, avoids the problem that the traditional scheme resets every time charging, software control and protection circuit are adopted to realize flexible activation and shielding of the reset function, a simple low-power circuit structure is constructed by using the reset function of the charge IC, the stable and reliable operation of the system is ensured through the perfect IO port protection, voltage clamping and anti-mis-triggering design, not only the dead machine recovery problem of the product without the key and the reset hole is solved, but also the overall cost is reduced through the optimized circuit design, and good user experience is provided.

[0064] Various modifications and variations without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application claims and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. A series capacitor-connected dead trigger reset circuit, characterized in that, The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit.

2. The cascading capacitance deadlock trigger reset circuit of claim 1, wherein, The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit.

3. The series capacitor kill trigger reset circuit of claim 2, wherein, The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit.

4. The series capacitor kill trigger reset circuit of claim 3, wherein, The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit.

5. The series capacitor kill trigger reset circuit of claim 4, wherein, The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit.

7. The cascading capacitance kill trigger reset circuit of claim 1, wherein, The application relates to a serial capacitor dead machine trigger reset circuit.

8. The cascading capacitance kill trigger reset circuit of claim 1, wherein, The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. The application relates to a serial capacitor dead machine trigger reset circuit. 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