Packaging structure capable of reducing packaging parasitic parameters

Abstract

The utility model discloses a packaging structure capable of reducing packaging parasitic parameters, which comprises the following steps of: S1, additionally arranging a plurality of salient points in a chip placing area of a packaging substrate for bonding a chip and the packaging substrate; s2, gluing the chip placing area, and placing the chip in the chip placing area; s3, after the chip is placed, continuously filling the insulating medium underfill among the plurality of salient points; and packaging by using a plastic packaging material to finish packaging processing. According to the utility model, the plurality of salient points are additionally arranged for bonding, so that the distance between the chip and the packaging substrate is effectively reduced, and the influence of parasitic parameters is reduced; meanwhile, aiming at material selection, size control and structural limitation of insulating medium underfill, parasitic parameters are further reduced, and mechanical strength, thermal management and stability are considered; in addition, the method is controllable in cost and convenient to popularize and use.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor packaging technical field, concretely relates to a packaging structure of reducing packaging parasitic parameter. BACKGROUND

[0002] In the field of high-performance chip packaging, the traditional wire bonding technology is usually used to realize the electrical interconnection between the chip and the packaging substrate. This process connects the pads on the chip and the corresponding pads on the substrate through thin metal wires, such as gold wires and copper wires. However, with the continuous improvement of chip operating frequency and the increasing demand for signal integrity, this traditional interconnection method gradually exposes obvious limitations. Due to the long length of the lead, the parasitic inductance and parasitic capacitance generated by the interconnection line increase significantly, causing problems such as signal delay, crosstalk, and high-frequency loss, which seriously affect the overall performance and stability of the chip.

[0003] More seriously, the wire bonding equipment and process level of most packaging manufacturers cannot effectively shorten the distance between the chip pads and the substrate pads, limiting the further optimization of the lead length. This bottleneck has become one of the key factors restricting the development of high-performance computing, radio frequency communication, and high-speed interface chips.

[0004] Currently, for the packaging of high-performance chips, the traditional method is to use the WB wire bonding process, also known as the bonding wire process. WB stands for Wire Bonding. This process is highly flexible, low-cost, and easy to design. However, due to the difficulty in optimizing the lead length, it is also difficult to reduce the impact of parasitic parameters, which may cause significant signal loss, leading to problems such as signal delay and crosstalk, seriously affecting overall performance. In addition, some companies also use multi-layer wafer stacking and trapezoidal slot flip-chip interconnection for packaging. However, when using multi-layer stacking, the process steps are complex, the equipment precision is high, and the cost is high, making it difficult to popularize. UTILITY MODEL CONTENT

[0005] To solve the above problems, the utility model aims to provide a packaging structure for reducing packaging parasitic parameters. By adding multiple bumps for bonding, the distance between the chip and the packaging substrate is effectively reduced, thereby reducing the impact of parasitic parameters. At the same time, considering material selection, size control, and the structure of the insulating medium filler, the parasitic parameters are further reduced while considering mechanical strength, thermal management, and stability. In addition, this method does not require multi-layer wafer stacking, and the cost is controllable, making it easy to popularize.

[0006] The following technical solutions are implemented:

[0007] A packaging structure for reducing packaging parasitic parameters, comprising a packaging substrate, a plurality of bumps, a chip and plastic packaging material: wherein the packaging substrate is provided with a chip placement area, the plurality of bumps are arranged in the chip placement area, and the plurality of bumps are used to bond the chip and the packaging substrate; the chip placement area is also coated with glue, and the chip is placed in the chip placement area; the plurality of bumps are filled with insulating medium underfill; and the plastic packaging material wraps the packaging substrate, the plurality of bumps and the chip.

[0008] Preferably, each bump comprises a tin cap, a plated pillar and a lower metal layer, the tin cap is connected to the chip, the lower metal layer is arranged between the plated pillar and the packaging substrate, and the lower metal layer is fixed to the packaging substrate through a pad.

[0009] Preferably, each bump further comprises a barrier layer arranged between the tin cap and the plated pillar.

[0010] Preferably, the tin cap is made of a tin-silver alloy, the barrier layer is made of a nickel barrier layer, and the plated pillar is made of a copper pillar.

[0011] Preferably, the diameter of each bump is between 60um and 130um, and the height of each bump is between 65um and 100um.

[0012] Preferably, the spacing between any two adjacent bumps is the same.

[0013] Preferably, the chip placement area comprises a central region and a peripheral region, and the number of bumps in the central region is greater than the number of bumps in the peripheral region.

[0014] Preferably, taking the packaging substrate as the bottommost part, the insulating medium underfill forms a trapezoidal structure, and two inclined sides of the trapezoidal structure are connected to the chip.

[0015] Preferably, the insulating medium underfill is made of an epoxy material.

[0016] The utility model discloses a packaging structure for reducing packaging parasitic parameters, comprising a packaging substrate, a plurality of bumps, a chip and plastic packaging material: wherein the packaging substrate is provided with a chip placement area, the plurality of bumps are arranged in the chip placement area, and the plurality of bumps are used to bond the chip and the packaging substrate; the chip placement area is also coated with glue, and the chip is placed in the chip placement area; the plurality of bumps are filled with insulating medium underfill; and the plastic packaging material wraps the packaging substrate, the plurality of bumps and the chip.

[0017] The utility model discloses a packaging structure for reducing packaging parasitic parameters, comprising a packaging substrate, a plurality of bumps, a chip and plastic packaging material: wherein the packaging substrate is provided with a chip placement area, the plurality of bumps are arranged in the chip placement area, and the plurality of bumps are used to bond the chip and the packaging substrate; the chip placement area is also coated with glue, and the chip is placed in the chip placement area; the plurality of bumps are filled with insulating medium underfill; and the plastic packaging material wraps the packaging substrate, the plurality of bumps and the chip. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a structure schematic view that a plurality of bumps are connected to the packaging substrate;

[0019] Figure 2 It is a structure schematic view that a chip is connected to the packaging substrate through a plurality of bumps;

[0020] Figure 3 This is a schematic diagram of a chip that is connected to a packaging substrate through multiple bumps and then encapsulated using molding compound.

[0021] Figure 4 This is a schematic diagram of a chip structure where a chip is connected to a packaging substrate via multiple bumps and then filled with an insulating dielectric filler. Detailed Implementation

[0022] The following will refer to the appendix in the embodiments of this utility model. Figures 1 to 4 The technical solutions in the embodiments of this utility model will be described in detail below.

[0023] like Figure 3 As shown in the figure, a schematic diagram of a chip is constructed by connecting it to a packaging substrate through multiple bumps and then encapsulating it with molding compound. In the figure, 1 represents a bump, 2 represents a packaging substrate, and 4 represents a chip. Multiple bumps can effectively achieve bonding between the chip and the packaging substrate. In this structure, multiple bumps replace traditional bonding wires or multi-layer wafers to connect the chip and the packaging substrate, greatly shortening the path between them and effectively reducing the influence of parasitic parameters. At the same time, it eliminates the need for high-precision equipment and complex multi-layer process steps, making the cost controllable and easier to promote.

[0024] The die-placement area of ​​the packaging substrate has multiple bumps for bonding the chip and the packaging substrate. The die-placement area is a pre-defined position on the packaging substrate for placing the chip.

[0025] In this embodiment, each bump includes at least a solder cap, an electroplated pillar, and a lower metal layer. The solder cap is used to connect the chip, providing good solderability and mechanical strength, and enabling reliable bonding between the chip and the substrate. The lower metal layer is disposed between the electroplated pillar and the packaging substrate, and is fixed to the packaging substrate by pads. The lower metal layer is fixed by pads to avoid the risk of peeling.

[0026] like Figure 1 The diagram shows a schematic of the connection between a bump and a packaging substrate. In the diagram, 10 is a pad, 20 is a lower metal layer, 30 is an electroplating pillar, 40 is a barrier layer, and 50 is a solder cap. In each bump, a barrier layer can also be set between the solder cap and the electroplating pillar to prevent the formation of intermetallic compounds between the solder cap and the electroplating pillar, thereby improving the reliability of long-term use.

[0027] In this embodiment, the tin cap is made of a tin-silver alloy, the barrier layer is made of nickel, and the electroplating pillar is made of copper. The tin-silver alloy is suitable for high-temperature applications and has a higher melting point than pure tin; the nickel barrier layer has high chemical stability and can suppress electromigration; copper pillars are chosen because they are widely used and have lower costs.

[0028] In this embodiment, the diameter of each bump is between 60µm and 130µm, and the height is between 65µm and 100µm. Controlling the size of each bump is equivalent to shortening the distance between the packaging substrate and the chip, thereby effectively reducing parasitic parameters. Controlling the height is to ensure a stable connection while shortening the distance between the chip and the packaging substrate; controlling the diameter is to control the impedance.

[0029] In this embodiment, the spacing between any two adjacent protrusions is the same. Uniform spacing can avoid differences in local capacitance or inductance, thereby reducing signal crosstalk.

[0030] The chip placement area is coated with adhesive, such as the U8410 series adhesive, which cures quickly and can be used to fix and protect the chip; the chip is stably placed in the chip placement area with the help of the adhesive.

[0031] In this embodiment, the die placement area includes a central area and a peripheral area, with the number of bumps in the central area being greater than the number of bumps in the peripheral area. During actual chip operation, heat is often generated, and the central area experiences significant expansion displacement. High-density bumps can disperse the stress during expansion, preventing cracking at the solder joints.

[0032] An insulating dielectric filler is used to fill the gaps between the multiple bumps, further strengthen the connection between the chip and the packaging substrate, and provide insulation protection.

[0033] like Figure 4 The diagram shows a structure in which a chip is connected to a packaging substrate through multiple bumps and then filled with an insulating dielectric filler. When filling the insulating dielectric filler, the packaging substrate is considered as the bottom. The insulating dielectric filler is in the form of a trapezoidal structure and the two inclined sides of the trapezoidal structure are connected to the chip. This not only fills the gaps between the multiple bumps, but also further helps to stabilize the connection between the chip and the packaging substrate.

[0034] like Figure 3 The diagram shows a chip connected to a packaging substrate via multiple bumps, which is then encapsulated using molding compound. In the diagram, 3 represents molding compound, and 5 represents insulating dielectric filler. After the insulating dielectric filler is filled, the molding compound can be used for overall encapsulation, completing the encapsulation process.

[0035] In this embodiment, the insulating dielectric bottom filler is made of epoxy resin, which has strong adhesion and excellent electrical insulation properties, making it suitable for this encapsulation.

[0036] In summary, the utility model discloses through the bonding of multiple convex points, effectively reduce the interval of chip and package substrate, thereby reduce the influence of parasitic parameter, simultaneously, for material selection, size control and the structure restriction of insulating medium bottom filler, further reduce parasitic parameter and give consideration to mechanical strength, thermal management and stability, in addition, need not carry out multilayer wafer stacking, controllable cost, convenient to use, with remarkable progress nature.

[0037] The above examples are only for illustrating the technical idea of the utility model, and cannot limit the protection scope of the utility model, and any modification made on the basis of the technical scheme according to the technical idea of the utility model falls within the protection scope of the utility model.

Claims

1. A packaging structure for reducing packaging parasitic parameters, characterized by, The package substrate, the plurality of bumps, the chip and the plastic encapsulation material are included. The package substrate is provided with a chip placement area, and the plurality of bumps are arranged in the chip placement area and used for bonding the chip and the package substrate.

2. The package structure of claim 1, wherein, The chip placement area is further coated with glue, and the chip is placed in the chip placement area.

3. The package structure of claim 2, wherein, The plurality of bumps are filled with insulating medium underfill material.

4. The package structure of claim 3, wherein, The plastic encapsulation material wraps the package substrate, the plurality of bumps and the chip.

5. The package structure of claim 1, wherein, Each bump includes a tin cap, an electroplated pillar and a lower metal layer.

6. The package structure of claim 1, wherein, The tin cap is connected to the chip, the lower metal layer is arranged between the electroplated pillar and the package substrate, and the lower metal layer is fixed to the package substrate through a solder pad.

7. The package structure of claim 1, wherein, Each bump further includes a barrier layer arranged between the tin cap and the electroplated pillar.

8. The package structure of claim 1, wherein, The tin cap is made of a tin-silver alloy, the barrier layer is made of a nickel barrier layer, and the electroplated pillar is made of a copper pillar.

9. The package structure of claim 1, wherein, The diameter of each bump is between 60um and 130um, and the height is between 65um and 100um. The spacing between any two adjacent bumps is the same. The chip placement area includes a central region and a peripheral region, and the number of bumps in the central region is greater than that in the peripheral region. The insulating medium underfill material forms a trapezoidal structure, and the two inclined sides of the trapezoidal structure are connected to the chip. The insulating medium underfill material is made of an epoxy resin material.

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