Power supply switching circuit, charging circuit and charging equipment

Abstract

The utility model provides a power supply switching circuit, through cooperative control of a first voltage stabilization unit and a first PMOS tube Q1, AC power supply rapid power-down and dual power supply seamless switching are realized, the first voltage stabilization unit is directly coupled to a Q1 grid electrode, when an AC power supply output end is disconnected, the grid electrode voltage of the first PMOS tube Q1 is actively pulled down through a dynamic discharge path of the first voltage stabilization unit, and the first PMOS tube Q1 is switched off. When an AC power supply is discharged, the first PMOS transistor Q1 is forced to be switched from conduction to cut-off, an AC power supply output path is cut off, drain voltage of the first PMOS transistor Q1 triggers the switch unit to be conducted through the second voltage stabilization unit, grid potential of the third PMOS transistor Q3 is pulled down, the third PMOS transistor Q3 is synchronously switched off, and discharge of an energy storage capacitor at the AC power supply output end is accelerated, so that traditional passive discharge time is shortened to millisecond level, and the output voltage of the AC power supply is reduced. And the switching delay caused by voltage residue is thoroughly eliminated. Therefore, the utility model provides a hardware architecture which can help to reduce the power supply switching response time.

Description

Technical Field

[0001] This utility model relates to the field of electronic technology, specifically to a power supply switching circuit, a charging circuit, and a charging device. Background Technology

[0002] Currently, lithium battery charging products use both AC power and TYPE-C power for power supply. If both methods are used in the product, a power supply switching circuit needs to be configured.

[0003] The existing power switching circuit has a significant delay defect when switching between AC power and TYPE-C power. When switching from AC power to TYPE-C power, it is necessary to wait for the AC terminal voltage to fully release. During this process, because a large electrolytic capacitor is connected to the AC power output terminal, the voltage across the electrolytic capacitor cannot change abruptly. Therefore, the voltage can only drop slowly, resulting in a power switching delay and interrupting the user experience. There is an urgent need to optimize the power switching response time. Utility Model Content

[0004] To address the aforementioned problems, this utility model proposes a power supply switching circuit, a charging circuit, and a charging device.

[0005] In a first aspect, this utility model provides a power supply switching circuit, which includes a power supply output terminal S1, characterized in that the circuit further includes:

[0006] The first PMOS transistor Q1 is electrically connected to the AC power supply output terminal.

[0007] The gate of the second PMOS transistor Q2 is electrically connected to the drain of the first PMOS transistor Q1, the drain of the second PMOS transistor Q2 is electrically connected to the TYPE-C power output terminal, and the source of the second PMOS transistor Q2 is electrically connected to the power output terminal S1.

[0008] The drain of the third PMOS transistor Q3 is electrically connected to the drain of the first PMOS transistor Q1, and the source of the third PMOS transistor Q3 is electrically connected to the power supply output terminal S1.

[0009] The first voltage regulator unit has its input terminal electrically connected to the AC power output terminal and the gate of the first PMOS transistor Q1, and its output terminal is grounded.

[0010] The second voltage regulator unit has its input terminal electrically connected to the drain of the first PMOS transistor Q1.

[0011] The switching unit has its controlled terminal electrically connected to the output terminal of the second voltage regulator unit, its input terminal electrically connected to the gate of the third PMOS transistor Q3 and the power supply output terminal S1, and its output terminal grounded.

[0012] Beneficial effects:

[0013] This invention achieves rapid AC power-off and seamless switching between dual power supplies through the coordinated control of a first voltage regulator unit and a first PMOS transistor Q1. The first voltage regulator unit is directly coupled to the gate of Q1. When the AC power output is disconnected, the dynamic discharge path of the first voltage regulator unit actively pulls down the gate voltage of the first PMOS transistor Q1, forcing Q1 to switch from on to off, thus cutting off the AC power output path. Simultaneously, the drain voltage of the first PMOS transistor Q1 is triggered by the second voltage regulator unit to turn on the switching unit, pulling down the gate potential of the third PMOS transistor Q3, simultaneously turning off the third PMOS transistor Q3 and accelerating the discharge of the energy storage capacitor at the AC power output, reducing the traditional passive discharge time to the millisecond level and completely eliminating the switching delay caused by voltage residue. Therefore, this invention provides a hardware architecture that helps reduce power switching response time.

[0014] Furthermore, the first voltage regulator unit includes a first Zener diode D1, the anode of the first Zener diode D1 is grounded, and the cathode of the first Zener diode D1 is electrically connected to the gate and source of the first PMOS transistor Q1.

[0015] Furthermore, the circuit also includes a third resistor R3, the first end of which is electrically connected to the source of the first PMOS transistor Q1 and the AC power output terminal, and the second end of which is electrically connected to the cathode of the first Zener diode D1 and the gate of the first PMOS transistor Q1.

[0016] Furthermore, the second voltage regulator unit includes a second Zener diode D2 and a fourth resistor R4. The cathode of the second voltage regulator unit is electrically connected to the drain of the first PMOS transistor Q1, the anode of the second voltage regulator unit is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the controlled end of the switching unit.

[0017] Furthermore, the switching unit includes a fourth transistor Q4, a first capacitor C1, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;

[0018] The base of the fourth transistor Q4 is electrically connected to the output terminal of the second voltage regulator unit, the first terminal of the fifth resistor R5, and the first terminal of the first capacitor.

[0019] The collector of the fourth transistor Q4 is electrically connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is electrically connected to the gate of the third PMOS transistor Q3 and one end of the seventh resistor R7, and the other end of the seventh resistor R7 is electrically connected to the power supply output terminal S1.

[0020] The emitter of the fourth transistor Q4, the second terminal of the fifth resistor R5, and the second terminal of the first capacitor are grounded.

[0021] Furthermore, the circuit also includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is electrically connected to the gate of the second PMOS transistor Q2 and the first end of the second resistor R2. The second end of the first resistor R1 is grounded, and the second end of the second resistor R2 is electrically connected to the drain of the first PMOS transistor Q1.

[0022] Furthermore, the circuit also includes a filtering unit, the input terminal of which is electrically connected to the source of the third PMOS transistor Q3 and the source of the second PMOS transistor Q2, and the output terminal of which is electrically connected to the power supply output terminal S1.

[0023] Furthermore, the filtering unit includes a second capacitor C2 and a third capacitor C3;

[0024] The first terminal of the second capacitor C2 is electrically connected to the source of the third PMOS transistor Q3 and the source of the second PMOS transistor Q2, and the second terminal of the second capacitor C2 is grounded.

[0025] The first terminal of the third capacitor C3 is electrically connected to the first terminal of the second capacitor C2 and the power supply output terminal S1, and the second terminal of the third capacitor C3 is grounded.

[0026] Secondly, the present invention provides a charging circuit, including a charging management chip circuit and a power supply switching circuit as described in any of the above embodiments, wherein the power supply output terminal S1 of the power supply switching circuit is electrically connected to the input terminal of the charging management chip circuit.

[0027] Thirdly, the present invention provides a charging device, including a charging circuit as described in the above embodiments. Attached Figure Description

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0029] Figure 1 This utility model provides a circuit diagram of a power supply switching circuit;

[0030] Figure 2 A circuit diagram of another power supply switching circuit provided by this utility model.

[0031] In the picture:

[0032] 1. First regulated power supply; 2. Second regulated unit; 3. Switching unit; 4. Filtering unit. Detailed Implementation

[0033] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] In this specification, unless otherwise expressly specified and limited, "above" or "below" a second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of a second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" of a second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] like Figure 1 As shown, this utility model provides a power supply switching circuit, which is provided with a power supply output terminal S1. The circuit further includes:

[0039] The first PMOS transistor Q1 is electrically connected to the AC power supply output terminal.

[0040] The gate of the second PMOS transistor Q2 is electrically connected to the drain of the first PMOS transistor Q1, the drain of the second PMOS transistor Q2 is electrically connected to the TYPE-C power output terminal, and the source of the second PMOS transistor Q2 is electrically connected to the power output terminal S1.

[0041] The drain of the third PMOS transistor Q3 is electrically connected to the drain of the first PMOS transistor Q1, and the source of the third PMOS transistor Q3 is electrically connected to the power supply output terminal S1.

[0042] The first voltage regulator unit has its input terminal electrically connected to the AC power output terminal and the gate of the first PMOS transistor Q1, and its output terminal is grounded.

[0043] The second voltage regulator unit has its input terminal electrically connected to the drain of the first PMOS transistor Q1.

[0044] The switching unit has its controlled terminal electrically connected to the output terminal of the second voltage regulator unit, its input terminal electrically connected to the gate of the third PMOS transistor Q3 and the power supply output terminal S1, and its output terminal grounded.

[0045] This embodiment achieves rapid AC power-off and seamless switching between dual power supplies through the coordinated control of the first voltage regulator unit and the first PMOS transistor Q1. The first voltage regulator unit is directly coupled to the gate of Q1. When the AC power output is disconnected, the dynamic discharge path of the first voltage regulator unit actively pulls down the gate voltage of the first PMOS transistor Q1, forcing Q1 to switch from on to off, thus cutting off the AC power output path. Simultaneously, the drain voltage of the first PMOS transistor Q1 triggers the switching unit to turn on via the second voltage regulator unit, pulling down the gate potential of the third PMOS transistor Q3, simultaneously turning off Q3 and accelerating the discharge of the energy storage capacitor at the AC power output, reducing the traditional passive discharge time to the millisecond level, and completely eliminating the switching delay caused by voltage residue. Therefore, this embodiment provides a hardware architecture that helps reduce power switching response time.

[0046] Furthermore, in this embodiment, the first voltage regulator stabilizes the gate potential of the first PMOS transistor Q1 when powered by the AC power output, ensuring that the first PMOS transistor Q1 conducts with low impedance. At the instant the AC power output is de-energized, the first voltage regulator quickly releases the gate charge of the first PMOS transistor Q1, achieving interlocked turn-off of Q1 and Q3. This avoids the risk of voltage backflow and short circuit caused by simultaneous conduction of the two power paths, improving system reliability. Moreover, the gate of the second PMOS transistor Q2 is directly controlled by the drain voltage of the first PMOS transistor Q1. When the first voltage regulator drives the first PMOS transistor Q1 to turn off, the gate voltage of the second PMOS transistor Q2 synchronously returns to zero, instantaneously turning on the TYPE-C power supply path. This eliminates the voltage drop caused by parasitic diodes in traditional solutions, increasing the TYPE-C power supply efficiency to nearly 100%.

[0047] Specifically, after the AC power output terminal is unplugged, the Zener diode D1 connected to the gate of the first PMOS transistor Q1 is quickly turned off, the gate of the first PMOS transistor Q1 is disconnected from ground, and the gate voltage of the first PMOS transistor Q1 quickly rises to the AC power output terminal voltage. At this time, the gate voltage Vg of the first PMOS transistor will be equal to the source voltage Vs of the first PMOS transistor, which will be at a high level. Q1 is quickly turned off, and the DC output voltage cannot supply power to the power output terminal S1 through Q1.

[0048] Preferably, such as Figure 2 The first voltage regulator unit 1 includes a first voltage regulator diode D1, the anode of the first voltage regulator diode D1 is grounded, and the cathode of the first voltage regulator diode D1 is electrically connected to the gate and source of the first PMOS transistor Q1.

[0049] Preferably, the circuit further includes a third resistor R3, the first end of which is electrically connected to the source of the first PMOS transistor Q1 and the AC power output terminal, and the second end of which is electrically connected to the cathode of the first Zener diode D1 and the gate of the first PMOS transistor Q1. The third resistor R3 serves as a pull-down resistor for the source of the first PMOS transistor Q1.

[0050] Preferably, such as Figure 2 As shown, the second voltage regulator unit includes a second Zener diode D2 and a fourth resistor R4. The cathode of the second voltage regulator unit is electrically connected to the drain of the first PMOS transistor Q1, the anode of the second voltage regulator unit is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the controlled end of the switching unit.

[0051] Preferably, such as Figure 2 As shown, the switching unit 3 includes a fourth transistor Q4, a first capacitor C1, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7.

[0052] The base of the fourth transistor Q4 is electrically connected to the output terminal of the second voltage regulator unit, the first terminal of the fifth resistor R5, and the first terminal of the first capacitor.

[0053] The collector of the fourth transistor Q4 is electrically connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is electrically connected to the gate of the third PMOS transistor Q3 and one end of the seventh resistor R7, and the other end of the seventh resistor R7 is electrically connected to the power supply output terminal S1.

[0054] The emitter of the fourth transistor Q4, the second terminal of the fifth resistor R5, and the second terminal of the first capacitor are grounded.

[0055] Specifically, the fourth transistor Q4 acts as a switch, controlled by the output signal of the second voltage regulator unit, determining the on / off state of the third PMOS transistor Q3. The fifth resistor R5 is the base current limiting resistor for the fourth transistor Q4, preventing excessive base current. The first capacitor C1 is a filter capacitor, suppressing sudden changes in the base voltage of the fourth transistor Q4 to avoid false triggering (such as noise interference) or introducing delay characteristics. The sixth resistor R6 is the collector load resistor for the fourth transistor Q4, limiting the current when Q4 is on, and, together with the seventh resistor R7, dividing the voltage to adjust the gate voltage of the third PMOS transistor Q3. The seventh resistor R7 is a pull-up resistor, ensuring that when the fourth transistor Q4 is off, the gate voltage of the third PMOS transistor Q3 is consistent with the power supply output terminal S1, reliably turning off the third PMOS transistor Q3.

[0056] Preferably, the circuit further includes a first resistor R1 and a second resistor R2, wherein the first end of the first resistor R1 is electrically connected to the gate of the second PMOS transistor Q2 and the first end of the second resistor R2, the second end of the first resistor R1 is grounded, and the second end of the second resistor R2 is electrically connected to the drain of the first PMOS transistor Q1.

[0057] Specifically, the 5V input voltage at the TYPE_C power output terminal is sent to the source of the second PMOS transistor Q2 through the drain and the built-in parasitic diode. At this time, the source voltage of the second PMOS transistor Q2 is about 4.7V. The gate of the second PMOS transistor Q2 is directly grounded through resistor R1. Therefore, the gate voltage Vg of the second PMOS transistor Q2 is less than the source voltage Vg (about 4.7V), and the second PMOS transistor Q2 is fully turned on.

[0058] Preferably, the circuit further includes a filter unit 4, the input terminal of which is electrically connected to the source of the third PMOS transistor Q3 and the source of the second PMOS transistor Q2, and the output terminal of which is electrically connected to the power supply output terminal S1. The filter unit 4 attenuates unwanted high-frequency, low-frequency, or random frequency components in the signal, retaining the useful signal.

[0059] Preferably, the filter unit 4 includes a second capacitor C2 and a third capacitor C3;

[0060] The first terminal of the second capacitor C2 is electrically connected to the source of the third PMOS transistor Q3 and the source of the second PMOS transistor Q2, and the second terminal of the second capacitor C2 is grounded.

[0061] The first terminal of the third capacitor C3 is electrically connected to the first terminal of the second capacitor C2 and the power supply output terminal S1, and the second terminal of the third capacitor C3 is grounded.

[0062] This embodiment also provides a charging circuit, including a charging management chip circuit and a power supply switching circuit as described in any of the above embodiments, wherein the power supply output terminal S1 of the power supply switching circuit is electrically connected to the input terminal of the charging management chip circuit.

[0063] The charging circuit provided in this embodiment achieves rapid AC power-off and seamless switching between dual power supplies through the coordinated control of the first voltage regulator unit and the first PMOS transistor Q1. The first voltage regulator unit is directly coupled to the gate of Q1. When the AC power output is disconnected, the gate voltage of the first PMOS transistor Q1 is actively pulled down through the dynamic discharge path of the first voltage regulator unit, forcing the first PMOS transistor Q1 to switch from on to off, thus cutting off the AC power output path. At the same time, the drain voltage of the first PMOS transistor Q1 is triggered by the second voltage regulator unit to turn on the switching unit, pulling down the gate potential of the third PMOS transistor Q3, simultaneously turning off the third PMOS transistor Q3 and accelerating the discharge of the energy storage capacitor at the AC power output, shortening the traditional passive discharge time to the millisecond level, and completely eliminating the switching delay caused by voltage residue. Therefore, this embodiment provides a hardware architecture that helps reduce power switching response time.

[0064] The present invention provides a charging device, including a charging circuit as described in the above embodiments.

[0065] The charging device provided in this embodiment achieves rapid AC power-off and seamless switching between dual power supplies through the coordinated control of the first voltage regulator unit and the first PMOS transistor Q1. The first voltage regulator unit is directly coupled to the gate of Q1. When the AC power output is disconnected, the gate voltage of the first PMOS transistor Q1 is actively pulled down through the dynamic discharge path of the first voltage regulator unit, forcing the first PMOS transistor Q1 to switch from on to off, thus cutting off the AC power output path. At the same time, the drain voltage of the first PMOS transistor Q1 is triggered by the second voltage regulator unit to turn on the switching unit, pulling down the gate potential of the third PMOS transistor Q3, simultaneously turning off the third PMOS transistor Q3 and accelerating the discharge of the energy storage capacitor at the AC power output, shortening the traditional passive discharge time to the millisecond level, and completely eliminating the switching delay caused by voltage residue.

[0066] It should be noted that the terms "horizontal" and "vertical" do not imply that the components must be absolutely horizontal or vertical, but rather that they can be slightly tilted. Similarly, the terms "parallel" and "perpendicular" do not imply that the components are absolutely parallel or perpendicular, but rather that they can have a certain angular deviation. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," not that the structure must be completely horizontal, but rather that it can be slightly tilted. Furthermore, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0067] It is understood that the term "multiple" in this document means at least two, such as two, three, etc., unless otherwise specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects are in an "or" relationship.

[0068] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A power supply switching circuit, comprising a power supply output terminal S1, characterized in that, The circuit also includes: The first PMOS transistor Q1 is electrically connected to the AC power supply output terminal. The gate of the second PMOS transistor Q2 is electrically connected to the drain of the first PMOS transistor Q1, the drain of the second PMOS transistor Q2 is electrically connected to the TYPE-C power output terminal, and the source of the second PMOS transistor Q2 is electrically connected to the power output terminal S1. The drain of the third PMOS transistor Q3 is electrically connected to the drain of the first PMOS transistor Q1, and the source of the third PMOS transistor Q3 is electrically connected to the power supply output terminal S1. The first voltage regulator unit has its input terminal electrically connected to the AC power output terminal and the gate of the first PMOS transistor Q1, and its output terminal is grounded. The second voltage regulator unit has its input terminal electrically connected to the drain of the first PMOS transistor Q1. The switching unit has its controlled terminal electrically connected to the output terminal of the second voltage regulator unit, its input terminal electrically connected to the gate of the third PMOS transistor Q3 and the power supply output terminal S1, and its output terminal grounded.

2. The power supply switching circuit according to claim 1, characterized in that: The first voltage regulator unit includes a first Zener diode D1, the anode of the first Zener diode D1 is grounded, and the cathode of the first Zener diode D1 is electrically connected to the gate and source of the first PMOS transistor Q1.

3. The power supply switching circuit according to claim 2, characterized in that: The circuit also includes a third resistor R3, the first end of which is electrically connected to the source of the first PMOS transistor Q1 and the AC power output terminal, and the second end of which is electrically connected to the cathode of the first Zener diode D1 and the gate of the first PMOS transistor Q1.

4. The power supply switching circuit according to claim 1, characterized in that: The second voltage regulator unit includes a second Zener diode D2 and a fourth resistor R4. The cathode of the second voltage regulator unit is electrically connected to the drain of the first PMOS transistor Q1, the anode of the second voltage regulator unit is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is electrically connected to the controlled end of the switching unit.

5. A power supply switching circuit according to claim 1, characterized in that: The switching unit includes a fourth transistor Q4, a first capacitor C1, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The base of the fourth transistor Q4 is electrically connected to the output terminal of the second voltage regulator unit, the first terminal of the fifth resistor R5, and the first terminal of the first capacitor. The collector of the fourth transistor Q4 is electrically connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is electrically connected to the gate of the third PMOS transistor Q3 and one end of the seventh resistor R7, and the other end of the seventh resistor R7 is electrically connected to the power supply output terminal S1. The emitter of the fourth transistor Q4, the second terminal of the fifth resistor R5, and the second terminal of the first capacitor are grounded.

6. The power supply switching circuit according to claim 1, characterized in that: The circuit also includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is electrically connected to the gate of the second PMOS transistor Q2 and the first end of the second resistor R2. The second end of the first resistor R1 is grounded, and the second end of the second resistor R2 is electrically connected to the drain of the first PMOS transistor Q1.

7. The power supply switching circuit according to claim 1, characterized in that: The circuit also includes a filtering unit, the input terminal of which is electrically connected to the source of the third PMOS transistor Q3 and the source of the second PMOS transistor Q2, and the output terminal of which is electrically connected to the power supply output terminal S1.

8. A power supply switching circuit according to claim 7, characterized in that: The filtering unit includes a second capacitor C2 and a third capacitor C3; The first terminal of the second capacitor C2 is electrically connected to the source of the third PMOS transistor Q3 and the source of the second PMOS transistor Q2, and the second terminal of the second capacitor C2 is grounded. The first terminal of the third capacitor C3 is electrically connected to the first terminal of the second capacitor C2 and the power supply output terminal S1, and the second terminal of the third capacitor C3 is grounded.

9. A charging circuit, characterized in that, The charging circuit includes a charging management chip circuit and a power supply switching circuit as described in any one of claims 1-8, wherein the power supply output terminal S1 of the power supply switching circuit is electrically connected to the input terminal of the charging management chip circuit.

10. A charging device, characterized in that, Includes a charging circuit as described in claim 9.

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