Semiconductor die package

Abstract

A semiconductor die package includes a semiconductor device layer, one or more integrated circuit devices, a first interconnect layer, a second interconnect layer, a metal pillar, a first metal pad, and a second metal pad. One or more integrated circuit devices are in the semiconductor device layer. The first interconnect layer is vertically adjacent a first side of the semiconductor device layer. The second interconnect layer is vertically adjacent a second side of the semiconductor device layer opposite the first side. A metal pillar extends through the semiconductor device layer. A first metal pad is in the first interconnect layer, wherein the first metal pad is in direct physical contact with the first end of the metal pillar. A second metal pad is in the second interconnect layer, wherein the second metal pad is in direct physical contact with a second end of the metal pillar opposite the first end. The semiconductor die package can realize low power consumption and improve signal propagation speed.

Description

Technical Field

[0001] This disclosure relates to a semiconductor die packaging. Background Technology

[0002] Various semiconductor device packaging technologies can be used to incorporate one or more semiconductor dies into a semiconductor die package. In some cases, semiconductor dies can be horizontally interconnected via interposers. Furthermore and / or alternatively, semiconductor dies can be vertically arranged within the semiconductor die package to achieve a smaller horizontal or lateral coverage area and / or increase the density of the semiconductor die package. Semiconductor dies can be directly connected via die-to-wafer (or wafer-to-wafer) bonding and / or via interconnects and one or more interposers. Utility Model Content

[0003] In some embodiments, a semiconductor die package includes a semiconductor device layer, one or more integrated circuit devices, a first interconnect layer, a second interconnect layer, metal pillars, a first metal pad, and a second metal pad. The one or more integrated circuit devices are located in the semiconductor device layer. The first interconnect layer is perpendicular to a first side of the semiconductor device layer. The second interconnect layer is perpendicular to a second side of the semiconductor device layer opposite to the first side. The metal pillars extend through the semiconductor device layer. The first metal pad is in the first interconnect layer, wherein the first metal pad is in direct physical contact with a first end of the metal pillar. The second metal pad is in the second interconnect layer, wherein the second metal pad is in direct physical contact with the second end of the metal pillar opposite to the first end.

[0004] In some embodiments, a semiconductor die package includes a semiconductor device layer, a first interconnect layer, a second interconnect layer, metal pillars, a first metal pad, a second metal pad, and a first barrier layer. The first interconnect layer is perpendicular to a first side of the semiconductor device layer. The second interconnect layer is perpendicular to a second side of the semiconductor device layer opposite to the first side. Metal pillars extend through the semiconductor device layer, wherein the cross-sectional width of a first end of the metal pillar is greater than the cross-sectional width of the second end of the metal pillar opposite to the first end. A first metal pad is in the first interconnect layer, wherein the first metal pad is in direct physical contact with the first end of the metal pillar. A second metal pad is in the second interconnect layer, wherein the second metal pad is in direct physical contact with the second end of the metal pillar. The first barrier layer is located between a plurality of sidewalls of the metal pillar and the semiconductor device layer, and between the sidewalls of the metal pillar and the dielectric layer of the first interconnect layer.

[0005] In some embodiments, a semiconductor die package includes a semiconductor substrate, a first interconnect layer, a second interconnect layer, metal pillars, a first metal pad, a second metal pad, and a first barrier layer. The first interconnect layer is perpendicular to a first side of the semiconductor substrate. The second interconnect layer is perpendicular to a second side of the semiconductor substrate opposite to the first side. The metal pillars extend through the semiconductor substrate. The first metal pad is in the first interconnect layer, wherein the first metal pad is in direct physical contact with a first end of the metal pillar. The second metal pad is in the second interconnect layer, wherein the second metal pad is in direct physical contact with a second end of the metal pillar opposite to the first end. The first barrier layer is located between a plurality of sidewalls of the first metal pad and the dielectric layer of the first interconnect layer. Attached Figure Description

[0006] The nature of this disclosure is best understood by reading it in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of explanation.

[0007] Figure 1A and Figure 1B This is a schematic diagram of the semiconductor die packaging example described in this article;

[0008] Figures 2A to 2E This is a schematic diagram illustrating an exemplary example of the semiconductor grain described herein;

[0009] Figures 3A to 3M This is a schematic diagram of an embodiment of forming the semiconductor die described herein;

[0010] Figures 4A to 4J This is a schematic diagram illustrating an embodiment of the semiconductor die packaging described herein;

[0011] Figure 5A and Figure 5B This is a schematic diagram of the semiconductor die packaging example described in this article;

[0012] Figure 6 This is a schematic diagram of the semiconductor die packaging example described in this article;

[0013] Figure 7 This is a flowchart of an exemplary process associated with the formation of the semiconductor die described herein;

[0014] Figure 8 This is a flowchart of an exemplary process associated with forming the semiconductor die package described herein;

[0015] Figures 9A to 9E This is a schematic diagram illustrating an embodiment of the semiconductor die packaging described herein;

[0016] Figure 10This is a flowchart of an exemplary process associated with forming the semiconductor die package described herein;

[0017] Figure 11 This is a flowchart of an exemplary process associated with forming the semiconductor die package described herein.

[0018] [Symbol Explanation]

[0019] 100: Semiconductor die packaging

[0020] 102: Semiconductor die

[0021] 104: Semiconductor die

[0022] 106: Joint Interface

[0023] 108: Device Layer

[0024] 110: Interconnection Layer

[0025] 112: Device Layer

[0026] 114: Interconnection Layer

[0027] 116: Integrated circuit device

[0028] 118: Integrated circuit device

[0029] 120: Dielectric layer

[0030] 122: Conductive Structure

[0031] 124: Joint Pad

[0032] 126: Dielectric layer

[0033] 128: Conductive Structure

[0034] 130: Joining pad

[0035] 132: Interconnection Layer

[0036] 134: Dielectric layer

[0037] 136: Conductive Structure

[0038] 138: Connection Structure

[0039] 140: Slender conductive structure

[0040] 142: Barrier Layer

[0041] 144: Barrier Layer

[0042] 146: Barrier Layer

[0043] 148: Interface

[0044] 150: Interface

[0045] 200: Exemplary Implementation Methods

[0046] 300: Exemplary Implementation Methods

[0047] 302: Groove

[0048] 304: Groove

[0049] 306: Barrier Layer

[0050] 308: Materials

[0051] 400: Exemplary Implementation Method

[0052] 402: Groove

[0053] 404: Barrier Layer

[0054] 406: Materials

[0055] 500: Semiconductor die packaging

[0056] 502: Semiconductor die

[0057] 504: Semiconductor die

[0058] 506: Joint Interface

[0059] 508: Device Layer

[0060] 510: Interconnection Layer

[0061] 512: Device Layer

[0062] 514: Interconnection Layer

[0063] 516: Integrated circuit device

[0064] 518: Integrated Circuit Device

[0065] 520: Dielectric layer

[0066] 522: Conductive structure

[0067] 524: Joint Pad

[0068] 526: Dielectric layer

[0069] 528: Conductive Structure

[0070] 530: Joint pad

[0071] 532: Interconnection Layer

[0072] 534: Dielectric layer

[0073] 536: Conductive Structure

[0074] 538: Connection Structure

[0075] 540: Slender conductive structure

[0076] 542: Barrier Layer

[0077] 544: Barrier Layer

[0078] 546: Barrier Layer

[0079] 548: Under-bump metallization (UBM) layer

[0080] 550: Interface

[0081] 552: Interface

[0082] 600: Semiconductor die packaging

[0083] 602: Device Layer

[0084] 604: Interconnection Layer

[0085] 606: Interconnect layer

[0086] 608: Integrated Circuit Device

[0087] 610: Dielectric layer

[0088] 612: Conductive Structure

[0089] 614: Dielectric layer

[0090] 616: Conductive structure

[0091] 618: Connection Structure

[0092] 620: Slender conductive structure

[0093] 622: Barrier Layer

[0094] 624: Barrier Layer

[0095] 626: Barrier Layer

[0096] 700: Process

[0097] 710: Block

[0098] 720: Block

[0099] 730: Block

[0100] 740: Block

[0101] 750: Block

[0102] 760: Block

[0103] 770: Block

[0104] 780: Block

[0105] 790: Block

[0106] 800: Process

[0107] 810: Block

[0108] 820: Block

[0109] 830: Block

[0110] 840: Block

[0111] 850: Block

[0112] 860: Block

[0113] 870: Block

[0114] 880: Block

[0115] 900: Exemplary Implementation Method

[0116] 902: Groove

[0117] 904: Barrier Layer

[0118] 1000: Process

[0119] 1010: Block

[0120] 1020: Block

[0121] 1030: Block

[0122] 1040: Block

[0123] 1050: Block

[0124] 1060: Block

[0125] 1100: Process

[0126] 1110: Block

[0127] 1120: Block

[0128] 1130: Block

[0129] 1140: Block

[0130] 1150: Block

[0131] 1160: Block 1170: Block

[0132] D1: Dimensions

[0133] D2: Dimensions

[0134] D3: Dimensions

[0135] D4: Dimensions

[0136] D5: Size

[0137] D6: Size

[0138] D7: Size

[0139] D8: Size

[0140] D9: Size

[0141] D10: Dimensions Detailed Implementation

[0142] The following disclosure provides numerous different implementations or examples for carrying out various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0143] Additionally, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0144] In some cases, the semiconductor die in a semiconductor die package can be connected to interconnect layers on both sides of the semiconductor die. For example, a first interconnect layer can be included on a first side (e.g., the front side) of the semiconductor die, and a second interconnect layer can be included on a second side (e.g., the rear side) of the semiconductor die opposite to the first die. In some cases, the first interconnect layer can be used for routing signals throughout the semiconductor die, and the second interconnect layer can be used to provide power to the integrated circuit device of the semiconductor die. Furthermore and / or alternatively, one of the first or second interconnect layers can be coupled to another semiconductor die and used for inter-die communication, and the other interconnect layer can be connected to a connector of the semiconductor die package for external connectivity.

[0145] To enable the transmission of signals and / or electrical power between first and second interconnect layers, one or more elongated conductive structures may be incorporated through a device layer (e.g., a semiconductor layer) containing integrated circuit devices. The elongated conductive structures (sometimes called through-silicon vias, TSVs) are connected to one or more metallization layers in the first and second interconnect layers and may be formed of a conductive metal such as copper (Cu) to achieve low resistance between the metallization layers in the first and second interconnect layers via the elongated conductive structures. However, the conductive metal of the elongated conductive structures (and from the metallization layers in the first and second interconnect layers) may diffuse into the surrounding dielectric layer of the first and second interconnect layers and / or into the device layer of the semiconductor die. This diffusion of the conductive metal can lead to an increase in the resistance of the elongated conductive structures and / or the metallization layers in the first and second interconnect layers. Furthermore, the diffusion of the conductive metal may lead to an increase in leakage current in the semiconductor die.

[0146] A barrier layer may be included between the elongated conductive structure and the surrounding dielectric and device layers, as well as between the metallization layers in the first and second interconnect layers, to reduce and / or minimize the diffusion of the conductive metal. However, the barrier layer has a higher resistivity than the conductive metal in the elongated conductive structure and the multiple metallization layers in the first and second interconnect layers. Therefore, if a barrier layer is included between the elongated conductive structure and the metallization layers in the first and second interconnect layers, the barrier layer may also cause an increase in the resistance of the elongated conductive structure and the metallization layers in the first and second interconnect layers.

[0147] In some embodiments described herein, an elongated conductive structure is included in the device layer of a semiconductor die included in a semiconductor die package. The elongated conductive structure is connected to a metallization layer in a plurality of interconnect layers on the opposite side of the device layer. To achieve low contact resistance between the elongated conductive structure and the metallization layer, a barrier material is used to suppress the growth of the barrier layer on the elongated conductive structure during the formation of the barrier layer for the metallization layer. This allows the metallization layer to fall directly onto the elongated conductive structure, rather than the barrier layer being located between the elongated conductive structure and the metallization layer. In this way, a metal-to-metal connection can be achieved between the conductive structure and the metallization layer, enabling low contact resistance while simultaneously forming a barrier layer to provide diffusion protection for the metallization layer. This allows the semiconductor die package to achieve low power consumption and improved signal propagation speed.

[0148] Figure 1A and Figure 1B This is a schematic diagram of an example of a semiconductor die package 100 described in this article. Figure 1A A cross-sectional view of the semiconductor die package 100 is shown. (See attached image.) Figure 1A As shown, the semiconductor die package 100 includes semiconductor dies 102 and semiconductor dies 104 bonded at a bonding interface 106, such that semiconductor dies 102 and semiconductor dies 104 are stacked and vertically arranged within the semiconductor die package 100. The bonding between semiconductor dies 102 and semiconductor dies 104 can be achieved by bonding multiple semiconductor wafers together (e.g., wafer-to-wafer bonding), by bonding multiple dies together (die-to-die bonding), and / or by bonding semiconductor die-to-wafer (e.g., die-to-wafer bonding), examples of other bonding configurations are not listed here. Bonding tools can be used to perform bonding operations to form bonded semiconductor dies 102 and semiconductor dies 104 by metal-to-metal bonding and / or dielectric-to-dielectric bonding at the bonding interface 106 between semiconductor dies 102 and semiconductor dies 104.

[0149] Semiconductor die 102 may include system-on-chip (SoC) dies, such as logic dies, central processing unit (CPU) dies, graphics processing unit (GPU) dies, digital signal processing (DSP) dies, application-specific integrated circuit (ASIC) dies, and / or another type of SoC die. Additionally and / or alternatively, semiconductor die 102 may include memory dies, input / output (I / O) dies, pixel sensor dies, and / or another type of semiconductor die. Memory dies may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, NAND dies, high bandwidth memory (HBM) dies, and / or another type of memory die. Semiconductor die 104 may include semiconductor dies of the same type as semiconductor die 102, or may include semiconductor dies of different types.

[0150] like Figure 1A As further shown, semiconductor die 102 may include device layer 108 and interconnect layer 110 above device layer 108. Semiconductor die 104 may include device layer 112 and interconnect layer 114 below device layer 112. Bonding interface 106 may be located between interconnect layer 110 and interconnect layer 114, and may include a portion of interconnect layer 110 and interconnect layer 114. Bonding interface 106 may include a plurality of conductive structures of interconnect layer 110 and interconnect layer 114 bonded together by metal-to-metal bonding and / or a plurality of dielectric layers of interconnect layer 110 and interconnect layer 114 bonded together by dielectric-to-dielectric bonding.

[0151] Device layer 108 may correspond to a portion of a semiconductor wafer on which semiconductor die 102 is formed, and device layer 112 may correspond to a portion of another semiconductor wafer on which semiconductor die 104 is formed. Device layer 108 and device layer 112 may each include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate.

[0152] Device layer 108 and device layer 112 may respectively include multiple integrated circuit devices 116 and multiple integrated circuit devices 118 of semiconductor die 102 and semiconductor die 104. Integrated circuit devices 116 and integrated circuit devices 118 may each include transistors (e.g., planar transistors, fin field-effect transistors, finFETs, gate all around (GAA) transistors), pixel sensors, capacitors, resistors, inductors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of passive and / or active integrated circuit devices.

[0153] Interconnect layer 110 and interconnect layer 114 may each include conductive structures that interconnect integrated circuit devices 116 and 118 of device layer 108 and device layer 112, respectively. In addition and / or alternatively, interconnect layer 110 and interconnect layer 114 may each include conductive structures that electrically connect semiconductor die 102 and semiconductor die 104.

[0154] The interconnect layer 110 of the semiconductor die 102 includes one or more dielectric layers 120 arranged in a direction generally perpendicular to the device layer 108. The dielectric layer 120 may include back-end dielectric layers (e.g., interlayer dielectric (ILD) layers and intermetal dielectric (IMD) layers) and etch stop layers (ESL) arranged alternately in the interconnect layer 110. Each dielectric layer 120 may each include an oxide (e.g., silicon oxide (SiOx) and / or another oxide material), undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), an extremely low dielectric constant (ELK) dielectric material having a dielectric constant less than about 2.5, or silicon nitride (SiOx). x N y ), silicon carbide (SiC), silicon oxynitride (SiON) and / or another suitable dielectric material.

[0155] Interconnect layer 110 includes a plurality of conductive structures 122 (e.g., conductive structures) in dielectric layer 120. The conductive structures 122 are electrically coupled and / or physically coupled to one or more integrated circuit devices 116 in device layer 108 and are electrically interconnected together in interconnect layer 110. The conductive structures 122 correspond to circuit wiring capable of providing signals and / or power to and / or from integrated circuit devices 116. The conductive structures 122 may include combinations of conductive structures (e.g., trenches, wires) extending primarily horizontally in interconnect layer 110 and conductive structures interconnected via interconnect structures (e.g., vias) extending primarily vertically in interconnect layer 110. Each conductive structure 122 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, examples of which are not listed here.

[0156] Multiple conductive interconnects of interconnect layer 110 may be arranged vertically to facilitate electrical signals and / or power between device layer 108 and semiconductor die 104, between multiple integrated circuit devices 116 via interconnect layer 110, and / or between integrated circuit devices 116 and integrated circuit devices 118 in semiconductor die 104. Conductive structures 122 may be arranged in alternating layers of metallization layers (referred to as "M" layers) and via layers (referred to as "V" layers). Each metallization layer may include one or more conductive structures arranged laterally in interconnect layer 110, and each via layer may include one or more interconnect structures interconnecting the metallization layers in interconnect layer 110. For example, a metal-0 (M0) layer may be located at the bottom of interconnect layer 110 and coupled to integrated circuit device 116 in device layer 108; a via-1 (V1) layer may be located above and coupled to M1 layer in interconnect layer 110; a metal-1 (M1) layer may be located above and coupled to V1 layer in interconnect layer 110; a via-2 (V2) layer may be located above and coupled to M1 layer in interconnect layer 110; a metal-2 (M2) layer may be located above and coupled to M1 layer in interconnect layer 110, and so on. In some embodiments, interconnect layer 110 includes nine (9) stacked metallization layers (e.g., M0 to M8). In some embodiments, interconnect layer 110 includes another number of stacked metallization layers.

[0157] At the bonding interface 106, the interconnect layer 110 may include a plurality of bonding pads 124. The bonding pads 124 may be electrically coupled to the conductive structures 122 in the interconnect layer 110 through a plurality of bonding vias and / or other types of conductive structures. The bonding pads 124 may each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and examples of other conductive metals are not listed here.

[0158] like Figure 1A As further shown, the interconnect layer 114 of semiconductor die 104 may include a combination and / or arrangement of structures and / or layers similar to the interconnect layer 110 of semiconductor die 102. For example, semiconductor die 104 may include a combination of one or more dielectric layers 126 and conductive structures 128 in the dielectric layers 126. Furthermore, interconnect layer 114 may include bonding pads 130 electrically coupled to one or more conductive structures 128 (e.g., through connecting vias and / or other types of conductive structures). These layers and / or structures may have a vertical arrangement opposite to semiconductor die 102, allowing semiconductor die 102 and semiconductor die 104 to bond at bonding interface 106 such that interconnect layer 110 and interconnect layer 114 face each other.

[0159] At the bonding interface 106, the bonding pads 124 of the semiconductor die 102 and the bonding pads 130 of the semiconductor die 104 are directly bonded by a plurality of metal-metal bonds. In addition, the dielectric layers of one or more dielectric layers 120 of the semiconductor die 102 and the dielectric layers of one or more dielectric layers 126 of the semiconductor die 104 are directly bonded by dielectric-dielectric bonds.

[0160] like Figure 1A As further shown, semiconductor die 104 may include another interconnect layer 132. Interconnect layer 114 may be located on a first side of device layer 112 of semiconductor die 104, and interconnect layer 132 may be located on a second side of device layer 112 opposite to the first side. Interconnect layer 114 may be configured to route signals and / or power between semiconductor die 102 and semiconductor die 104, and / or may be configured to route signals and / or power between integrated circuit devices 118 of semiconductor die 104. Interconnect layer 132 may be configured to route signals and / or power between semiconductor die 104 and devices outside semiconductor die package 100. For example, interconnect layer 132 may be configured to route signals and / or power between semiconductor die 104 and another type of device outside of external high-bandwidth memory (HBM) die, external system-on-chip (SoC) die, external input / output (I / O) die, and / or semiconductor die package 100.

[0161] The interconnect layer 132 of the semiconductor die 104 includes one or more dielectric layers 134 (e.g., ILD layer, IMD layer, ESL) and conductive structures 136 (e.g., trenches, metallization layers, vias, interconnect structures) within the dielectric layers 134. Each dielectric layer 134 may each include an oxide (e.g., silicon oxide (SiO2)). x(and / or another oxide material), undoped silicate glass (USG), boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), extremely low dielectric constant (ELK) dielectric materials with a dielectric constant less than about 2.5, silicon nitride (Si) x N y The conductive structure 136 may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and examples of other conductive materials are not listed here.

[0162] Interconnect layer 132 also includes connection structure 138, which enables semiconductor die package 100 to connect to a substrate (e.g., an interposer, a printed circuit board (PCB)), another semiconductor die package, and / or to another structure. Connection structure 138 may include multiple bonding pads and / or another type of connection structure.

[0163] like Figure 1A As further shown, the semiconductor die package 100 includes one or more elongated conductive structures 140 that extend through the device layer 112 of the semiconductor die 104 between interconnect layers 114 and 132. The elongated conductive structures 140 include TSVs, metal pillars, metal cylinders, and / or other types of vertical elongated conductive structures 140 (e.g., conductive pillars, conductive vias). Each elongated conductive structure 140 is physically and electrically connected at its first end to a conductive structure 128 (e.g., a metal pad) in the interconnect layer 114 and to a conductive structure 136 (e.g., a metal pad) in each interconnect layer 132. The elongated conductive structure 140 may be referred to as a TSV structure. The elongated conductive structure 140 extends completely through the semiconductor layer (e.g., a silicon substrate) of the device layer 112, rather than extending completely through the dielectric or insulating layer. The elongated conductive structure 140 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0164] Conductive structures 128, 136, and 140 may each include a metallic material readily diffused into dielectric layers 126 and 134 and / or into the semiconductor layer of device layer 112. Therefore, barrier layer 142 may be included between one or more conductive structures 128 and dielectric layers 126 in interconnect layer 114 (including conductive structures 128 connected to the elongated conductive structure 140 (metallization layer)). Similarly, multiple barrier layers 144 may be included between one or more conductive structures 136 and dielectric layers 134 in interconnect layer 132 (including conductive structures 136 connected to the elongated conductive structure 140). Furthermore, barrier layer 146 may be included between elongated conductive structure 140 and dielectric layer 126, between elongated conductive structure 140 and dielectric layer 134, and between elongated conductive structure 140 and semiconductor layer of device layer 112.

[0165] Barrier layers 142, 144, and 146 each include one or more materials capable of blocking or inhibiting the diffusion of metal atoms (e.g., copper atoms) into the semiconductor layers of dielectric layer 126, dielectric layer 134, and / or device layer 112. Examples of such materials include tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples are not listed here.

[0166] Figure 1B Close-up views illustrate the elongated conductive structure 140, associated conductive structures 128 and 136, and barrier layers 142, 144, and 146. (See attached image.) Figure 1B As shown, barrier layer 142 may be included between multiple sidewalls of conductive structure 128 and dielectric layer 126. Barrier layer 144 may be included between multiple sidewalls of conductive structure 136 and dielectric layer 134. Barrier layer 146 may be included between multiple sidewalls of elongated conductive structure 140 and dielectric layer 126, between multiple sidewalls of elongated conductive structure 140 and dielectric layer 134, and between multiple sidewalls of elongated conductive structure 140 and semiconductor layer of device layer 112.

[0167] Combined with the following text Figures 3A to 3J and Figures 4A to 4JAs described, the barrier layers 142, 144, and 146 of the elongated conductive structure 140, as well as the associated conductive structures 128 and 136, are formed such that the barrier layers 142, 144, and 146 are not present at the interface between the elongated conductive structure 140 and the associated conductive structures 128 and 136. In other words, the formation of the barrier layers 142, 144, and 146 ensures that the material of the elongated conductive structure 140 is in direct physical contact with the material of the associated conductive structure 128 (e.g., without an intermediate barrier layer), and that the material of the elongated conductive structure 140 is in direct physical contact with the material of the associated conductive structure 136 (e.g., without an intermediate barrier layer). Therefore, the interface 148 between the elongated conductive structure 140 and the associated conductive structure 128 is a direct metal-to-metal connection (e.g., a direct copper-to-copper connection), and the interface 150 between the elongated conductive structure 140 and the associated conductive structure 136 is a direct metal-to-metal connection (e.g., a direct copper-to-copper connection). This enables low contact resistance between the elongated conductive structure 140 and the associated conductive structure 128, and between the elongated conductive structure 140 and the associated conductive structure 136. Specifically, the resistivity of the material of each of the barrier layers 142, 144, and 146 is higher than the resistivity of the materials of the elongated conductive structure 140 and the associated conductive structures 128 and 136. The formation of barrier layers 142, 144, and 146 prevents the barrier layers 142, 144, and 146 from increasing the resistance between the elongated conductive structure 140 and the associated conductive structures 128 and 136, as these barrier layers are not connected between the elongated conductive structure 140 and the associated conductive structures 128 and 136.

[0168] like Figure 1BAs further shown, the elongated conductive structure 140 may have a cross-sectional profile, wherein the elongated conductive structure 140 is tapered between the associated conductive structure 128 and the associated conductive structure 136. The shape of the tapered shape may depend on the formation of the elongated conductive structure 140 during the fabrication of the semiconductor die package 100. For example, the elongated conductive structure 140 may have a dimension D1 corresponding to the cross-sectional width of the elongated conductive structure 140 at the interface 150 between the elongated conductive structure 140 and the associated conductive structure 136, and may have a dimension D2 corresponding to the cross-sectional width of the elongated conductive structure 140 at the interface 148 between the elongated conductive structure 140 and the associated conductive structure 128. In embodiments where the elongated conductive structure 140 is formed during the fabrication of the interconnect layer 114, dimension D2 may be larger than dimension D1, and the cross-sectional width of the elongated conductive structure decreases from interface 148 to interface 150. This is because the grooves for the elongated conductive structure 140 are formed in a direction from the interconnect layer 114 to the device layer 112. Etching along this direction results in the top of the groove in the interconnect layer 114 having a larger cross-sectional width than the groove in the device layer 112.

[0169] Alternatively, the elongated conductive structure 140 is formed during the fabrication of the interconnect layer 132, where the dimension D1 may be larger than the dimension D2, due to the grooves for the elongated conductive structure 140 being etched from the interconnect layer 132 into the interconnect layer 114 through the device layer 112.

[0170] In some embodiments, the size D1 may range from about 10 nanometers to about 100 nanometers. If the size D1 is less than about 10 nanometers, voids may form in the elongated conductive structure 140 due to poor copper gap filling performance. If the size D1 is greater than about 100 nanometers, the density of the integrated circuit devices 118 in the device layer 112 may be negatively affected. If the size D1 is included in the range of about 10 nanometers to about 100 nanometers, the possibility of voids forming in the elongated conductive structure 140 can be minimized, while enabling high density of integrated circuit devices 118 to be achieved in the device layer 112. However, other values ​​for the size D1 and ranges other than about 10 nanometers to about 100 nanometers are within the scope of this disclosure.

[0171] In some embodiments, the size D2 may range from about 10 nanometers to about 100 nanometers. If the size D2 is less than about 10 nanometers, voids may form in the elongated conductive structure 140 due to poor copper gap filling performance. If the size D2 is greater than about 100 nanometers, the density of the integrated circuit devices 118 in the device layer 112 may be negatively affected. If the size D2 is included in the range of about 10 nanometers to about 100 nanometers, the possibility of voids forming in the elongated conductive structure 140 can be minimized, while enabling high density of integrated circuit devices 118 in the device layer 112. However, other values ​​for the size D2 and ranges other than about 10 nanometers to about 100 nanometers are within the scope of this disclosure.

[0172] Another example of semiconductor die 104 includes a dimension D3 comprising the thickness or vertical length of an elongated conductive structure 140. In some embodiments, dimension D3 comprises approximately 50 nanometers to approximately 150 nanometers. In some embodiments, the ratio of dimension D3 to dimension D1 is in the range of approximately 1.5:1 to approximately 5:1. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the ratio of dimension D3 to dimension D2 is in the range of approximately 1.5:1 to approximately 5:1. However, other values ​​within this range are also within the scope of this disclosure.

[0173] Another example of semiconductor die 104 includes a dimension D4 comprising the angle between the sidewall of the elongated conductive structure 140 and the bottom surface of the associated conductive structure 136. In some embodiments, dimension D4 includes a range greater than about 60 degrees and less than about 90 degrees. However, other values ​​within this range are also within the scope of this disclosure. Another example of semiconductor die 104 includes a dimension D5 comprising the angle between the sidewall of the elongated conductive structure 140 and the bottom surface of the associated conductive structure 128. In some embodiments, dimension D5 includes a range greater than about 90 degrees and less than about 120 degrees. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the difference between dimension D5 and dimension D4 includes a range from about 0 degrees to about 10 degrees. However, other values ​​within this range are also within the scope of this disclosure.

[0174] As mentioned above, Figure 1A and Figure 1B Provided as an example. Other examples may be provided in relation to... Figure 1A and Figure 1B The descriptions are different.

[0175] Figures 2A to 2EThis is an illustration of an exemplary embodiment 200 for forming a semiconductor die as described herein. In some embodiments, exemplary embodiment 200 includes an exemplary process for forming a semiconductor die 102 or a portion thereof. In some embodiments, one or more operations described in conjunction with exemplary embodiment 200 may be performed to form another semiconductor die as described herein, such as... Figure 5A The semiconductor die 502 shown is illustrated. In some embodiments, one or more semiconductor process tools may be used to perform one or more operations described in conjunction with exemplary embodiment 200, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or another type of semiconductor process tool.

[0176] refer to Figure 2A In exemplary embodiment 200, one or more operations can be performed on the semiconductor layer of the device layer 108 in conjunction with the semiconductor die 102. The semiconductor layer of the device layer 108 may be provided in the form of a semiconductor wafer or another type of semiconductor substrate.

[0177] like Figure 2B As shown, integrated circuit device 116 may be formed in and / or on device layer 108 of semiconductor die 102. One or more semiconductor process tools may be used to form one or more portions of integrated circuit device 116. For example, deposition tools may be used to perform various deposition operations to deposit layers of integrated circuit device 116 and / or to deposit photoresist layers for etching semiconductor layers and / or portions of the deposited layers of device layer 108. As another example, exposure tools may be used to expose photoresist layers to form patterns in the photoresist layers. As another example, development tools may be used to develop patterns in photoresist layers. As another example, etching tools may be used to etch semiconductor layers and / or portions of the deposited layers to form integrated circuit device 116. As another example, planarization tools may be used to planarize portions of integrated circuit device 116. As another example, ion implantation tools may be used to implant ions in semiconductor layers to dope portions of the semiconductor layer of device layer 108 with one or more types of dopants (e.g., p-type dopants, n-type dopants).

[0178] like Figures 2C to 2EAs shown, the interconnect layer 110 of the semiconductor die 102 may be formed on and / or on the device layer 108. One or more semiconductor processing tools may be used to form the interconnect layer 110 by forming one or more dielectric layers 120 and forming a plurality of conductive structures 122 in the dielectric layers 120. For example, a deposition tool may be used to deposit a first layer of the dielectric layer 120 (e.g., using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), oxidation technology and / or another type of deposition technology), an etching tool may be used to remove portions of the first layer to form a trench in the first layer, and the deposition tool may be used to form a first layer of one or more conductive structures 122 in the trench (e.g., via layer, metallization layer) (e.g., using CVD, ALD, PVD, electroplating technology and / or another type of deposition technology). At least a portion of the first layer of conductive structure 122 may be electrically and / or physically connected (e.g., directly connected or via contact) to integrated circuit device 116 in device layer 108. Similar process operations may be performed to form additional layers of interconnect layer 110 until a sufficient or desired arrangement of conductive structure 122 is achieved.

[0179] like Figure 2E As shown, bonding pad 124 may be formed in interconnect layer 110. Bonding pad 124 may be formed in dielectric layer of dielectric layer 120. Dielectric layer may be bonding dielectric layer. Bonding pad 124 may be formed on bonding via in interconnect layer 110, and bonding via can electrically connect bonding pad 124 to one or more conductive structures 122 in interconnect layer 110.

[0180] As mentioned above, Figures 2A to 2E Provided as an example. Other examples may be found in relation to [the relevant information]. Figures 2A to 2E The descriptions are different.

[0181] Figures 3A to 3M This is an illustration of an exemplary embodiment 300 for forming a semiconductor die as described herein. In some embodiments, exemplary embodiment 300 includes an exemplary process for forming a semiconductor die 104 or a portion thereof. In some embodiments, one or more operations described in conjunction with exemplary embodiment 300 may be performed to form another semiconductor die as described herein, such as... Figure 5A The semiconductor die 504 shown is illustrated. In some embodiments, one or more operations described in conjunction with exemplary embodiment 300 may be performed to form part of the semiconductor die package described herein, such as... Figure 6The semiconductor die package 600 shown is illustrated. In some embodiments, one or more semiconductor process tools may be used to perform one or more operations described in conjunction with exemplary embodiment 300, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or another type of semiconductor process tool.

[0182] refer to Figure 3A In the exemplary embodiment 300, one or more operations can be performed on the semiconductor layer of the device layer 112 in conjunction with the semiconductor die 104. The semiconductor layer of the device layer 112 may be provided in the form of a semiconductor wafer or another type of semiconductor substrate.

[0183] like Figure 3B As shown, an integrated circuit device 118 may be formed in and / or on a device layer 112 of a semiconductor die 104. One or more semiconductor process tools may be used to form one or more portions of the integrated circuit device 118. For example, deposition tools may be used to perform various deposition operations to deposit layers of the integrated circuit device 118 and / or to deposit a photoresist layer for etching the semiconductor layer and / or portions of the deposited layer of the device layer 112. As another example, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a developing tool may be used to develop the pattern in the photoresist layer. As another example, an etching tool may be used to etch the semiconductor layer and / or portions of the deposited layer to form the integrated circuit device 118. As another example, a planarization tool may be used to planarize portions of the integrated circuit device 118. As another example, an ion implantation tool may be used to implant ions in the semiconductor layer to dope portions of the semiconductor layer of the device layer 112 with one or more types of dopants (e.g., p-type dopants, n-type dopants).

[0184] like Figure 3C As shown, a first portion of the dielectric layer 126 of the interconnect layer 114 may be formed on a first side of the semiconductor layer of the device layer 112. Deposition tools may be used to deposit the first portion of the dielectric layer 126 using CVD, ALD, PVD, oxidation, and / or another type of deposition technique. In some embodiments, a planarization tool is used to planarize the first portion of the dielectric layer 126.

[0185] like Figure 3CAs further shown, a first subset of the conductive structures 128 of the interconnect layer 114 may be formed in a first portion of the dielectric layer 126. The first subset of the conductive structures 128 may be formed in a groove within the first portion of the dielectric layer 126. In some embodiments, a pattern of the photoresist layer may be used to etch the first portion of the dielectric layer 126 to form a groove. In these embodiments, a deposition tool may be used to form a photoresist layer on the first portion of the dielectric layer 126. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the first portion of the dielectric layer 126 in a pattern-based manner to form a groove. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based groove formation.

[0186] The deposition tools can be used to deposit a first subset of the conductive structure 128 using CVD, ALD, PVD, electroplating, and / or another type of deposition technique. In some embodiments, after depositing the first subset of the conductive structure 128, a planarization tool is used to planarize the first subset of the conductive structure 128.

[0187] like Figure 3D As shown, the groove 302 extends through a first portion of the dielectric layer 126 and is formed within a portion of the semiconductor layer of the device layer 112. The first portion of the dielectric layer 126 and the semiconductor layer of the device layer 112 can be etched to form the groove 302. (As shown in the diagram...) Figure 1B The etching direction (e.g., from the first portion of dielectric layer 126 to the semiconductor layer of device layer 112) results in the groove 302 having a tapered profile similar to the elongated conductive structure 140.

[0188] The recess 302 includes multiple sidewalls having dielectric portions (corresponding to the first portion of dielectric layer 126) and semiconductor portions (corresponding to the semiconductor layer of device layer 112). The bottom surface of the recess 302 includes a semiconductor surface corresponding to the semiconductor layer of device layer 112.

[0189] In some embodiments, the pattern of the photoresist layer can be used to etch a first portion of the dielectric layer 126 to form the groove 302. In these embodiments, a deposition tool can be used to form the photoresist layer on the first portion of the dielectric layer 126. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the first portion of the dielectric layer 126 in a pattern-based manner to form the groove 302. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the groove 302.

[0190] like Figure 3E As shown, the barrier layer 146 is formed on the sidewalls and bottom surface of the groove 302. Alternatively, as in combination... Figures 9A to 9D As described, a barrier layer can be used to prevent the barrier layer 146 from forming on the bottom surface of the groove 302, so that the barrier layer 146 forms only on the sidewalls of the groove 302. The barrier layer 146 can be conformally deposited using ALD technology, CVD technology, and / or another suitable conformal deposition technique.

[0191] like Figure 3F As shown, an elongated conductive structure 140 is formed on a barrier layer 146 in a recess 302. Therefore, the barrier layer 146 is located between the dielectric portions of the sidewalls of the elongated conductive structure 140 and the sidewalls of the recess 302, between the semiconductor portions of the sidewalls of the elongated conductive structure 140 and the sidewalls of the recess 302, and between the bottom end of the elongated conductive structure 140 and the bottom surface of the recess 302. Deposition tools may be used with CVD, ALD, PVD, electroplating, and / or another type of deposition technique to deposit the elongated conductive structure 140. In some embodiments, after depositing the elongated conductive structure 140, a planarization tool is used to planarize the elongated conductive structure 140.

[0192] like Figure 3G As shown, a second portion of the dielectric layer 126 of the interconnect layer 114 may be formed on the first portion and on the top side of the elongated conductive structure 140. Deposition tools may be used with CVD, ALD, PVD, oxidation, and / or another type of deposition technique to deposit the second portion of the dielectric layer 126. In some embodiments, a planarization tool is used to planarize the second portion of the dielectric layer 126.

[0193] like Figure 3HAs shown, the groove 304 is formed through the second portion of the dielectric layer 126 and to the top of the elongated conductive structure 140. The groove 304 may be formed to prepare for the formation of a conductive structure 128 on the top side of the elongated conductive structure 140. In some embodiments, additional grooves are formed to prepare for the formation of additional conductive structures 128 in the second portion of the dielectric layer 126.

[0194] The groove 304 includes sidewalls and a bottom surface. A portion of the sidewalls and bottom surface of the groove 304 corresponds to a second portion of the dielectric layer 126. Another portion of the bottom surface of the groove 304 corresponds to an exposed portion of the barrier layer 146. However, another portion of the bottom surface of the groove 304 corresponds to the top side of the elongated conductive structure 140.

[0195] In some embodiments, the pattern in the photoresist layer is used to etch a second portion of the dielectric layer 126 to form a groove 304. In these embodiments, a deposition tool can be used to form the photoresist layer on the second portion of the dielectric layer 126. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the second portion of the dielectric layer 126 in a pattern-based manner to form the groove 304. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the groove 304.

[0196] like Figure 3I As shown, the barrier layer 306 is formed on the top side of the elongated conductive structure 140 in the groove 304. Specifically, the barrier layer 306 is formed on the top side of the elongated conductive structure 140, rather than on the sidewalls and part of the bottom surface of the groove 304, which corresponds to the exposed portion of the dielectric layer 126 and / or the barrier layer 146.

[0197] The barrier layer 306 may include one or more materials 308 that selectively adhere to the material on the top side of the elongated conductive structure 140 and do not adhere to (or minimally adhere to) the material on the dielectric sidewalls of the recess 304 and the dielectric portion of the bottom surface including the exposed portion of the barrier layer 146. For example, the material of the elongated conductive structure 140 may include copper (Cu), and the material 308 of the barrier layer 306 may include benzotriazole (BTA), tolytriazole (TTA), and / or another material selectively bonded to the top of the elongated conductive structure 140 that does not bond to the dielectric material in the recess 304.

[0198] To form the barrier layer 306, a surface treatment operation may be performed to treat the surface of the tip of the elongated conductive structure 140. The surface treatment operation may include providing a material 308 of the barrier layer 306 into a recess 304 such that the surface of the tip of the elongated conductive structure 140 is immersed for a period of time to form the barrier layer 306 on the surface of the tip of the elongated conductive structure 140. While the surface of the tip of the elongated conductive structure 140 is immersed in the material 308 of the barrier layer 306, a material composite is formed on the surface of the tip of the elongated conductive structure 140. The material composite includes a copper-BTA composite, a copper-TTA composite, and / or another type of material composite that acts as a copper corrosion inhibitor. The material composite forms electron donor sites for the material 308 of the barrier layer 306, which are covalently bonded to electron acceptor sites of the material of the elongated conductive structure 140. The electron donor sites include lone pairs of electrons from nitrogen atoms in the material 308 of the barrier layer 306, and those lone pairs are bonded to electron acceptor sites in the metallic material of the elongated conductive structure 140.

[0199] like Figure 3J As shown, when the barrier layer 306 is on the top side of the elongated conductive structure 140, the barrier layer 142 is formed on the dielectric sidewalls and dielectric bottom of the groove 304, including on the exposed portion of the barrier layer 146. Therefore, the barrier layer 142 is connected to the barrier layer 146 to provide a continuous barrier layer to prevent material diffusion. The barrier layer 306 inhibits or prevents the growth of the barrier layer 142 on the top side of the elongated conductive structure 140. Specifically, the material 308 of the barrier layer 306 inhibits the absorption of the material of the barrier layer 142 by hydrophobicity, blocking it from entering the surface of the top side of the elongated conductive structure 140.

[0200] As an example, the material of the elongated conductive structure 140 may include copper (Cu), and the material of the barrier layer 142 may include tantalum nitride (TaN). The material 308 of the barrier layer 306 acts as a copper corrosion inhibitor and prevents, minimizes, and / or reduces the absorption of tantalum nitride precursors (e.g., pentakis(dimethylamino)tantalum, PDMAT) into the copper surface on the top side of the elongated conductive structure 140.

[0201] like Figure 3KAs shown, after the barrier layer 142 is formed in the groove 304, the barrier layer 306 is subsequently removed from the top side of the elongated conductive structure 140. The barrier layer 306 can be removed by etching, plasma treatment (e.g., plasma ashing or plasma etching), and / or another material removal technique. For example, an amino plasma, an oxygen plasma, a hydrogen-based plasma, or a plasma including another type of ions can be used to perform a plasma treatment operation to remove the barrier layer 306 from the top side of the elongated conductive structure 140. The plasma can be used to bombard the barrier layer 306 with ammonia ions, oxygen ions, or another type of ions to sputter-etch the barrier layer 306 on the top side of the elongated conductive structure 140 to remove the barrier layer 306. Annealing can be performed to evaporate the material 308 removed from the barrier layer 306, and the evaporated material can be evacuated from a processing chamber in which the semiconductor die 104 is located.

[0202] like Figure 3L As shown, the conductive structure 128 can be formed in the groove 304. The formation of the conductive structure 128 is such that the conductive structure 128 rests directly on the top side of the elongated conductive structure 140 and is in solid contact with the top side of the elongated conductive structure 140. Therefore, the interface 148 between a portion of the bottom surface of the conductive structure 128 and the elongated conductive structure 140 is a direct metal-to-metal (e.g., copper-to-copper) solid connection. The remaining portions of the bottom surface of the conductive structure 128 and the sidewalls of the conductive structure 128 are in solid contact with the barrier layer 142. Deposition tools can be used to deposit the conductive structure 128 using CVD, ALD, PVD, electroplating, and / or another type of deposition technique. In some embodiments, after depositing the conductive structure 128, a planarization tool is used to planarize the conductive structure 128.

[0203] like Figure 3M As shown, additional portions of the dielectric layer 126 and additional conductive structures 128 can be formed in the interconnect layer 114 above the elongated conductive structure 140. Furthermore, bonding pads 130 can be formed on the topmost conductive structure 128. The additional portions of the dielectric layer 126, the additional conductive structures 128, and the bonding pads 130 can use similar bonding methods. Figures 2C to 2E Those described techniques are used to form.

[0204] As mentioned above, Figures 3A to 3M Provided as an example. Other examples may be found in relation to [the relevant information]. Figures 3A to 3M The descriptions are different.

[0205] Figures 4A to 4J This is an illustration of an exemplary embodiment 400 of forming a semiconductor die package as described herein. For example, exemplary embodiment 400 may include an example of forming a semiconductor die package 100. In some embodiments, one or more operations described in conjunction with exemplary embodiment 400 may be performed to form another semiconductor die package as described herein, such as... Figure 5AThe semiconductor die package 500 and / or described herein Figure 6 The semiconductor die package 600 described herein is an example; other examples are not listed here. In some embodiments, one or more semiconductor process tools may be used to perform one or more operations described in conjunction with exemplary embodiment 400, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or another type of semiconductor process tool.

[0206] like Figure 4A and Figure 4B As shown, a bonding operation is performed to bond semiconductor dies 102 and 104 at bonding interface 106, such that semiconductor dies 102 and 104 are vertically arranged or stacked in semiconductor die package 100. Semiconductor dies 102 and 104 can be vertically arranged or stacked in a wafer-on-wafer (WoW) configuration, a die-on-wafer configuration, a die-on-die configuration, and / or another direct bonding configuration. A bonding tool can be used to perform the bonding operation to bond semiconductor dies 102 and 104 at bonding interface 106. The bonding operation may include a direct physical connection through bonding pads 124 of semiconductor die 102 to bonding pads 130 of semiconductor die 104 and a direct physical connection through one or more dielectric layers 120 of semiconductor die 102 to one or more dielectric layers 126 of semiconductor die 104 to form a direct bond between semiconductor dies 102 and semiconductor die 104.

[0207] like Figure 4C As shown, the second side of the semiconductor layer of device layer 112 can be thinned to expose the bottom end of the elongated conductive structure 140 through the second side of the semiconductor layer of device layer 112. Planarization tools or polishing tools can be used to perform planarization or polishing operations (e.g., silicon polishing operations) to remove material from the second side of the semiconductor layer of device layer 112. The planarization or polishing operation also removes the barrier layer 146 from the bottom end of the elongated conductive structure 140.

[0208] As shown in the figure Figure 4D As shown, a portion of the dielectric layer 134 of the interconnect layer 132 may be formed on the second side of the semiconductor layer of the device layer 112. A portion of the dielectric layer 134 may also be formed on the exposed bottom end of the elongated conductive structure 140. Deposition tools may be used to deposit portions of the dielectric layer 134 using CVD, ALD, PVD, oxidation, and / or another type of deposition technique. In some embodiments, a planarization tool is used to planarize portions of the dielectric layer 134.

[0209] like Figure 4EAs shown, a groove 402 is formed in and extends through a portion of dielectric layer 134. The groove 402 is formed above the bottom end of elongated conductive structure 140, such that the bottom end of elongated conductive structure 140 is exposed through the groove 402. The groove 402 includes dielectric sidewalls corresponding to the portion of dielectric layer 134. The groove 402 also includes a bottom surface, a portion of which corresponds to the semiconductor layer of device layer 112 (or alternatively, to a portion of dielectric layer 134), another portion of which corresponds to an exposed portion of barrier layer 146, and yet another portion of which corresponds to the bottom end of elongated conductive structure 140.

[0210] In some embodiments, the pattern in the photoresist layer is used to etch portions of the dielectric layer 134 to form the groove 402. In some embodiments, a deposition tool can be used to form the photoresist layer on portions of the dielectric layer 134. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch portions of the dielectric layer 134 based on the pattern to form the groove 402. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for forming the groove 402 based on the pattern.

[0211] like Figure 4F As shown, the barrier layer 404 is used in conjunction with... Figure 3I A similar technique to that described for barrier layer 306 is formed on the bottom end of the elongated conductive structure 140 in the groove 402. Specifically, barrier layer 404 is formed on the bottom end of the elongated conductive structure 140, rather than on the dielectric sidewalls and semiconductor portions (or dielectric portions) of the bottom surface of the groove 402. Furthermore, the material 406 of barrier layer 404 inhibits the growth of barrier layer 404 on the exposed portions of barrier layer 146.

[0212] like Figure 4G As shown, when barrier layer 404 is on the bottom end of elongated conductive structure 140, barrier layer 144 is formed on the dielectric sidewalls of groove 402, and on the semiconductor and dielectric portions of the bottom surface of groove 402. Therefore, barrier layer 144 is connected to barrier layer 146 to provide a continuous barrier layer preventing material diffusion. Barrier layer 404 is combined with... Figure 3J The described method inhibits or blocks the growth of the barrier layer 144 on the bottom end of the elongated conductive structure 140.

[0213] like Figure 4HAs shown, after the barrier layer 144 is formed in the groove 402, the barrier layer 404 is subsequently removed from the bottom end of the elongated conductive structure 140. This can be combined with... Figure 3K The blocking layer 404 is removed in a similar manner as described.

[0214] like Figure 4I As shown, the conductive structure 136 can be formed in the groove 402. The formation of the conductive structure 136 is such that the conductive structure 136 rests directly on the bottom end of the elongated conductive structure 140 and is in solid contact with the elongated conductive structure 140. Therefore, the interface 150 between a portion of the bottom surface of the conductive structure 136 and the elongated conductive structure 140 is a direct metal-to-metal (e.g., copper-to-copper) solid connection. The remaining portions of the bottom surface of the conductive structure 136 and the sidewalls of the conductive structure 136 are in solid contact with the barrier layer 144. Deposition tools can be used to deposit the conductive structure 136 using CVD, ALD, PVD, electroplating, and / or another type of deposition technique. In some embodiments, after depositing the conductive structure 136, a planarization tool is used to planarize the conductive structure 136.

[0215] like Figure 4J As shown, additional portions of dielectric layer 134 and additional conductive structures 136 may be formed in interconnect layer 132. Furthermore, connection structures 138 may be formed on the topmost conductive structure 136. The additional portions of dielectric layer 134, additional conductive structures 136, and connection structures 138 may be formed using techniques similar to those used to form interconnect layers 110 and 114.

[0216] As mentioned above, Figures 4A to 4J Provided as an example. Other examples may be found in relation to [the relevant information]. Figures 4A to 4J The descriptions are different.

[0217] Figure 5A and Figure 5B This is an illustration of the semiconductor die package 500 described in this article. Figure 5A A cross-sectional view of a semiconductor die package 500 is shown. Figure 5A As shown, semiconductor die package 500 includes a combination and arrangement of structures and layers similar to those of semiconductor die package 100. For example, semiconductor die package 500 includes semiconductor die 502 and semiconductor die 504 bonded at a bonding interface, similar to semiconductor die 102 and semiconductor die 104 of semiconductor die package 100.

[0218] Furthermore, semiconductor die 502 and semiconductor die 504 respectively include combinations and arrangements of layers and structures similar to those of semiconductor die 102 and semiconductor die 104. For example, semiconductor die 502 includes a device layer 508, an interconnect layer 510, an integrated circuit device 516 in device layer 508, one or more dielectric layers 520 and multiple conductive structures 522 in interconnect layer 510, and bonding pads 524 in interconnect layer 510. As another example, semiconductor die 504 includes a device layer 512, an interconnect layer 514 on a first side of device layer 512, an integrated circuit device 518 in device layer 512, one or more dielectric layers 526 and multiple conductive structures 528 in interconnect layer 514, and bonding pads 530 in interconnect layer 514. Furthermore, an interconnect layer 532 is included on a second side of the device layer 512 opposite to the first side, and the interconnect layer 532 includes one or more dielectric layers 534, a plurality of conductive structures 536 in the one or more dielectric layers 534, and a connection structure 538 connected to the conductive structures 536. One or more elongated conductive structures 540 extend through the semiconductor layer of the device layer 512 between the interconnect layer 514 and the interconnect layer 532. The elongated conductive structures 540 are connected at opposite ends to the conductive structures 528 in the interconnect layer 514 and the conductive structures 536 in the interconnect layer 532. Barrier layers 542, 544, and 546 are respectively included on the sidewalls of the conductive structures 528, 536, and elongated conductive structures 540. Barrier layers 542, 544, and 546 are combined... Figures 3A to 3M and Figures 4A to 4J The described manner forms such that the elongated conductive structure 540 is in direct physical contact with the associated conductive structures 528 and 536 (e.g., metal-to-metal contact or copper-to-copper contact).

[0219] However, the connection structure 538 differs from the connection structure 138 in that it includes microbumps, controlled-collapse die connection (C4) bumps, ball grid array (BGA) connections, and / or another type of connection structure, enabling the semiconductor die package 500 to be mounted to a substrate (e.g., an interposer, a device package substrate) via solder connections. An under-bump metallization (UBM) layer 548 may be included between the connection structure 538 and the underlying conductive structure 536 to facilitate adhesion between the connection structure 538 and the underlying conductive structure 536.

[0220] Furthermore, the elongated conductive structure 540 differs from the elongated conductive structure 140 in that it extends further (or deeper) into the interconnect layer 114 than the elongated conductive structure 140 extends into the interconnect layer 114. For example, the elongated conductive structure 540 may be connected to a bonding via near the bonding interface 506, or to one or more conductive structures 528 connected to the bonding via. Therefore, the elongated conductive structure 540 is taller than the elongated conductive structure 140 (or longer in the vertical direction within the semiconductor die package 500).

[0221] like Figure 5B As shown, the semiconductor die 504 may have one or more exemplary dimensions. Exemplary dimension D6 includes the cross-sectional width of the elongated conductive structure 540 at the interface 550 between the elongated conductive structure 540 and the associated conductive structure 536. Another exemplary dimension D7 includes the cross-sectional width of the elongated conductive structure 540 at the interface 552 between the elongated conductive structure 540 and the associated conductive structure 528. Yet another exemplary dimension D8 includes the thickness or vertical length of the elongated conductive structure 540.

[0222] Another example, dimension D9, includes the angle between the sidewall of the elongated conductive structure 540 and the bottom surface of the associated conductive structure 536. Another example, dimension D10, includes the angle between the sidewall of the elongated conductive structure 540 and the bottom surface of the associated conductive structure 528.

[0223] In some embodiments, for a system-on-integrated-chip (SoIC) type semiconductor die package 500, size D6 is included in the range of about 1.6 micrometers to about 2.0 micrometers, size D7 is included in the range of about 1.8 micrometers to about 2.2 micrometers, and size D8 is included in the range of about 10 micrometers to about 40 micrometers. However, other values ​​and ranges of these dimensions are also within the scope of this disclosure. In some embodiments, for a SoIC type semiconductor die package 500, the ratio of size D7 to size D6 is included in the range of about 1.1:1 to about 1.13:1, the ratio of size D8 to size D6 is included in the range of about 6.25:1 to about 20:1, and / or the ratio of size D8 to size D7 is included in the range of about 5.5:1 to about 18:1. However, other values ​​and ranges of these ratios are also within the scope of this disclosure.

[0224] In some embodiments, for the SoIC type semiconductor die package 500, size D6 is included in the range of about 2.6 micrometers to about 3.0 micrometers, size D7 is included in the range of about 2.8 micrometers to about 3.2 micrometers, and size D8 is included in the range of about 10 micrometers to about 40 micrometers. However, other values ​​and ranges of these dimensions are also within the scope of this disclosure. In some embodiments, for the SoIC type semiconductor die package 500, the ratio of size D7 to size D6 is included in the range of about 1.06:1 to about 1.08:1, the ratio of size D8 to size D6 is included in the range of about 4:1 to about 13.33:1, and / or the ratio of size D8 to size D7 is included in the range of about 3.5:1 to about 12.5:1. However, other values ​​and ranges of these ratios are also within the scope of this disclosure.

[0225] In some embodiments, for another type of three-dimensional stacked semiconductor die package 500, size D6 is included in the range of about 4.1 micrometers to about 4.5 micrometers, size D7 is included in the range of about 4.3 micrometers to about 4.7 micrometers, and size D8 is included in the range of about 40 micrometers to about 65 micrometers. However, other values ​​and ranges of these dimensions are also within the scope of this disclosure. In some embodiments, for another type of three-dimensional stacked semiconductor die package 500, the ratio of size D7 to size D6 is included in the range of about 1.04:1 to about 1.05:1, the ratio of size D8 to size D6 is included in the range of about 9.75:1 to about 14.5:1, and / or the ratio of size D8 to size D7 is included in the range of about 9.25:1 to about 13:1. However, other values ​​and ranges of these ratios are also within the scope of this disclosure.

[0226] In some embodiments, dimension D9 is included in the range of about 60 degrees to about 90 degrees. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, dimension D10 is included in the range of about 90 degrees to about 120 degrees. However, other values ​​within this range are also within the scope of this disclosure. In some embodiments, the difference between dimension D9 and dimension D10 is included in the range of about 0 degrees to about 10 degrees. However, other values ​​within this range are also within the scope of this disclosure.

[0227] As mentioned above, Figure 5A and Figure 5B Provided as an example. Other examples may be found in relation to [the relevant information]. Figure 5A and Figure 5B The descriptions are different.

[0228] Figure 6 This is an attached figure of the semiconductor die package 600 described in this article. Figure 6A cross-sectional view of a semiconductor die package 600 is shown. Figure 6 As shown, semiconductor die package 600 includes a combination and arrangement of structures and layers similar to those of semiconductor die 104 in semiconductor die package 100. In other words, semiconductor die package 600 may include a single packaged semiconductor die. For example, semiconductor die package 600 includes device layer 602 (corresponding to device layer 112), interconnect layer 604 (corresponding to interconnect layer 114) on a first side of device layer 602, and interconnect layer 606 (corresponding to interconnect layer 132) on a second side of device layer 602 opposite to the first side.

[0229] In some embodiments, interconnect layer 604 is configured to provide routing signals between a plurality of integrated circuit devices 608 (corresponding to integrated circuit device 118) in device layer 602 and / or between integrated circuit devices 608 and external integrated circuit devices, and interconnect layer 606 is configured to provide power delivery to the integrated circuit devices 608 in device layer 602. In some embodiments, interconnect layer 606 is configured to provide routing signals between a plurality of integrated circuit devices 608 in device layer 602 and / or between integrated circuit devices 608 and external integrated circuit devices, and interconnect layer 604 is configured to provide power delivery to the integrated circuit devices 608 in device layer 602. In some embodiments, interconnect layer 604 and interconnect layer 606 are configured to provide a mixture of routing signals for semiconductor die package 600 and power delivery within semiconductor die package 600.

[0230] Interconnect layer 604 includes one or more dielectric layers 610 (corresponding to dielectric layer 126) and one or more conductive structures 612 (corresponding to conductive structure 128) in the dielectric layers 610. Interconnect layer 606 includes one or more dielectric layers 614 (corresponding to dielectric layer 134), one or more conductive structures 616 (corresponding to conductive structure 136) in the dielectric layers 614, and connection structures 618 (corresponding to connection structure 138) connected to the conductive structures 616.

[0231] like Figure 6As further shown, the semiconductor die package 600 includes one or more elongated conductive structures 620 (corresponding to elongated conductive structures 140), which extend through the semiconductor layer of the device layer 602 between interconnect layers 604 and 606. The elongated conductive structures 620 are connected at opposite ends to conductive structures 612 in interconnect layer 604 and conductive structures 616 in interconnect layer 606. Barrier layers 622, 624, and 626 (corresponding to barrier layers 142, 144, and 146, respectively) are included on the sidewalls of conductive structures 612, 616, and 620, respectively. Barrier layers 622, 624, and 626 are coupled to form a composite structure. Figures 3A to 3M and Figures 4A to 4J The described manner forms such that the elongated conductive structure 620 is in direct physical contact with the associated conductive structures 612 and 616 (e.g., metal-to-metal contact or copper-to-copper contact).

[0232] As mentioned above, providing Figure 6 As an example. Other examples may be related to... Figure 6 The descriptions are different.

[0233] Figure 7 This is a flowchart of a process 700 associated with an example of forming the semiconductor die described herein. In some embodiments, one or more semiconductor process tools are used to perform the process. Figure 7 One or more process blocks.

[0234] like Figure 7 As shown, process 700 may include a first portion (block 710) of an interconnect layer formed over a semiconductor device layer of a semiconductor die. As described herein, for example, one or more semiconductor process tools may be used to form a first portion of an interconnect layer (e.g., interconnect layer 114, interconnect layer 514, and / or interconnect layer 604) over a semiconductor device layer (e.g., device layer 112, device layer 512, and / or device layer 602) of a semiconductor die (e.g., semiconductor die 104, semiconductor die 504, semiconductor die in semiconductor die package 600).

[0235] like Figure 7 As further shown, process 700 may include forming a first recess (block 720) extending through a first portion of the interconnect layer and into the semiconductor device layer. As described herein, for example, one or more semiconductor process tools may be used to form the first recess (e.g., recess 302) extending through the first portion of the interconnect layer and into the semiconductor device layer.

[0236] like Figure 7As further shown, process 700 may include forming a first barrier layer (block 730) on the sidewalls of the first recess and on the bottom surface of the first recess. As described herein, for example, one or more semiconductor process tools may be used to form the first barrier layer (e.g., barrier layer 146, barrier layer 546, and / or barrier layer 626) on the sidewalls of the first recess and on the bottom surface of the first recess.

[0237] like Figure 7 As further shown, process 700 may include forming an elongated conductive structure (block 740) on a first barrier layer in a first recess that extends through a first portion of the interconnect layer and into a semiconductor device layer. As described herein, for example, one or more semiconductor process tools may be used to form elongated conductive structures (e.g., elongated conductive structure 140, elongated conductive structure 540, and / or elongated conductive structure 620) on a first barrier layer in a first recess that extends through a first portion of the interconnect layer and into a semiconductor device layer.

[0238] like Figure 7 As further shown, process 700 may include forming a second portion of the interconnect layer over a first portion of the interconnect layer and over the elongated conductive structure (block 750). As described herein, for example, one or more semiconductor process tools may be used to form the second portion of the interconnect layer over the first portion of the interconnect layer and over the elongated conductive structure.

[0239] like Figure 7 As further shown, process 700 may include forming a second recess (block 760) in a second portion of the interconnect layer. As described herein, for example, one or more semiconductor process tools may be used to form the second recess (e.g., recess 304) in the second portion of the interconnect layer. In some embodiments, the tip of an elongated conductive structure is exposed through the second recess.

[0240] like Figure 7 As further shown, process 700 may include a barrier layer (block 770) formed on the top of an elongated conductive structure in the second recess. As described herein, for example, one or more semiconductor process tools may be used to form a barrier layer (e.g., barrier layer 306) on the top of the elongated conductive structure in the second recess.

[0241] like Figure 7 As further shown, process 700 may include forming a second barrier layer (block 780) on the sidewall of the second recess in the second recess. As described herein, for example, one or more semiconductor process tools may be used to form the second barrier layer (e.g., barrier layer 142, barrier layer 542, and / or barrier layer 622) on the sidewall of the second recess in the second recess. In some embodiments, the barrier layer suppresses the growth of the second barrier layer on the tip of the elongated conductive structure.

[0242] like Figure 7 As further shown, process 700 may include forming a conductive structure (block 790) in the second recess after forming the second barrier layer. As described herein, for example, one or more semiconductor process tools may be used to form the conductive structure (e.g., conductive structure 128, conductive structure 528, and / or conductive structure 612) in the second recess after forming the second barrier layer. In some embodiments, the conductive structure rests directly on the top of the elongated conductive structure.

[0243] Process 700 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0244] In the first embodiment, the barrier layer is bonded to the top of the elongated conductive structure and not bonded to the sidewall of the second groove.

[0245] In a second embodiment alone or in combination with a first embodiment, the material of the barrier layer (e.g., material 308) includes electron donor sites covalently bonded to electron acceptor sites of the material of the elongated conductive structure.

[0246] In a single third embodiment or in combination with one or more first and second embodiments, the material of the elongated conductive structure includes copper (Cu), and the material of the barrier layer (e.g., material 308) includes at least one benzotriazole (BTA) or toluenetriazole (TTA).

[0247] In a single fourth embodiment or in combination with one or more first to third embodiments, the material precursor of the second barrier layer includes pentapenta(dimethylamino)tantalum (PDMAT), and the material of the barrier layer prevents PDMAT from being deposited on the top of the elongated conductive structure.

[0248] In a single fifth embodiment or in combination with one or more of the first to fourth embodiments, the first portion of the bottom of the second groove corresponds to the top of the elongated conductive structure, the second portion of the second groove corresponds to the dielectric layer of the interconnect layer (e.g., dielectric layer 126, dielectric layer 526 and / or dielectric layer 610), and the barrier layer is engaged with the first portion of the bottom of the second groove but not with the second portion of the bottom of the second groove.

[0249] In a single sixth embodiment or in combination with one or more of the first to fourth embodiments, process 700 includes removing the barrier layer after forming the second barrier layer and before forming the conductive structure.

[0250] although Figure 7 An example block of process 700 is shown, but in some embodiments, process 700 includes... Figure 7 The blocks described herein may be additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more blocks of process 700 may be executed in parallel.

[0251] Figure 8 This is a flowchart of a process 800, an example of a process related to the formation of the semiconductor die package described herein. In some embodiments, one or more semiconductor process tools are used to perform the process. Figure 8 One or more process blocks.

[0252] like Figure 8 As shown, process 800 may include forming an elongated conductive structure (block 810) in a semiconductor device layer extending from a first side of the semiconductor device layer to a first semiconductor die. As described herein, for example, one or more semiconductor process tools may be used to form an elongated conductive structure (e.g., elongated conductive structure 140 and / or elongated conductive structure 540) in a semiconductor device layer (e.g., device layer 112 and / or device layer 512) extending from a first side of the semiconductor device layer to a first semiconductor die (e.g., semiconductor die 104 and / or semiconductor die 504). In some embodiments, a first barrier layer (e.g., barrier layer 146 and / or barrier layer 546) is included between the semiconductor device layer and the sidewalls and bottom of the elongated conductive structure.

[0253] like Figure 8 As further shown, process 800 may include bonding a first semiconductor die and a second semiconductor die (block 820) after forming an elongated conductive structure. As described herein, for example, after forming the elongated conductive structure, one or more semiconductor process tools may be used to bond the first semiconductor die and the second semiconductor die (e.g., semiconductor die 102 and / or semiconductor die 502).

[0254] like Figure 8 As further shown, process 800 may include removing a portion of the semiconductor device layer after bonding the first semiconductor die and the second semiconductor die, such that the bottom end of the elongated conductive structure is exposed through a second side opposite the first side of the semiconductor device layer (block 830). As described herein, for example, after bonding the first semiconductor die and the second semiconductor die, one or more semiconductor process tools may be used to remove a portion of the semiconductor device layer, such that the bottom end of the elongated conductive structure is exposed through a second side opposite the first side of the semiconductor device layer.

[0255] like Figure 8As further shown, process 800 may include a first portion (block 840) of an interconnect layer formed over a second side of the semiconductor device layer and over an elongated conductive structure. As described herein, for example, one or more semiconductor process tools may be used to form the first portion of the interconnect layer (e.g., interconnect layer 132 and / or interconnect layer 532) over the second side of the semiconductor device layer and over the elongated conductive structure.

[0256] like Figure 8 As further shown, process 800 may include forming a recess (block 850) in a first portion of the interconnect layer. As described herein, for example, one or more semiconductor process tools may be used to form the recess (e.g., recess 402) in the first portion of the interconnect layer. In some embodiments, the bottom end of the elongated conductive structure is exposed through the recess.

[0257] like Figure 8 As further shown, process 800 may include a barrier layer (block 860) on the bottom end of an elongated conductive structure formed in the trench. As described herein, for example, one or more semiconductor process tools may be used to form a barrier layer (e.g., barrier layer 404) on the bottom end of an elongated conductive structure formed in the trench.

[0258] like Figure 8 As further shown, process 800 may include a second barrier layer (block 870) formed on the sidewalls of the recess in the recess. As described herein, for example, one or more semiconductor process tools may be used to form the second barrier layer (e.g., barrier layer 144 and / or barrier layer 544) on the sidewalls of the recess in the recess. In some embodiments, the barrier layer inhibits the growth of the second barrier layer on the bottom end of the elongated conductive structure.

[0259] like Figure 8 As further shown, process 800 may include forming a conductive structure (block 880) in the trench after forming the second barrier layer. As described herein, for example, after forming the second barrier layer, one or more semiconductor process tools may be used to form the conductive structure in the trench (e.g., conductive structure 136 and / or conductive structure 536). In some embodiments, the conductive structure is in direct contact with the bottom end of the elongated conductive structure.

[0260] Process 800 may include additional implementations, such as any single implementation or any combination of implementations that are combined with one or more other processes as described below and / or described elsewhere herein.

[0261] In the first embodiment, the material of the barrier layer (e.g., material 406) includes a copper corrosion inhibitor.

[0262] In a second embodiment alone or in combination with a first embodiment, forming a barrier layer includes providing a barrier layer material (e.g., material 406) to the bottom end of an elongated conductive structure in a groove and immersing the bottom end of the elongated conductive structure in the barrier layer material to form a barrier layer on the bottom end of the elongated conductive structure.

[0263] In a third embodiment alone or in combination with one or more first and second embodiments, forming a barrier layer includes providing a material of the barrier layer (e.g., material 406) to the bottom end of an elongated conductive structure in a groove, such that nitrogen lone pair electrons in the material of the barrier layer are bonded to the metallic material of the elongated conductive structure.

[0264] In a single fourth embodiment or in combination with one or more first to third embodiments, the first portion of the bottom of the groove corresponds to the bottom end of the elongated conductive structure, the second portion of the groove corresponds to a part of the semiconductor device layer, and the barrier layer is engaged with the first portion of the bottom of the groove but not with the second portion of the bottom of the groove.

[0265] In a single fifth embodiment or in combination with one or more of the first to fourth embodiments, the precursor of the material of the barrier layer that blocks the second barrier layer is absorbed by the bottom end of the elongated conductive structure.

[0266] In a single sixth embodiment or in combination with one or more of the first to fourth embodiments, process 800 includes removing the barrier layer after forming the second barrier layer and before forming the conductive structure.

[0267] although Figure 8 An example block of process 800 is shown, but in some embodiments, process 800 includes... Figure 8 The blocks described herein may be additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more blocks of process 800 may be executed in parallel.

[0268] Figures 9A to 9E This is an accompanying drawing illustrating an exemplary embodiment 900 of forming the semiconductor die described herein. In some embodiments, exemplary embodiment 900 includes an exemplary process for forming an elongated conductive structure 140 through a device layer 112 of semiconductor die 104 after bonding semiconductor die 102 and semiconductor die 104. In other words, exemplary embodiment 900 is a combination of... Figures 3A to 3M and Figures 4A to 4J Alternatives to the elongated conductive structure 140 formation technique shown and described. In some embodiments, one or more operations described in conjunction with exemplary embodiment 900 may be performed to form part of the semiconductor die package described herein, such as Figure 6The semiconductor die package 600 shown is illustrated. In some embodiments, one or more semiconductor process tools may be used to perform one or more operations described in conjunction with exemplary embodiment 900, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or another type of semiconductor process tool.

[0269] like Figure 9A As shown, one or more operations in Exemplary Embodiment 300 and / or Exemplary Embodiment 400 can be performed to form semiconductor dies 102 and semiconductor dies 104, and to bond semiconductor dies 102 and semiconductor dies 104 at bonding interface 106.

[0270] like Figure 9B As shown, a groove 902 is formed from the back side of the device layer 112 (e.g., the side opposite to the side where the interconnect layer 114 is formed) through the device layer 112 and into the interconnect layer 114 to the underlying conductive structure 128. Thus, the groove 902 for the elongated conductive structure 140 is formed after the semiconductor die 102 and the semiconductor die 104 are bonded.

[0271] like Figure 9C and Figure 9D As shown, to combine Figure 3E A similar manner as described above forms a barrier layer 146 on the sidewall of the groove 902. However, instead of forming the barrier layer 146 on the bottom surface of the groove 902, a barrier layer 904 is formed in a manner similar to... Figure 9C The groove 902 shown is formed on the bottom surface, and the barrier layer 904 inhibits the growth of the barrier layer 146 on the bottom surface of the groove 902 (e.g., on the conductive structure 128 at the bottom surface of the groove 902), such that the barrier layer 146 only grows on the bottom surface of the groove 902. Figure 9D It is formed on the sidewall of the groove 902 shown. The barrier layer 904 can be combined with... Figure 3I The described barrier layer 306 is formed in a similar manner.

[0272] like Figure 9E As shown, after the barrier layer 146 is formed, the barrier layer 904 can then be removed from the bottom surface of the groove 902. This can be combined with... Figure 3K The barrier layer 306 described herein is removed in a similar manner to the barrier layer 904.

[0273] like Figure 9E As further shown, an elongated conductive structure 140 is formed in a recess 902, such that a barrier layer 146 is located between the sidewall of the elongated conductive structure 140 and the dielectric layer 126 of the interconnect layer 114, and between the sidewall of the elongated conductive structure 140 and the device layer 112. The elongated conductive structure 140 can be combined with... Figure 3FA similar formation is described, except that the elongated conductive structure 140 is formed from the back side of the device layer 112 after the interconnect layer 114 is formed, rather than from the front side of the device layer 112 before the interconnect layer 114 is formed. The elongated conductive structure 140 extends completely through the device layer 112 and into the interconnect layer 114 to reach the conductive structure below.

[0274] Furthermore, since the barrier layer 904 prevents the barrier layer 146 from forming on the bottom surface of the groove 902 (e.g., on the surface of the underlying conductive structure 128 at the bottom of the groove 902), the elongated conductive structure 140 directly rests on the surface of the underlying conductive structure 128 at the bottom of the groove 902. Therefore, a direct copper-copper bond is formed between the elongated conductive structure 140 and the underlying conductive structure 128.

[0275] As mentioned above, Figures 9A to 9E Provided as an example. Other examples may be found in relation to [the relevant information]. Figures 9A to 9E The descriptions are different.

[0276] Figure 10 This is a flowchart of a process 1000, an example of a process related to the formation of the semiconductor die package described herein. In some embodiments, one or more semiconductor process tools are used to perform the process. Figure 10 One or more process blocks, wherein the semiconductor process tools are, for example, deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transport tools and / or another type of semiconductor process tool.

[0277] like Figure 10 As shown, process 1000 may include forming a first conductive structure (block 1010) of a semiconductor device layer extending through a first portion of an interconnect layer and into a semiconductor die. As described herein, for example, one or more semiconductor process tools may be used to form a first conductive structure (e.g., elongated conductive structure 140) of a semiconductor device layer (e.g., device layer 112) extending through a first portion of an interconnect layer (e.g., interconnect layer 114) and into a semiconductor die (e.g., semiconductor die 104).

[0278] like Figure 10 As further shown, process 1000 may include forming a second portion of the interconnect layer over a first portion of the interconnect layer and over a first conductive structure (block 1020). As described herein, for example, one or more semiconductor process tools may be used to form the second portion of the interconnect layer over the first portion of the interconnect layer and over the first conductive structure.

[0279] like Figure 10As further shown, process 1000 may include forming a recess (block 1030) in a second portion of the interconnect layer. As described herein, for example, one or more semiconductor process tools may be used to form the recess (e.g., recess 304) in the second portion of the interconnect layer. In some embodiments, the top end of the first conductive structure is exposed through the recess.

[0280] like Figure 10 As further shown, process 1000 may include a barrier layer (block 1040) formed in the recess on the top of the first conductive structure. As described herein, for example, one or more semiconductor process tools may be used to form a barrier layer (e.g., barrier layer 306) in the recess on the top of the first conductive structure.

[0281] like Figure 10 As further shown, process 1000 may include a barrier layer (block 1050) formed on the sidewall of a second recess in the recess. As described herein, for example, one or more semiconductor process tools may be used to form a barrier layer (e.g., barrier layer 142) on the sidewall of the recess in the recess.

[0282] like Figure 10 As further shown, process 1000 may include forming a second conductive structure (block 1060) in the recess. As described herein, for example, one or more semiconductor process tools may be used to form the second conductive structure in the recess (e.g., conductive structure 128).

[0283] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations in combination with one or more other processes described elsewhere herein, as described below.

[0284] In a first embodiment, the barrier layer inhibits the growth of the barrier layer on the top of the first conductive structure, and wherein the barrier layer is bonded to the top of the first conductive structure and is not bonded to the sidewall of the groove.

[0285] In a separate second embodiment or in combination with a first embodiment, the material of the barrier layer includes electron donor sites covalently bonded to electron acceptor sites of the material of the first conductive structure.

[0286] In a single third embodiment or in combination with one or more first and second embodiments, the material of the first conductive structure includes copper (Cu), and the material of the barrier layer includes at least one benzotriazole (BTA) or toluenetriazole (TTA).

[0287] In a single fourth embodiment or in combination with one or more first to third embodiments, the material precursor of the barrier layer includes pentapenta(dimethylamino)tantalum (PDMAT), and the material of the barrier layer prevents PDMAT from being deposited on top of the first conductive structure.

[0288] In a single fifth embodiment or in combination with one or more of the first to fourth embodiments, a first portion of the bottom of the groove corresponds to the top of the first conductive structure, a second portion of the groove corresponds to the dielectric layer of the interconnect layer, and a barrier layer is engaged with the first portion of the bottom of the groove but not with the second portion of the bottom of the second groove.

[0289] In a single sixth embodiment or in combination with one or more first to fifth embodiments, process 1000 includes removing the barrier layer after forming the second barrier layer and before forming the conductive structure, wherein the second conductive structure rests directly on top of the first conductive structure.

[0290] although Figure 10 An example block of process 1000 is shown, but in some embodiments, process 1000 includes... Figure 10 The blocks described herein may be additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more blocks of process 1000 may be executed in parallel.

[0291] Figure 11 This is a flowchart of a process 1100, an example of a process related to the formation of the semiconductor die package described herein. In some embodiments, one or more semiconductor process tools are used to perform the process. Figure 11 One or more process blocks, wherein the semiconductor process tools are, for example, deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or another type of semiconductor process tools.

[0292] like Figure 11 As shown, process 1100 may include forming a first conductive structure (block 1110) in a semiconductor device layer extending from a first side of the semiconductor device layer to a semiconductor die. As described herein, for example, one or more semiconductor process tools may be used to form a first conductive structure (e.g., elongated conductive structure 140) in a semiconductor device layer (e.g., device layer 112) extending from a first side (e.g., front side) of the semiconductor device layer to a semiconductor die (e.g., semiconductor die 104).

[0293] like Figure 11As further shown herein, process 1100 may include removing a portion of the semiconductor device layer such that the bottom end of the first conductive structure is exposed through a second side of the semiconductor device layer opposite to the first side (block 1120). As described herein, for example, one or more semiconductor process tools may be used to remove a portion of the semiconductor device layer such that the bottom end of the first conductive structure is exposed through a second side (e.g., the back side) of the semiconductor device layer opposite to the first side.

[0294] like Figure 11 As further shown, process 1100 may include a first portion (block 1130) of an interconnect layer formed over a second side of the semiconductor device layer and over a first conductive structure. As described herein, for example, one or more semiconductor process tools may be used to form the first portion of the interconnect layer (e.g., interconnect layer 132) over the second side of the semiconductor device layer and over the first conductive structure.

[0295] like Figure 11 As further shown, process 1100 may include forming a recess (block 1140) in a first portion of the interconnect layer. As described herein, for example, one or more semiconductor process tools may be used to form the recess (e.g., recess 402) in the first portion of the interconnect layer. In some embodiments, the bottom end of the first conductive structure is exposed through the recess.

[0296] like Figure 11 As further shown, process 1100 may include a barrier layer (block 1150) on the bottom end of the first conductive structure formed in the trench. As described herein, for example, one or more semiconductor process tools may be used to form a barrier layer (e.g., barrier layer 404) on the bottom end of the first conductive structure formed in the trench.

[0297] like Figure 11 As further shown, process 1100 may include a second barrier layer (block 1160) formed on the sidewall of the recess in the recess. As described herein, for example, one or more semiconductor process tools may be used to form the second barrier layer (e.g., barrier layer 144) on the sidewall of the recess in the recess.

[0298] like Figure 11 As further shown, process 1100 may include forming a second conductive structure (block 1170) in the recess. As described herein, for example, one or more semiconductor process tools may be used to form the second conductive structure (e.g., conductive structure 136) in the recess.

[0299] Process 1100 may include additional implementations, such as any single implementation or any combination of implementations in combination with one or more other processes described elsewhere herein, as described below.

[0300] In the first embodiment, the barrier layer is made of a copper corrosion inhibitor, and the barrier layer inhibits the growth of a barrier layer on the bottom end of the first conductive structure.

[0301] In a separate second embodiment or in combination with a first embodiment, forming the barrier layer includes providing a barrier layer material to the bottom end of a first conductive structure in a groove, and immersing the bottom end of the first conductive structure in the barrier layer material to form a barrier layer on the bottom end of the first conductive structure.

[0302] In a third embodiment alone or in combination with one or more first and second embodiments, the formation of the barrier layer includes providing a material of the barrier layer to the bottom end of a first conductive structure in a groove, such that nitrogen lone pair electrons in the material of the barrier layer bind to the metallic material of the first conductive structure.

[0303] In a single fourth embodiment or in combination with one or more of the first to third embodiments, a first portion of the bottom of the groove corresponds to the bottom end of the first conductive structure, a second portion of the groove corresponds to a part of the semiconductor device layer, and a barrier layer is engaged with the first portion of the bottom of the groove but not with the second portion of the bottom of the groove.

[0304] In a single fifth embodiment or in combination with one or more of the first to fourth embodiments, the precursor of the material of the second barrier layer that the barrier layer blocks is absorbed by the bottom end of the first conductive structure.

[0305] In a single sixth embodiment or in combination with one or more of the first to fifth embodiments, process 1100 includes removing the barrier layer after forming the second barrier layer and before forming the conductive structure, wherein the second conductive structure rests directly on the bottom of the first conductive structure.

[0306] although Figure 11 An example block of process 1100 is shown, but in some embodiments, process 1100 includes... Figure 11 The blocks described herein may be additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Alternatively, two or more blocks of process 1100 may be executed in parallel.

[0307] In this way, an elongated conductive structure is included in the device layer of the semiconductor die contained in the semiconductor die package. The elongated conductive structure is connected to a metallization layer in an interconnect layer on the opposite side of the device layer. To achieve low contact resistance between the elongated conductive structure and the metallization layer, a barrier material is used to suppress the growth of the barrier layer on the elongated conductive structure during the formation of the barrier layer for the metallization layer. This allows the metallization layer to fall directly onto the elongated conductive structure, rather than the barrier layer being between the elongated conductive structure and the metallization layer. In this way, a metal-metal connection can be achieved between the conductive structure and the metallization layer, enabling low contact resistance while forming a barrier layer to provide diffusion protection for the metallization layer. This allows for low power consumption and improved signal propagation speed in semiconductor die packages.

[0308] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor die package. This method includes forming a first portion of an interconnect layer over a semiconductor device layer of the semiconductor die. This method includes forming a first recess extending through the first portion of the interconnect layer and into the semiconductor device layer. This method includes forming a first barrier layer on the sidewalls of the first recess and on the bottom surface of the first recess. This method includes forming an elongated conductive structure extending through the first portion of the interconnect layer and into the semiconductor device layer on the first barrier layer in the first recess. This method includes forming a second portion of the interconnect layer over the first portion of the interconnect layer and over the elongated conductive structure. This method includes forming a second recess in the second portion of the interconnect layer, wherein the tip of the elongated conductive structure is exposed through the second recess. This method includes forming a barrier layer on the tip of the elongated conductive structure in the second recess. This method includes forming a second barrier layer on the sidewalls of the second recess in the second recess, wherein the barrier layer inhibits the growth of the second barrier layer on the tip of the elongated conductive structure. This method includes forming a conductive structure in the second recess after forming the second barrier layer, wherein the conductive structure rests directly on the tip of the elongated conductive structure.

[0309] In some embodiments, the barrier layer inhibits the growth of the barrier layer at the top of the first conductive structure and wherein the barrier layer is bonded to the top of the first conductive structure and is not bonded to the plurality of sidewalls of the groove.

[0310] In some embodiments, the material of the barrier layer includes multiple electron donor sites covalently bonded to multiple electron acceptor sites of the material of the first conductive structure.

[0311] In some embodiments, the material of the first conductive structure includes copper, and the material of the barrier layer includes at least one of benzotriazole or toluenetriazole.

[0312] In some embodiments, the material precursor of the barrier layer includes penta(dimethylamino)tantalum and wherein the material of the barrier layer prevents penta(dimethylamino)tantalum from being deposited on top of the first conductive structure.

[0313] In some embodiments, a first portion of the bottom of the groove corresponds to the top of the first conductive structure, wherein a second portion of the groove corresponds to the dielectric layer of the interconnect layer, and wherein a barrier layer is engaged with the first portion of the bottom of the groove but not with the second portion of the bottom of the groove.

[0314] In some embodiments, the method of forming a semiconductor die package further includes removing the barrier layer after forming the barrier layer and before forming the second conductive structure, wherein the second conductive structure rests directly on top of the first conductive structure.

[0315] As described in more detail above, some embodiments described herein provide a method for forming a semiconductor die package. This method includes forming an elongated conductive structure in a semiconductor device layer extending from a first side of a semiconductor device layer to a first semiconductor die, wherein a first barrier layer is included between the semiconductor device layer and the sidewalls and bottom end of the elongated conductive structure. This method includes bonding a first semiconductor die and a second semiconductor die after forming the elongated conductive structure. This method includes removing a portion of the semiconductor device layer after bonding the first semiconductor die and the second semiconductor die, such that the bottom end of the elongated conductive structure is exposed through a second side of the semiconductor device layer opposite the first side. This method includes forming a first portion of an interconnect layer over the second side of the semiconductor device layer and over the elongated conductive structure. This method includes forming a recess in the first portion of the interconnect layer, wherein the bottom end of the elongated conductive structure is exposed through the recess. This method includes forming a barrier layer on the bottom end of the elongated conductive structure in the recess. This method includes forming a second barrier layer on the sidewall of the recess in the recess, wherein the barrier layer inhibits the growth of the second barrier layer on the bottom end of the elongated conductive structure. This method includes forming a conductive structure in a groove after forming a second barrier layer, wherein the conductive structure is in direct contact with the bottom end of an elongated conductive structure.

[0316] In some embodiments, the barrier layer is made of a copper corrosion inhibitor and wherein the barrier layer inhibits the growth of a second barrier layer on the bottom end of the first conductive structure.

[0317] In some embodiments, forming a barrier layer includes providing a barrier layer material to the bottom end of a first conductive structure in a groove and immersing the bottom end of the first conductive structure in the barrier layer material to form a barrier layer on the bottom end of the first conductive structure.

[0318] In some embodiments, forming the barrier layer includes providing a material of the barrier layer on the bottom end of the first conductive structure in the groove, such that a plurality of nitrogen lone pairs in the material of the barrier layer are bonded to the metallic material of the first conductive structure.

[0319] In some embodiments, a first portion of the bottom of the groove corresponds to the bottom end of a first conductive structure, wherein a second portion of the groove corresponds to a portion of a semiconductor device layer, and wherein a barrier layer is engaged with the first portion of the bottom of the groove but not with the second portion of the bottom of the groove.

[0320] In some embodiments, multiple precursors of the material of the second barrier layer are absorbed by the bottom end of the first conductive structure.

[0321] In some embodiments, the method of forming a semiconductor die package further includes removing the barrier layer after forming the second barrier layer and before forming the second conductive structure, wherein the second conductive structure rests directly on the bottom end of the first conductive structure.

[0322] As described in more detail above, some embodiments described herein provide a semiconductor die package. The semiconductor die package includes a semiconductor device layer. The semiconductor die package includes one or more integrated circuit devices in the semiconductor device layer. The semiconductor die package includes a first interconnect layer perpendicularly adjacent to a first side of the semiconductor device layer. The semiconductor die package includes a second interconnect layer perpendicularly adjacent to a second side of the semiconductor device layer opposite to the first side. The semiconductor die package includes a metal pillar extending through the semiconductor device layer. The semiconductor die package includes a first metal pad in the first interconnect layer, wherein the first metal pad is in direct physical contact with a first end of the metal pillar. The semiconductor die package includes a second metal pad in the second interconnect layer, wherein the second metal pad is in direct physical contact with a second end of the metal pillar opposite the first end.

[0323] In some implementations, the cross-sectional width of the metal column decreases from the first end of the metal column to the second end of the metal column.

[0324] In some embodiments, the semiconductor die package further includes a first barrier layer between a plurality of sidewalls of the metal pillar and the semiconductor device layer and between a plurality of sidewalls of the metal pillar and the dielectric layer of the first interconnect layer, and a second barrier layer between a plurality of sidewalls of the first metal pad and the dielectric layer of the first interconnect layer.

[0325] In some embodiments, the semiconductor die package further includes a third barrier layer between the plurality of sidewalls of the second metal pad and the dielectric layer of the second interconnect layer.

[0326] In some embodiments, a portion of the second barrier layer is in direct physical contact with a first portion of the first barrier layer, and a portion of the third barrier layer is in direct physical contact with a second portion of the first barrier layer.

[0327] In some embodiments, the cross-sectional width of the first end of the metal column is greater than the cross-sectional width of the second end of the metal column.

[0328] A semiconductor die package includes a semiconductor device layer, a first interconnect layer, a second interconnect layer, metal pillars, a first metal pad, a second metal pad, and a first barrier layer. The first interconnect layer is perpendicular to a first side of the semiconductor device layer. The second interconnect layer is perpendicular to a second side of the semiconductor device layer opposite to the first side. Metal pillars extend through the semiconductor device layer, wherein the cross-sectional width of a first end of the metal pillar is greater than the cross-sectional width of the second end of the metal pillar opposite to the first end. A first metal pad is in the first interconnect layer, wherein the first metal pad is in direct physical contact with the first end of the metal pillar. A second metal pad is in the second interconnect layer, wherein the second metal pad is in direct physical contact with the second end of the metal pillar. The first barrier layer is located between a plurality of sidewalls of the metal pillar and the semiconductor device layer, and between the sidewalls of the metal pillar and the dielectric layer of the first interconnect layer.

[0329] In some embodiments, the semiconductor die package further includes a second barrier layer and a third barrier layer. The second barrier layer is located between a plurality of sidewalls of the first metal pad and the dielectric layer of the first interconnect layer. The third barrier layer is located between a plurality of sidewalls of the second metal pad and the dielectric layer of the second interconnect layer.

[0330] A semiconductor die package includes a semiconductor substrate, a first interconnect layer, a second interconnect layer, metal pillars, a first metal pad, a second metal pad, and a first barrier layer. The first interconnect layer is perpendicularly adjacent to a first side of the semiconductor substrate. The second interconnect layer is perpendicularly adjacent to a second side of the semiconductor substrate opposite to the first side. Metal pillars extend through the semiconductor substrate. The first metal pad is in the first interconnect layer, wherein the first metal pad is in direct physical contact with a first end of the metal pillar. The second metal pad is in the second interconnect layer, wherein the second metal pad is in direct physical contact with a second end of the metal pillar opposite to the first end. The first barrier layer is located between a plurality of sidewalls of the first metal pad and a dielectric layer of the first interconnect layer.

[0331] In some embodiments, the semiconductor die package further includes a second barrier layer and a third barrier layer. The second barrier layer is located between the plurality of sidewalls of the metal pillar and the semiconductor substrate, and between the sidewalls of the metal pillar and the dielectric layer of the first interconnect layer. The third barrier layer is located between the plurality of sidewalls of the second metal pad and the dielectric layer of the second interconnect layer.

[0332] In some embodiments, the metal pillar has a cross-sectional width at the interface between the metal pillar and the first metal pad, corresponding to the metal pillar, the dimension being in the range of 10 nanometers to 100 nanometers.

[0333] In some embodiments, the metal column has a dimension at the interface between the metal column and the second metal pad that corresponds to the cross-sectional width of the metal column, and the dimension is in the range of 10 nanometers to 100 nanometers.

[0334] In some implementations, the vertical length of the metal column ranges from 50 nanometers to 150 nanometers.

[0335] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., values ​​of ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not intended to be limiting. It should be understood that, as per this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0336] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor die package, comprising: include: A semiconductor device layer; One or more integrated circuit devices are located in the semiconductor device layer; A first interconnect layer, perpendicularly adjacent to a first side of the semiconductor device layer; A second interconnect layer is perpendicularly adjacent to a second side of the semiconductor device layer opposite to the first side; A metal pillar extends through the semiconductor device layer; A first metal pad, in the first interconnect layer, The first metal pad is in direct physical contact with a first end of the metal pillar; and A second metal pad, in the second interconnect layer, The second metal pad is in direct physical contact with the metal post and the second end opposite to the first end.

2. The semiconductor die packaging as described in claim 1, characterized in that, Also includes: A first barrier layer is provided between the plurality of sidewalls of the metal pillar and the semiconductor device layer, and between the plurality of sidewalls of the metal pillar and a dielectric layer of the first interconnect layer. as well as A second barrier layer is located between the plurality of sidewalls of the first metal pad and the dielectric layer of the first interconnect layer.

3. The semiconductor die packaging as described in claim 1 or 2, characterized in that, Also includes: A third barrier layer is located between the plurality of sidewalls of the second metal pad and a dielectric layer of the second interconnect layer.

4. A semiconductor die package, characterized in that, include: A semiconductor device layer; A first interconnect layer, perpendicularly adjacent to a first side of the semiconductor device layer; A second interconnect layer is perpendicularly adjacent to a second side of the semiconductor device layer opposite to the first side; A metal pillar extends through the semiconductor device layer, wherein a cross-sectional width at a first end of the metal pillar is greater than a cross-sectional width at a second end of the metal pillar opposite to the first end; A first metal pad, in the first interconnect layer, The first metal pad is in direct physical contact with the first end of the metal column; A second metal pad, in the second interconnect layer, The second metal pad is in direct physical contact with the second end of the metal pillar; and A first barrier layer is provided between the plurality of sidewalls of the metal pillar and the semiconductor device layer, and between the plurality of sidewalls of the metal pillar and a dielectric layer of the first interconnect layer.

5. The semiconductor die packaging as described in claim 4, characterized in that, Also includes: A second barrier layer is located between the plurality of sidewalls of the first metal pad and the dielectric layer of the first interconnect layer; as well as A third barrier layer is located between the plurality of sidewalls of the second metal pad and a dielectric layer of the second interconnect layer.

6. A semiconductor die package, characterized in that, include: A semiconductor substrate; A first interconnect layer is perpendicularly adjacent to a first side of the semiconductor substrate; A second interconnect layer is perpendicularly adjacent to a second side of the semiconductor substrate opposite to the first side; A metal pillar extends through the semiconductor substrate; A first metal pad, in the first interconnect layer, The first metal pad is in direct physical contact with a first end of the metal column; A second metal pad, in the second interconnect layer, The second metal pad is in direct physical contact with the metal post and a second end opposite to the first end; and A first barrier layer is located between a plurality of sidewalls of the first metal pad and a dielectric layer of the first interconnect layer.

7. The semiconductor die package as described in claim 6, characterized in that, Also includes: A second barrier layer is provided between the plurality of sidewalls of the metal pillar and the semiconductor substrate, and between the plurality of sidewalls of the metal pillar and the dielectric layer of the first interconnect layer. as well as A third barrier layer is located between the plurality of sidewalls of the second metal pad and a dielectric layer of the second interconnect layer.

8. The semiconductor die package as described in claim 6 or 7, characterized in that, The metal pillar has a dimension of a cross-sectional width corresponding to the metal pillar at an interface between the metal pillar and the first metal pad, the dimension being in the range of 10 nanometers to 100 nanometers.

9. The semiconductor die package as described in claim 6 or 7, characterized in that, The metal pillar has a dimension at an interface between the metal pillar and the second metal pad that corresponds to a cross-sectional width of the metal pillar, the dimension being in the range of 10 nanometers to 100 nanometers.

10. The semiconductor die package as described in claim 6 or 7, characterized in that, The vertical length of the metal column ranges from 50 nanometers to 150 nanometers.

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