Electronic parking system controller and vehicle

Abstract

The utility model provides an electronic parking system controller and a vehicle, and relates to the technical field of automobiles. The electronic parking system controller comprises a main control chip, a first gate driving chip, a second gate driving chip, a left caliper driving circuit and a right caliper driving circuit, the first end of the first gate driving chip is connected with the main control chip, and the second end is connected with the left caliper driving circuit; the first end of the second gate driving chip is connected with the main control chip, and the second end of the second gate driving chip is connected with the right caliper driving circuit; the left caliper driving circuit is used for driving the left caliper motor, and the right caliper driving circuit is used for driving the right caliper motor; wherein the parameters of the first gate driving chip and the second gate driving chip are different. According to the invention, the two gate driving chips are used for driving respectively, so that the other chip can work normally when one chip fails. And the parameters of the two chips are different, so that the probability that the two chips fail at the same time is further reduced, and the safety and reliability of the vehicle are improved.

Description

Technical Field

[0001] This application relates to the field of automotive technology, and more particularly to an electronic parking system controller and vehicle. Background Technology

[0002] The Electronic Parking Brake (EPB) system uses an electronic controller and a motor actuator to achieve the parking braking function. It replaces the traditional mechanical handbrake, allowing the driver to activate the parking brake simply by pressing the parking button in the cockpit, eliminating the need to pull a lever to tighten the steel cable as with a traditional mechanical handbrake.

[0003] In the prior art, reference Figure 1 The EPB controller typically uses a gate driver chip to control the left and right caliper drive circuits, driving the left and right caliper motors in both directions. This allows the calipers to clamp or release the wheels, achieving parking brake operation or disengaging the parking brake. When the gate driver chip fails, both motors lose control, the EPB fails, and the vehicle's safety and reliability are severely compromised. Utility Model Content

[0004] This application provides an electronic parking system controller and a vehicle, aiming to avoid the problem of electronic parking system failure caused by gate driver chip failure, which affects vehicle safety and reliability.

[0005] In a first aspect, embodiments of this application provide an electronic parking system controller, including: a main control chip, a first gate drive chip, a second gate drive chip, a left caliper drive circuit, and a right caliper drive circuit;

[0006] The first end of the first gate driver chip is connected to the main control chip, and the second end of the first gate driver chip is connected to the left caliper drive circuit.

[0007] The first end of the second gate driver chip is connected to the main control chip, and the second end of the second gate driver chip is connected to the right caliper drive circuit.

[0008] The left caliper drive circuit is used to drive the left caliper motor, and the right caliper drive circuit is used to drive the right caliper motor.

[0009] The parameters of the first gate driver chip and the second gate driver chip are different.

[0010] The solution shown in this application embodiment, compared with the prior art, uses two different gate drive chips to drive the left caliper drive circuit and the right caliper drive circuit respectively. When one of the chips fails and causes the motor to become uncontrollable, the other motor can still work normally. Moreover, the parameters of the two chips are different, and the probability of the two motors failing at the same time is very low, which effectively improves the safety and reliability of the vehicle.

[0011] In some embodiments, the first gate driver chip and the second gate driver chip are manufactured by different manufacturers.

[0012] In the above technical solution, the two gate driver chips come from different manufacturers. Compared with chips from the same manufacturer, the differences between the chips are greater, and the probability of failure is lower.

[0013] In some embodiments, the first gate driver chip and the second gate driver chip are of different models.

[0014] In the above technical solution, the two gate driver chips are of different models, with significant differences between the chips, and the probability of failure is lower.

[0015] In some embodiments, the electronic parking system controller further includes: a first redundant power supply module and a second redundant power supply module;

[0016] The first redundant power supply module includes two different input power supplies for powering the first gate driver chip;

[0017] The second redundant power supply module includes two different input power supplies for powering the second gate driver chip.

[0018] In the above technical solution, redundant power supplies are set for the two gate driver chips, which are powered by two different external power supplies, thus providing redundancy for each other and improving the stability and reliability of the power supply.

[0019] In some embodiments, the first gate driver chip includes a battery power supply terminal and a 3.3V power supply terminal; the first redundant power supply module includes a battery power supply unit and a 3.3V power supply unit;

[0020] The first input terminal of the battery power supply unit is connected to the first battery module, the second input terminal of the battery power supply unit is connected to the second battery module, and the output terminal of the battery power supply unit is connected to the battery power supply terminal of the first gate driver chip.

[0021] The first input terminal of the 3.3V power supply unit is connected to the first DC power supply, the second input terminal of the 3.3V power supply unit is connected to the second DC power supply, and the output terminal of the 3.3V power supply unit is connected to the 3.3V power supply terminal of the first gate driver chip.

[0022] In the above embodiments, since the first gate driver chip includes two power supply terminals, redundant power supply is provided for both power supply terminals, which improves the stability and reliability of the power supply.

[0023] In some embodiments, the electronic parking system controller further includes: a third redundant power supply module and a fourth redundant power supply module;

[0024] The third redundant power supply module includes two different input power supplies for powering the left caliper drive circuit;

[0025] The fourth redundant power supply module includes two different input power supplies for powering the right caliper drive circuit.

[0026] In the above embodiments, redundant power supplies are also provided for the left caliper drive circuit and the right caliper drive circuit respectively, so as to improve the reliability and stability of the power supply.

[0027] In some embodiments, both the left caliper drive circuit and the right caliper drive circuit are H-bridge drive circuits.

[0028] In some embodiments, the first terminal of the first gate driver chip includes: a first communication interface, a reset terminal, a wake-up terminal, a synchronization terminal, a first protection shutdown terminal, and a second protection shutdown terminal;

[0029] The first communication interface is used to communicate with the main control chip;

[0030] The reset terminal is used to receive the reset signal sent by the main control chip;

[0031] The wake-up terminal is used to receive the wake-up signal sent by the main control chip;

[0032] The synchronization terminal is used to receive the synchronization signal sent by the main control chip;

[0033] The first protection shutdown terminal and the second protection shutdown terminal are respectively used to receive the first shutdown signal and the second shutdown signal sent by the main control chip; wherein, the first shutdown signal is used to indicate the shutdown of the lower transistor of the left bridge arm of the H-bridge drive circuit, and the second shutdown signal is used to indicate the shutdown of the lower transistor of the right bridge arm of the H-bridge drive circuit.

[0034] The first gate driver chip also includes an EPB switch hardwire terminal, used to receive the switch hardwire signal sent by the host computer.

[0035] In some embodiments, the first terminal of the second gate driver chip includes: a second communication interface, a sleep terminal, a drive shutdown terminal, and a fault output terminal;

[0036] The second communication interface is used to communicate with the main control chip;

[0037] The sleep terminal is used to receive the sleep signal sent by the main control chip;

[0038] The drive shutdown terminal is used to receive the third shutdown signal sent by the main control chip; wherein, the third shutdown signal is used to indicate the shutdown of the lower transistor of the left bridge arm and the lower transistor of the right bridge arm of the H-bridge drive circuit.

[0039] The fault output terminal is used to send a fault signal to the main control chip.

[0040] In the above embodiments, the first gate driver chip and the second gate driver chip are configured with different functions, and the same function is implemented in different ways, which reduces the probability of diagnostic failure.

[0041] Secondly, embodiments of this application also provide a vehicle, including the electronic parking system controller provided in the first aspect embodiment above.

[0042] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of EPB in the prior art;

[0046] Figure 2 This is a schematic diagram of the current path of an H-bridge drive circuit provided in an embodiment of this application;

[0047] Figure 3 This is a schematic diagram of the current path of an H-bridge drive circuit provided in another embodiment of this application;

[0048] Figure 4 This is a schematic diagram of the structure of an electronic parking system controller provided in one embodiment of this application;

[0049] Figure 5 This is a schematic diagram of the structure of an electronic parking system controller provided in another embodiment of this application;

[0050] Figure 6 This is a first gate driver chip and peripheral circuit diagram provided in an embodiment of this application;

[0051] Figure 7This is a diagram of a second gate driver chip and its peripheral circuitry provided in one embodiment of this application;

[0052] Figure 8 This is a verification flowchart provided in one embodiment of this application. Detailed Implementation

[0053] The present application will be described more clearly below with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the technical solutions of the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0054] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0055] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0056] In the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0057] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0058] Furthermore, the term "multiple" mentioned in the embodiments of this application should be interpreted as two or more.

[0059] With the advancement of automotive intelligence, more and more electronic control technologies are being applied to vehicles. The Electronic Parking Brake (EPB) system is one such example. It replaces the traditional mechanical handbrake, allowing the driver to simply press the parking button in the cockpit to activate the parking brake function via controllers and actuators, eliminating the need to pull a lever to tighten a steel cable for parking, as with a traditional mechanical handbrake.

[0060] The EPB controller analyzes and processes information from the vehicle network or directly from vehicle buttons, and controls the left and right caliper motors through the drive circuit to control the clamping and releasing of the left and right brake calipers, thereby achieving parking brake or releasing the parking brake.

[0061] Reliability is a crucial concept in automotive electronics design for measuring product quality. A reliable product means that it can reliably perform its intended functions under specified conditions and within a defined lifespan. Reliability design work during the product design phase involves measuring system reliability using methods such as failure rate prediction, failure mode analysis, and fault tree analysis. This allows for improvements during the design phase, ensuring stable performance throughout the product's lifecycle and preventing injuries to personnel and vehicles, as well as excessive maintenance costs, resulting from product failure.

[0062] As part of the braking system, the EPB (Electronic Safety Integrity Level) has the highest functional safety rating in the entire vehicle, ASIL D (Automotive Safety Integrity Level). This means that the risk to occupants is most severe if this function fails. For the EPB, not only must the design process comply with functional safety regulations, but the design quality must also achieve a lower failure rate and higher reliability.

[0063] In the prior art, reference Figure 1 Typically, a single gate driver chip (e.g., ASIL D certified) and peripheral low-power MOS transistors are used. For example, the left and right caliper motors are DC brushed motors, and two H-bridge driver circuits composed of eight MOS transistors (Q1 to Q8) are used to drive the two motors in forward and reverse directions respectively.

[0064] refer to Figure 2 and Figure 3 Q1, Q2, Q3, and Q4 form an H-bridge; Q1 and Q4 are on, Q2 and Q3 are off, and the current direction is as follows: Figure 2 When the motor rotates clockwise, the clamps tighten; Q2 and Q3 are turned on, while Q1 and Q4 are turned off, and the current direction is as follows. Figure 3The motor rotates counterclockwise, releasing the caliper. The other H-bridge works similarly. Eight MOSFETs are controlled by a gate driver chip, and the MOSFETs control the current flow. Only a high level needs to be applied to the gate. Each MOSFET has three pins: source, gate, and drain. When the gate level is high, the drain and source are connected; when the gate level is low, the drain and source are disconnected. Here, "high level" is relative to the source. When Vg – Vs > Vgsth, and the difference between the gate and source voltages exceeds the turn-on threshold, the MOSFET turns on.

[0065] When the gate driver chip fails, both the left and right motors will lose control, the entire EPB will fail, and the safety and reliability of the vehicle will be seriously affected.

[0066] Based on the above issues, refer to Figure 4 This application provides an electronic parking system controller, including: a main control chip 1, a first gate drive chip 2, a second gate drive chip 3, a left caliper drive circuit 4, and a right caliper drive circuit 5;

[0067] The first end of the first gate driver chip 2 is connected to the main control chip 1, and the second end of the first gate driver chip 2 is connected to the left caliper drive circuit 4.

[0068] The first end of the second gate driver chip 3 is connected to the main control chip 1, and the second end of the second gate driver chip 3 is connected to the right caliper drive circuit 5.

[0069] Left caliper drive circuit 4 is used to drive the left caliper motor, and right caliper drive circuit 5 is used to drive the right caliper motor.

[0070] The parameters of the first gate driver chip 2 and the second gate driver chip 3 are different.

[0071] Chip failure is an "inevitable result" under the laws of physics, and it cannot be avoided in practical applications; it can only be reduced, not eliminated. Based on the above issues, this application splits the drive chip into two, which drive the left caliper drive circuit 4 and the right caliper drive circuit 5 respectively. When one chip fails, the other chip can still work normally, and the motor it drives can still brake normally, thus maintaining the braking force on one wheel. The EPB will not completely fail.

[0072] Furthermore, chip failure is not only related to its quality coefficient, but also to factors such as wafer size, wafer temperature coefficient, packaging type, packaging environment, and chip production time. Specifically, the chip failure rate can be expressed as λ. IC (The unit is parts per million per hour).

[0073] λ IC =(π) T ·C1+πE ·C2)·π Q ·π L

[0074] Where C1 is the chip wafer size (related to its doping type and gate count); C2 is the chip packaging form; π T π is the temperature coefficient; E This refers to the environmental factor (different chips have different environmental factors under the same environment); π Q This is the chip's quality coefficient (related to the chip's grade); π L This refers to the time when the chip goes into production.

[0075] As can be seen from the above formulas, two chips with the same parameters, under the same design scheme, the same production line process, the same environment, and the same fault impact, will have an increased probability of simultaneous failure. Therefore, the different parameters of the two gate driver chips (first gate driver chip 2 and second gate driver chip 3) in this application can effectively reduce the probability of simultaneous failure of the two gate driver chips, that is, reduce the probability of EPB failure, and greatly improve the safety and reliability of the vehicle.

[0076] For example: Suppose that the failure probability of the gate driver chip is 1%.

[0077] With existing technology, a single gate driver chip is used. If the gate driver chip fails, it will directly cause the EPB to fail. Therefore, the probability of the EPB being normal is 1-1%=99%.

[0078] In this application, the EPB will only fail if both gate driver chips fail simultaneously. The probability of both chips failing simultaneously is 1% * 1% = 0.01%, therefore the probability of the EPB functioning normally is 1 - 0.01% = 99.99%. Thus, using two gate driver chips significantly reduces the failure probability of the EPB.

[0079] Meanwhile, it is assumed that the first gate driver chip 2 fails under condition 1, the second gate driver chip 3 fails under condition 2, and condition 1 ≠ condition 2, and the severity is assumed to be: condition 2 ≥ condition 1.

[0080] If the parameters of the two gate driver chips are the same, the probability of both gate driver chips failing simultaneously under condition 1 is very high; if the parameters of the two gate driver chips are different, the risk points can be staggered, reducing the risk of simultaneous failure and reducing the failure probability of EPB.

[0081] In one possible implementation, the first gate driver chip 2 and the second gate driver chip 3 are manufactured by different manufacturers.

[0082] Different manufacturers have differences in their technical approaches, equipment, processes, quality control systems, raw material supply, and quality management. As a result, the parameters of the two gate driver chips will be significantly different. This difference makes it unlikely that the two chips will fail simultaneously due to the same problem, thus ensuring the continuous and stable operation of the EPB.

[0083] In one possible implementation, the first gate driver chip 2 and the second gate driver chip 3 are of different models.

[0084] Different models of chips are often optimized for specific application scenarios. This functional differentiation allows the two chips to perform different tasks in the system. Even when faced with various complex operating conditions, they generally will not fail simultaneously due to their inability to withstand the pressure of the operating conditions, because of their respective design advantages and applicable scenarios.

[0085] At the performance parameter level, there are significant differences in the core indicators of different chip models. These differences in core indicators mean that when faced with various operating conditions, the chips will exhibit different anti-interference capabilities and fault tolerance capabilities due to their different parameter characteristics, making it unlikely that they will fail simultaneously.

[0086] From the perspective of failure mechanism analysis, the differences in internal structure, manufacturing process, and material selection among different chip models determine the diversity of their failure modes. Furthermore, the core semiconductor materials and circuit architecture design of different chip models also lead to different failure triggers. This difference in failure mechanisms makes it unlikely that two chips will fail simultaneously due to the same environmental factors or system malfunctions.

[0087] In real-world applications, EPB systems face various complex operating conditions. Different gate driver chips, due to differences in their functional characteristics, performance parameters, and failure mechanisms, can form a complementary fault protection system. The two chips serve as redundant backups for each other, further reducing the probability of simultaneous failure and ensuring the continuous and stable operation of the EPB.

[0088] For example, the first gate driver chip 2 can be of model number L9369S, and the second gate driver chip 3 can be of model number DRV8705.

[0089] As the foundation of system operation, the power supply will also cause the EPB to fail if it fails, affecting the safety and reliability of the vehicle.

[0090] Based on this, in one possible implementation, refer to Figure 5 The electronic parking system controller may also include: a first redundant power supply module 6 and a second redundant power supply module 7;

[0091] The first redundant power supply module 6 includes two different input power supplies for powering the first gate driver chip 2.

[0092] The second redundant power supply module 7 includes two different input power supplies for powering the second gate driver chip 3.

[0093] In this application, redundant power supply modules are set for two gate driver chips, which include two power supplies. When one power supply fails, the corresponding gate driver chip loses its main power supply, but the other power supply is normal, which can ensure that the corresponding gate driver chip works normally and improve the fault tolerance capability of the EPB system.

[0094] The redundant power supply and the redundant design of the two gate driver chips provide dual protection, further improving the reliability of the EPB.

[0095] Furthermore, gate driver chips typically include two power supply terminals, and redundant power supplies can be configured for each of the two power supply terminals.

[0096] In one possible implementation, refer to Figure 6 The first gate driver chip 2 may include a battery power supply terminal and a 3.3V power supply terminal; the first redundant power supply module 6 includes a battery power supply unit 61 and a 3.3V power supply unit 62.

[0097] The first input terminal (Vbat) of the battery power supply unit 61 is connected to the first battery module, the second input terminal (Vbat1) of the battery power supply unit 61 is connected to the second battery module, and the output terminal of the battery power supply unit 61 is connected to the battery power supply terminal of the first gate driver chip 2.

[0098] The first input terminal (3V3) of the 3.3V power supply unit 62 is connected to the first DC power supply, the second input terminal (S3.3V) of the 3.3V power supply unit 62 is connected to the second DC power supply, and the output terminal of the 3.3V power supply unit 62 is connected to the 3.3V power supply terminal of the first gate driver chip 2.

[0099] In the above embodiments, since the first gate driver chip 2 includes two power supply terminals, redundant power supply is provided for both power supply terminals, which improves the stability and reliability of the power supply.

[0100] In one possible implementation, the circuitry of the battery power supply unit 61 and the 3.3V power supply unit 62 can be referenced. Figure 6 The specifics will not be elaborated here.

[0101] refer to Figure 7 The second gate driver chip 3 also includes two power supply terminals, both of which are equipped with redundant power supplies. For specific circuit details, please refer to [reference needed]. Figure 7 This will not be elaborated upon here.

[0102] In one possible implementation, refer to Figure 5The electronic parking system controller may also include: a third redundant power supply module 8 and a fourth redundant power supply module 9;

[0103] The third redundant power supply module 8 includes two different input power supplies for powering the left caliper drive circuit 4;

[0104] The fourth redundant power supply module 9 includes two different input power supplies for powering the right caliper drive circuit 5.

[0105] In the above embodiments, redundant power supplies are also provided for the left caliper drive circuit 4 and the right caliper drive circuit 5 to improve the reliability and stability of the power supply.

[0106] In one possible implementation, refer to Figure 4 and Figure 5 Both the left caliper drive circuit 4 and the right caliper drive circuit 5 are H-bridge drive circuits.

[0107] In this application, both left and right calipers use H-bridge drive circuits, and the specific circuits are the same as those in the application. Figure 2 and Figure 3 The specifics will not be elaborated here.

[0108] Based on the above embodiments, the first gate driver chip 2 and the second gate driver chip 3 have different models, and their pins and functions will also be slightly different. Therefore, different functions can be set according to the specific model of the gate driver chip, and the implementation methods can also be different for the same function.

[0109] In one possible implementation, refer to Figure 6 The first terminal of the first gate driver chip 2 includes: a first communication interface, a reset terminal, a wake-up terminal, a synchronization terminal, a first protection shutdown terminal, and a second protection shutdown terminal;

[0110] The first communication interface is used to communicate with the main control chip 1;

[0111] The reset terminal is used to receive the reset signal sent by the main control chip 1;

[0112] The wake-up terminal is used to receive the wake-up signal sent by the main control chip 1;

[0113] The synchronization terminal is used to receive the synchronization signal sent by the main control chip 1;

[0114] The first protection shutdown terminal and the second protection shutdown terminal are respectively used to receive the first shutdown signal and the second shutdown signal sent by the main control chip 1; wherein, the first shutdown signal is used to indicate the shutdown of the lower transistor of the left bridge arm of the H-bridge drive circuit, and the second shutdown signal is used to indicate the shutdown of the lower transistor of the right bridge arm of the H-bridge drive circuit.

[0115] The first gate driver chip 2 also includes an EPB switch hardwire terminal, used to receive the switch hardwire signal sent by the host computer.

[0116] For example, refer to Figure 6 The first gate driver chip 2 is model L9369S. It can directly connect pins 40 to 43 (EPB switch hard-wire terminal) to the switch hard-wire signal of EPB, and the first gate driver chip 2 can confirm the on / off state of EPB.

[0117] Pins 61 to 64 of the chip (first communication interface) are connected to the main control chip 1 for communication. The main control chip 1 and the first gate driver chip 2 exchange control commands, diagnostic commands, and chip operating status through the first communication interface; for example, it can be SPI communication.

[0118] To reduce energy consumption, the first gate driver chip 2 will enter sleep mode when it is not working to reduce its current consumption, and will be woken up when it needs to work. Pin 48 (wake-up terminal) receives the wake-up signal sent by the main control chip 1; when pin 48 is low, the chip enters sleep mode.

[0119] Pin 47 (reset terminal) of the chip is used to receive the reset signal sent by the main control chip 1. When an abnormal state is detected, the main control chip 1 will trigger a reset command and send a reset signal to the first gate driver chip 2 to indicate that the corresponding drive circuit should be reset.

[0120] Pins 59 and 60 (synchronization terminals) of the chip are connected to the main control chip 1 to receive the synchronization signal sent by the main control chip 1, which is used for the ADC voltage / current measurement path.

[0121] Pins 30 and 32 of the chip (first protection shutdown pin and second protection shutdown pin) are used to receive the first shutdown signal and the second shutdown signal sent by the main control chip 1, serving as a hardware shutdown path to prevent the chip from issuing unexpected start commands, or to shut down the motor through this path when the software interface control fails.

[0122] Also, see reference Figure 6 The chip's pins 12, 13, 29, 33, 34, 35, 36, and 37 can also have four pins for controlling four MOSFETs. These four pins are used to monitor the source and drain voltages of the MOSFETs, ensuring that the operating status of the MOSFETs can be monitored while they are working, and that abnormal signals can be dealt with in a timely manner.

[0123] Pins 27, 28, 38, and 39 of the chip form two sets of current samples, one for the high-end and one for the low-end of the corresponding motor, thus creating a closed-loop control.

[0124] The chip may also include functions such as external lighting control, which will not be elaborated here.

[0125] In one possible implementation, refer to Figure 7 The first terminal of the second gate driver chip 3 may include: a second communication interface, a sleep terminal, a drive shutdown terminal, and a fault output terminal;

[0126] The second communication interface is used to communicate with the main control chip 1;

[0127] The sleep terminal is used to receive the sleep signal sent by the main control chip 1;

[0128] The drive shutdown terminal is used to receive the third shutdown signal sent by the main control chip 1; wherein, the third shutdown signal is used to indicate the shutdown of the lower transistor of the left bridge arm and the lower transistor of the right bridge arm of the H-bridge drive circuit.

[0129] The fault output terminal is used to send a fault signal to the main control chip 1.

[0130] For example, refer to Figure 7 The second gate driver chip 3 is model DRV8705, and unlike the first gate driver chip 2, it does not have an EPB switch hard-wired terminal.

[0131] Pins 3 to 6 of the chip (second communication interface) are connected to the main control chip 1 for communication. SPI communication can also be used.

[0132] Pin 7 (sleep pin) of the chip is used to receive the sleep signal sent by the main control chip 1. Setting it to a logic low level can turn off the device and enter sleep mode. It has an internal pull-down resistor.

[0133] Pin 13 (fault output terminal) of the chip sends a fault signal to the main control chip 1. Pulling this pin to a logic low level can indicate the fault condition. It is an open-drain output and requires an external pull-up resistor.

[0134] Pin 12 (drive shutdown terminal) of the chip receives the third shutdown signal sent by the main control chip 1. Unlike L9369S, only one signal can shut down two low-side MOS transistors. Setting it to logic high level can pull down the output of the high-side and low-side gate drivers. Internal pull-down resistors are used.

[0135] Additionally, pins 18 and 19 of the chip are used to monitor the low-end current of the sampling motor.

[0136] In the above embodiments, the first gate driver chip 2 and the second gate driver chip 3 are configured with different functions, and the same function is implemented in different ways, which reduces the probability of diagnostic failure.

[0137] Based on the above, this application employs two gate driver chips to reduce the probability of simultaneous failure. Furthermore, their functions and implementation methods differ. When the main control chip 1 receives voltage, current, over-temperature, and short-circuit signals from the first gate driver chip 2, it compares and verifies these signals with those from the second gate driver chip 3. When one of the gate driver chips shows a tendency to malfunction, the difference between the two signals gradually increases, allowing for earlier anomaly identification. Moreover, because the two gate driver chips use different detection methods, detecting the same error using two different methods reduces the probability of diagnostic failure. For a detailed comparison and verification process, please refer to [reference needed]. Figure 8 The specifics will not be elaborated here (among which, motor 1 is the right caliper motor and motor 2 is the left caliper motor).

[0138] Secondly, this application also provides a vehicle that includes the electronic parking system controller provided in the first aspect embodiment above, and has the advantages of any of the above electronic parking system controllers, which will not be elaborated here.

[0139] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An electronic parking system controller, characterized by include: Main control chip, first gate driver chip, second gate driver chip, left caliper driver circuit and right caliper driver circuit; The first end of the first gate driver chip is connected to the main control chip, and the second end of the first gate driver chip is connected to the left caliper drive circuit. The first end of the second gate driver chip is connected to the main control chip, and the second end of the second gate driver chip is connected to the right caliper drive circuit. The left caliper drive circuit is used to drive the left caliper motor, and the right caliper drive circuit is used to drive the right caliper motor. The parameters of the first gate driver chip and the second gate driver chip are different.

2. The electronic parking system controller of claim 1, wherein, The first gate driver chip and the second gate driver chip are manufactured by different manufacturers.

3. The electronic parking system controller of claim 2, wherein, The first gate driver chip and the second gate driver chip have different models.

4. The electronic parking system controller according to any one of claims 1 to 3, characterized in that The electronic parking system controller also includes: a first redundant power supply module and a second redundant power supply module; The first redundant power supply module includes two different input power supplies for powering the first gate driver chip; The second redundant power supply module includes two different input power supplies for powering the second gate driver chip.

5. The electronic parking system controller of claim 4, wherein, The first gate driver chip includes a battery power supply terminal and a 3.3V power supply terminal; the first redundant power supply module includes a battery power supply unit and a 3.3V power supply unit. The first input terminal of the battery power supply unit is connected to the first battery module, the second input terminal of the battery power supply unit is connected to the second battery module, and the output terminal of the battery power supply unit is connected to the battery power supply terminal of the first gate driver chip. The first input terminal of the 3.3V power supply unit is connected to the first DC power supply, the second input terminal of the 3.3V power supply unit is connected to the second DC power supply, and the output terminal of the 3.3V power supply unit is connected to the 3.3V power supply terminal of the first gate driver chip.

6. The electronic parking system controller according to any one of claims 1 to 3, characterized in that The electronic parking system controller also includes: a third redundant power supply module and a fourth redundant power supply module; The third redundant power supply module includes two different input power supplies for powering the left caliper drive circuit; The fourth redundant power supply module includes two different input power supplies for powering the right caliper drive circuit.

7. The electronic parking system controller according to any one of claims 1 to 3, characterized in that Both the left caliper drive circuit and the right caliper drive circuit are H-bridge drive circuits.

8. The electronic parking system controller of claim 7, wherein, The first terminal of the first gate driver chip includes: a first communication interface, a reset terminal, a wake-up terminal, a synchronization terminal, a first protection shutdown terminal, and a second protection shutdown terminal; The first communication interface is used to communicate with the main control chip; The reset terminal is used to receive the reset signal sent by the main control chip; The wake-up terminal is used to receive the wake-up signal sent by the main control chip; The synchronization terminal is used to receive the synchronization signal sent by the main control chip; The first protection shutdown terminal and the second protection shutdown terminal are respectively used to receive the first shutdown signal and the second shutdown signal sent by the main control chip; wherein, the first shutdown signal is used to indicate the shutdown of the lower transistor of the left bridge arm of the H-bridge drive circuit, and the second shutdown signal is used to indicate the shutdown of the lower transistor of the right bridge arm of the H-bridge drive circuit. The first gate driver chip also includes an electronic parking brake system switch hardwire terminal for receiving switch hardwire signals sent by the host computer.

9. The electronic parking system controller of claim 7, wherein, The first terminal of the second gate driver chip includes: a second communication interface, a sleep terminal, a drive shutdown terminal, and a fault output terminal; The second communication interface is used to communicate with the main control chip; The sleep terminal is used to receive the sleep signal sent by the main control chip; The drive shutdown terminal is used to receive a third shutdown signal sent by the main control chip; wherein, the third shutdown signal is used to indicate the shutdown of the lower transistor of the left bridge arm and the lower transistor of the right bridge arm of the H-bridge drive circuit. The fault output terminal is used to send a fault signal to the main control chip.

10. A vehicle characterized by comprising: Includes the electronic parking system controller as described in any one of claims 1 to 9.

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