Bimodal intelligent management and self-protection circuit of battery power supply system

Abstract

The utility model belongs to the technical field of power supply protection, and particularly relates to a bimodal intelligent management and self-protection circuit of a battery power supply system, which comprises a driving module and a detection module, the driving module comprises an NAND gate I0, the output end of the NAND gate I0 is connected with the input end of a phase inverter I1, and the output end of the phase inverter I1 is connected with the output end of the phase inverter I2. The output end of the phase inverter I1 is connected with the grid electrode of a switch transistor M0 and the grid electrode of a switch transistor M1, the drain electrode of the switch transistor M0 is connected to the anode of a diode D0, the drain electrode of a transistor M2 and the grid electrode of an output driving transistor M4 through a resistor R1, and the grid electrode of the output driving transistor M4 is connected with a resistor R3 and a compensation capacitor C0 in series. According to the utility model, a feedback branch composed of a divider resistor R4, a voltage stabilizing diode D1 and a transistor M6 and zero compensation formed by connecting a resistor R3 and a compensation capacitor C0 in series between the grid electrode and the drain electrode of the output driving transistor M4 are adopted, so that the output voltage Vout of the output driving transistor M4 can be effectively controlled.

Description

Technical Field

[0001] This utility model belongs to the field of power protection technology, specifically relating to a dual-mode intelligent management and self-protection circuit for a battery power supply system. Background Technology

[0002] In recent years, the widespread application of mobile robots has placed higher demands on the stability and safety of power supply systems. Mobile robots typically rely on battery packs for power, but the voltage output of these packs is affected by discharge characteristics and load changes, resulting in significant fluctuations that can lead to instability or malfunctions in the overall operation. Traditional power management solutions often struggle to balance stable power supply and effective protection when dealing with wide-range voltage fluctuations, failing to isolate faults in a timely manner under abnormal conditions, thus posing potential risks to core chips or battery packs. Utility Model Content

[0003] This invention provides a dual-modal intelligent management and self-protection circuit for a battery-powered system to address the aforementioned problems.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A dual-mode intelligent management and self-protection circuit for a battery-powered system includes a drive module and a detection module. The drive module includes a NAND gate I0, whose input is used to receive control signals DRIVE_EN and DET_EN. The output of the NAND gate I0 is connected to the input of an inverter I1. The output of the inverter I1 is connected to the gates of switching transistors M0 and M1. The drain of the switching transistor M0 is connected via a resistor R1 to the anode of diode D0, the drain of transistor M2, and the gate of output drive transistor M4. A voltage divider resistor R0 is connected in parallel across diode D0. The cathode of diode D0 is connected to the source of output drive transistor M4. 2. A current mirror is formed by transistor M2 and transistor M3 sharing a common gate, with a bias resistor R2 connected in series at the common gate node. The sources of transistors M2 and M3, as well as the other end of the bias resistor R2, are all connected to the source of the output drive transistor M4. The drain of the control switch transistor M1 is connected to the drain and gate of transistor M3. The source of the control switch transistor M1 is connected to the drain of transistor M5. Transistors M5 and M6 share a common gate to form a current mirror. The gates of transistors M5 and M6 are both connected to the anode of Zener diode D1. The sources of the switch transistors M0, M5, and M6 are all grounded. The drain of transistor M6 is connected to the anode of Zener diode D1. The cathode of Zener diode D1... One end of the voltage divider resistor R4 is connected to the drain of the output driving transistor M4. The drain of the output driving transistor M4 is connected to the drain of the high-voltage transistor M7 in the detection module. The gate of the high-voltage transistor M7 is used to receive the control signal IN_DET_EN. The source of the high-voltage transistor M7 is connected to the gate of the transistor M8 through the current-limiting resistor R5. The gate of the transistor M8 is also connected to the cathode of the protection diode D2. The source of the transistor M8 is connected to the drain and gate of the transistor M9. A resistor R6 is connected in parallel between the drain and source of the transistor M9. The transistor M9 and the transistor M10 share a common gate to form a current mirror. The source of the transistor M9 and the transistor M10... The source of transistor I10 and the anode of protection diode D2 are both grounded. The drain of transistor M8 is connected to the source of switching transistor M11 through voltage divider resistor R7. The drain of transistor M10 is connected to the input terminal of inverter I2. The drain of transistor M10 is connected to the source of switching transistor M11 through voltage divider resistor R8. The drain of transistor M10 is also connected to the drain of switching transistor M11 through voltage divider resistor R9. The source of switching transistor M11 is connected to the source of transistor M12. The drain and gate of transistor M12 are respectively connected to the input and output terminals of inverter I3, forming a latching structure. Inverters I2, I3, I4, I5, and I6 are cascaded in sequence.The drain of the switching transistor M11 is connected to the input terminal of inverter I5, and the output terminal of inverter I6 is used to output a control signal.

[0006] Furthermore, a resistor R3 and a compensation capacitor C0 are connected in series with the gate of the output driving transistor M4. The other end of the compensation capacitor C0 is connected to the source of the output driving transistor M4 to introduce a zero point for compensation, thereby optimizing the loop bandwidth and improving the dynamic response characteristics.

[0007] Furthermore, the resistance of the voltage divider resistor R8 is 50Ω to 200Ω, and the capacitance of the compensation capacitor C0 is 1μF to 100μF.

[0008] Furthermore, the maximum drain-source voltage of the output drive transistor M4, transistor M6, high-voltage transistor M7, transistor M8, switching transistor M11, and transistor M12 is greater than 100V, and the internal on-resistance is 10mΩ to 50mΩ, so that it has low on-resistance and high withstand voltage performance to meet the operating requirements of a wide voltage range of 4.7V to 80V and maintain stable output in different modes.

[0009] Compared with the prior art, the present invention has the following advantages:

[0010] This invention employs a feedback branch consisting of a voltage divider resistor R4, a Zener diode D1, and a transistor M6, as well as zero-point compensation using a resistor R3 and a compensation capacitor C0 connected in series between the gate and drain of the output drive transistor M4, which can effectively control the output voltage Vout of the output drive transistor M4.

[0011] In this invention, the drain and gate of transistor M12 in the detection module are connected to the input and output terminals of inverter I3, respectively, forming a latching structure. Inverters I2, I3, I4, I5 and I6 are cascaded in sequence, introducing a certain hysteresis to prevent output errors caused by voltage fluctuations and protect the safety of subsequent circuits.

[0012] This utility model integrates an overvoltage and current limiting protection structure consisting of a high-voltage transistor M7, a protection diode D2, and a current-limiting resistor R5 to ensure the safety of the main circuit. At the same time, the feedback branch consisting of a voltage divider resistor R4, a Zener diode D1, and a transistor M6 also provides a discharge path to improve system safety, thus having a complete protection mechanism.

[0013] This invention introduces a dual-mode intelligent management mechanism. When the battery pack voltage VBAT is below 8V, the current mirrors formed by transistors M2 and M3 and M5 and M6 are turned off. The output drive transistor M4 operates in the linear region under the static bias set by the voltage divider resistor R0 and resistor R1, limiting the output voltage and avoiding false triggering and premature driving. When VBAT is above or equal to 8V, transistor M6 is turned on, and feedback is sent to the current mirrors via the output drive transistor R4 and the Zener diode D1. This causes the current mirrors formed by transistors M2 and M3 and M5 and M6 to operate, forming a three-stage common-source feedback amplification structure composed of transistor M2, output drive transistor M4, and M5. This achieves intelligent judgment and automatic adjustment under power supply conditions, effectively improving the adaptability and safety of the circuit over a wide voltage range. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of this utility model. Detailed Implementation

[0015] To further illustrate the technical solution of this utility model, the following embodiments will be used to further explain this utility model.

[0016] like Figure 1As shown, a dual-mode intelligent management and self-protection circuit for a battery-powered system includes a drive module and a detection module. The drive module includes a NAND gate I0, whose input is used to receive control signals DRIVE_EN and DET_EN. The output of the NAND gate I0 is connected to the input of an inverter I1. The output of the inverter I1 is connected to the gates of switching transistors M0 and M1. The drain of the switching transistor M0 is connected via a resistor R1 to the anode of diode D0, the drain of transistor M2, and the gate of output drive transistor M4. A resistor R3 and a compensation capacitor C0 are connected in series with the gate of the output drive transistor M4. The other end of the compensation capacitor C0 is connected to... The source of the output drive transistor M4 is connected to introduce a zero point for compensation, thereby optimizing loop bandwidth and improving dynamic response characteristics. A voltage divider resistor R0 is connected in parallel across diode D0. The cathode of diode D0 is connected to the source of the output drive transistor M4. Transistors M2 and M3 form a current mirror through a common gate, and a bias resistor R2 is connected in series at the common gate node. The sources of transistors M2 and M3, as well as the other end of the bias resistor R2, are all connected to the source of the output drive transistor M4. The drain of the control switch transistor M1 is connected to the drain and gate of transistor M3. The source of the control switch transistor M1 is connected to the drain of transistor M5. Transistors M5 and M6 form a current mirror through a common gate. In this configuration, the gates of transistors M5 and M6 are both connected to the anode of Zener diode D1. The sources of switching transistors M0, M5, and M6 are all grounded. The drain of transistor M6 is connected to the anode of Zener diode D1. The cathode of Zener diode D1 is connected to one end of voltage divider resistor R4, and the other end of voltage divider resistor R4 is connected to the drain of output drive transistor M4. The drain of output drive transistor M4 is connected to the drain of high-voltage transistor M7 in the detection module. The gate of high-voltage transistor M7 is used to receive the control signal IN_DET_EN. The source of high-voltage transistor M7 is connected to the gate of transistor M8 through current-limiting resistor R5. The gate of transistor M8 is also connected to... The cathode of the protection diode D2 is connected. The source of transistor M8 is connected to the drain and gate of transistor M9. A resistor R6 is connected in parallel between the drain and source of transistor M9. Transistors M9 and M10 form a current mirror with a common gate. The sources of transistors M9 and M10, as well as the anode of the protection diode D2, are all grounded. The drain of transistor M8 is connected to the source of switching transistor M11 through a voltage divider resistor R7. The drain of transistor M10 is connected to the input terminal of inverter I2. The drain of transistor M10 is connected to the source of switching transistor M11 through a voltage divider resistor R8. The drain of transistor M10 is also connected to the drain of switching transistor M11 through a voltage divider resistor R9.The source of the switching transistor M11 is connected to the source of transistor M12. The drain and gate of transistor M12 are connected to the input and output terminals of inverter I3, respectively, forming a latching structure. Inverters I2, I3, I4, I5, and I6 are cascaded in sequence. The drain of switching transistor M11 is connected to the input terminal of inverter I5. The output terminal of inverter I6 is used to output a control signal. The voltage divider resistor R8 has a resistance of 50Ω to 200Ω, and the compensation capacitor C0 has a capacitance of 1μF to 100μF. The maximum drain-source voltage of the output drive transistors M4, M6, M7, M8, M11, and M12 is greater than 100V, and the internal on-resistance is 10mΩ to 50mΩ, so that they have low on-resistance and high voltage withstand performance to meet the operating requirements of a wide voltage range of 4.7V to 80V and maintain stable output in different modes. The input of NAND gate I0, the gate of high-voltage transistor M7, and the output of inverter I6 are all connected to the microcontroller unit (MCU). The MCU determines whether to issue a command to blow the external fuse of the battery pack based on the output level of the detection module, thus quickly isolating abnormal voltages and protecting subsequent circuits and the battery pack.

[0017] In the above embodiment, voltage divider resistors R8 and R9 constitute a current reference module, and a reference current I is set. ref The circuit controls the switching action of the output drive transistor M11 to adjust the reference current I. ref The change occurs. It is compared with the drain current of transistor M10 to control the change in the output signal.

[0018] When the detection module detects that the output voltage Vout of the output driving transistor M4 is too high, the voltage divider resistor R4, the Zener diode D1 and the transistor M6 in the driving module can provide a current discharge path and play a protective role.

[0019] Working principle: When the voltage V of the battery-powered system BAT When the voltage is less than 8V, it is in the first operating mode, due to the drain output voltage V of the output drive transistor M4. DS The voltage drop across the voltage divider resistor R4, the reverse bias voltage of the Zener diode D1, and the gate voltage V of the transistor M6. GS The combined effect prevents the provision of an approximately 8V operating voltage, causing the current mirror formed by transistors M5 and M6 to stop working. Simultaneously, the self-biasing of bias resistor R2 turns off the current mirror formed by transistors M2 and M3. At this time, the gate voltage of the output drive transistor M4 is obtained by the voltage divider resistors R0 and R1, allowing the output drive transistor M4 to operate in its linear region, with its output voltage determined by its internal on-resistance. Meanwhile, when the voltage V of the battery-powered system...BAT When the voltage is greater than or equal to 8V, the system is in the second operating mode. The branch of transistor M6 is turned on, and its current is replicated to transistor M5 through the current mirror, reducing the gate voltage of transistor M3. This activates the current mirror formed by transistors M2 and M3, creating a three-stage common-source amplifier circuit consisting of transistor M2, output drive transistor M4, and transistor M5. The output voltage is determined using a negative feedback loop formed by voltage divider resistor R4, Zener diode D1, and transistor M6. Simultaneously, zero-point compensation is introduced by connecting a series resistor R3 and a compensation capacitor C0 to the gate of output drive transistor M4 to prevent oscillation and ensure system stability. The output voltage V of output drive transistor M4 is... out The setup time is limited by the loop bandwidth and the output current of the output drive transistor M4: when the voltage V of the battery-powered system... BAT When the voltage is less than 8V, the bandwidth of the feedback branch, consisting of voltage divider resistor R4, Zener diode D1, and transistor M6, is mainly determined. When the voltage V of the battery-powered system... BAT When the voltage is greater than or equal to 8V, the gate voltage V of the output drive transistor M4 is... GS The increase in voltage is limited by the reverse bias voltage of diode D0, and the settling time is mainly determined by the fixed slew rate I. out / CL (CL is the total output capacitance, I out The output current of the drive transistor M4 is determined by the signal. When the control signal IN_DET_EN is enabled, the detection module starts. High voltage is isolated by high-voltage transistor M7, and the gate of transistor M8 is protected by protection diode D2 and current-limiting resistor R5. The signal after being stepped down by transistor M8 is converted into a current I. comp The current mirror formed by transistors M9 and M10 replicates the current to transistor M10, and forms I with voltage divider resistors R8 and R9. ref By comparing the values ​​of the input resistances of the switching transistor M11, the output voltage V of the drain of the output driving transistor M4 is achieved. DS The hysteresis in both upward and downward directions, along with the latch structure formed by transistor M12 and inverter I3, prevents false triggering caused by voltage fluctuations near the threshold, thereby controlling the output voltage V of the output drive transistor M4. out Perform real-time monitoring, and then use the reference current I ref and current I comp By comparison, transistor M9 converts the current I obtained by transistor M8 proportionally. comp As a reference, transistor M10 mirrors this current with the reference current I. ref Comparisons were made, and the rising and falling phases corresponded to different I values. ref This value leads to upward and downward lag.

[0020] The foregoing has shown and described the main features and advantages of this utility model. It will be apparent to those skilled in the art that this utility model is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this utility model. Therefore, the embodiments should be considered exemplary and non-limiting in all respects. The scope of this utility model is defined by the appended claims rather than the foregoing description, and thus all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this utility model.

[0021] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A dual-mode intelligent management and self-protection circuit for a battery-powered system, characterized in that: The system comprises two parts: a driving module and a detection module. The driving module includes a NAND gate I0, whose input is used to receive control signals DRIVE_EN and DET_EN. The output of the NAND gate I0 is connected to the input of an inverter I1. The output of the inverter I1 is connected to the gates of switching transistors M0 and M1. The drain of switching transistor M0 is connected via resistor R1 to the anode of diode D0, the drain of transistor M2, and the gate of output driving transistor M4. A voltage divider resistor R0 is connected in parallel across diode D0. The cathode of diode D0 is connected to the source of output driving transistor M4. Transistors M2 and M3 form a current mirror with a common gate and are connected in series at the common gate node. A bias resistor R2 is provided. The source of transistor M2, the source of transistor M3, and the other end of the bias resistor R2 are all connected to the source of output drive transistor M4. The drain and gate of transistor M3 are connected to the drain of control switch transistor M1. The source of control switch transistor M1 is connected to the drain of transistor M5. Transistors M5 and M6 form a current mirror with a common gate. The gates of transistors M5 and M6 are both connected to the anode of Zener diode D1. The sources of switch transistors M0, M5, and M6 are all grounded. The drain of transistor M6 is connected to the anode of Zener diode D1. The cathode of Zener diode D1 is connected to one end of voltage divider resistor R4. The other end of voltage divider resistor R4... One end is connected to the drain of the output driving transistor M4. The drain of the output driving transistor M4 is connected to the drain of the high-voltage transistor M7 in the detection module. The gate of the high-voltage transistor M7 is used to receive the control signal IN_DET_EN. The source of the high-voltage transistor M7 is connected to the gate of transistor M8 through a current-limiting resistor R5. The gate of transistor M8 is also connected to the cathode of the protection diode D2. The source of transistor M8 is connected to the drain and gate of transistor M9. A resistor R6 is connected in parallel between the drain and source of transistor M9. Transistor M9 and transistor M10 form a current mirror with a common gate. The sources of transistors M9 and M10, as well as the anode of the protection diode D2, are all grounded. The drain of transistor M8 is connected to the source of switching transistor M11 via voltage divider resistor R7. The drain of transistor M10 is connected to the input of inverter I2. The drain of transistor M10 is connected to the source of switching transistor M11 via voltage divider resistor R8. The drain of transistor M10 is also connected to the drain of switching transistor M11 via voltage divider resistor R9. The source of switching transistor M11 is connected to the source of transistor M12. The drain and gate of transistor M12 are connected to the input and output of inverter I3, respectively, forming a latching structure. Inverters I2, I3, I4, I5, and I6 are cascaded in sequence. The drain of switching transistor M11 is connected to the input of inverter I5.The output terminal of the inverter I6 is used for outputting a control signal.

2. A dual mode intelligent management and self-protection circuit for a battery powered system as claimed in claim 1, wherein: A resistor R3 and a compensation capacitor C0 are connected in series with the gate of the output driving transistor M4. The other end of the compensation capacitor C0 is connected to the source of the output driving transistor M4 to introduce a zero point for compensation, thereby optimizing the loop bandwidth and improving the dynamic response characteristics.

3. A dual mode intelligent management and self-protection circuit for a battery powered system as claimed in claim 2, wherein: The voltage divider resistor R8 has a resistance of 50Ω to 200Ω, and the compensation capacitor C0 has a capacitance of 1μF to 100μF.

4. The dual mode intelligent management and self-protection circuit for battery powered systems of claim 1, wherein: The output drive transistors M4, M6, M7, M8, M11, and M12 have a maximum drain-source voltage greater than 100V and an internal on-resistance of 10mΩ to 50mΩ, which enables them to have low on-resistance and high voltage withstand performance to meet the operating requirements of a wide voltage range from 4.7V to 80V and maintain stable output in different modes.

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