Signal processing circuit, chip and electronic equipment
By working together with the bandwidth control module, the adjustment module, and the signal selection module, the problem of power wastage of PGA under different signal amplitudes is solved, and power consumption optimization and processing speed improvement are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CHIPSEA TECH SHENZHEN CO LTD
- Filing Date
- 2025-03-26
- Publication Date
- 2026-04-17
AI Technical Summary
Using a PGA with the same bandwidth to process input signals results in wasted power consumption and increased system cost.
The bandwidth control module generates a bandwidth control signal, the bandwidth adjustment module generates a bias current, the programmable gain amplifier module performs amplification processing at different bandwidths, and the signal selection module selects the voltage output with matching bandwidth.
It reduces power consumption and increases signal processing speed.
Smart Images
Figure CN224138976U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic circuit technology, specifically to a signal processing circuit, chip, and electronic device. Background Technology
[0002] In signal processing, a programmable gain amplifier (PGA) is used to process the input signal, which may have different amplitudes.
[0003] However, using a PGA with the same bandwidth to process the input signal will result in wasted power consumption and increased system cost. Utility Model Content
[0004] In view of the above problems, embodiments of this application provide a signal processing circuit, chip, and electronic device to solve the above technical problems.
[0005] In a first aspect, embodiments of this application provide a signal processing circuit, which includes a bandwidth control module, a bandwidth adjustment module, a programmable gain amplification module, and a signal selection module. The input terminal of the bandwidth control module is connected to a voltage input terminal, and the bandwidth control module is used to generate a bandwidth control signal based on the voltage comparison result between the voltage input terminal and a reference voltage terminal. The input terminal of the bandwidth adjustment module is connected to the output terminal of the bandwidth control module, and the bandwidth adjustment module is used to generate a first bias current and a second bias current based on the bandwidth control signal. The programmable gain amplification module is connected to the voltage input terminal and the bandwidth adjustment module, and the programmable gain amplification module is used to amplify the signal at the voltage input terminal with different bandwidths based on the first bias current and the second bias current to generate corresponding first voltage and second voltage. The first voltage is a single voltage signal or a differential voltage signal, and the second voltage is a single voltage signal or a differential voltage signal. The signal selection module is connected to the bandwidth control module and the programmable gain amplification module, and the signal selection module is used to select the output first voltage or second voltage that matches the bandwidth based on the bandwidth control signal.
[0006] Secondly, embodiments of this application also include a chip that includes the signal processing circuit described above.
[0007] Thirdly, embodiments of this application also provide an electronic device, which includes a device body and the aforementioned signal processing circuit or chip disposed on the device body.
[0008] The signal processing circuit, chip, and electronic device provided in this application embodiment generate a bandwidth control signal based on the voltage comparison result between the voltage input terminal and the reference voltage terminal through a bandwidth control module. A bandwidth adjustment module generates a first bias current and a second bias current based on the bandwidth control signal. A programmable gain amplification module amplifies the signal at the voltage input terminal with different bandwidths based on the first bias current and the second bias current to generate corresponding first voltage and second voltage. A signal selection module selects to output a first voltage or a second voltage that matches the bandwidth based on the bandwidth control signal. In this way, for a large input voltage, the signal selection module can be controlled to select the output voltage generated by high bandwidth processing, and for a small input voltage, the signal selection module can be controlled to select the output voltage generated by low bandwidth processing, thereby reducing power consumption and improving processing speed.
[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] Figure 1 A first schematic block diagram of the signal processing circuit provided in an embodiment of this application is shown.
[0012] Figure 2 The circuit schematic of the programmable gain amplifier module is shown.
[0013] Figure 3 The first circuit schematic of the bandwidth control module is shown.
[0014] Figure 4 The second circuit schematic for the bandwidth control module is shown.
[0015] Figure 5 A waveform diagram of the bandwidth control module is shown.
[0016] Figure 6 The circuit schematic of the bandwidth adjustment module is shown.
[0017] Figure 7 The second circuit schematic of the second bias unit is shown.
[0018] Figure 8 A second schematic diagram of the signal processing circuit provided in an embodiment of this application is shown.
[0019] Figure 9 A schematic diagram of the chip structure provided in an embodiment of this application is shown.
[0020] Figure 10 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.
[0021] Explanation of reference numerals in the attached figures:
[0022] 10. Bandwidth control module; COMP1, comparator; R, first resistor; C, first capacitor; Vhp, bandwidth control signal; AGND, ground terminal; V1, first voltage; V2, second voltage;
[0023] 20. Bandwidth adjustment module;
[0024] 21. First mirror unit; VDD, power supply terminal; A1, current source; MP1, first transistor; MN2, second transistor; MN3, third transistor;
[0025] 22. First bias unit; MP2, fourth transistor; MP4, fifth transistor; MP3, sixth transistor; MP5, seventh transistor; Ib1, first bias current;
[0026] 23. Second bias unit; MP6, eighth transistor; MP7, ninth transistor; Ib2, second bias current;
[0027] 30. Programmable gain amplifier module; PGA1, first programmable gain amplifier; PGA2, second programmable gain amplifier;
[0028] 40. Signal selection module;
[0029] 50. Analog-to-digital converter;
[0030] 60. Digital processing module;
[0031] 100. Signal processing circuit;
[0032] 200. Chip;
[0033] 300. Electronic devices. Detailed Implementation
[0034] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0035] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0036] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0037] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0038] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.
[0039] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.
[0040] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0041] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.
[0042] like Figure 1 As shown in the figure, this application embodiment provides a signal processing circuit 100, which includes a bandwidth control module 10, a bandwidth adjustment module 20, a programmable gain amplifier module 30, and a signal selection module 40. The voltage input terminals are connected to the input terminals of the bandwidth control module 10 and the programmable gain amplifier module 30, respectively. The output terminals of the bandwidth control module 10 are connected to the input terminals of the bandwidth adjustment module 20 and the control terminal of the signal selection module 40, respectively. The first output terminal of the bandwidth adjustment module 20 is connected to the first bias terminal of the programmable gain amplifier module 30, and the second output terminal of the bandwidth adjustment module 20 is connected to the second bias terminal of the programmable gain amplifier module 30. The first output terminal of the programmable gain amplifier module 30 is connected to the first input terminal of the signal selection module 40, and the second output terminal of the programmable gain amplifier module 30 is connected to the second input terminal of the signal selection module 40. The first bias terminal is used to connect to a first bias current Ib1, and the second bias terminal is used to connect to a second bias current Ib2. The first input terminal of the signal selection module 40 is used to connect to a first voltage V1, and the second input terminal of the signal selection module 40 is used to connect to a second voltage V2.
[0043] The bandwidth control module 10 generates a bandwidth control signal Vhp based on the voltage comparison result between the voltage input terminal and the reference voltage terminal. The bandwidth adjustment module 20 generates a first bias current Ib1 and a second bias current Ib2 based on the bandwidth control signal Vhp. The programmable gain amplification module 30 amplifies the signal at the voltage input terminal with different bandwidths based on the first bias current Ib1 and the second bias current Ib2 to generate corresponding first voltage V1 and second voltage V2. The signal selection module 40 selects to output the first voltage V1 or the second voltage V2 that matches the bandwidth based on the bandwidth control signal Vhp, thereby reducing power consumption and improving processing speed.
[0044] This application provides a signal processing circuit 100. Please refer to [link / reference]. Figures 1 to 8 ,like Figure 1As shown, the signal processing circuit 100 includes a bandwidth control module 10, a bandwidth adjustment module 20, a programmable gain amplifier module 30, and a signal selection module 40. The input terminal of the bandwidth control module 10 is connected to the voltage input terminal, and the bandwidth control module 10 is used to generate a bandwidth control signal Vhp based on the voltage comparison result between the voltage input terminal and the reference voltage terminal. The input terminal of the bandwidth adjustment module 20 is connected to the output terminal of the bandwidth control module 10, and the bandwidth adjustment module 20 is used to generate a first bias current Ib1 and a second bias current Ib2 based on the bandwidth control signal Vhp. The programmable gain amplifier module 30 is connected to the voltage input terminal and the bandwidth adjustment module 20, and the programmable gain amplifier module 30 is used to amplify the signal at the voltage input terminal with different bandwidths based on the first bias current Ib1 and the second bias current Ib2 to generate corresponding first voltage V1 and second voltage V2. The signal selection module 40 is connected to the bandwidth control module 10 and the programmable gain amplifier module 30, and the signal selection module 40 is used to select the output of the first voltage V1 or the second voltage V2 that matches the bandwidth based on the bandwidth control signal Vhp.
[0045] It is understood that the signal processing circuit 100 provided in this application embodiment generates a bandwidth control signal Vhp based on the voltage comparison result between the voltage input terminal and the reference voltage terminal through the bandwidth control module 10. The bandwidth adjustment module 20 generates a first bias current Ib1 and a second bias current Ib2 based on the bandwidth control signal Vhp. The programmable gain amplification module 30 amplifies the signal at the voltage input terminal with different bandwidths based on the first bias current Ib1 and the second bias current Ib2 to generate corresponding first voltage V1 and second voltage V2. The signal selection module 40 selects to output the first voltage V1 or the second voltage V2 that matches the bandwidth based on the bandwidth control signal Vhp. In this way, for a large input voltage, the signal selection module 40 can be controlled to select the output voltage generated by high bandwidth processing, and for a small input voltage, the signal selection module 40 can be controlled to select the output voltage generated by low bandwidth processing, thereby reducing power consumption and improving processing speed.
[0046] It should be noted that the voltage input terminal is used to transmit the input voltage Vin. The output voltage Vout of the signal selection module 40 is either a first voltage V1 or a second voltage V2 that matches the bandwidth.
[0047] Wherein, the first voltage V1 is either a single voltage signal or a differential voltage signal, and the second voltage V2 is either a single voltage signal or a differential voltage signal. If both the first voltage V1 and the second voltage V2 are single voltage signals, the output voltage Vout of the signal selection module 40 is also a single voltage signal. If both the first voltage V1 and the second voltage V2 are differential voltage signals, the output voltage Vout of the signal selection module 40 is also a differential voltage signal.
[0048] In some of these embodiments, such as Figure 2 As shown, the programmable gain amplifier module 30 includes a first programmable gain amplifier PGA1 and a second programmable gain amplifier PGA2. The first input terminal of the first programmable gain amplifier PGA1 is connected to the voltage input terminal, the second input terminal of the first programmable gain amplifier PGA1 is connected to the common-mode terminal, the current bias terminal of the first programmable gain amplifier PGA1 is connected to the first bias current Ib1, and the output terminal of the first programmable gain amplifier PGA1 outputs a first voltage V1. The first input terminal of the second programmable gain amplifier PGA2 is connected to the voltage input terminal, the second input terminal of the second programmable gain amplifier PGA2 is connected to the common-mode terminal, the current bias terminal of the second programmable gain amplifier PGA2 is connected to the second bias current Ib2, and the output terminal of the second programmable gain amplifier PGA2 outputs a second voltage V2.
[0049] It should be noted that the common-mode terminal is used to connect the common-mode voltage Vcm. Different first bias currents Ib1 and second bias currents Ib2 can give the first programmable gain amplifier PGA1 and the second programmable gain amplifier PGA2 different bandwidths. This allows the higher amplitude input voltage Vin to be amplified by the higher bandwidth first programmable gain amplifier PGA1 and the lower bandwidth second programmable gain amplifier PGA2 to generate the corresponding first voltage V1 and second voltage V2. Then, the signal selection module 40 will select the output first voltage V1 according to the bandwidth control signal Vhp. Alternatively, for the lower amplitude input voltage Vin, it can be amplified by the higher bandwidth first programmable gain amplifier PGA1 and the lower bandwidth second programmable gain amplifier PGA2 to generate the corresponding first voltage V1 and second voltage V2. Then, the signal selection module 40 will select the output second voltage V2 according to the bandwidth control signal Vhp. This allows the amplitude of the input voltage Vin to match the bandwidth of the programmable gain amplifier, thereby optimizing the system power consumption and processing speed.
[0050] In some of these embodiments, such as Figure 3 As shown, the bandwidth control module 10 includes a comparator COMP1. The first input terminal of the comparator COMP1 is connected to the voltage input terminal, the second input terminal of the comparator COMP1 is connected to the reference voltage terminal, and the output terminal of the comparator COMP1 outputs the bandwidth control signal Vhp.
[0051] It should be noted that the first input terminal of comparator COMP1 can be an inverting input (-), and the second input terminal of comparator COMP1 can be a non-inverting input (+). The reference voltage terminal is used to reference the voltage Vref. Figure 5As shown, the input voltage Vin is compared with the reference voltage Vref by the comparator COMP1. When the input voltage Vin is greater than the reference voltage Vref, the bandwidth control signal Vhp is low; when the input voltage Vin is less than the reference voltage Vref, the bandwidth control signal Vhp is high.
[0052] In some of these embodiments, such as Figure 4 As shown, the bandwidth control module 10 also includes a first resistor R and a first capacitor C. The first end of the first resistor R is connected to the output of the comparator COMP1, and the second end of the first resistor R outputs the bandwidth control signal Vhp. The first end of the first capacitor C is connected to the second end of the first resistor R, and the second end of the first capacitor C is connected to the ground terminal AGND.
[0053] It should be noted that in this embodiment, the bandwidth control signal Vhp is filtered by the first resistor R and the first capacitor C to remove interference and improve the accuracy of the bandwidth control signal Vhp.
[0054] In some of these embodiments, such as Figure 6 As shown, the bandwidth adjustment module 20 includes a first mirror unit 21, a first bias unit 22, and a second bias unit 23. The first mirror unit 21 is used to generate a first current. The first bias unit 22 is connected to the first mirror unit 21 and is used to generate a first bias current Ib1 based on the first current and the bandwidth control signal Vhp. The second bias unit 23 is connected to the first mirror unit 21 and is used to generate a second bias current Ib2 based on the first current.
[0055] It should be noted that the first mirror unit 21 is connected to the first bias unit 22 and the second bias unit 23. In this embodiment, different first bias currents Ib1 and second bias currents Ib2 can be generated according to the level of the bandwidth control signal Vhp to control the first programmable gain amplifier PGA1 and the second programmable gain amplifier PGA2 to have different bandwidths.
[0056] In some of these embodiments, such as Figure 6As shown, the first mirror unit 21 includes a current source A1, a first transistor MP1, a second transistor MN2, and a third transistor MN3. The first terminal of the current source A1 is connected to the power supply terminal VDD; the first terminal of the first transistor MP1 is connected to the power supply terminal VDD, and the second terminal of the first transistor MP1 is connected to the control terminal of the first transistor MP1; the first terminal of the second transistor MN2 is connected to the second terminal of the first transistor MP1, and the second terminal of the second transistor MN2 is connected to the ground terminal AGND; the first terminal of the third transistor MN3 is connected to the control terminal of the third transistor MN3, the control terminal of the second transistor MN2, and the second terminal of the current source A1, and the second terminal of the third transistor MN3 is connected to the ground terminal AGND.
[0057] It should be noted that the current supplied by current source A1 is equal to the current flowing through the third transistor MN3. Since the third transistor MN3 and the second transistor MN2 form a mirror image structure, the current flowing through the second transistor MN2 is proportional to the current flowing through the third transistor MN3. Because the second transistor MN2 and the first transistor MP1 are connected in series, the current flowing through the first transistor MP1, i.e., the first current, is equal to the current flowing through the second transistor MN2.
[0058] In some of these embodiments, such as Figure 6 As shown, the first bias unit 22 includes a fourth transistor MP2, a fifth transistor MP4, a sixth transistor MP3, and a seventh transistor MP5. The first terminal of the fourth transistor MP2 is connected to the power supply terminal VDD, and the control terminal of the fourth transistor MP2 is connected to the control terminal of the first transistor MP1. The first terminal of the fifth transistor MP4 is connected to the second terminal of the fourth transistor MP2, and the control terminal of the fifth transistor MP4 is connected to the ground terminal AGND. The second terminal of the fifth transistor MP4 is used to output the first bias current Ib1. The first terminal of the sixth transistor MP3 is connected to the power supply terminal VDD, and the control terminal of the sixth transistor MP3 is connected to the control terminal of the first transistor MP1. The first terminal of the seventh transistor MP5 is connected to the second terminal of the sixth transistor MP3, the control terminal of the seventh transistor MP5 is connected to the bandwidth control signal Vhp, and the second terminal of the seventh transistor MP5 is connected to the second terminal of the fifth transistor MP4.
[0059] It should be noted that the fourth transistor MP2 and the first transistor MP1 form a mirror image structure. Therefore, the current flowing through the fourth transistor MP2 and the first current flowing through the first transistor MP1 are proportionally related. Since the fourth transistor MP2 and the fifth transistor MP4 are connected in series, and the fifth transistor MP4 is always conducting, the current flowing through the fourth transistor MP2 is equal to the current flowing through the fifth transistor MP4. The current flowing through the fifth transistor MP4 is used to ensure that the first programmable gain amplifier PGA1 is in a low-power mode or sleep mode. Compared to the time required from power-on to operation, it can directly enter operation from sleep mode, saving power-on time.
[0060] The sixth transistor MP3 and the first transistor MP1 form a mirror image structure. Therefore, the current flowing through the sixth transistor MP3 and the first current flowing through the first transistor MP1 are proportional. Since the sixth transistor MP3 and the seventh transistor MP5 are connected in series, when the seventh transistor MP5 is turned on, the current flowing through the sixth transistor MP3 is equal to the current flowing through the seventh transistor MP5.
[0061] The first bias current Ib1 is equal to the sum of the current flowing through the fifth transistor MP4 and the current flowing through the seventh transistor MP5.
[0062] In some of these embodiments, such as Figure 6 As shown, the second bias unit 23 includes an eighth transistor MP6 and a ninth transistor MP7. The first terminal of the eighth transistor MP6 is connected to the power supply terminal VDD, and the control terminal of the eighth transistor MP6 is connected to the control terminal of the first transistor MP1. The first terminal of the ninth transistor MP7 is connected to the second terminal of the eighth transistor MP6, and the control terminal of the ninth transistor MP7 is connected to the ground terminal AGND. The second terminal of the ninth transistor MP7 is used to output the second bias current Ib2.
[0063] It should be noted that the eighth transistor MP6 and the first transistor MP1 form a mirror structure. Therefore, the current flowing through the eighth transistor MP6 and the first current flowing through the first transistor MP1 are proportional. Since the eighth transistor MP6 and the ninth transistor MP7 are connected in series, and the ninth transistor MP7 is always on, the current flowing through the eighth transistor MP6 is equal to the current flowing through the ninth transistor MP7. The current flowing through the ninth transistor MP7 is used to ensure that the second programmable gain amplifier PGA2 is in low-power mode or sleep mode. Compared with the time required from power-on to operation, it can directly enter operation from sleep mode, saving power-on time.
[0064] In some of these embodiments, such as Figure 7As shown, the second bias unit 23 includes an eighth transistor MP6 and a ninth transistor MP7. The first terminal of the eighth transistor MP6 is connected to the power supply terminal VDD, and the control terminal of the eighth transistor MP6 is connected to the control terminal of the first transistor MP1. The first terminal of the ninth transistor MP7 is connected to the second terminal of the eighth transistor MP6, the control terminal of the ninth transistor MP7 is connected to the bandwidth control signal Vhp, and the second terminal of the ninth transistor MP7 is used to output the second bias current Ib2.
[0065] It should be noted that the eighth transistor MP6 and the first transistor MP1 form a mirror structure. Therefore, the current flowing through the eighth transistor MP6 and the first current flowing through the first transistor MP1 are proportional. Since the eighth transistor MP6 and the ninth transistor MP7 are connected in series, when the ninth transistor MP7 is turned on, the current flowing through the eighth transistor MP6 is equal to the current flowing through the ninth transistor MP7, which is the second bias current Ib2.
[0066] In summary, the first bias current Ib1 is greater than or equal to the second bias current Ib2, and the bandwidth of the first programmable gain amplifier PGA1 is greater than or equal to the bandwidth of the second programmable gain amplifier PGA2. When the input voltage Vin is greater than the reference voltage Vref, and the bandwidth control signal Vhp is low, the seventh transistor MP5 and the ninth transistor MP7 are turned on, increasing the first bias current Ib1 and the bandwidth of the first programmable gain amplifier PGA1. Simultaneously, the low-level bandwidth control signal Vhp controls the signal selection module 40 to output the first voltage V1. Thus, the first voltage V1 obtained after amplifying the large-amplitude input voltage Vin through the high-bandwidth first programmable gain amplifier PGA1 is obtained, thereby reducing power consumption and improving processing speed.
[0067] When the input voltage Vin is smaller than the reference voltage Vref, the bandwidth control signal Vhp is high, the seventh transistor MP5 is turned off, the first bias current Ib1 decreases, and the bandwidth of the first programmable gain amplifier PGA1 also decreases. The high-level bandwidth control signal Vhp controls the signal selection module 40 to output the second voltage V2, thus obtaining the second voltage V2 after the small-amplitude input voltage Vin has been amplified by the low-bandwidth second programmable gain amplifier PGA2, thereby reducing power consumption and improving processing speed.
[0068] In some of these embodiments, such as Figure 8 As shown, the signal processing circuit 100 also includes an analog-to-digital converter 50, which is connected to the signal selection module 40. The analog-to-digital converter 50 is used to convert the first voltage V1 or the second voltage V2 into the corresponding digital voltage.
[0069] It should be noted that since the bandwidth control signal Vhp controls both the bandwidth adjustment module 20 and the signal selection module 40, and connects the input terminal of the analog-to-digital converter 50 to the output terminal of the signal selection module 40, the first voltage V1 or the second voltage V2 processed by the analog-to-digital converter 50 can be synchronized with the input voltage Vin, thereby improving the synchronization of signal processing.
[0070] If both the first programmable gain amplifier PGA1 and the second programmable gain amplifier PGA2 are single-ended outputs, then the first voltage V1 and the second voltage V2 are both single-voltage signals, and the output voltage Vout of the signal selection module 40 is also a single-voltage signal. If both the first programmable gain amplifier PGA1 and the second programmable gain amplifier PGA2 are differential outputs, then the first voltage V1 and the second voltage V2 are both differential voltage signals, and the output voltage Vout of the signal selection module 40 is also a differential voltage signal.
[0071] In some of these embodiments, such as Figure 8 As shown, the signal processing circuit 100 also includes a digital processing module 60, the input of which is connected to the output of the analog-to-digital converter 50.
[0072] It should be noted that the digital processing module 60 is used to perform digital processing on the digital voltage output by the analog-to-digital converter 50.
[0073] This application embodiment also provides a chip 200, such as Figure 9 As shown, the chip 200 includes the signal processing circuit 100 described above. The chip 200 is also called an integrated circuit (IC), and the chip 200 may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.
[0074] It is understood that, since the chip 200 provided in this application embodiment includes the signal processing circuit 100 described above, it can also generate a bandwidth control signal Vhp through the bandwidth control module 10 based on the voltage comparison result between the voltage input terminal and the reference voltage terminal. The bandwidth adjustment module 20 generates a first bias current Ib1 and a second bias current Ib2 based on the bandwidth control signal Vhp. The programmable gain amplification module 30 amplifies the signal at the voltage input terminal with different bandwidths based on the first bias current Ib1 and the second bias current Ib2 to generate corresponding first voltage V1 and second voltage V2. The signal selection module 40 selects to output the first voltage V1 or the second voltage V2 that matches the bandwidth based on the bandwidth control signal Vhp. In this way, for a large input voltage, the signal selection module 40 can be controlled to select the output voltage generated by high bandwidth processing, and for a small input voltage, the signal selection module 40 can be controlled to select the output voltage generated by low bandwidth processing, thereby reducing power consumption and improving processing speed.
[0075] This application also provides an electronic device 300, such as... Figure 10 As shown, the electronic device 300 includes a device body and the aforementioned signal processing circuit 100 or chip 200 disposed within the device body. The electronic device 300 may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.
[0076] It is understood that since the electronic device 300 provided in this application embodiment includes the above-mentioned signal processing circuit 100 or chip 200, it can also generate a bandwidth control signal Vhp through the bandwidth control module 10 based on the voltage comparison result between the voltage input terminal and the reference voltage terminal. The bandwidth adjustment module 20 generates a first bias current Ib1 and a second bias current Ib2 based on the bandwidth control signal Vhp. The programmable gain amplification module 30 amplifies the signal at the voltage input terminal with different bandwidths based on the first bias current Ib1 and the second bias current Ib2 to generate corresponding first voltage V1 and second voltage V2. The signal selection module 40 selects to output the first voltage V1 or the second voltage V2 that matches the bandwidth based on the bandwidth control signal Vhp. In this way, for a large input voltage, the signal selection module 40 can be controlled to select the output voltage generated by high bandwidth processing, and for a small input voltage, the signal selection module 40 can be controlled to select the output voltage generated by low bandwidth processing, thereby reducing power consumption and improving processing speed.
[0077] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A signal processing circuit, characterized by comprising: The signal processing circuit includes: A bandwidth control module, wherein the input terminal of the bandwidth control module is connected to the voltage input terminal, and the bandwidth control module is used to generate a bandwidth control signal based on the voltage comparison result between the voltage input terminal and the reference voltage terminal; A bandwidth adjustment module, wherein the input terminal of the bandwidth adjustment module is connected to the output terminal of the bandwidth control module, and the bandwidth adjustment module is used to generate a first bias current and a second bias current according to the bandwidth control signal; A programmable gain amplifier module is connected to the voltage input terminal and the bandwidth adjustment module. The programmable gain amplifier module is used to amplify the signal at the voltage input terminal with different bandwidths according to the first bias current and the second bias current to generate corresponding first voltage and second voltage. The first voltage is a single voltage signal or a differential voltage signal, and the second voltage is a single voltage signal or a differential voltage signal. A signal selection module is connected to the bandwidth control module and the programmable gain amplifier module. The signal selection module is used to select either the first voltage or the second voltage that matches the bandwidth according to the bandwidth control signal.
2. The signal processing circuit of claim 1, wherein, The programmable gain amplifier module includes: A first programmable gain amplifier has a first input terminal connected to the voltage input terminal, a second input terminal connected to the common-mode terminal, a current bias terminal connected to the first bias current, and an output terminal outputting the first voltage. The second programmable gain amplifier has a first input terminal connected to the voltage input terminal, a second input terminal connected to the common-mode terminal, a current bias terminal connected to the second bias current, and an output terminal outputting the second voltage.
3. The signal processing circuit of claim 1, wherein, The bandwidth control module includes a comparator, the first input terminal of which is connected to the voltage input terminal, the second input terminal of which is connected to the reference voltage terminal, and the output terminal of which outputs the bandwidth control signal.
4. The signal processing circuit of claim 3, wherein, The bandwidth control module also includes: A first resistor, the first end of which is connected to the output of the comparator, and the second end of which outputs the bandwidth control signal; A first capacitor, the first end of which is connected to the second end of the first resistor, and the second end of which is connected to the ground terminal.
5. The signal processing circuit of claim 1, wherein, The bandwidth adjustment module includes: The first mirror unit is used to generate the first current; A first bias unit is connected to the first mirror unit, and the first bias unit is used to generate the first bias current according to the first current and the bandwidth control signal. The second bias unit is connected to the first mirror unit and is used to generate the second bias current based on the first current.
6. The signal processing circuit of claim 5, wherein, The first mirror unit includes: A current source, wherein the first end of the current source is connected to a power supply terminal; A first transistor, wherein the first terminal of the first transistor is connected to the power supply terminal, and the second terminal of the first transistor is connected to the control terminal of the first transistor; The second transistor has its first terminal connected to the second terminal of the first transistor, and its second terminal connected to the ground terminal. The third transistor has its first terminal connected to the control terminal of the third transistor, the control terminal of the second transistor, and the second terminal of the current source, and its second terminal connected to the ground terminal.
7. The signal processing circuit of claim 6, wherein, The first bias unit includes: The fourth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the control terminal of the first transistor. The fifth transistor has its first terminal connected to the second terminal of the fourth transistor, its control terminal connected to the ground terminal, and its second terminal used to output the first bias current. The sixth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the control terminal of the first transistor. The seventh transistor has its first terminal connected to the second terminal of the sixth transistor, its control terminal connected to the bandwidth control signal, and its second terminal connected to the second terminal of the fifth transistor.
8. The signal processing circuit of claim 7, wherein, The second bias unit includes: The eighth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the control terminal of the first transistor. The ninth transistor has its first terminal connected to the second terminal of the eighth transistor, its control terminal connected to the ground terminal, and its second terminal used to output the second bias current.
9. The signal processing circuit of claim 7, wherein, The second bias unit includes: The eighth transistor has its first terminal connected to the power supply terminal and its control terminal connected to the control terminal of the first transistor. The ninth transistor has its first terminal connected to the second terminal of the eighth transistor, its control terminal connected to the bandwidth control signal, and its second terminal used to output the second bias current.
10. The signal processing circuit according to any one of claims 1 to 9, wherein The signal processing circuit further includes an analog-to-digital converter, which is connected to the signal selection module. The analog-to-digital converter is used to convert the first voltage or the second voltage into a corresponding digital voltage.
11. A chip, characterized by The chip includes the signal processing circuit as described in any one of claims 1 to 10.
12. An electronic device, comprising: The electronic device includes a device body and a chip as described in claim 11 disposed on the device body.