Semiconductor device
By employing a closed-loop structure where the gate surrounds the source in GaN-based HEMTs, the leakage problem is solved, the stability and reliability of the device are improved, and the current density and withstand voltage performance are enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XUZHOU ZHINENG SEMICON CO LTD
- Filing Date
- 2025-03-28
- Publication Date
- 2026-04-17
AI Technical Summary
Existing GaN-based high electron mobility transistors (HEMTs) suffer from leakage current issues in their bar-gate structures, leading to device instability and poor reliability.
A first closed-loop structure is formed by surrounding the source with the gate, which separates the source and drain in the stacking direction and the vertical projection plane to form a ring source structure, thereby blocking the flow of two-dimensional electron gas (2DEG) and improving the isolation effect.
It effectively prevents electrons from leaking from the gate end, improves the stability and reliability of the device, enhances current density, reduces physical area, avoids electric field concentration, and improves withstand voltage performance.
Smart Images
Figure CN224139370U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor technology, and more specifically, to a semiconductor device. Background Technology
[0002] GaN-based high electron mobility transistors (HEMTs) are widely used in high-speed, high-voltage, and high-power applications due to their high breakdown electric field and high electron mobility. In recent years, with the rapid development of consumer electronics and electric vehicles, the demand for high current, high power, and fast charging has been increasing. To achieve high current and high voltage withstand characteristics, the bar-gate multi-finger structure is a commonly used structure. In the bar-gate structure, the cross-sectional treatment of the gate and isolation regions is a key technology. Improper treatment of the gate metal and the active region mesa can easily lead to leakage current, breakdown, and other problems. Furthermore, the high voltage on the drain has a significant impact on the device; high electric fields bring challenges such as leakage current, high power consumption, and reliability issues. Utility Model Content
[0003] The purpose of this invention is to provide a semiconductor device that can solve the problem of leakage current in devices using bar grid structures in the prior art, thereby improving the stability and reliability of the device.
[0004] The embodiments of this utility model are implemented as follows:
[0005] This invention provides a semiconductor device comprising at least one cell, the cell including a source, a drain, and a gate. The gate forms a first closed-loop structure around the source to separate the source and the drain in the stacking direction and in a projection plane perpendicular to the stacking direction. This semiconductor device solves the leakage problem inherent in devices using bar-gate structures in the prior art, thereby improving the stability and reliability of the device.
[0006] In one possible implementation, there are multiple gates, and another gate forms a second closed-loop structure around the drain.
[0007] As one possible implementation, along the gate finger direction, the length of the drain is equal to, greater than, or less than the length of the source.
[0008] As one possible implementation, when the length of the drain is greater than the length of the source, the drain extends from the active region toward the side closer to the isolation region.
[0009] In one possible implementation, there are multiple sources connected by source pads, and the gate is arranged around the multiple sources and the source pads.
[0010] In one possible implementation, there are multiple drains connected by drain pads, with the drain pads positioned opposite to the source pads, or the drain pads arranged around the gate.
[0011] In one possible implementation, the number of gates is equal to or greater than the number of sources.
[0012] As one possible implementation, when the source electrode has a ring structure, the number of gate electrodes is greater than the number of source electrodes, with one gate electrode arranged along the inner periphery of the ring structure and the other gate electrode arranged along the outer periphery of the ring structure.
[0013] As one possible implementation, it also includes a gate field plate electrode, which is disposed around the cell on the projection plane, and the drain and the gate are grounded or coupled to an external power supply through the gate field plate electrode.
[0014] As one possible implementation, the gate field plate electrode is arranged in the active region or the isolation region on the projection plane.
[0015] As one possible implementation, the bend of the first closed-loop structure has a transition structure, and the shape of the transition structure on the projection plane is a fan shape or a trapezoid.
[0016] As one possible implementation, when the transition structure is fan-shaped on the projection plane, the diameter of the fan shape first gradually increases and then gradually decreases.
[0017] The beneficial effects of this utility model embodiment include:
[0018] This semiconductor device includes at least one cell, each cell comprising a source, a drain, and a gate. The gate forms a first closed-loop structure around the source to separate the source and drain in the stacking direction and in a projection plane perpendicular to the stacking direction. As a result, the gate can disrupt the 2DEG along the first closed path, preventing electron leakage from around the ends of the bar-gate structure as is possible in prior art. This ensures good isolation between the source and drain. Therefore, this semiconductor device solves the leakage problem inherent in prior art devices using bar-gate structures, thereby improving the stability and reliability of the device. Attached Figure Description
[0019] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in the first embodiment of the present invention;
[0021] Figure 2 This is a schematic diagram of the structure of the semiconductor device provided in the second embodiment of the present invention;
[0022] Figure 3 This is a schematic diagram of the structure of the semiconductor device provided in the third embodiment of the present invention;
[0023] Figure 4 This is a schematic diagram of the structure of the semiconductor device provided in the fourth embodiment of the present invention;
[0024] Figure 5 This is a schematic diagram of the structure of the semiconductor device provided in the fifth embodiment of the present invention;
[0025] Figure 6 This is a schematic diagram of the structure of the semiconductor device provided in the sixth embodiment of the present invention;
[0026] Figure 7 This is a schematic diagram of the structure of the semiconductor device provided in the seventh embodiment of the present invention;
[0027] Figure 8 This is a schematic diagram of the structure of the semiconductor device provided in the eighth embodiment of the present invention;
[0028] Figure 9 One of the structural schematic diagrams of the first closed-loop structure provided in the embodiment of this utility model;
[0029] Figure 10 A second schematic diagram of the first closed-loop structure provided in this embodiment of the utility model;
[0030] Figure 11 The third schematic diagram of the first closed-loop structure provided in the embodiment of this utility model.
[0031] Icons: 10-Source; 11-Source pad; 20-Drain; 21-Drain pad; 30-Gate; 31-Transition structure; 40-Gate field plate electrode; A-Active region. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0034] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0035] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0036] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0037] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0038] In recent years, GaN-based high electron mobility transistors (HEMTs) have been widely used in many modern electronic devices. Typically, a transistor includes a substrate and an active layer and a passivation layer stacked sequentially on the substrate. Along the stacking direction, the upper surface of the active layer and the lower surface of the passivation layer are in contact, thus forming a heterojunction at the interface between the active layer and the passivation layer. Due to the inherent presence of a two-dimensional electron gas (2DEG) at the heterojunction, electrons can move freely along the interface.
[0039] A 2DEG-based transistor typically includes an active region and an isolation region surrounding the active region. The isolation region has a damaged lattice to disrupt the 2DEG and impede electron movement, thereby confining the 2DEG within the active region. Furthermore, to prevent electrons from flowing between the source and drain located within the active region (i.e., forming a normally-off mode), a gate can be placed within the active region to interrupt the 2DEG and thus prevent free electron movement.
[0040] In existing technologies, a bar-gate structure is typically used, where the gate is a bar-shaped or rectangular "gate finger" that extends across the width of the active region. This allows the movement of electrons between the source and drain to be confined within the active region. However, with technological advancements, more and more engineers have recognized that isolation regions cannot provide complete isolation and may exhibit undesirable leakage currents. Therefore, even with a bar-gate structure, devices are still prone to leakage.
[0041] To solve the above problems, please refer to the following: Figures 1 to 8 This application provides a semiconductor device including at least one cell. Each cell includes a source 10, a drain, and a gate 30. The gate 30 forms a first closed-loop structure around the source 10 to separate the source 10 and the drain in the stacking direction and in a projection plane perpendicular to the stacking direction. This semiconductor device can solve the leakage problem of devices using bar-gate structures in the prior art, thereby improving the stability and reliability of the device.
[0042] It should be noted that the semiconductor device includes at least one cell, and each cell includes at least one source 10, at least one drain, and at least one gate 30, such as... Figure 1 As shown, on the projection plane, the gate 30 is arranged around the source 10 along a first closed path, so that the first closed-loop structure formed by the gate 30 encloses the source 10. In this way, the gate 30 can disrupt the 2DEG along the first closed path, and unlike the bar grid structure in the prior art, electrons will not leak from around the ends of the bar grid structure, thus ensuring that the gate 30 can provide a good isolation effect between the source 10 and the drain.
[0043] Those skilled in the art should understand that although the accompanying drawings show only schematic diagrams of the semiconductor device along the projection direction (i.e., top views) and do not provide schematic diagrams of the semiconductor device along the stacking direction, it should be emphasized that the gate 30 described above can not only separate the source 10 and the drain on the projection plane, but also separate the source 10 and the drain in the stacking direction, thereby ensuring that the gate 30 can provide good isolation between the source 10 and the drain.
[0044] Compared to the existing bar grid structure, the ring source structure (i.e., the gate 30 is arranged around the source 10) provided in this application can prevent electrons from leaking from the ends of the bar grid structure, thereby increasing the current density of the device and reducing the physical area of the chip. Compared to the existing ring drain structure (i.e., the gate 30 is arranged around the drain), the ring source structure (i.e., the gate 30 is arranged around the source 10) provided in this application has a low electric field inside, and there is no high voltage electric field concentration at the radius of curvature.
[0045] Furthermore, regarding the specific shapes of the source 10 and drain mentioned above, the accompanying drawings are for illustrative purposes only and are not intended to limit their application. Those skilled in the art should be able to make reasonable selections and designs based on actual conditions; no specific limitations are imposed here. For example, the source 10 can be a regular shape such as circular, square, rectangular, annular, sawtooth, or gourd-shaped, or other irregular shapes. The first closed-loop structure formed by the gate 30 only needs to be able to enclose the source 10. Regarding the specific shape of the gate 30 mentioned above, the accompanying drawings are for illustrative purposes only and are not intended to limit its application. Additionally, the ring-source structure provided in this application is applicable to D-mode and E-mode HEMTs.
[0046] As one possible implementation method, such as Figure 2 As shown, there are multiple gates 30, and another gate 30 forms a second closed-loop structure around the drain. That is, each cell includes at least one source 10, at least one drain, and at least two gates 30, one of which is arranged around at least one source 10 to form a first closed-loop structure, and the other gate 30 is arranged around at least one drain to form a second closed-loop structure, so as to further improve the isolation effect between the source 10 and the drain through the two gates 30.
[0047] Furthermore, the aforementioned arrangement of both source and drain can increase the grid width density, thereby further improving the current density of the device. The distribution of battery strength can also be more uniform, without the phenomenon of electric field concentration in a certain area, and can achieve lower leakage current and high voltage resistance.
[0048] As one possible implementation, along the gate finger direction (i.e., the width direction of the active region A mentioned above), the length of the drain can be equal to, greater than, or less than the length of the source 10. Those skilled in the art should be able to make reasonable selections and designs based on actual circumstances; no specific limitations are imposed here. For example, such as... Figure 1 and Figure 2 As shown, the length of the drain is equal to the length of the source 10.
[0049] For example, such as Figure 3 As shown, the length of the drain is greater than the length of the source 10. In this case, as one possible implementation, such as Figure 3 As shown, when the length of the drain is greater than the length of the source 10, the drain can extend from the active region A toward the side closer to the isolation region and into the isolation region. That is, the ohmic groove of the drain not only penetrates the active region A but also extends into the isolation region. This reduces the accumulation concentration of the 2DEG at the curvature radius head of the gate 30, reduces the impact of electrons on the gate 30 head, and improves withstand voltage and reliability. Of course, in other embodiments, when the length of the drain is greater than the length of the source 10, the drain can also extend from the active region A toward the side closer to the isolation region, but not into the isolation region. Those skilled in the art should be able to make reasonable choices and designs based on actual conditions; no specific limitations are made here.
[0050] As one possible implementation method, such as Figure 4 As shown, each cell can contain multiple source electrodes 10, which are connected by source pads 11. The gate 30 is arranged around the multiple source electrodes 10 and source pads 11. In this case, the actual shape of the gate 30 should be similar to the shape of the irregular structure formed by the multiple source electrodes 10 and source pads 11. Regarding the actual number of source electrodes 10, those skilled in the art should be able to make reasonable selections and designs based on the actual situation, and no specific restrictions are imposed here.
[0051] As one possible implementation method, such as Figure 4 As shown, the number of drains in each cell can also be multiple, and the multiple drains are connected through drain pads 21. The drain pads 21 are arranged opposite to the source pads 11, or, as... Figure 5 As shown, the drain pad 21 is arranged around the gate 30, which can increase the gate width density.
[0052] As one possible implementation method, such as Figure 1 and Figure 3 As shown, the number of gates 30 is equal to the number of sources 10; Figure 6 and Figure 7 As shown, the number of gates 30 is greater than the number of sources 10. As one possible implementation, such as... Figure 6 and Figure 7As shown, when the source 10 itself has a closed ring structure, the number of gates 30 should be greater than the number of sources 10, so that one gate 30 is arranged along the inner periphery of the ring structure and the other gate 30 is arranged along the outer periphery of the ring structure, so as to wrap the source 10 from the inner and outer peripheries.
[0053] Because the drain is located near the isolation region, a high electric field accumulates at the edge of the active region A during high-voltage operation, causing charge accumulation and adsorption at the chip edge. To solve this problem, one possible solution is... Figure 8 As shown, the semiconductor device also includes a gate field plate electrode 40. On the projection plane, the gate field plate electrode 40 is arranged around multiple cells. The drain and gate 30 are directly grounded or coupled to an external power supply through the gate field plate electrode 40. By increasing the gate field plate electrode 40, the electric field concentration phenomenon at the chip edge in the semiconductor device caused by the application of drain voltage can be reduced.
[0054] As one possible implementation, the gate field plate electrode 40 is disposed within the active region A or the isolation region on the projection plane. For example, as... Figure 8 As shown, the gate field plate electrode 40 is arranged in the active region A.
[0055] As one possible implementation, the bend of the first closed-loop structure has a transition structure 31, and the shape of the transition structure 31 on the projection plane is fan-shaped (e.g., Figure 9 and Figure 10 ) or trapezoidal (e.g.) Figure 11 For example, such as Figure 11 As shown, when the transition structure 31 is fan-shaped on the projection plane, the diameter of the fan can gradually increase first and then gradually decrease.
[0056] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.
[0057] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable way without contradiction. In order to avoid unnecessary repetition, this utility model will not describe the various possible combinations separately.
Claims
1. A semiconductor device, characterized by, It includes at least one cell, the cell including a source, a drain and a gate, the gate forming a first closed-loop structure around the source to separate the source and the drain in the stacking direction and in a projection plane perpendicular to the stacking direction.
2. The semiconductor device according to claim 1, wherein The number of gates is multiple, and another gate forms a second closed-loop structure around the drain.
3. The semiconductor device of claim 1, wherein Along the gate finger direction, the length of the drain is equal to, greater than, or less than the length of the source.
4. The semiconductor device according to claim 3, wherein When the length of the drain is greater than the length of the source, the drain extends from the active region toward the side closer to the isolation region.
5. The semiconductor device of claim 1, wherein, The number of sources is multiple, and the multiple sources are connected by source pads. The gate is arranged around the multiple sources and the source pads.
6. The semiconductor device according to claim 5, wherein The number of drains is multiple, and the multiple drains are connected by drain pads. The drain pads are arranged opposite to the source pads, or the drain pads are arranged around the gate.
7. The semiconductor device of claim 1, wherein The number of gates is equal to or greater than the number of sources.
8. The semiconductor device of claim 7, wherein, When the source electrode has a ring structure, the number of gate electrodes is greater than the number of source electrodes, with one gate electrode arranged along the inner periphery of the ring structure and the other gate electrode arranged along the outer periphery of the ring structure.
9. The semiconductor device of claim 1, wherein, It also includes a gate field plate electrode, which is arranged around the cell on the projection plane, and the drain and the gate are grounded or coupled to an external power supply through the gate field plate electrode.
10. The semiconductor device of claim 9, wherein, On the projection plane, the gate field plate electrodes are arranged in the active region or the isolation region.
11. The semiconductor device according to any one of Claims 1 to 10, wherein The first closed-loop structure has a transition structure at the bend, and the shape of the transition structure on the projection plane is either fan-shaped or trapezoidal.
12. The semiconductor device of claim 11, wherein, When the transition structure is fan-shaped on the projection plane, the diameter of the fan shape first gradually increases and then gradually decreases.