Display substrate, pixel circuit and display device

Abstract

The utility model provides a display substrate, a pixel circuit and a display device. The display substrate comprises a substrate; a plurality of pixel driving circuits; each light-emitting device comprises a light-emitting layer, a first light-emitting functional layer and a second light-emitting functional layer, and the first light-emitting functional layer and the second light-emitting functional layer are located on the two sides of the light-emitting layer respectively; the display substrate comprises a plurality of sub-pixels, and each sub-pixel comprises a light-emitting device and a pixel driving circuit electrically connected with the light-emitting device. The plurality of sub-pixels comprise at least one sub-pixel group, the sub-pixel group comprises at least two light-emitting devices and a pixel driving circuit, and the two light-emitting devices are electrically connected with the same pixel driving circuit; the sub-pixel group comprises at least one first sub-pixel and at least one second sub-pixel, in the light-emitting device of the first sub-pixel, the first light-emitting functional layer is located on the side, close to the substrate, of the light-emitting layer, and in the light-emitting device of the second sub-pixel, the second light-emitting functional layer is located on the side, close to the substrate, of the light-emitting layer.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a display substrate, pixel circuit and display device. Background Technology

[0002] Micro light-emitting diodes (LEDs) are light-emitting diodes with dimensions on the micrometer scale. Due to their small size, Micro LEDs can be used as pixels on display panels, and display panels made using Micro LEDs are called Micro LED display panels. Micro LED technology involves miniaturizing existing LEDs to below 100µm, approximately 1% of the current LED size, and then using mass transfer technology to transfer these micrometer-sized Micro / mini-LEDs onto a driving substrate, thereby forming Micro LED displays of various sizes. Improving the resolution of Micro LED displays is one of the important research topics for researchers.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this utility model. Therefore, the above information may include information that does not constitute prior art. Utility Model Content

[0004] In one aspect, a display substrate is provided, comprising:

[0005] Substrate;

[0006] A driving circuit layer, located on the substrate, includes a plurality of pixel driving circuits; and

[0007] A light-emitting device layer is located on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices, which are electrically connected to the driving circuit layer. Each light-emitting device includes a light-emitting layer, a first light-emitting functional layer, a second light-emitting functional layer, a first electrode, and a second electrode. The substrate has a first surface facing the driving circuit layer. Along a direction perpendicular to the first surface, the first light-emitting functional layer and the second light-emitting functional layer are located on opposite sides of the light-emitting layer. The first electrode is located on the side of the first light-emitting functional layer away from the light-emitting layer, and the second electrode is located on the side of the second light-emitting functional layer away from the light-emitting layer.

[0008] The display substrate includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device;

[0009] The plurality of said sub-pixels include at least one sub-pixel group, the sub-pixel group including at least two said light-emitting devices and one said pixel driving circuit, the two said light-emitting devices being electrically connected to the same said pixel driving circuit; and

[0010] The sub-pixel group includes at least one first sub-pixel and at least one second sub-pixel. In the light-emitting device of the at least one first sub-pixel, the first light-emitting functional layer is located on the side of the light-emitting layer closer to the substrate. In the light-emitting device of the at least one second sub-pixel, the second light-emitting functional layer is located on the side of the light-emitting layer closer to the substrate.

[0011] According to some exemplary embodiments, in at least one of the said sub-pixel groups, the emitted light color of at least one first sub-pixel is the same as the emitted light color of at least one second sub-pixel; and / or,

[0012] In at least one of the sub-pixel groups, the emitted light color of at least one first sub-pixel is different from the emitted light color of at least one second sub-pixel.

[0013] According to some exemplary embodiments, in at least one of the sub-pixel groups, the light-emitting devices of at least one first sub-pixel and at least one second sub-pixel are arranged adjacent to each other along a first direction; and / or,

[0014] In at least one of the sub-pixel groups, the light-emitting devices of at least one first sub-pixel and the light-emitting devices of at least one second sub-pixel are arranged adjacent to each other along a second direction, wherein the first direction intersects the second direction.

[0015] According to some exemplary embodiments, the plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels, wherein the emitted light colors of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are different from each other;

[0016] The plurality of sub-pixels include a plurality of pixel units arranged along a first direction and a second direction. Each pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel arranged along the first direction. The second color sub-pixel is located between the first color sub-pixel and the third color sub-pixel.

[0017] In at least one of the pixel units, at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel belongs to the sub-pixel group.

[0018] According to some exemplary embodiments, at least one of the sub-pixel groups includes at least one first sub-pixel group, the first sub-pixel group including two first color sub-pixels adjacent along the second direction; and / or,

[0019] At least one of the sub-pixel groups includes at least one second sub-pixel group, the second sub-pixel group comprising two adjacent second color sub-pixels along the second direction; and / or,

[0020] At least one of the sub-pixel groups includes at least one third sub-pixel group, the third sub-pixel group including two adjacent third color sub-pixels along the second direction.

[0021] According to some exemplary embodiments, two adjacent pixel units along the second direction include a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group.

[0022] According to some exemplary embodiments, at least one of the sub-pixel groups includes at least one fourth sub-pixel group, the fourth sub-pixel group including a first-color sub-pixel and a second-color sub-pixel adjacent along the first direction; and / or,

[0023] At least one of the sub-pixel groups includes at least one fifth sub-pixel group, the fifth sub-pixel group including a first-color sub-pixel and a third-color sub-pixel adjacent along the first direction; and / or,

[0024] At least one of the sub-pixel groups includes at least one sixth sub-pixel group, the sixth sub-pixel group including a second color sub-pixel and a third color sub-pixel that are adjacent along the first direction.

[0025] According to some exemplary embodiments, two adjacent pixel units along the first direction include a fourth sub-pixel group, a fifth sub-pixel group, and a sixth sub-pixel group.

[0026] According to some exemplary embodiments, in one pixel unit, the pixel driving circuit in the first color sub-pixel is electrically connected only to the light-emitting device in the first color sub-pixel, and the light-emitting devices in the second color sub-pixel and the light-emitting devices in the third color sub-pixel are electrically connected to the same pixel driving circuit.

[0027] According to some exemplary embodiments, two adjacent pixel units along the second direction include two sixth sub-pixel groups and a first sub-pixel group, wherein the first sub-pixel group includes two first color sub-pixels that are adjacent along the second direction.

[0028] According to some exemplary embodiments, the plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels, wherein the emitted light colors of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are different from each other;

[0029] The plurality of said sub-pixels include a plurality of pixel units arranged along a first direction and a second direction, each pixel unit including two first color sub-pixels, at least one second color sub-pixel, and at least one third color sub-pixel, wherein two first color sub-pixels are arranged adjacent to each other along the first direction or the second direction; and

[0030] At least one of the sub-pixel groups includes a seventh sub-pixel group, the seventh sub-pixel group including two adjacent first color sub-pixels, and at least one of the pixel units includes the seventh sub-pixel group.

[0031] According to some exemplary embodiments, two first color sub-pixels are arranged adjacently along the first direction, a second color sub-pixel is located on one side of the two first color sub-pixels along the first direction, and a third color sub-pixel is located on the side of the second color sub-pixels away from the first color sub-pixels; and

[0032] The seventh sub-pixel group includes two adjacent sub-pixels of the first color along the first direction.

[0033] According to some exemplary embodiments, in at least one of the pixel units, the pixel driving circuit in the second color sub-pixel is electrically connected only to the light-emitting device in that second color sub-pixel; and / or,

[0034] In at least one of the pixel units, the pixel driving circuit in the third color sub-pixel is electrically connected only to the light-emitting device in the third color sub-pixel.

[0035] According to some exemplary embodiments, at least one of the pixel units includes a sixth sub-pixel group, the sixth sub-pixel group including a second color sub-pixel and a third color sub-pixel adjacent along the first direction.

[0036] According to some exemplary embodiments, two adjacent pixel units along the second direction comprise a second sub-pixel group, the second sub-pixel group comprising two adjacent second color sub-pixels along the second direction; and / or,

[0037] Two adjacent pixel units along the second direction comprise a third sub-pixel group, the third sub-pixel group comprising two adjacent third color sub-pixels along the second direction.

[0038] According to some exemplary embodiments, in the light-emitting device of the first sub-pixel, the first light-emitting functional layer includes a P-type semiconductor layer, and the second light-emitting functional layer includes an N-type semiconductor layer.

[0039] In the light-emitting device of the second sub-pixel, the second light-emitting functional layer includes an N-type semiconductor layer, and the first light-emitting functional layer includes a P-type heavily doped semiconductor layer and an N-type heavily doped semiconductor layer located on the side of the P-type heavily doped semiconductor layer away from the substrate; and

[0040] The second electrode of the first sub-pixel and the first electrode of the second sub-pixel are located in the same layer.

[0041] According to some exemplary embodiments, in the light-emitting device of the first sub-pixel, the first light-emitting functional layer includes a P-type semiconductor layer, and the second light-emitting functional layer includes an N-type heavily doped semiconductor layer and a P-type heavily doped semiconductor layer located on the side of the N-type heavily doped semiconductor layer away from the substrate.

[0042] In the light-emitting device of the second sub-pixel, the second light-emitting functional layer includes an N-type semiconductor layer, and the first light-emitting functional layer includes a P-type semiconductor layer; and

[0043] The second electrode of the first sub-pixel and the first electrode of the second sub-pixel are located in the same layer.

[0044] According to some exemplary embodiments, the light-emitting device layer includes a top electrode layer, a second electrode of the first sub-pixel and a first electrode of the second sub-pixel are located in the top electrode layer, and the material of the top electrode layer includes a transparent conductive material.

[0045] According to some exemplary embodiments, the orthogonal projection of the top electrode layer on the substrate covers the orthogonal projection of the light-emitting layer on the substrate; and

[0046] The display substrate further includes an auxiliary electrode located on the side of the top electrode layer away from the substrate. The auxiliary electrode is electrically connected to the top electrode layer, and the orthographic projection of the auxiliary electrode on the substrate is spaced apart from the orthographic projection of the light-emitting layer on the substrate.

[0047] According to some exemplary embodiments, the light-emitting device of the first color sub-pixel emits light of a first color, the light-emitting device of the second color sub-pixel emits light of a second color, and the light-emitting device of the third color sub-pixel emits light of a third color.

[0048] According to some exemplary embodiments, the light-emitting devices of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel emit light of the same color respectively.

[0049] The display substrate further includes a color conversion layer located on the side of the light-emitting device layer away from the substrate. The color conversion layer includes a first color conversion portion located on the side of the light-emitting device of the first color sub-pixel away from the substrate, a second color conversion portion located on the side of the light-emitting device of the second color sub-pixel away from the substrate, and a third color conversion portion located on the side of the light-emitting device of the third color sub-pixel away from the substrate.

[0050] The light emitted by the light-emitting device becomes a first color after passing through the first color conversion section, the light emitted by the light-emitting device becomes a second color after passing through the second color conversion section, and the light emitted by the light-emitting device becomes a third color after passing through the third color conversion section.

[0051] In another aspect, a pixel circuit is provided, the pixel circuit including a pixel driving circuit, at least two light-emitting devices, and a second power signal terminal;

[0052] The light-emitting device includes a first electrode and a second electrode; and

[0053] The at least two light-emitting devices include at least one first light-emitting device and at least one second light-emitting device. The first electrode of the first light-emitting device is electrically connected to the pixel driving circuit, the second electrode of the first light-emitting device is electrically connected to the second power signal terminal, the second electrode of the second light-emitting device is electrically connected to the pixel driving circuit, and the first electrode of the second light-emitting device is electrically connected to the second power signal terminal.

[0054] In another aspect, a display device is provided, the display device comprising a display substrate or the aforementioned pixel circuit according to any one of the preceding claims. Attached Figure Description

[0055] Other objects and advantages of the present invention will become apparent from the following description of the invention with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the invention.

[0056] Figures 1A-1C The diagram schematically illustrates the fabrication process of a display substrate in the related art.

[0057] Figure 2 A schematic plan view of a display substrate according to some embodiments of the present invention is shown.

[0058] Figure 3 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0059] Figure 4 Schematic illustration along Figure 3 A cross-sectional view taken along the centerline B-B'.

[0060] Figure 5 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0061] Figure 6A Schematic illustration along Figure 5 A cross-sectional view taken along the centerline C1-C1'.

[0062] Figure 6B Schematic illustration along Figure 5 A cross-sectional view taken from the centerline C2-C2'.

[0063] Figure 6C Schematic illustration along Figure 5 A cross-sectional view taken along the centerline C3-C3'.

[0064] Figure 7 The schematic diagram illustrates the working principle of a tunnel junction light-emitting diode.

[0065] Figure 8 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0066] Figure 9 Schematic illustration along Figure 8 A cross-sectional view taken along the centerline D-D'.

[0067] Figure 10 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0068] Figure 11A Schematic illustration along Figure 10 A cross-sectional view taken from the centerline E1-E1'.

[0069] Figure 11B Schematic illustration along Figure 10 A cross-sectional view taken from the centerline E2-E2'.

[0070] Figure 11C Schematic illustration along Figure 10 A cross-sectional view taken from the centerline E3-E3'.

[0071] Figure 12 An equivalent circuit diagram of a pixel circuit according to some embodiments of the present invention is shown schematically.

[0072] Figure 13A schematic diagram of the driving timing of a pixel circuit according to some embodiments of the present invention is shown.

[0073] Figure 14 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0074] Figure 15 Schematic illustration along Figure 14 A cross-sectional view taken along the centerline F-F'.

[0075] Figure 16 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0076] Figure 17 Schematic illustration along Figure 16 A cross-sectional view taken along the midline G-G'.

[0077] Figure 18 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0078] Figure 19 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A2.

[0079] Figure 20 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A3.

[0080] Figure 21 Schematic illustration along Figure 20 A cross-sectional view taken along the midline H-H'.

[0081] Figure 22 The brightness-temperature curves of different colored light-emitting diodes are schematically shown.

[0082] Figure 23 A schematic diagram of the driving timing of a pixel circuit according to some embodiments of the present invention is shown.

[0083] Figure 24 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A3.

[0084] Figure 25 Schematic illustration along Figure 24 A cross-sectional view taken along the centerline I-I'.

[0085] Figure 26 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A3.

[0086] Figure 27 A flowchart illustrating a method for fabricating a display substrate according to some embodiments of the present invention is shown.

[0087] Figures 28A-28O The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0088] Figures 29A-29C The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0089] Figures 30A-30O The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0090] Figures 31A-31O The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0091] Figures 32A-32H The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0092] Figures 33A-33H The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0093] Figures 34A-34J The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0094] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the drawings used to describe embodiments of the present invention may be enlarged or reduced, i.e., these drawings are not drawn to actual scale. Detailed Implementation

[0095] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0096] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0097] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements present. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this invention, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed related terms.

[0098] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0099] In this article, inorganic light-emitting diodes (LEDs) refer to light-emitting elements made using inorganic materials. LEDs specifically represent inorganic light-emitting elements distinct from OLEDs. Specifically, inorganic light-emitting elements can include miniature LEDs (Mini Light Emitting Diodes) and micro LEDs (Micro Light Emitting Diodes). Micro LEDs are ultra-small LEDs with a die size of less than 100 micrometers, while miniature LEDs are small LEDs with a die size between Micro LEDs and traditional LEDs; for example, the die size of a Mini LED can be between 50 and 400 micrometers. PPI (Pixels Per Inch) represents the number of pixels per inch.

[0100] Figures 1A-1C The diagram schematically illustrates the fabrication process of a display substrate in the related art.

[0101] In related technologies, the fabrication process of a display substrate includes the following steps:

[0102] Reference Figure 1A Multiple pixel driving circuits 210' are formed on the substrate 100', and the multiple pixel driving circuits 210' are arranged in an array on the substrate 100'.

[0103] Combined with reference Figure 1A and Figure 1B Multiple bonding pads 410' are formed on the side of the multiple pixel driving circuits 210' away from the substrate 100', and the multiple bonding pads 410' are electrically connected to the multiple pixel driving circuits 210' one by one.

[0104] Combined with reference Figure 1A , Figure 1B and Figure 1C Multiple light-emitting devices (LEDs) are formed on the side of multiple bonding pads 410' away from the substrate 100'. The multiple light-emitting devices (LEDs) are electrically connected to the multiple bonding pads 410' one by one. Each light-emitting device (LED) is electrically connected to a pixel driving circuit 210' through a bonding pad 410'.

[0105] The inventors discovered through research that the display substrate prepared by this process is difficult to achieve a high resolution. In order to achieve a breakthrough in display resolution, the inventors designed the structure of the display substrate.

[0106] Figure 2A schematic plan view of a display substrate according to some embodiments of the present invention is shown. Figure 3 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1. Figure 4 Schematic illustration along Figure 3 A cross-sectional view taken along the centerline B-B'.

[0107] According to some exemplary embodiments, in conjunction with reference to Figure 2 , Figure 3 and Figure 4 The display substrate includes a display area AA and a peripheral area NA located around the display area AA. Within the display area AA, a plurality of sub-pixels SP are arranged at intervals along a first direction X and a second direction Y.

[0108] The display substrate includes a substrate 100, a driving circuit layer 200, and a light-emitting device layer 300. The driving circuit layer 200 is located on the substrate 100 and includes multiple pixel driving circuits 210 located within the display area AA. The light-emitting device layer 300 is located on the side of the driving circuit layer 200 away from the substrate 100 and includes multiple light-emitting devices (LEDs), each of which is electrically connected to the driving circuit layer 200. A sub-pixel SP includes one LED and a pixel driving circuit 210 electrically connected to that LED.

[0109] The light-emitting device LED includes a light-emitting functional layer 310, a first electrode 320, and a second electrode 330. The light-emitting functional layer 310 includes a light-emitting layer 311, a first light-emitting functional layer 312, and a second light-emitting functional layer 313. The substrate 100 has a first surface 100a facing the driving circuit layer 200. Along a direction perpendicular to the first surface 100a, the first light-emitting functional layer 312 and the second light-emitting functional layer 313 are located on opposite sides of the light-emitting layer 311. The first electrode 320 is located on the side of the first light-emitting functional layer 312 away from the light-emitting layer 311, and the second electrode 330 is located on the side of the second light-emitting functional layer 313 away from the light-emitting layer 311.

[0110] For example, the light-emitting device LED may include a light-emitting diode, the first light-emitting functional layer 312 may include a P-type semiconductor layer, the first electrode 320 may include a P-electrode material, the second light-emitting functional layer 313 may include an N-type semiconductor layer, and the first electrode 320 may include an N-electrode material. The light-emitting layer 311 may include a multiple quantum well (MQW) structure.

[0111] For example, the material of the P-type semiconductor layer may include P-GaN, and optionally, P-GaN may be Mg-doped GaN.

[0112] For example, the material of the N-type semiconductor layer may include P-GaN, and optionally, N-GaN may be Si-doped GaN.

[0113] For example, when an LED emits light, current flows from the first electrode to the second electrode.

[0114] Combined with reference Figure 2 , Figure 3 and Figure 4 The plurality of sub-pixels SP includes at least one sub-pixel group SPX, and the sub-pixel group SPX includes at least two light-emitting devices (LEDs) and a pixel driving circuit 210. The at least two light-emitting devices (LEDs) are electrically connected to the same pixel driving circuit 210. The sub-pixel group SPX includes at least one first sub-pixel SPA and at least one second sub-pixel SPB. In the light-emitting devices (LEDs) of the at least one first sub-pixel SPA, a first light-emitting functional layer 312 is located on the side of the light-emitting layer 311 near the substrate 100. In the light-emitting devices (LEDs) of the at least one second sub-pixel SPB, a second light-emitting functional layer 313 is located on the side of the light-emitting layer 311 near the substrate 100.

[0115] It should be noted that, in order to simplify the description, the following description uses the example of a subpixel group SPX including a first subpixel SPA and a second subpixel SPB to illustrate the embodiments of the present invention. However, the following exemplary description should not be construed as a limitation on the embodiments of the present invention. In the embodiments of the present invention, the number of first subpixels SPA and second subpixels SPB included in the subpixel group SPX is not particularly limited.

[0116] In a sub-pixel group SPX, the light-emitting diodes (LEDs) of the first sub-pixel SPA and the second sub-pixel SPB are electrically connected to the same pixel driving circuit 210. The film layer stacking order of the LEDs in the first sub-pixel SPX is reversed compared to that in the second sub-pixel SPB. This allows the LEDs of the first sub-pixel SPA and the second sub-pixel SPB to be illuminated in a time-division manner by controlling the driving signal of the pixel driving circuit 210. The specific driving method is described later. This reduces the number of pixel driving circuits 210, which is beneficial for achieving higher resolution.

[0117] According to some exemplary embodiments, in conjunction with reference to Figure 3 and Figure 4The display substrate also includes a bonding layer 400, which is located between the driving circuit layer 200 and the light-emitting device layer 300. The bonding layer 400 includes a plurality of bonding pads 410 arranged at intervals. A sub-pixel group SPX includes a bonding pad 410, and the light-emitting device LED of the first sub-pixel SPA and the light-emitting device LED of the second sub-pixel SPB are electrically connected to a pixel driving circuit 210 through a bonding pad 410.

[0118] According to some exemplary embodiments, in conjunction with reference to Figure 3 and Figure 4 In the LED light-emitting device of the first sub-pixel SPA, the first light-emitting functional layer 312 includes a P-type semiconductor layer PSL, and the second light-emitting functional layer 313 includes an N-type semiconductor layer NSL. A first electrode 320 is located on the side of the first light-emitting functional layer 312 closest to the substrate 100. The first electrode 320 may include a first sub-layer 321 located on the bonding pad 410 and a second sub-layer 322 located between the first sub-layer 321 and the first light-emitting functional layer 312. The first sub-layer 321 is bonded to the bonding pad 410, and the second sub-layer 322 includes a P-electrode material. A second electrode 330 is located on the side of the second light-emitting functional layer 313 furthest from the substrate 100, and the second electrode 330 includes an N-electrode material.

[0119] In the LED light-emitting device of the second sub-pixel SPB, the first light-emitting functional layer 312 includes a P-type semiconductor layer PSL, and the second light-emitting functional layer 313 includes an N-type semiconductor layer NSL. The second electrode 330 is located on the side of the second light-emitting functional layer 313 closest to the substrate 100. The second electrode 330 may include a third sub-layer 311 located on the bonding pad 410 and a fourth sub-layer 312 located between the third sub-layer 311 and the second light-emitting functional layer 313. The third sub-layer 311 is bonded to the bonding pad 410, and the fourth sub-layer 312 includes an N-electrode material. The first electrode 320 is located on the side of the first light-emitting functional layer 312 furthest from the substrate 100, and the first electrode 320 includes a P-electrode material.

[0120] Since the material of the second electrode 330 of the first sub-pixel SPA is different from the material of the first electrode 320 of the second sub-pixel SPB, the second electrode 330 of the first sub-pixel SPA and the first electrode 320 of the second sub-pixel SPB are formed by two processes.

[0121] For example, the P electrode material may include at least one of indium tin oxide, gold, and platinum.

[0122] For example, the N electrode material may include at least one of titanium, titanium nitride, and aluminum.

[0123] For example, the material of the first sub-layer 321 of the first electrode 320 of the first sub-pixel SPA may include at least one of copper, gold, chromium, tin, nickel, aluminum and silver.

[0124] For example, the material of the third sub-layer 331 of the second electrode 330 of the second sub-pixel SPB may include at least one of copper, gold, chromium, tin, nickel, aluminum and silver.

[0125] Figure 5 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1. Figure 6A Schematic illustration along Figure 5 A cross-sectional view taken along the centerline C1-C1'. Figure 6B Schematic illustration along Figure 5 A cross-sectional view taken from the centerline C2-C2'. Figure 6C Schematic illustration along Figure 5 A cross-sectional view taken along the centerline C3-C3'. Figure 7 The schematic diagram illustrates the working principle of a tunnel junction light-emitting diode.

[0126] According to some exemplary embodiments, in conjunction with reference to Figure 5 and Figure 6A In the LED light-emitting device of the first sub-pixel SPA, the first light-emitting functional layer 312 includes a P-type semiconductor layer PSL, and the second light-emitting functional layer 313 includes an N-type semiconductor layer NSL. A first electrode 320 is located on the side of the first light-emitting functional layer 312 closest to the substrate 100. The first electrode 320 may include a first sub-layer 321 located on the bonding pad 410 and a second sub-layer 322 located between the first sub-layer 321 and the first light-emitting functional layer 312. The first sub-layer 321 is bonded to the bonding pad 410, and the second sub-layer 322 includes a P-electrode material. A second electrode 330 is located on the side of the second light-emitting functional layer 313 furthest from the substrate 100, and the second electrode 330 includes an N-electrode material.

[0127] In the LED light-emitting device of the second sub-pixel SPB, the second light-emitting functional layer 313 includes an N-type semiconductor layer NSL, and the first light-emitting functional layer 312 includes a P-type heavily doped semiconductor layer P++ and an N-type heavily doped semiconductor layer N++ located on the side of the P-type heavily doped semiconductor layer P++ away from the substrate 100. The second electrode 330 is located on the side of the second light-emitting functional layer 313 closest to the substrate 100. The second electrode 330 may include a third sub-layer 331 located on the bonding pad 410 and a fourth sub-layer 332 located between the third sub-layer 331 and the second light-emitting functional layer 313. The third sub-layer 331 is bonded to the bonding pad 410, and the fourth sub-layer 332 includes N-electrode material. The first electrode 320 is located on the side of the first light-emitting functional layer 312 away from the substrate 100, and the first electrode 320 includes N-electrode material.

[0128] The second electrode 330 of the light-emitting device LED of the first sub-pixel SPA and the first electrode 320 of the light-emitting device LED of the second sub-pixel SPB are made of the same material. The second electrode 330 of the first sub-pixel SPA and the first electrode 320 of the second sub-pixel SPB can be located in the same layer. For ease of description, the layer in which the second electrode 330 of the first sub-pixel SPA and the first electrode 320 of the second sub-pixel SPB are located is called the top electrode layer 500.

[0129] By setting the first light-emitting functional layer 312 of the second sub-pixel SPB to have a tunnel junction structure, the second electrode 330 of the light-emitting device LED of the first sub-pixel SPB and the first electrode 320 of the light-emitting device LED of the second sub-pixel SPB can be located on the same layer, thereby saving one film deposition process and patterning process.

[0130] For example, the material of the heavily doped P-type semiconductor layer includes P-GaN, and the doping concentration of the heavily doped P-type semiconductor layer is greater than that of a typical P-type semiconductor layer. Optionally, the doping concentration of the heavily doped P-type semiconductor layer is greater than or equal to 10¹⁰. 8 cm.

[0131] For example, the material of the heavily doped N-type semiconductor layer includes N-GaN, and the doping concentration of the heavily doped N-type semiconductor layer is greater than that of the N-type semiconductor layer. Optionally, the doping concentration of the heavily doped N-type semiconductor layer is greater than or equal to 10¹. 8 cm.

[0132] Reference Figure 7 In a light-emitting diode with a tunnel junction, when the applied bias voltage reaches a certain value, electrons tunnel from the valence band of the heavily doped N-type semiconductor layer to the conduction band of the heavily doped P-type semiconductor layer, ultimately enabling holes to be effectively injected into the active region of the light-emitting device.

[0133] According to some exemplary embodiments, in conjunction with reference to Figure 5 and Figure 6A The display substrate also includes a second light-emitting functional layer 313 of the light-emitting device LED of the first sub-pixel SPA, a first light-emitting functional layer 312 of the light-emitting device LED of the second sub-pixel SPB, and a planarization layer PLN between the top electrode layer 500. The planarization layer PLN has a first via VH1 and a second via VH2. The top electrode layer 500 contacts the second light-emitting functional layer 313 of the light-emitting device LED of the first sub-pixel SPA through the first via VH1, and contacts the first light-emitting functional layer 312 of the light-emitting device LED of the second sub-pixel SPB through the second via VH2.

[0134] According to some exemplary embodiments, in conjunction with reference to Figure 5 and Figure 6A The material of the top electrode layer 500 includes N-electrode materials. For example, it may include at least one of titanium, titanium nitride, and aluminum. The top electrode layer 500 is a light-blocking structure. To avoid the top electrode layer 500 blocking the light emission of the light-emitting device LED, the orthographic projection of the top electrode layer 500 on the substrate 100 and the orthographic projection of the light-emitting functional layer 310 on the substrate 100 only partially overlap. The overlap area is small, ensuring that the top electrode layer 500 and the second light-emitting functional layer 313 of the light-emitting device LED of the first sub-pixel SPA and the first light-emitting functional layer 312 of the light-emitting device LED of the second sub-pixel SPB can make contact.

[0135] According to some exemplary embodiments, in conjunction with reference to Figure 5 and Figure 6A The top electrode layer 500 includes an electrode body portion 510 and a plurality of electrode connection portions 520 connected to the electrode body portion 510. The orthographic projection of the electrode body portion 510 on the substrate 100 is located in the interval region between the orthographic projections of the plurality of light-emitting functional layers 310 on the substrate 100. The orthographic projections of the electrode connection portions 520 on the substrate 100 overlap with the orthographic projections of the light-emitting functional layers 310 on the substrate 100, and the plurality of electrode connection portions 520 respectively contact the light-emitting functional layers 310 of the plurality of light-emitting devices LEDs.

[0136] Figure 8 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1. Figure 9 Schematic illustration along Figure 8 A cross-sectional view taken along the centerline D-D'.

[0137] According to some exemplary embodiments, in conjunction with reference to Figure 8 and Figure 9In the LED light-emitting device of the first sub-pixel SPA, the first light-emitting functional layer 312 includes a P-type semiconductor layer PSL, and the second light-emitting functional layer 313 includes an N-type heavily doped semiconductor layer N++ and a P-type heavily doped semiconductor layer P++ located on the side of the N-type heavily doped semiconductor layer N++ away from the substrate 100. A first electrode 320 is located on the side of the first light-emitting functional layer 312 closest to the substrate 100. The first electrode 320 may include a first sub-layer 321 located on the bonding pad 410 and a second sub-layer 322 located between the first sub-layer 321 and the first light-emitting functional layer 312. The first sub-layer 321 is bonded to the bonding pad 410, and the second sub-layer 322 includes a P-electrode material. A second electrode 330 is located on the side of the second light-emitting functional layer 313 away from the substrate 100, and the second electrode 330 includes a P-electrode material.

[0138] In the LED light-emitting device of the second sub-pixel SPB, the second light-emitting functional layer 313 includes an N-type semiconductor layer NSL, and the first light-emitting functional layer 312 includes a P-type semiconductor layer PSL. The second electrode 330 is located on the side of the second light-emitting functional layer 313 closest to the substrate 100. The second electrode 330 may include a third sub-layer 331 located on the bonding pad 410 and a fourth sub-layer 332 located between the third sub-layer 331 and the second light-emitting functional layer 313. The third sub-layer 331 is bonded to the bonding pad 410, and the fourth sub-layer 332 includes an N-electrode material. The first electrode 320 is located on the side of the first light-emitting functional layer 312 furthest from the substrate 100, and the first electrode 320 includes a P-electrode material.

[0139] The second electrode 330 of the light-emitting device LED of the first sub-pixel SPA and the first electrode 320 of the light-emitting device LED of the second sub-pixel SPB are made of the same material, and the second electrode 330 of the first sub-pixel SPA and the first electrode 320 of the second sub-pixel SPB can both be located in the top electrode layer 500. By setting the second light-emitting functional layer 313 of the first sub-pixel SPA to have a tunnel junction structure, the second electrode 330 of the light-emitting device LED of the first sub-pixel SPA and the first electrode 320 of the light-emitting device LED of the second sub-pixel SPB can be located in the same layer, thereby saving one film deposition process and patterning process.

[0140] According to some exemplary embodiments, in conjunction with reference to Figure 2 , Figure 8 and Figure 9 The top electrode layer 500 is made of a P-electrode material, for example, indium tin oxide. The top electrode layer 500 is a light-transmitting structure and will not obstruct the light emitted by the LED light-emitting device. The top electrode layer 500 can be configured as a continuous film layer covering the light-emitting functional layer 310 of multiple LED light-emitting devices; for example, the top electrode layer 500 covers the display area AA.

[0141] According to some exemplary embodiments, in conjunction with reference to Figure 8 and Figure 9 The display substrate also includes an auxiliary electrode 600 located on the side of the top electrode layer 500 away from the substrate 100. The material of the auxiliary electrode 600 may include a metallic material. The auxiliary electrode 600 has low resistance, which can reduce the voltage drop generated when the voltage signal is transmitted within the top electrode layer 500, thereby improving display uniformity. To prevent the auxiliary electrode 600 from blocking the light emission of the LED light-emitting device, the auxiliary electrode 600 is in a grid shape. The orthographic projection of the auxiliary electrode 600 on the substrate 100 is located in the interval region between the orthographic projections of the multiple light-emitting functional layers 310 on the substrate 100.

[0142] According to some exemplary embodiments, in at least one sub-pixel group, the light-emitting color of a first sub-pixel is the same as the light-emitting color of a second sub-pixel; and / or, in at least one sub-pixel group, the light-emitting color of a first sub-pixel is not the same as the light-emitting color of a second sub-pixel.

[0143] According to some exemplary embodiments, in at least one sub-pixel group, the light-emitting device of a first sub-pixel and the light-emitting device of a second sub-pixel are arranged adjacent to each other along a first direction; and / or, in at least one sub-pixel group, the light-emitting device of a first sub-pixel and the light-emitting device of a second sub-pixel are arranged adjacent to each other along a second direction, wherein the first direction and the second direction intersect.

[0144] According to some exemplary embodiments, refer to Figure 5 The plurality of sub-pixels SP includes a plurality of first-color sub-pixels SP1, a plurality of second-color sub-pixels SP2, and a plurality of third-color sub-pixels SP3, wherein the emitted light colors of the first-color sub-pixels SP1, the second-color sub-pixels SP2, and the third-color sub-pixels SP3 are different from each other. The plurality of sub-pixels SP includes a plurality of pixel units PU arranged along a first direction X and a second direction Y. Each pixel unit PU includes one first-color sub-pixel SP1, one second-color sub-pixel SP2, and one third-color sub-pixel SP3 arranged along the first direction X, with the second-color sub-pixel SP2 located between the first-color sub-pixels SP1 and the third-color sub-pixels SP3. In two adjacent pixel units PU along the second direction Y, two first-color sub-pixels SP1 are arranged adjacently along the second direction Y, two second-color sub-pixels SP2 are arranged adjacently along the second direction Y, and two third-color sub-pixels SP3 are arranged adjacently along the second direction Y. In at least one pixel unit PU, at least one of the first-color sub-pixels SP1, the second-color sub-pixels SP2, and the third-color sub-pixels SP3 belongs to a sub-pixel group SPX.

[0145] It should be noted that in this article, the arrangement of subpixels should be understood as the arrangement of the light-emitting layers of the light-emitting devices of the subpixels.

[0146] According to some exemplary embodiments, refer to Figure 5 At least one subpixel group SPX includes at least one first subpixel group SPX1, the first subpixel group SPX1 including two first color subpixels SP1 adjacent along the second direction Y; and / or, at least one subpixel group SPX includes at least one second subpixel group SPX2, the second subpixel group SPX2 including two second color subpixels SP2 adjacent along the second direction Y; and / or, at least one subpixel group SPX includes at least one third subpixel group SPX3, the third subpixel group SPX3 including two third color subpixels SP3 adjacent along the second direction Y.

[0147] According to some exemplary embodiments, refer to Figure 5 In a pixel unit PU adjacent to each other along the second direction Y, there is a first sub-pixel group SPX1, a second sub-pixel group SPX2, and a third sub-pixel group SPX3. That is, in a pixel unit PU adjacent to each other along the second direction Y, the two first color sub-pixels SP1 adjacent to each other along the second direction Y share a pixel driving circuit, the two second color sub-pixels SP2 adjacent to each other along the second direction Y share a pixel driving circuit, and the two third color sub-pixels SP3 adjacent to each other along the second direction Y share a pixel driving circuit.

[0148] According to some exemplary embodiments, the first color, the second color, and the third color are selected from red, green, and blue, respectively. For example, the first color can be red, the second color can be green, and the third color can be blue.

[0149] According to some exemplary embodiments, in conjunction with reference to Figure 5 , Figure 6A , Figure 6B and Figure 6C In the first sub-pixel group SPX1, the light-emitting layer 311 of the LEDs in the two first-color sub-pixels SP1 is a first-color light-emitting layer 3111, meaning that the LEDs in the two first-color sub-pixels SP1 emit light of the first color. In the second sub-pixel group SPX2, the light-emitting layer 311 of the LEDs in the two second-color sub-pixels SP2 is a second-color light-emitting layer 3112, meaning that the LEDs in the two second-color sub-pixels SP2 emit light of the second color. In the third sub-pixel group SPX3, the light-emitting layer 311 of the LEDs in the two third-color sub-pixels SP3 is a third-color light-emitting layer 3113, meaning that the LEDs in the two third-color sub-pixels SP3 emit light of the third color.

[0150] Figure 10 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1. Figure 11A Schematic illustration along Figure 10 A cross-sectional view taken from the centerline E1-E1'. Figure 11B Schematic illustration along Figure 10 A cross-sectional view taken from the centerline E2-E2'. Figure 11C Schematic illustration along Figure 10 A cross-sectional view taken from the centerline E3-E3'.

[0151] According to some exemplary embodiments, in conjunction with reference to Figure 10 , Figure 11A , Figure 11B and Figure 11C The light-emitting layer 311 of the LED of the first color sub-pixel SP1, the light-emitting layer 311 of the LED of the second color sub-pixel SP2, and the light-emitting layer 311 of the LED of the third color sub-pixel SP3 are the same light-emitting layer 311. The LEDs of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 emit light of the same color.

[0152] The display substrate also includes a color conversion layer 700 located on the side of the top electrode layer 500 away from the substrate 100. The color conversion layer 700 includes a first color conversion section 710, a second color conversion section 720, and a third color conversion section 730. The first color conversion section 710 is located on the side of the light-emitting device LED of the first color sub-pixel SP1 away from the substrate 100, the second color conversion section 720 is located on the side of the light-emitting device LED of the second color sub-pixel SP2 away from the substrate 100, and the third color conversion section 730 is located on the side of the light-emitting device LED of the third color sub-pixel SP3 away from the substrate 100. The light emitted by the light-emitting device LED is of the first color after passing through the first color conversion section 710, the light emitted by the light-emitting device LED is of the second color after passing through the second color conversion section 720, and the light emitted by the light-emitting device LED is of the third color after passing through the third color conversion section 730.

[0153] For example, the light-emitting device LED of the first color sub-pixel SP1, the light-emitting device LED of the second color sub-pixel SP2, and the light-emitting device LED of the third color sub-pixel SP3 respectively emit light of the third color. The material of the first color conversion unit 710 includes a first color quantum dot material, the material of the second color conversion unit 720 includes a second color quantum dot material, and the third color conversion unit 730 includes a transparent material and scattering particles doped in the transparent material.

[0154] For example, the light-emitting devices LED of the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 emit ultraviolet light respectively. The material of the first color conversion unit 710 includes a first color quantum dot material, the material of the second color conversion unit 720 includes a second color quantum dot material, and the material of the third color conversion unit 730 includes a third color quantum dot material.

[0155] Figure 12 An equivalent circuit diagram of a pixel circuit according to some embodiments of the present invention is shown schematically. Figure 13 A schematic diagram of the driving timing of a pixel circuit according to some embodiments of the present invention is shown.

[0156] According to some exemplary embodiments, in conjunction with reference to Figure 4 and Figure 12 The pixel circuit includes a pixel driving circuit 210, at least two light-emitting devices (LEDs), and a second power signal terminal (ELVSS). Each LED includes a first electrode 320, a light-emitting functional layer 310 located on one side of the first electrode 320, and a second electrode 330 located on the side of the LED away from the first electrode 320. The at least two LEDs include at least one first LED1 and at least one second LED2. The first electrode 320 of the first LED1 is electrically connected to a first node N1 of the pixel driving circuit 210, and the second electrode 330 of the first LED1 is electrically connected to the second power signal terminal. The second electrode 330 of the second LED2 is also electrically connected to the first node N1 of the pixel driving circuit 210, and the first electrode 320 of the second LED2 is electrically connected to the second power signal terminal (ELVSS).

[0157] Combined with reference Figure 3 and Figure 12 The first light-emitting device LED1 and the second light-emitting device LED2 are electrically connected to the same pixel driving circuit 210. This pixel driving circuit 210 and the first and second light-emitting devices LED1 and LED2 electrically connected to it constitute a sub-pixel group SPX as described above. The first sub-pixel SPX includes the first light-emitting device LED1 and the pixel driving circuit 210, and the second sub-pixel SPB includes the second light-emitting device LED2 and the pixel driving circuit 210.

[0158] According to some exemplary embodiments, refer to Figure 12 The pixel driving circuit 210 can be a 7T1C type pixel driving circuit. The pixel driving circuit 210 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0159] For example, refer to Figure 12 The gate of the first transistor T1 is coupled to the reset signal terminal Reset, the first terminal of the first transistor T1 is coupled to the initialization signal terminal Vinit, and the second terminal of the first transistor T1 is coupled to the fourth node N4, which is also coupled to the second terminal of the fifth transistor T5. Specifically, the first transistor T1 is configured to turn on under the control of the reset signal terminal Reset, and write the initialization signal of the initialization signal terminal Vinit to the fourth node N4, thereby resetting the fourth node N4.

[0160] For example, refer to Figure 12 The gate of the second transistor T2 is coupled to the access scan signal terminal Gate, the first terminal of the second transistor T2 is coupled to the initialization signal terminal Vinit, and the second terminal of the second transistor T2 is coupled to the first node N1. The second transistor T2 is configured to be turned on under the control of the scan signal terminal Gate, and to write the initialization signal of the initialization signal terminal Vinit to the first node N1, thereby resetting the first node N1.

[0161] For example, refer to Figure 12 The gate of the third transistor T3 is coupled to the scan signal terminal Gate, the first terminal of the third transistor T3 is coupled to the data signal terminal Data, and the second terminal of the third transistor T3 is coupled to the second node N2, which is also coupled to the first terminal of the fourth transistor T4. The third transistor T3 is configured to be turned on under the control of the scan signal terminal Gate, and to write the data signal at the data signal terminal Data to the second node N2.

[0162] For example, refer to Figure 12 The gate of the fourth transistor T4 is coupled to the fourth node N4, the first terminal of the fourth transistor T4 is coupled to the second node N2, and the second terminal of the fourth transistor T4 is coupled to the third node N3. The fourth transistor T4 is configured to conduct under the control of the voltage at the fourth node N4, writing a signal (e.g., a data signal) from the second node N2 to the third node N3.

[0163] For example, refer to Figure 12 The gate of the fifth transistor T5 is coupled to the scan signal terminal Gate. The first terminal of the fifth transistor T5 is coupled to the third node N3, which is also coupled to the second terminal of the fourth transistor T4. The second terminal of the fifth transistor T5 is coupled to the fourth node N4, which is also coupled to the gate of the fourth transistor T4. The fifth transistor T5 is configured to be turned on under the control of the scan signal terminal Gate, writing an electrical signal (e.g., a data signal) from the third node N3 to the fourth node N4.

[0164] For example, refer to Figure 12 The gate of the sixth transistor T6 is connected to the light-emitting control signal terminal EM, the first terminal of the sixth transistor T6 is coupled to the first power supply signal terminal ELVDD, and the second terminal of the sixth transistor T6 is coupled to the second node N2. The sixth transistor T6 is configured to be turned on under the control of the light-emitting control signal terminal EM, and to write the first power supply signal of the first power supply signal terminal ELVDD to the second node N2.

[0165] For example, refer to Figure 12 The gate of the seventh transistor T7 is connected to the light-emitting control signal terminal EM, the first terminal of the seventh transistor T7 is coupled to the third node N3, and the second terminal of the seventh transistor T7 is coupled to the first node N1. The seventh transistor T7 is configured to be turned on under the control of the light-emitting control signal terminal EM, transmitting an electrical signal (e.g., a voltage signal) from the third node N3 to the first node N1.

[0166] For example, refer to Figure 12 The first terminal of the storage capacitor Cst is coupled to the fourth node N4, and the second terminal of the storage capacitor Cst is coupled to the first power signal terminal ELVDD.

[0167] For example, refer to Figure 12 The first electrode of the first light-emitting device LED1 is coupled to the first node N1, and the second electrode of the second light-emitting device LED2 is coupled to the first node N1. The second electrode of the first light-emitting device LED1 is coupled to the second power signal terminal ELVSS, and the first electrode of the second light-emitting device LED2 is coupled to the second power signal terminal ELVSS.

[0168] Depending on the actual process requirements, the pixel driving circuit 210 can also be a pixel driving circuit with a structure such as 4T1C, 4T2C, 6T1C, or 8T1C.

[0169] Combined with reference 12 and Figure 13 The driving method includes a first driving phase t1 and a second driving phase t2, which are performed continuously within the same frame display time.

[0170] In the first driving phase t1, the pixel driving circuit 210 outputs a driving current to the first light-emitting device LED1, causing LED1 to emit light. In the second driving phase t2, the pixel driving circuit 210 outputs a driving current to the second light-emitting device LED2, causing LED2 to emit light. By controlling the driving signal of the pixel driving circuit 210, the first light-emitting device LED1 and the second light-emitting device LED2 are lit sequentially. Of course, it is also possible to light up the second light-emitting device LED2 first, and then light up the first light-emitting device LED1, as needed.

[0171] According to some exemplary embodiments, in conjunction with reference to Figure 12 and Figure 13 In the first driving stage t1, the data signal terminal Data writes the first data signal to the pixel driving circuit 210, and the pixel driving circuit 210 outputs the first driving current to the first light-emitting device LED1. In the second driving stage t2, the data signal terminal Data writes the second data signal to the pixel driving circuit 210, and the pixel driving circuit 210 outputs the second driving current to the second light-emitting device LED2.

[0172] For example, in the first driving stage t1, the first data signal written to the data signal terminal is a positive voltage signal, and in the second driving stage t2, the second data signal written to the data signal terminal is a negative voltage signal.

[0173] According to some exemplary embodiments, in conjunction with reference to Figure 12 and Figure 13 The first driving stage t1 includes a first reset stage t11, a first data writing stage t12, and a first light emission stage t13. The second driving stage t2 includes a second reset stage t21, a second data writing stage t22, and a second light emission stage t23.

[0174] During the first reset phase t11, the low level of the reset signal terminal Reset is active, while the scan signal terminal Gate and the light emission control signal terminal EM are high. Under the control of the reset signal terminal Reset, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the fourth transistor T4.

[0175] During the first data writing phase t12, the low level of the scan signal terminal Gate is active, while the reset signal terminal Reset and the light-emitting control signal terminal EM are high. Under the control of the scan signal terminal Gate, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on. The first data signal is written to the fourth node N4 along the path from the data signal terminal Data through the third transistor T3, the second node N2, the fourth transistor T4, the third node N3, and the fifth transistor T5. Simultaneously, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit through the second transistor T2, thereby resetting the voltage of the first electrode of the first light-emitting device LED1 and the second electrode of the second light-emitting device LED2.

[0176] During the first light-emitting stage t13, the low level of the light-emitting control signal terminal EM is an effective level, while the reset signal terminal Reset and the scan signal terminal Gate are high levels. Under the control of the light-emitting control signal terminal EM, the sixth transistor T6 and the seventh transistor T7 are turned on. The fourth transistor T4 is turned on by the voltage signal stored in the storage capacitor Cst. The drive current associated with the first data signal is applied to the first light-emitting device LED1 along the path from the sixth transistor T6, the fourth transistor T4, and the seventh transistor T7, so that the first light-emitting device LED1 emits light.

[0177] During the second reset phase t21, the low level of the reset signal terminal Reset is an effective level, while the scan signal terminal Gate and the light emission control signal terminal EM are at high levels. Under the control of the reset signal terminal Reset, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the fourth transistor T4.

[0178] During the second data writing phase t22, the low level of the scan signal terminal Gate is active, while the reset signal terminal Reset and the light-emitting control signal terminal EM are high. Under the control of the scan signal terminal Gate, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on. The second data signal is written to the fourth node N4 along the path from the data signal terminal Data through the third transistor T3, the second node N2, the fourth transistor T4, the third node N3, and the fifth transistor T5. Simultaneously, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit through the second transistor T2, thereby resetting the voltage of the first electrode of the first light-emitting device LED1 and the second electrode of the second light-emitting device LED2.

[0179] During the second light-emitting stage t23, the low level of the light-emitting control signal terminal EM is an effective level, while the reset signal terminal Reset and the scan signal terminal Gate are high levels. Under the control of the light-emitting control signal terminal EM, the sixth transistor T6 and the seventh transistor T7 are turned on. The fourth transistor T4 is turned on by the voltage signal stored in the storage capacitor Cst. The drive current associated with the second data signal is applied to the second light-emitting device LED2 along the path from the sixth transistor T6, the fourth transistor T4, and the seventh transistor T7, causing the second light-emitting device LED2 to emit light.

[0180] According to some exemplary embodiments, the driving methods for the first sub-pixel group SPX1, the second sub-pixel group SPX2, and the third sub-pixel group SPX3 described above can all be referred to. Figure 13 .

[0181] According to some exemplary embodiments, in conjunction with reference to Figure 5 , Figure 6A Figure 12 and Figure 13 Two adjacent rows of sub-pixels SP share a row of pixel driving circuit 210. During the display time of one frame, in the first driving stage t1, each pixel driving circuit 210 in the row of pixel driving circuit 210 drives the first sub-pixel SPA (i.e., the first light-emitting device LED1) in each group of sub-pixel groups SPX to light up. Then, in the second driving stage t2, it drives the second sub-pixel SPB (i.e., the second light-emitting device LED2) in each group of sub-pixel groups SPX to light up. Through time-division driving, the row of pixel driving circuit 210 is used to light up both rows of sub-pixels SP.

[0182] in addition, Figure 3 , Figure 8 and Figure 10 The schematic display substrate display method and Figure 5 The illustrated display substrate is similar and will not be described in detail here.

[0183] Figure 14 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1. Figure 15 Schematic illustration along Figure 14 A cross-sectional view taken along the centerline F-F'.

[0184] According to some exemplary embodiments, refer to Figure 14 At least one subpixel group SPX includes at least one fourth subpixel group SPX4, which includes a first-color subpixel SP1 and a second-color subpixel SP2 adjacent along the first direction X; and / or, at least one subpixel group SPX includes at least one fifth subpixel group SPX5, which includes a first-color subpixel SP1 and a third-color subpixel SP3 adjacent along the first direction X; and / or, at least one subpixel group SPX includes at least one sixth subpixel group SPX6, which includes a second-color subpixel SP2 and a third-color subpixel SP3 adjacent along the first direction X. Figure 14 The sixth subpixel group SPX is shown only schematically; the fourth subpixel group SPX4 and the fifth subpixel group SPX5 are described in detail later.

[0185] It should be noted that sharing a pixel driving circuit with adjacent sub-pixels SP along the first direction X can reduce the number of columns of the pixel driving circuit, which means reducing the number of data lines. On the other hand, sharing a pixel driving circuit with adjacent sub-pixels SP along the second direction Y can reduce the number of rows of the pixel driving circuit, which means reducing the number of scan lines. The specific choice should be made based on the actual panel design.

[0186] According to some exemplary embodiments, in conjunction with reference to Figure 14 and Figure 15 In a pixel unit PU, there is a sixth sub-pixel group SPX6, where adjacent second-color sub-pixels SP2 and third-color sub-pixels SP3 along the first direction X share a pixel driving circuit 210. The light-emitting devices (LEDs) in the second-color sub-pixels SP2 and SP3 are electrically connected to the same pixel driving circuit 210. The pixel driving circuit 210 in another first-color sub-pixel SP1 is not electrically connected to the LEDs in other sub-pixels SP; that is, the pixel driving circuit 210 in the first-color sub-pixel SP1 is only electrically connected to the LEDs in that first-color sub-pixel SP1.

[0187] It should be noted that the structures of the multiple pixel driving circuits on the display substrate are identical. That is, the structure of a pixel driving circuit electrically connected to two light-emitting devices is the same as that electrically connected to one light-emitting device. The only difference is that the size and arrangement of the bonding pads are used to achieve the connection: some pixel driving circuits are electrically connected to one light-emitting device, while others are electrically connected to two. The area of ​​the bonding pads electrically connected to two light-emitting devices is larger than the area of ​​the bonding pads electrically connected to one light-emitting device.

[0188] exist Figure 15 In this diagram, only to more clearly illustrate the corresponding connection relationship between the pixel driving circuit, bonding pads and light-emitting devices, the pixel driving circuit electrically connected to two light-emitting devices is shown as larger than the pixel driving circuit electrically connected to one light-emitting device.

[0189] According to some exemplary embodiments, in conjunction with reference to Figure 14 and Figure 15 In a pixel unit PU, the light-emitting device LED of the first color sub-pixel SP1 includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a first color light-emitting layer 3111 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the first color light-emitting layer 3111 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0190] The light-emitting device LED of the second color sub-pixel SP2 includes a second electrode 330, an N-type semiconductor layer NSL located on the side of the second electrode 330 away from the substrate 100, a second color light-emitting layer 3112 located on the side of the N-type semiconductor layer NSL away from the substrate 100, a P-type semiconductor layer PSL located on the side of the second color light-emitting layer 3112 away from the substrate 100, and a first electrode 320 located on the side of the P-type semiconductor layer PSL away from the substrate 100, wherein the first electrode 320 includes a P-electrode material.

[0191] The light-emitting device LED of the third color sub-pixel SP3 includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a third color light-emitting layer 3113 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the third color light-emitting layer 3113 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0192] The second electrode 330 of the first color sub-pixel SP1 and the second electrode 330 of the third color sub-pixel SP3 can be located on the same layer, while the first electrode 320 of the second color sub-pixel SP2 is located on another layer.

[0193] It should be noted that the first electrode 320 of the second color sub-pixel SP2 can also be set on the side closer to the substrate 100, and the second electrode 330 of the second color sub-pixel SP2 can also be set on the side closer to the substrate 100.

[0194] Figure 16 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1. Figure 17 Schematic illustration along Figure 16 A cross-sectional view taken along the midline G-G'.

[0195] According to some exemplary embodiments, in conjunction with reference to Figure 16 and Figure 17 In a pixel unit PU, the light-emitting device LED of the first color sub-pixel SP1 includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a first color light-emitting layer 3111 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the first color light-emitting layer 3111 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0196] The light-emitting device LED of the second color sub-pixel SP2 includes a second electrode 330, an N-type semiconductor layer NSL located on the side of the second electrode 330 away from the substrate 100, a second color light-emitting layer 3112 located on the side of the N-type semiconductor layer NSL away from the substrate 100, a P-type heavily doped semiconductor layer P++ located on the side of the second color light-emitting layer 3112 away from the substrate 100, an N-type heavily doped semiconductor layer N++ located on the side of the P-type heavily doped semiconductor layer P++ away from the substrate 100, and a first electrode 320 located on the side of the N-type heavily doped semiconductor layer N++ away from the substrate 100, wherein the first electrode 320 includes an N-electrode material.

[0197] The light-emitting device LED of the third color sub-pixel SP3 includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a third color light-emitting layer 3113 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the third color light-emitting layer 3113 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0198] The second electrode 330 of the first color sub-pixel SP1, the second electrode 330 of the third color sub-pixel SP3, and the first electrode 320 of the second color sub-pixel SP2 are made of the same material and can be located in the same top electrode layer 500, which includes N electrode material.

[0199] It should be noted that a tunnel junction can also be provided on the side of the third color sub-pixel SP3 away from the substrate 100, while the first electrode 320 of the first color sub-pixel SP1 is provided on the side away from the substrate 100, so that only one top electrode layer 500 including P electrode material can be provided.

[0200] According to some exemplary embodiments, for Figure 14 or Figure 16 The schematic display substrate, the driving circuit and driving method of the sixth sub-pixel group SPX6 can be referred to Figure 12 , Figure 13 And as described above. During the display time of one frame, for a pixel unit PU, the third color sub-pixel SP3 is lit up in the first driving phase t1, and the second color sub-pixel SP2 is lit up in the second driving phase t2. The first color sub-pixel SP1 can be lit up in either the first driving phase t1 or the second driving phase t2.

[0201] Figure 18 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A1.

[0202] According to some exemplary embodiments, refer to Figure 18 Two adjacent pixel units PU along the second direction Y include two sixth sub-pixel groups SPX6 and one first sub-pixel group SPX1. The first sub-pixel group SPX1 includes two first color sub-pixels SP1 adjacent along the second direction Y. That is, two adjacent pixel units PU along the second direction Y include three pixel driving circuits 210. The two first color sub-pixels SP1 adjacent along the second direction Y share one pixel driving circuit 210, a group of second color sub-pixels SP2 and third color sub-pixels SP3 adjacent along the first direction X share another pixel driving circuit 210, and another group of second color sub-pixels SP2 and third color sub-pixels SP3 adjacent along the first direction X share yet another pixel driving circuit 210.

[0203] According to some exemplary embodiments, refer to Figure 18 The driving circuits and driving methods for the first sub-pixel group SPX1 and the sixth sub-pixel group SPX6 can be found in [reference needed]. Figure 12 , Figure 13 As described above. The first sub-pixel group SPX1 can share a gate signal line with either of the two sixth sub-pixel groups SPX6. For example, the first sub-pixel group SPX1 can share a gate signal line with the upper sixth sub-pixel group SPX6. During the display time of one frame, for two adjacent pixel units PU along the second direction Y, for the pixel driving circuit 210 of the first sub-pixel group SPX1 and the upper sixth sub-pixel group SPX6, in the first driving stage t1, one first color sub-pixel SP1 is lit, and one of the second color sub-pixel SP2 and the third color sub-pixel SP3 is lit. In the second driving stage t2, the other first color sub-pixel SP1 is lit, and the other of the second color sub-pixel SP2 and the third color sub-pixel SP3 is lit. The driving timing of the sixth sub-pixel group SPX6 located on the lower side immediately follows the second driving stage t2 of the first sub-pixel group SPX1 and the sixth sub-pixel group SPX6 on the upper side. In the first driving stage t1, one of the second color sub-pixel SP2 and the third color sub-pixel SP3 is lit up, and in the second driving stage t2, the other of the second color sub-pixel SP2 and the third color sub-pixel SP3 is lit up.

[0204] Figure 19 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A2.

[0205] According to some exemplary embodiments, refer to Figure 19Two adjacent pixel units PU along the first direction X include a fourth sub-pixel group SPX4, a fifth sub-pixel group SPX5, and a sixth sub-pixel group SPX6. That is, two adjacent pixel units PU along the first direction X include three pixel driving circuits 210. The first color sub-pixel SP1 and the second color sub-pixel SP2, which are adjacent along the first direction X, share one pixel driving circuit 210. The third color sub-pixel SP3 and the first color sub-pixel SP1, which are adjacent along the first direction X, share another pixel driving circuit 210. The second color sub-pixel SP2 and the third color sub-pixel SP3, which are adjacent along the first direction X, share yet another pixel driving circuit 210.

[0206] According to some exemplary embodiments, refer to Figure 19 The driving circuits and driving methods for the fourth sub-pixel group SPX4, the fifth sub-pixel group SPX5, and the sixth sub-pixel group SPX6 can be found in [reference needed]. Figure 12 , Figure 13 And as described above. During the display time of one frame, for two adjacent pixel units PU along the second direction Y, in the first driving phase t1, one of the first color sub-pixel SP1 and the second color sub-pixel SP2 in the fourth sub-pixel group SPX4 is lit, one of the third color sub-pixel SP3 and the first color sub-pixel SP1 in the fifth sub-pixel group SPX5 is lit, and one of the second color sub-pixel SP2 and the third color sub-pixel SP3 in the sixth sub-pixel group SPX6 is lit. In the second driving phase t2, the other of the first color sub-pixel SP1 and the second color sub-pixel SP2 in the fourth sub-pixel group SPX4 is lit, the other of the third color sub-pixel SP3 and the first color sub-pixel SP1 in the fifth sub-pixel group SPX5 is lit, and the other of the second color sub-pixel SP2 and the third color sub-pixel SP3 in the sixth sub-pixel group SPX6 is lit.

[0207] Figure 20 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A3. Figure 21 Schematic illustration along Figure 20 A cross-sectional view taken along the midline H-H'. Figure 22 The brightness-temperature curves of different colored light-emitting diodes are schematically shown. Figure 23 A schematic diagram of the driving timing of a pixel circuit according to some embodiments of the present invention is shown.

[0208] According to some exemplary embodiments, in conjunction with reference to Figure 20 and Figure 21The plurality of sub-pixels SP includes a plurality of first-color sub-pixels SP1, a plurality of second-color sub-pixels SP2, and a plurality of third-color sub-pixels SP3, wherein the emitted light colors of the first-color sub-pixels SP1, the second-color sub-pixels SP2, and the third-color sub-pixels SP3 are different from each other. The plurality of sub-pixels SP includes a plurality of pixel units PU arranged along a first direction X and a second direction Y, wherein a pixel unit PU includes two first-color sub-pixels SP1, one second-color sub-pixel SP2, and one third-color sub-pixel SP3. At least one sub-pixel group SPX includes a seventh sub-pixel group SPX7, wherein the seventh sub-pixel group SPX7 includes two adjacent first-color sub-pixels SP1, and at least one pixel unit PU includes the seventh sub-pixel group SPX7.

[0209] The pixel circuit reference for the seventh sub-pixel group SPX7 Figure 12 The driving method for the seventh sub-pixel group SPX7 is as follows: Figure 23 The driving method includes a first driving stage t1 and a second driving stage t2. In a portion of the displayed frames, each signal terminal in the pixel driving circuit writes signals according to the first driving stage t1, driving one of the first color sub-pixels SP1 in the seventh sub-pixel group SPX7 to emit light. In another portion of the displayed frames, each signal terminal in the pixel driving circuit writes signals according to the second driving stage t2, driving another first color sub-pixel SP1 in the seventh sub-pixel group SPX7 to emit light.

[0210] It should be noted that, unlike Figure 13 The illustrated driving method, in Figure 23 In the process, the first driving phase t1 and the second driving phase t2 are respectively within the display time of two frames of the display screen, while Figure 23 In the process, the first driving phase t1 and the second driving phase t2 are within the display time of one frame of the display image.

[0211] By setting two first color sub-pixels SP1 in a pixel unit PU, and controlling them through the pixel driving circuit 210, these two first color sub-pixels SP1 are alternately lit in different frames of the display, which can effectively avoid the problem of brightness decrease due to the increase of the operating temperature of the first color sub-pixels SP1, thus avoiding the problem of color deviation in the display.

[0212] For example, in odd-numbered frames, one of the first color subpixels SP1 in the seventh subpixel group SPX7 is driven to emit light, and in even-numbered frames, another first color subpixel SP1 in the seventh subpixel group SPX7 is driven to emit light.

[0213] Reference Figure 22During the use of red, green, and blue LEDs, one color LED may experience a greater decrease in brightness as the temperature rises compared to other colors, resulting in color shift. This is due to factors such as different LED substrates, materials, and manufacturing processes. The LED that experiences a greater decrease in brightness is likely to be one of the red, green, or blue LEDs. For example, in... Figure 22 In a certain product, the brightness of a red LED decreases more significantly during use due to increased temperature. In this case, two LEDs can be set in a pixel unit, with the two LEDs sharing a pixel driving circuit. Under the control of the pixel driving circuit, the two red LEDs light up alternately in different frames of the display.

[0214] In some exemplary embodiments, in conjunction with reference to Figure 20 and Figure 21 In a pixel unit PU, two first-color sub-pixels SP1 are arranged adjacently along the first direction X, a second-color sub-pixel SP2 is located on one side of the two first-color sub-pixels SP1 along the first direction X, and a third-color sub-pixel SP3 is located on the side of the second-color sub-pixel SP2 away from the first-color sub-pixel SP1. In two pixel units PU adjacent along the second direction Y, two first-color sub-pixels SP1 in one row are arranged adjacently with two first-color sub-pixels SP1 in another row along the second direction Y, one second-color sub-pixel SP2 is arranged adjacently with another second-color sub-pixel SP2 along the second direction Y, and one third-color sub-pixel SP3 is arranged adjacently with another third-color sub-pixel SP3 along the second direction Y. The seventh sub-pixel group SPX7 includes two first-color sub-pixels SP1 adjacent along the first direction X.

[0215] In some exemplary embodiments, in conjunction with reference to Figure 20 and Figure 21 In at least one pixel unit PU, the pixel driving circuit 210 in the second color sub-pixel SP2 is not electrically connected to the light-emitting device LED in other sub-pixels SP, that is, the pixel driving circuit 210 in the second color sub-pixel SP2 is only electrically connected to the light-emitting device LED in the second color sub-pixel SP2; and / or, in at least one pixel unit PU, the pixel driving circuit 210 in the third color sub-pixel SP3 is not electrically connected to the light-emitting device LED in other sub-pixels SP, that is, the pixel driving circuit 210 in the third color sub-pixel SP3 is only electrically connected to the light-emitting device LED in the third color sub-pixel SP3.

[0216] In some exemplary embodiments, reference is made to Figure 20A pixel unit PU includes a seventh sub-pixel group SPX7. Furthermore, the pixel driving circuit 210 in the second color sub-pixel SP2 is not electrically connected to the light-emitting devices (LEDs) in other sub-pixels SP, and the pixel driving circuit 210 in the third color sub-pixel SP3 is not electrically connected to the light-emitting devices (LEDs) in other sub-pixels SP.

[0217] exist Figure 20 In the illustrated display substrate, for a pixel unit PU, in one frame of the display image, a first-color sub-pixel SP1 in the seventh sub-pixel group SPX7 is lit up, while simultaneously, the second-color sub-pixel SP2 and the third-color sub-pixel SP3 are also lit up. In another frame of the display image, another first-color sub-pixel SP1 in the seventh sub-pixel group SPX7 is lit up, while simultaneously, the second-color sub-pixel SP2 and the third-color sub-pixel SP3 are also lit up.

[0218] In some exemplary embodiments, in conjunction with reference to Figure 20 and Figure 21 In a pixel unit PU, in a first color sub-pixel SP1, the light-emitting device LED includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a first color light-emitting layer 3111 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the first color light-emitting layer 3111 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0219] In another first color sub-pixel SP1, the light-emitting device LED includes a second electrode 330, an N-type semiconductor layer NSL located on the side of the second electrode 330 away from the substrate 100, a first color light-emitting layer 3111 located on the side of the N-type semiconductor layer NSL away from the substrate 100, a P-type heavily doped semiconductor layer P++ located on the side of the first color light-emitting layer 3111 away from the substrate 100, an N-type heavily doped semiconductor layer N++ located on the side of the P-type heavily doped semiconductor layer P++ away from the substrate 100, and a first electrode 320 located on the side of the N-type heavily doped semiconductor layer N++ away from the substrate 100, wherein the first electrode 320 includes an N-electrode material.

[0220] In the second color sub-pixel SP2, the light-emitting device LED includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a second color light-emitting layer 3112 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the second color light-emitting layer 3112 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100. The second electrode 330 includes an N-electrode material.

[0221] In the third color sub-pixel SP3, the light-emitting device LED includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a third color light-emitting layer 3113 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the third color light-emitting layer 3113 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0222] In this pixel unit PU, the second electrode 330 of a first color sub-pixel SP1, the first electrode 320 of another first color sub-pixel SP1, the second electrode 330 of a second color sub-pixel SP2, and the second electrode 330 of a third color sub-pixel SP3 all contain the same material and can be located in the same top electrode layer 500.

[0223] Figure 24 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A3. Figure 25 Schematic illustration along Figure 24 A cross-sectional view taken along the centerline I-I'.

[0224] According to some exemplary embodiments, in conjunction with reference to Figure 24 and Figure 25 At least one pixel unit PU includes a seventh sub-pixel group SPX7 and a sixth sub-pixel group SPX6. The sixth sub-pixel group SPX6 includes a second-color sub-pixel SP2 and a third-color sub-pixel SP3 adjacent along the first direction X. That is, in this pixel unit PU, two first-color sub-pixels SP1 share a pixel driving circuit 210, and a second-color sub-pixel SP2 and a third-color sub-pixel SP3 share a pixel driving circuit 210.

[0225] exist Figure 24 In the schematic display substrate, the driving circuits for the sixth sub-pixel group SPX6 and the seventh sub-pixel group SPX7 are shown in reference. Figure 12 The driving method for the seventh sub-pixel group SPX7 is as follows: Figure 23 The driving method for the sixth sub-pixel group SPX6 is referred to Figure 13 .

[0226] For a pixel unit PU, in one frame of the display, during the first driving phase t1, one of the second color sub-pixels SP2 and SP3 in the sixth sub-pixel group SPX6 is lit; during the second driving phase t2, the other of the second color sub-pixels SP2 and SP3 in the sixth sub-pixel group SPX6 is lit. During either the first driving phase t1 or the second driving phase t2, one of the first color sub-pixels SP1 in the seventh sub-pixel group SPX7 is lit.

[0227] In another frame of the display, during the first driving phase t1, one of the second color subpixels SP2 and SP3 in the sixth subpixel group SPX6 is illuminated; during the second driving phase t2, the other of the second color subpixels SP2 and SP3 in the sixth subpixel group SPX6 is illuminated. During either the first driving phase t1 or the second driving phase t2, the other first color subpixel SP1 in the seventh subpixel group SPX7 is illuminated.

[0228] According to some exemplary embodiments, in conjunction with reference to Figure 24 and Figure 25 In a pixel unit PU, in a first color sub-pixel SP1, the light-emitting device LED includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a first color light-emitting layer 3111 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the first color light-emitting layer 3111 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0229] In another first color sub-pixel SP1, the light-emitting device LED includes a second electrode 330, an N-type semiconductor layer NSL located on the side of the second electrode 330 away from the substrate 100, a first color light-emitting layer 3111 located on the side of the N-type semiconductor layer NSL away from the substrate 100, a P-type heavily doped semiconductor layer P++ located on the side of the first color light-emitting layer 3111 away from the substrate 100, an N-type heavily doped semiconductor layer N++ located on the side of the P-type heavily doped semiconductor layer P++ away from the substrate 100, and a first electrode 320 located on the side of the N-type heavily doped semiconductor layer N++ away from the substrate 100, wherein the first electrode 320 includes an N-electrode material.

[0230] In the second color sub-pixel SP2, the light-emitting device LED includes a second electrode 330, an N-type semiconductor layer NSL located on the side of the second electrode 330 away from the substrate 100, a second color light-emitting layer 3112 located on the side of the N-type semiconductor layer NSL away from the substrate 100, a P-type heavily doped semiconductor layer P++ located on the side of the second color light-emitting layer 3112 away from the substrate 100, an N-type heavily doped semiconductor layer N++ located on the side of the P-type heavily doped semiconductor layer P++ away from the substrate 100, and a first electrode 320 located on the side of the N-type heavily doped semiconductor layer N++ away from the substrate 100, wherein the first electrode 320 includes an N-electrode material.

[0231] In the third color sub-pixel SP3, the light-emitting device LED includes a first electrode 320, a P-type semiconductor layer PSL located on the side of the first electrode 320 away from the substrate 100, a third color light-emitting layer 3113 located on the side of the P-type semiconductor layer PSL away from the substrate 100, an N-type semiconductor layer NSL located on the side of the third color light-emitting layer 3113 away from the substrate 100, and a second electrode 330 located on the side of the N-type semiconductor layer NSL away from the substrate 100, wherein the second electrode 330 includes an N-electrode material.

[0232] In this pixel unit PU, the second electrode 330 of a first color sub-pixel SP1, the first electrode 320 of another first color sub-pixel SP1, the first electrode 320 of a second color sub-pixel SP2, and the second electrode 330 of a third color sub-pixel SP3 all contain the same material and can be located in the same top electrode layer 500.

[0233] Figure 26 The display substrate according to some embodiments of the present invention is schematically illustrated. Figure 2 A magnified view of region A3.

[0234] According to some exemplary embodiments, refer to Figure 26Two adjacent pixel units PU along the second direction Y include a second sub-pixel group SPX2, a third sub-pixel group SPX3, and two seventh sub-pixel groups SPX7. The second sub-pixel group SPX2 includes two second-color sub-pixels SP2 adjacent along the second direction Y, and the third sub-pixel group SPX3 includes two third-color sub-pixels SP3 adjacent along the second direction Y. That is, in two adjacent pixel units PU along the second direction Y, two adjacent first-color sub-pixels SP1 in one pixel unit PU share a pixel driving circuit 210, two adjacent first-color sub-pixels SP1 in the other pixel unit PU share a pixel driving circuit 210, two adjacent second-color sub-pixels SP2 along the second direction Y share a pixel driving circuit 210, and two adjacent third-color sub-pixels SP3 along the second direction Y share a pixel driving circuit 210.

[0235] exist Figure 26 In the schematic display substrate, the driving circuits for the second sub-pixel group SPX2, the third sub-pixel group SPX3, and the seventh sub-pixel group SPX7 are shown below. Figure 12 The driving method for the seventh sub-pixel group SPX7 is as follows: Figure 23 The driving methods for the second sub-pixel group SPX2 and the third sub-pixel group SPX3 are as follows: Figure 13 .

[0236] For a pixel unit PU, in one frame of the display, for the second sub-pixel group SPX2 and the third sub-pixel group SPX3, in the first driving phase t1, a second-color sub-pixel SP2 in the second sub-pixel group SPX2 is lit, and a third-color sub-pixel SP3 in the third sub-pixel group SPX3 is lit. In the second driving phase t2, another second-color sub-pixel SP2 in the second sub-pixel group SPX2 is lit, and another third-color sub-pixel SP3 in the third sub-pixel group SPX3 is lit. Additionally, in the first driving phase t1, a first-color sub-pixel SP1 in a seventh sub-pixel group SPX7 is lit, and in the second driving phase t2, another first-color sub-pixel SP1 in another seventh sub-pixel group SPX7 is lit.

[0237] In another frame of the display, for the second sub-pixel group SPX2 and the third sub-pixel group SPX3, in the first driving phase t1, a second-color sub-pixel SP2 in the second sub-pixel group SPX2 is illuminated, and a third-color sub-pixel SP3 in the third sub-pixel group SPX3 is illuminated. In the second driving phase t2, another second-color sub-pixel SP2 in the second sub-pixel group SPX2 is illuminated, and another third-color sub-pixel SP3 in the third sub-pixel group SPX3 is illuminated. Additionally, in the first driving phase t1, another first-color sub-pixel SP1 in a seventh sub-pixel group SPX7 is illuminated, and in the second driving phase t2, another first-color sub-pixel SP1 in another seventh sub-pixel group SPX7 is illuminated.

[0238] Figure 27 A flowchart illustrating a method for fabricating a display substrate according to some embodiments of the present invention is shown.

[0239] Some embodiments of this utility model provide a method for preparing a display substrate, referring to... Figure 27 The preparation method includes the following steps S10-S20.

[0240] In step S10, a driving circuit layer is formed on the substrate, the driving circuit layer including multiple pixel driving circuits.

[0241] In step S20, a light-emitting device layer is formed on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes multiple light-emitting devices, which are electrically connected to the driving circuit layer. Each light-emitting device includes a light-emitting layer, a first light-emitting functional layer, and a second light-emitting functional layer. The substrate has a first surface facing the driving circuit layer. Along a direction perpendicular to the first surface, the first light-emitting functional layer and the second light-emitting functional layer are located on opposite sides of the light-emitting layer. The display substrate includes multiple sub-pixels. Each sub-pixel includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device. The multiple sub-pixels include at least one sub-pixel group. Each sub-pixel group includes at least two light-emitting devices and a pixel driving circuit. The two light-emitting devices are electrically connected to the same pixel driving circuit. Each sub-pixel group includes at least one first sub-pixel and at least one second sub-pixel. In the light-emitting device of the first sub-pixel, the first light-emitting functional layer is located on the side of the light-emitting layer closer to the substrate. In the light-emitting device of the second sub-pixel, the second light-emitting functional layer is located on the side of the light-emitting layer closer to the substrate.

[0242] Figures 28A-28O The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0243] Reference Figure 28AAn N-type semiconductor layer NSL is formed on the first epitaxial substrate SUB1, a first color emitting layer 3111 is formed on the side of the N-type semiconductor layer NSL away from the first epitaxial substrate SUB1, and a P-type semiconductor layer PSL is formed on the side of the first color emitting layer 3111 away from the first epitaxial substrate SUB1.

[0244] Reference Figure 28B A first electrode 320 is formed on the side of the P-type semiconductor layer PSL away from the first epitaxial substrate SUB1 to obtain the first substrate to be transferred.

[0245] Reference Figure 28C An N-type semiconductor layer NSL is formed on the second epitaxial substrate SUB2. A first color emitting layer 3111 is formed on the side of the N-type semiconductor layer NSL away from the second epitaxial substrate SUB2. A P-type heavily doped semiconductor layer P++ is formed on the side of the first color emitting layer 3111 away from the second epitaxial substrate SUB2. An N-type heavily doped semiconductor layer N++ is formed on the side of the P-type heavily doped semiconductor layer P++ away from the second epitaxial substrate SUB2.

[0246] Reference Figure 28D The epitaxial layer formed on the second epitaxial substrate SUB2 is bonded to the temporary substrate 920 using bonding adhesive 910, and the N-type heavily doped semiconductor layer N++ is in contact with the bonding adhesive 910.

[0247] Combined with reference Figure 28D and Figure 28E The second epitaxial substrate SUB2 is removed, exposing the N-type semiconductor layer NSL.

[0248] Reference Figure 28F A second electrode 330 is formed on the side of the N-type semiconductor layer NSL away from the temporary substrate 920 to obtain a second substrate to be transferred.

[0249] Combined with reference Figure 28G and Figure 28H ( Figure 28H For along Figure 28G (A cross-sectional view taken by the cut line) Multiple pixel driving circuits 210 are formed on the substrate 100.

[0250] Combined with reference Figure 28I and Figure 28J ( Figure 28J For along Figure 28I (Cross-sectional view taken by the cut line), multiple bonding pads 410 are formed on the side of the multiple pixel driving circuits 210 away from the substrate 100.

[0251] Combined with reference Figure 28K , Figure 28L and Figure 28M ( Figure 28M For along Figure 28K (Cross-section view taken by the cut line) The first substrate to be transferred and the second substrate to be transferred are respectively transferred onto the substrate 100. A first electrode 320 in the first substrate to be transferred is electrically connected to a bonding pad 410, and a second electrode 330 in the second substrate to be transferred is electrically connected to the same bonding pad 410.

[0252] Next, the first epitaxial substrate SUB1 in the first substrate to be transferred is removed, and the temporary substrate 920 and bonding adhesive 910 in the second substrate to be transferred are removed, thus obtaining two first color emitting functional layers 3101. The two first color emitting functional layers 3101 are arranged adjacently along the second direction Y and are electrically connected to the same pixel driving circuit 210 through the same bonding pad 410. Along the direction away from the substrate 100, one first color emitting functional layer 3101 sequentially includes a P-type semiconductor layer PSL, a first color emitting layer 3111, and an N-type semiconductor layer NSL. This first color emitting functional layer 3101 is connected to the bonding pad 410 through a first electrode 320. The other first color emitting functional layer 3101 sequentially includes an N-type semiconductor layer NSL, a first color emitting layer 3111, a P-type heavily doped semiconductor layer P++, and an N-type heavily doped semiconductor layer N++. This first color emitting functional layer 3101 is connected to the bonding pad 410 through a second electrode 330.

[0253] Similarly, refer to Figures 28A-28M The schematic process involves forming multiple second-color light-emitting functional layers 3102 and multiple third-color light-emitting functional layers 3103 on the substrate 100.

[0254] At least two second-color emitting functional layers 3102 are arranged adjacently along the second direction Y and electrically connected to the same pixel driving circuit 210 through the same bonding pad 410. Along the direction away from the substrate, one second-color emitting functional layer 3102 sequentially includes a P-type semiconductor layer, a second-color emitting layer, and an N-type semiconductor layer, and this second-color emitting functional layer 3102 is connected to the bonding pad 410 through a first electrode. The other second-color emitting functional layer 3102 sequentially includes an N-type semiconductor layer, a second-color emitting layer, a heavily doped P-type semiconductor layer, and a heavily doped N-type semiconductor layer, and this second-color emitting functional layer 3102 is connected to the bonding pad 410 through a second electrode.

[0255] Two third-color emitting functional layers 3103 are arranged adjacently along the second direction Y and electrically connected to the same pixel driving circuit 210 through the same bonding pad 410. Along the direction away from the substrate, one third-color emitting functional layer 3103 sequentially includes a P-type semiconductor layer, a third-color emitting layer, and an N-type semiconductor layer, and this third-color emitting functional layer 3103 is connected to the bonding pad 410 through a first electrode. The other third-color emitting functional layer 3103 sequentially includes an N-type semiconductor layer, a third-color emitting layer, a heavily doped P-type semiconductor layer, and a heavily doped N-type semiconductor layer, and this third-color emitting functional layer 3103 is connected to the bonding pad 410 through a second electrode.

[0256] Combined with reference Figure 28O and Figure 28N ( Figure 28O For along Figure 28N (A cross-sectional view taken from the cut line) A planarization layer PLN is formed on the side of the plurality of first color emitting functional layers 3101, the plurality of second color emitting functional layers 3102, and the plurality of third color emitting functional layers 3103 away from the substrate 100. A top electrode layer 500 is formed on the side of the planarization layer PLN away from the substrate 100. The planarization layer PLN has a plurality of vias VH. The top electrode layer 500 contacts at least one N-type semiconductor layer NSL in at least one first color emitting functional layer 3101, at least one N-type heavily doped semiconductor layer N++ in at least one first color emitting functional layer 3101, at least one N-type semiconductor layer NSL in at least one second color emitting functional layer 3102, at least one N-type heavily doped semiconductor layer N++ in at least one second color emitting functional layer 3102, at least one N-type semiconductor layer NSL in at least one third color emitting functional layer 3103, and at least one N-type heavily doped semiconductor layer N++ in at least one third color emitting functional layer 3103 through the plurality of vias VH in the planarization layer PLN.

[0257] Figures 29A-29C The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0258] Reference Figure 29AA pixel driving circuit 210 is formed on a substrate 100. A bonding pad 410 is formed on the side of the pixel driving circuit 210 away from the substrate 100, and the bonding pad 410 is electrically connected to the pixel driving circuit 210. Two first color emitting functional layers 3101 are formed on the side of the bonding pad 410 away from the substrate 100. Along the direction away from the substrate 100, one first color emitting functional layer 3101 sequentially includes a P-type semiconductor layer PSL, a first color emitting layer 3111, and an N-type semiconductor layer NSL. This first color emitting functional layer 3101 is connected to the bonding pad 410 through a first electrode 320. The other first color emitting functional layer 3101 sequentially includes an N-type semiconductor layer NSL, a first color emitting layer 3111, and a P-type semiconductor layer PSL. This first color emitting functional layer 3101 is connected to the bonding pad 410 through a second electrode 330.

[0259] Reference Figure 29B A planarization layer PLN is formed on the side of the plurality of first color emitting functional layers 3101 away from the substrate 100. The planarization layer PLN includes a first via VH1 and a second via VH2. A first top electrode layer 510 is formed on the side of the planarization layer PLN away from the substrate 100. The first top electrode layer 510 is in contact with an N-type semiconductor layer NSL in one of the first color emitting functional layers 3101 through the first via VH1.

[0260] Reference Figure 29C A second top electrode layer 520 is formed on the side of the first top electrode layer 510 away from the substrate 100. The second top electrode layer 520 is in contact with the P-type semiconductor layer PSL in another first color emitting functional layer 3101 through the second via VH2.

[0261] Figures 30A-30O The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0262] Reference Figure 30A A P-type heavily doped semiconductor layer P++, an N-type heavily doped semiconductor layer N++, a first color emitting layer 3111, and a P-type semiconductor layer PSL are sequentially formed on the first epitaxial substrate SUB1.

[0263] Reference Figure 30B A first electrode 320 is formed on the side of the P-type semiconductor layer PSL away from the first epitaxial substrate SUB1, thus obtaining the first substrate to be transferred.

[0264] Reference Figure 30C An N-type semiconductor layer NSL, a first color emitting layer 3111, and a P-type semiconductor layer PSL are sequentially formed on the second epitaxial substrate SUB2.

[0265] Reference Figure 30DThe epitaxial layer formed on the second epitaxial substrate SUB2 is bonded to the temporary substrate 920 using bonding adhesive 910, and the P-type semiconductor layer PSL is in contact with the bonding adhesive 910.

[0266] Reference Figure 30E The second epitaxial substrate SUB2 is removed, exposing the N-type semiconductor layer NSL.

[0267] Reference Figure 30F A second electrode 330 is formed on the side of the N-type semiconductor layer NSL away from the temporary substrate 920, thus obtaining the second substrate to be transferred.

[0268] Combined with reference Figure 30G and Figure 30H ( Figure 30H For along Figure 30G (A cross-sectional view taken by the cut line in the figure) A pixel driving circuit 210 is formed on the substrate 100, and a bonding pad 410 is formed on the side of the pixel driving circuit 210 away from the substrate 100. The bonding pad 410 is electrically connected to the pixel driving circuit 210.

[0269] Combined with reference Figure 30I , Figure 30J and Figure 30K ( Figure 30K For along Figure 30I (The cross-sectional view taken by the cut line in the figure) The first substrate to be transferred and the second substrate to be transferred are respectively transferred onto the substrate 100. A first electrode 320 in the first substrate to be transferred is electrically connected to a bonding pad 410, and a second electrode 330 in the second substrate to be transferred is electrically connected to the same bonding pad 410.

[0270] Then, the first epitaxial substrate SUB1 in the first substrate to be transferred is removed, and the temporary substrate 920 and bonding adhesive 910 in the second substrate to be transferred are removed, thus obtaining two first color light-emitting functional layers 3101. The two first color light-emitting functional layers 3101 are arranged adjacently along the second direction Y and are electrically connected to the same pixel driving circuit 210 through the same bonding pad 410.

[0271] Along the direction away from the substrate 100, a first color emitting functional layer 3101 sequentially includes a P-type semiconductor layer PSL, a first color emitting layer 3111, an N-type heavily doped semiconductor layer N++, and a P-type heavily doped semiconductor layer P++. This first color emitting functional layer 3101 is connected to the bonding pad 410 via a first electrode 320. Another first color emitting functional layer 3101 sequentially includes an N-type semiconductor layer NSL, a first color emitting layer 3111, and a P-type semiconductor layer PSL. This first color emitting functional layer 3101 is connected to the bonding pad 410 via a second electrode 330.

[0272] Similarly, refer to Figures 30A-30K The schematic process involves forming multiple second-color light-emitting functional layers 3102 and multiple third-color light-emitting functional layers 3103 on the substrate 100.

[0273] At least two second-color emitting functional layers 3102 are arranged adjacently along the second direction Y and electrically connected to the same pixel driving circuit 210 through the same bonding pad 410. Along the direction away from the substrate 100, one second-color emitting functional layer 3102 sequentially includes a P-type semiconductor layer, a second-color emitting layer, an N-type heavily doped semiconductor layer, and a P-type heavily doped semiconductor layer, and this second-color emitting functional layer 3102 is connected to the bonding pad 410 through a first electrode. The other second-color emitting functional layer 3102 sequentially includes an N-type semiconductor layer, a second-color emitting layer, and a P-type semiconductor layer, and this second-color emitting functional layer 3102 is connected to the bonding pad 410 through a second electrode.

[0274] Two third-color emitting functional layers 3103 are arranged adjacently along the second direction Y and electrically connected to the same pixel driving circuit 210 through the same bonding pad 410. Along the direction away from the substrate 100, one third-color emitting functional layer 3103 sequentially includes a P-type semiconductor layer, a third-color emitting layer, an N-type heavily doped semiconductor layer, and a P-type heavily doped semiconductor layer, and this third-color emitting functional layer 3103 is connected to the bonding pad 410 through a first electrode. The other third-color emitting functional layer 3103 sequentially includes an N-type semiconductor layer, a third-color emitting layer, and a P-type semiconductor layer, and this third-color emitting functional layer 3103 is connected to the bonding pad 410 through a second electrode.

[0275] Combined with reference Figure 30L and Figure 30M ( Figure 30M For along Figure 30L(A cross-sectional view taken by the cut line in the figure) A planarization layer PLN is formed on the side of the plurality of first color emitting functional layers 3101, the plurality of second color emitting functional layers 3102, and the plurality of third color emitting functional layers 3103 away from the substrate 100, and a top electrode layer 500 is formed on the side of the planarization layer PLN away from the substrate 100. The planarization layer PLN has a plurality of vias VH, and the top electrode layer 500 contacts at least one N-type semiconductor layer NSL in at least one first color emitting functional layer 3101, at least one N-type heavily doped semiconductor layer N++ in at least one first color emitting functional layer 3101, at least one N-type semiconductor layer NSL in at least one second color emitting functional layer 3102, at least one N-type heavily doped semiconductor layer N++ in at least one second color emitting functional layer 3102, at least one N-type semiconductor layer NSL in at least one third color emitting functional layer 3103, and at least one N-type heavily doped semiconductor layer N++ in at least one third color emitting functional layer 3103 through the plurality of vias VH in the planarization layer PLN.

[0276] The top electrode layer 500 may include a transparent conductive material, such as indium tin oxide.

[0277] Combined with reference Figure 30N and Figure 30O An auxiliary electrode 600 is formed on the side of the top electrode layer 500 away from the substrate 100. The auxiliary electrode 600 is electrically connected to the top electrode layer 500. The orthographic projection of the auxiliary electrode 600 on the substrate 100 is located in the interval region between the orthographic projections of the multiple light-emitting functional layers 310 on the substrate 100.

[0278] Figures 31A-31O The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0279] Reference Figure 31A An N-type semiconductor layer NSL, a first color emitting layer 3111, and a P-type semiconductor layer PSL are sequentially formed on the first epitaxial substrate SUB1.

[0280] Reference Figure 31B A first electrode 320 is formed on the side of the P-type semiconductor layer PSL away from the first epitaxial substrate SUB1, thus obtaining the first substrate to be transferred.

[0281] Reference Figure 31C An N-type semiconductor layer NSL, a second color emitting layer 3112, a P-type heavily doped semiconductor layer P++, and an N-type heavily doped semiconductor layer N++ are sequentially formed on the second epitaxial substrate SUB2.

[0282] Reference Figure 31DThe epitaxial layer formed on the second epitaxial substrate SUB2 is bonded to the temporary substrate 920 using bonding adhesive 910, and the N-type heavily doped semiconductor layer N++ is in contact with the bonding adhesive 910.

[0283] Reference Figure 31E The second epitaxial substrate SUB2 is removed, exposing the N-type semiconductor layer NSL.

[0284] Reference Figure 31F A second electrode 330 is formed on the side of the N-type semiconductor layer NSL away from the temporary substrate 920, thus obtaining the second substrate to be transferred.

[0285] Reference Figure 31G An N-type semiconductor layer NSL, a third color emitting layer 3113, and a P-type semiconductor layer PSL are sequentially formed on the third epitaxial substrate SUB3.

[0286] Reference Figure 31H A first electrode 320 is formed on the side of the P-type semiconductor layer PSL away from the third epitaxial substrate SUB3, thus obtaining the third substrate to be transferred.

[0287] Combined with reference Figure 31I and Figure 31J ( Figure 31J For along Figure 31I (A cross-sectional view taken by the cut line in the figure) A pixel driving circuit 210 is formed on the substrate 100, and a bonding pad 410 is formed on the side of the pixel driving circuit 210 away from the substrate 100. The bonding pad 410 is electrically connected to the pixel driving circuit 210.

[0288] Combined with reference Figure 31K , Figure 31L and Figure 31M ( Figure 31M For along Figure 31K (The cross-sectional view taken by the cut line in the figure) The first substrate to be transferred, the second substrate to be transferred and the third substrate to be transferred are respectively transferred onto the substrate 100. The first electrode 320 in the first substrate to be transferred is electrically connected to a bonding pad 410, and the second electrode 330 in the second substrate to be transferred is electrically connected to the first electrode 320 in the third substrate to be transferred and the same bonding pad 410.

[0289] Next, the first epitaxial substrate SUB1 in the first substrate to be transferred is removed, the temporary substrate 920 and bonding adhesive 910 in the second substrate to be transferred are removed, and the third epitaxial substrate SUB3 in the third substrate to be transferred is removed, thus obtaining the first color emitting functional layer 3101, the second color emitting functional layer 3102, and the third color emitting functional layer 3103. An adjacent second color emitting layer 3112 and a third color emitting layer 3113 along the first direction X are electrically connected to the same pixel driving circuit 210 through the same bonding pad 410.

[0290] Combined with reference Figure 31N and Figure 31O ( Figure 31O For along Figure 31N (A cross-sectional view taken by the cut line in the diagram) A planarization layer PLN is formed on the side of the plurality of first color emitting functional layers 3101, the plurality of second color emitting functional layers 3102, and the plurality of third color emitting functional layers 3103 away from the substrate 100. A top electrode layer 500 is formed on the side of the planarization layer PLN away from the substrate 100. The planarization layer PLN has a plurality of vias VH. The top electrode layer 500 contacts the N-type semiconductor layer NSL in the first color emitting functional layer 3101, the N-type heavily doped semiconductor layer N++ in the second color emitting functional layer 3102, and the N-type semiconductor layer NSL in the third color emitting functional layer 3103 through the plurality of vias VH in the planarization layer PLN.

[0291] Figures 32A-32H The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0292] Combined with reference Figure 32A and Figure 32B ( Figure 32B For along Figure 32A (The cross-sectional view of the cut line in the figure) forms multiple pixel driving circuits 210 on the substrate 100.

[0293] Combined with reference Figure 32C and Figure 32D ( Figure 32D For along Figure 32C (The cross-sectional view taken by the cut line in the figure) A plurality of bonding pads 410 are formed on the side of the pixel driving circuit 210 away from the substrate 100, and the plurality of bonding pads 410 are electrically connected to the plurality of pixel driving circuits 210.

[0294] Combined with reference Figure 32E and Figure 32F ( Figure 32F For along Figure 32E(A cross-sectional view taken by the cut line in the figure) shows that multiple first-color emitting functional layers 3101, multiple second-color emitting functional layers 3102, and multiple third-color emitting functional layers 3103 are formed on the side of the bonding pad 410 away from the substrate 100. Two adjacent first-color emitting functional layers 3101 along the second direction Y are connected to the same bonding pad 410. Along the direction away from the substrate 100, one of the first-color emitting functional layers 3101 includes an N-type semiconductor layer NSL, a first-color emitting layer 3111, a P-type heavily doped semiconductor layer P++, and an N-type heavily doped semiconductor layer N++. This first-color emitting functional layer 3101 is connected to the bonding pad 410 through a second electrode 330. The other first-color emitting functional layer 3101 includes a P-type semiconductor layer PSL, a first-color emitting layer 3111, and an N-type semiconductor layer NSL. This first-color emitting layer 3111 is connected to a bonding pad 410 through a first electrode 320. The second color emitting functional layer 3102 includes a P-type semiconductor layer PSL, a second color emitting layer 3112, and an N-type semiconductor layer NSL. The second color emitting functional layer 3102 is connected to a bonding pad 410 via a first electrode 320. The third color emitting functional layer 3103 includes a P-type semiconductor layer PSL, a second color emitting layer 3112, and an N-type semiconductor layer NSL. The third color emitting functional layer 3103 is connected to a bonding pad 410 via a first electrode 320.

[0295] Combined with reference Figure 32G and Figure 32H ( Figure 32H For along Figure 32G (The cross-sectional view taken by the cut line in the figure) A planarization layer PLN and a top electrode layer 500 are formed on the side of the first color light-emitting functional layer 3101, the multiple second color light-emitting functional layers 3102 and the multiple third color light-emitting functional layers 3103 away from the substrate 100. The top electrode layer 500 is in contact with the multiple first color light-emitting functional layers 3101, the multiple second color light-emitting functional layers 3102 and the multiple third color light-emitting functional layers 3103 through the vias VH in the planarization layer PLN.

[0296] Figures 33A-33H The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0297] Combined with reference Figure 33A and Figure 33B ( Figure 33B For along Figure 33A (The cross-sectional view of the cut line in the figure) forms multiple pixel driving circuits 210 on the substrate 100.

[0298] Combined with reference Figure 33C and Figure 33D ( Figure 33DFor along Figure 33C (The cross-sectional view taken by the cut line in the figure) A plurality of bonding pads 410 are formed on the side of the pixel driving circuit 210 away from the substrate 100, and the plurality of bonding pads 410 are electrically connected to the plurality of pixel driving circuits 210.

[0299] Combined with reference Figure 33E and Figure 33F ( Figure 33F For along Figure 33E (A cross-sectional view taken by the cut line in the figure) shows that multiple first-color emitting functional layers 3101, multiple second-color emitting functional layers 3102, and multiple third-color emitting functional layers 3103 are formed on the side of the bonding pad 410 away from the substrate 100. Two adjacent first-color emitting functional layers 3101 along the second direction Y are connected to the same bonding pad 410. Along the direction away from the substrate 100, one of the first-color emitting functional layers 3101 includes an N-type semiconductor layer NSL, a first-color emitting layer 3111, a P-type heavily doped semiconductor layer P++, and an N-type heavily doped semiconductor layer N++. This first-color emitting functional layer 3101 is connected to the bonding pad 410 through a second electrode 330. The other first-color emitting functional layer 3101 includes a P-type semiconductor layer PSL, a first-color emitting layer 3111, and an N-type semiconductor layer NSL. This first-color emitting functional layer 3101 is connected to the bonding pad 410 through a first electrode 320.

[0300] Along the second direction Y, a second color emitting functional layer 3102 and a third color emitting functional layer 3103 adjacent to each other are connected to the same bonding pad 410. Along the direction away from the substrate 100, the second color emitting functional layer 3102 includes an N-type semiconductor layer NSL, a second color emitting layer 3112, a P-type heavily doped semiconductor layer P++, and an N-type heavily doped semiconductor layer N++. The second color emitting functional layer 3102 is connected to the bonding pad 410 through a second electrode 330. The third color emitting functional layer 3103 includes a P-type semiconductor layer PSL, a third color emitting layer 3113, and an N-type semiconductor layer NSL. The third color emitting functional layer 3103 is connected to the bonding pad 410 through a first electrode 320.

[0301] Combined with reference Figure 33G and Figure 33H ( Figure 33H For along Figure 33G(The cross-sectional view taken by the cut line in the figure) A planarization layer PLN and a top electrode layer 500 are formed on the side away from the substrate 100 of the plurality of first color light-emitting functional layers 3101, the plurality of second color light-emitting functional layers 3102 and the plurality of third color light-emitting functional layers 3103. The top electrode layer 500 contacts the plurality of first color light-emitting functional layers 3101, the plurality of second color light-emitting functional layers 3102 and the plurality of third color light-emitting functional layers 3103 through the vias VH in the planarization layer PLN.

[0302] Figures 34A-34J The diagram schematically illustrates the fabrication process of a display substrate according to some embodiments of the present invention.

[0303] Combined with reference Figure 34A and Figure 34B ( Figure 34B For along Figure 34A (The cross-sectional view of the cut line in the figure) forms multiple pixel driving circuits 210 on the substrate 100.

[0304] Combined with reference Figure 34C and Figure 34D ( Figure 34D For along Figure 34C (The cross-sectional view taken by the cut line in the figure) A plurality of bonding pads 410 are formed on the side of the pixel driving circuit 210 away from the substrate 100, and the plurality of bonding pads 410 are electrically connected to the plurality of pixel driving circuits 210.

[0305] Combined with reference Figure 34E and Figure 34F ( Figure 34F For along Figure 34E (A cross-sectional view taken by the cut line in the image) shows that multiple third-color emitting functional layers 3103 are formed on the side of the bonding pad 410 away from the substrate 100. These multiple third-color emitting functional layers 3103 include multiple sets of third-color emitting functional groups 3103X. Each third-color emitting functional group 3103X includes two adjacent third-color emitting functional layers 3103 along the second direction Y, and these two third-color emitting functional layers 3103 are connected to the same bonding pad 410. Within a third-color emitting functional group 3103X, along the direction away from the substrate 100, a third-color emitting functional layer 3103 includes a P-type semiconductor layer PSL, a third-color emitting layer 3113, and an N-type semiconductor layer NSL. This third-color emitting functional layer 3103 is connected to the bonding pad 410 through the first electrode 320. Another third color emitting functional layer 3103 includes an N-type semiconductor layer NSL, a third color emitting layer 3113, a P-type heavily doped semiconductor layer P++, and an N-type heavily doped semiconductor layer N++. The third color emitting functional layer 3103 is connected through a second electrode 330 and a bonding pad 410.

[0306] Combined with reference Figure 34G and Figure 34H ( Figure 34H For along Figure 34G (The cross-sectional view taken by the cut line in the figure) A planarization layer PLN and a top electrode layer 500 are formed on the side of the multiple third color light-emitting functional layers 3103 away from the substrate 100. The top electrode layer 500 contacts the multiple third color light-emitting functional layers 3103 respectively through the vias VH in the planarization layer PLN.

[0307] Combined with reference Figure 34I and Figure 34J ( Figure 34J For along Figure 34I (A cross-sectional view taken by the cut line in the image) shows that a barrier layer BANK and a color conversion layer 700 are formed on the side of the top electrode layer 500 away from the substrate 100. The barrier layer BANK includes multiple openings KK, and the color conversion layer 700 includes multiple first color conversion portions 710, multiple second color conversion portions 720, and multiple third color conversion portions 730, which are respectively located within the multiple openings KK. The material of the first color conversion portion 710 includes a first color quantum dot material, the material of the second color conversion portion 720 includes a second color quantum dot material, and the third color conversion portion 730 includes a transparent material and scattering particles doped within the transparent material.

[0308] It should be understood that the display device according to some exemplary embodiments of the present invention has all the features and advantages of the above-described display substrate, which can be referred to the above description of the display substrate and will not be repeated here.

[0309] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0310] While some embodiments of the general inventive concept of this utility model have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this utility model, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate; A driving circuit layer, located on the substrate, includes a plurality of pixel driving circuits; and A light-emitting device layer is located on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices, which are electrically connected to the driving circuit layer. Each light-emitting device includes a light-emitting layer, a first light-emitting functional layer, a second light-emitting functional layer, a first electrode, and a second electrode. The substrate has a first surface facing the driving circuit layer. Along a direction perpendicular to the first surface, the first light-emitting functional layer and the second light-emitting functional layer are located on opposite sides of the light-emitting layer. The first electrode is located on the side of the first light-emitting functional layer away from the light-emitting layer, and the second electrode is located on the side of the second light-emitting functional layer away from the light-emitting layer. The display substrate includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device; The plurality of said sub-pixels include at least one sub-pixel group, the sub-pixel group including at least two said light-emitting devices and one said pixel driving circuit, the two said light-emitting devices being electrically connected to the same said pixel driving circuit; and The sub-pixel group includes at least one first sub-pixel and at least one second sub-pixel. In the light-emitting device of the at least one first sub-pixel, the first light-emitting functional layer is located on the side of the light-emitting layer closer to the substrate. In the light-emitting device of the at least one second sub-pixel, the second light-emitting functional layer is located on the side of the light-emitting layer closer to the substrate. 2.The display substrate of claim 1, wherein, In at least one of the said sub-pixel groups, the emitted light color of at least one first sub-pixel is the same as the emitted light color of at least one second sub-pixel; and / or, In at least one of the sub-pixel groups, the emitted light color of at least one first sub-pixel is different from the emitted light color of at least one second sub-pixel. 3.The display substrate according to claim 1 or 2, wherein, In at least one of the sub-pixel groups, the light-emitting devices of at least one first sub-pixel and the light-emitting devices of at least one second sub-pixel are arranged adjacent to each other along a first direction; and / or, In at least one of the sub-pixel groups, the light-emitting devices of at least one first sub-pixel and the light-emitting devices of at least one second sub-pixel are arranged adjacent to each other along a second direction, and the first direction intersects the second direction. 4.The display substrate of claim 3, wherein, The plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels, wherein the emitted light colors of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are different from each other; The plurality of sub-pixels include a plurality of pixel units arranged along a first direction and a second direction. Each pixel unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel arranged along the first direction. The second color sub-pixel is located between the first color sub-pixel and the third color sub-pixel. In at least one of the pixel units, at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel belongs to the sub-pixel group. 5.The display substrate of claim 4, wherein, At least one of the sub-pixel groups includes at least one first sub-pixel group, the first sub-pixel group comprising two first color sub-pixels adjacent along the second direction; and / or, At least one of the said sub-pixel groups includes at least one second sub-pixel group, the second sub-pixel group comprising two adjacent second color sub-pixels along a second direction; and / or, At least one of the sub-pixel groups includes at least one third sub-pixel group, the third sub-pixel group including two third color sub-pixels that are adjacent along the second direction. 6.The display substrate of claim 5, wherein, Two adjacent pixel units along the second direction include a first sub-pixel group, a second sub-pixel group, and a third sub-pixel group. 7.The display substrate of claim 4, wherein, At least one of the sub-pixel groups includes at least one fourth sub-pixel group, the fourth sub-pixel group including a first-color sub-pixel and a second-color sub-pixel adjacent along the first direction; and / or, At least one of the sub-pixel groups includes at least one fifth sub-pixel group, the fifth sub-pixel group including a first-color sub-pixel and a third-color sub-pixel adjacent along the first direction; and / or, At least one of the sub-pixel groups includes at least one sixth sub-pixel group, the sixth sub-pixel group including a second color sub-pixel and a third color sub-pixel that are adjacent along the first direction. 8.The display substrate of claim 7, wherein, Two adjacent pixel units along the first direction include a fourth sub-pixel group, a fifth sub-pixel group, and a sixth sub-pixel group. 9.The display substrate of claim 7, wherein, In one pixel unit, the pixel driving circuit in the first color sub-pixel is electrically connected only to the light-emitting device in the first color sub-pixel, and the light-emitting devices in the second color sub-pixel and the light-emitting devices in the third color sub-pixel are electrically connected to the same pixel driving circuit. 10.The display substrate of claim 7, wherein, Two adjacent pixel units along the second direction include two sixth sub-pixel groups and a first sub-pixel group, wherein the first sub-pixel group includes two first color sub-pixels that are adjacent along the second direction. 11.The display substrate of claim 3, wherein, The plurality of sub-pixels include a plurality of first color sub-pixels, a plurality of second color sub-pixels, and a plurality of third color sub-pixels, wherein the emitted light colors of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are different from each other; The plurality of sub-pixels include a plurality of pixel units arranged along a first direction and a second direction. Each pixel unit includes two first color sub-pixels, at least one second color sub-pixel, and at least one third color sub-pixel. The two first color sub-pixels are arranged adjacent to each other along the first direction or the second direction. as well as At least one of the sub-pixel groups includes a seventh sub-pixel group, the seventh sub-pixel group including two adjacent first color sub-pixels, and at least one of the pixel units includes the seventh sub-pixel group. 12.The display substrate of claim 11, wherein, Two first color sub-pixels are arranged adjacently along the first direction, a second color sub-pixel is located on one side of the two first color sub-pixels along the first direction, and a third color sub-pixel is located on the side of the second color sub-pixel away from the first color sub-pixel; and The seventh sub-pixel group includes two adjacent sub-pixels of the first color along the first direction. 13.The display substrate according to claim 11 or 12, wherein, In at least one of the pixel units, the pixel driving circuit in the second color sub-pixel is electrically connected only to the light-emitting device in that second color sub-pixel; and / or, In at least one of the pixel units, the pixel driving circuit in the third color sub-pixel is electrically connected only to the light-emitting device in the third color sub-pixel. 14.The display substrate of claim 12, wherein, At least one of the pixel units includes a sixth sub-pixel group, the sixth sub-pixel group including a second color sub-pixel and a third color sub-pixel that are adjacent along the first direction. 15.The display substrate of claim 12, wherein, Two adjacent pixel units along the second direction comprise a second sub-pixel group, the second sub-pixel group comprising two adjacent second color sub-pixels along the second direction; and / or, Two adjacent pixel units along the second direction comprise a third sub-pixel group, the third sub-pixel group comprising two adjacent third color sub-pixels along the second direction. 16.The display substrate according to any one of claims 1-2, 4-12, 14-15, wherein, In the light-emitting device of the first sub-pixel, the first light-emitting functional layer includes a P-type semiconductor layer, and the second light-emitting functional layer includes an N-type semiconductor layer; In the light-emitting device of the second sub-pixel, the second light-emitting functional layer includes an N-type semiconductor layer, and the first light-emitting functional layer includes a P-type heavily doped semiconductor layer and an N-type heavily doped semiconductor layer located on the side of the P-type heavily doped semiconductor layer away from the substrate. as well as The second electrode of the first sub-pixel and the first electrode of the second sub-pixel are located in the same layer. 17.The display substrate according to any one of claims 1-2, 4-12, 14-15, wherein, In the light-emitting device of the first sub-pixel, The first light-emitting functional layer includes a P-type semiconductor layer, and the second light-emitting functional layer includes an N-type heavily doped semiconductor layer and a P-type heavily doped semiconductor layer located on the side of the N-type heavily doped semiconductor layer away from the substrate. In the light-emitting device of the second sub-pixel, the second light-emitting functional layer includes an N-type semiconductor layer, and the first light-emitting functional layer includes a P-type semiconductor layer; and The second electrode of the first sub-pixel and the first electrode of the second sub-pixel are located in the same layer. 18.The display substrate of claim 17, wherein, The light-emitting device layer includes a top electrode layer, the second electrode of the first sub-pixel and the first electrode of the second sub-pixel are located in the top electrode layer, and the material of the top electrode layer includes a transparent conductive material.

19. The display substrate of claim 18, wherein, The orthogonal projection of the top electrode layer on the substrate covers the orthogonal projection of the light-emitting layer on the substrate; and The display substrate further includes an auxiliary electrode located on the side of the top electrode layer away from the substrate. The auxiliary electrode is electrically connected to the top electrode layer, and the orthographic projection of the auxiliary electrode on the substrate is spaced apart from the orthographic projection of the light-emitting layer on the substrate. 20.The display substrate according to any one of claims 4-12, 14-15, wherein, The light-emitting device of the first color sub-pixel emits light of the first color, the light-emitting device of the second color sub-pixel emits light of the second color, and the light-emitting device of the third color sub-pixel emits light of the third color.

21. The display substrate of any one of claims 4-12, 14-15, wherein, The light-emitting devices of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel emit light of the same color respectively; The display substrate further includes a color conversion layer located on the side of the light-emitting device layer away from the substrate. The color conversion layer includes a first color conversion portion located on the side of the light-emitting device of the first color sub-pixel away from the substrate, a second color conversion portion located on the side of the light-emitting device of the second color sub-pixel away from the substrate, and a third color conversion portion located on the side of the light-emitting device of the third color sub-pixel away from the substrate. The light emitted by the light-emitting device becomes a first color after passing through the first color conversion section, the light emitted by the light-emitting device becomes a second color after passing through the second color conversion section, and the light emitted by the light-emitting device becomes a third color after passing through the third color conversion section.

22. A pixel circuit, comprising: The pixel circuit includes a pixel driving circuit, at least two light-emitting devices, and a second power signal terminal; The light-emitting device includes a first electrode and a second electrode; as well as The at least two light-emitting devices include at least one first light-emitting device and at least one second light-emitting device. The first electrode of the first light-emitting device is electrically connected to the pixel driving circuit, the second electrode of the first light-emitting device is electrically connected to the second power signal terminal, the second electrode of the second light-emitting device is electrically connected to the pixel driving circuit, and the first electrode of the second light-emitting device is electrically connected to the second power signal terminal.

23. A display device comprising: The display device includes a display substrate according to any one of claims 1-21 or a pixel circuit according to claim 22.

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