Wearable electroencephalogram monitoring device

Abstract

The wearable electroencephalogram monitoring device comprises an electroencephalogram cap, an earphone and an electroencephalogram collecting device, a plurality of electroencephalogram electrodes are arranged on the electroencephalogram cap, and the electroencephalogram collecting device is installed on the electroencephalogram cap and comprises a shell. A power supply interface, a power supply circuit, a sound source interface, an audio generation circuit, an audio drive circuit, an earphone interface, a signal acquisition interface, a signal acquisition circuit, a control circuit, a storage circuit, an operation indication circuit and a communication circuit are integrated in the shell; the electroencephalogram acquisition assembly and the sound stimulation assembly are integrated to form the electroencephalogram acquisition device, the electroencephalogram stimulation device is installed on the electroencephalogram cap, generation of sound stimulation and acquisition of signals are facilitated, occupied space is small, the electroencephalogram acquisition device is neat and orderly, circuits in the electroencephalogram acquisition device are optimally designed, and the electroencephalogram acquisition device is convenient to use. And multi-channel electroencephalogram signals can be collected more accurately.

Description

Technical Field

[0001] This utility model relates to the field of electroencephalogram (EEG) signal acquisition technology, and in particular to a wearable EEG monitoring device. Background Technology

[0002] An EEG cap is worn on the head of the user to detect their electroencephalogram (EEG) signals. The cap is designed for comfortable wear, good contact, and normal signal acquisition. Existing EEG caps, earphones for sound stimulation, EEG acquisition devices containing EEG acquisition circuitry, and sound stimulation devices containing sound stimulation generation circuitry are generally designed separately, resulting in large space requirements and a cluttered appearance. For example, the utility model patent with application number CN2 01510038162.9, entitled "A Portable EEG Headset," discloses an EEG headset with electrodes and earphones. While this existing patent integrates the EEG electrodes and earphones into the headset, it does not integrate the EEG acquisition device and the sound stimulation device. Therefore, this utility model designs a wearable EEG monitoring device that integrates both the EEG acquisition device and the sound stimulation device into an EEG cap. This facilitates sound stimulation generation and signal acquisition while occupying less space and maintaining a neat and orderly appearance. Utility Model Content

[0003] This invention addresses the problems and shortcomings of existing technologies by providing a wearable electroencephalogram (EEG) monitoring device.

[0004] The present invention solves the above-mentioned technical problems through the following technical solution:

[0005] This utility model provides a wearable electroencephalogram (EEG) monitoring device, characterized in that it includes an EEG cap and earphones for the user to wear, and an EEG acquisition device. The EEG cap is equipped with multiple EEG electrodes, and the EEG acquisition device is installed on the EEG cap. The EEG acquisition device includes a housing, and the housing integrates a power supply interface, a power circuit, a sound source interface, an audio generation circuit, an audio drive circuit, an earphone interface, a signal acquisition interface, a signal acquisition circuit, a control circuit, a storage circuit, an operation indicator circuit, and a communication circuit.

[0006] The power supply circuit is electrically connected to the power supply interface, control circuit, audio generation circuit, audio drive circuit, signal acquisition circuit, storage circuit, operation indicator circuit, and communication circuit to supply power to the circuit. The sound source interface, audio generation circuit, and control circuit are electrically connected in sequence to generate audio signals for the audio generation circuit. The audio generation circuit and audio drive circuit are electrically connected to generate audio drive signals for the audio drive circuit. The headphone interface, audio drive circuit, and control circuit are electrically connected in sequence to emit sound stimulation through the headphone interface for the audio drive circuit. The audio drive circuit and signal acquisition circuit are electrically connected to generate synchronization signals for the signal acquisition circuit. The EEG electrodes, signal acquisition interface, signal acquisition circuit, and control circuit are electrically connected in sequence to acquire multi-channel EEG signals sensed by multiple EEG electrodes through the signal acquisition interface for the signal acquisition circuit. The storage circuit, operation indicator circuit, and communication circuit are all electrically connected to the control circuit.

[0007] The positive and progressive effects of this utility model are as follows:

[0008] This invention integrates both the EEG acquisition component and the acoustic stimulation component to form an EEG acquisition device, and installs the EEG stimulation device on the EEG cap, which is beneficial for the generation of acoustic stimulation and the acquisition of signals. It also occupies little space and is neat and orderly. Furthermore, this invention has optimized the design of each circuit in the EEG acquisition device, which can more accurately acquire multi-channel EEG signals. Attached Figure Description

[0009] Figure 1-3 This is a schematic diagram of the EEG cap according to a preferred embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of a wearable electroencephalogram (EEG) monitoring device according to a preferred embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram of the power supply circuit of a preferred embodiment of the present invention.

[0012] Figure 6 This is a circuit diagram of the main power switch of a preferred embodiment of the present invention.

[0013] Figure 7 This is a first DC-DC circuit diagram of a preferred embodiment of the present invention.

[0014] Figure 8 This is a diagram of the first protection circuit and communication circuit of a preferred embodiment of the present invention.

[0015] Figure 9 The diagram shows the first voltage regulator circuit, the first switching circuit, and the audio driver circuit of a preferred embodiment of this utility model.

[0016] Figure 10 The diagram shows the second switching circuit and the audio generation circuit of a preferred embodiment of this utility model.

[0017] Figure 11 The diagram shows the third switching circuit and storage circuit of a preferred embodiment of this utility model.

[0018] Figure 12 The diagram shows the fourth switching circuit, filter circuit, second DC-DC circuit, second voltage regulator circuit, and third voltage regulator circuit of a preferred embodiment of this utility model.

[0019] Figure 13 This is a control circuit diagram of a preferred embodiment of the present invention.

[0020] Figure 14 The diagram shows the signal acquisition interface and EEG acquisition protection circuit of a preferred embodiment of this utility model.

[0021] Figure 15 This is a circuit diagram of a preferred embodiment of the present invention for signal acquisition.

[0022] Figure 16 This is a circuit diagram of the operation indicator of a preferred embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0024] like Figure 1-4 As shown, this embodiment provides a wearable EEG monitoring device, which includes an EEG cap 100 and an earphone 200 for the user to wear, as well as an EEG acquisition device 300. The EEG cap 100 is equipped with multiple EEG electrodes 101. The EEG acquisition device 300 is mounted on the EEG cap 100. The EEG acquisition device 300 includes a housing 301, which integrates a power supply interface 302, a power circuit 303, an audio source interface 304, an audio generation circuit 305, an audio driving circuit 306, an earphone interface 307, a signal acquisition interface 308, a signal acquisition circuit 309, a control circuit 310, a storage circuit 311, a running indicator circuit 312, and a communication circuit 313.

[0025] The power supply circuit 303 is used to connect to an external power supply through the power supply interface 302 and convert the external power supply into a power supply voltage to power the control circuit 310, audio generation circuit 305, audio drive circuit 306, signal acquisition circuit 309, storage circuit 311, operation indicator circuit 312 and communication circuit 313.

[0026] The control circuit 310 is connected to the host computer via the communication circuit 313. The sound source interface 304, the audio generation circuit 305 and the control circuit 310 are electrically connected in sequence. After receiving an EEG signal acquisition command through the communication circuit 313, the control circuit 310 controls the sending of a trigger signal to the audio generation circuit 305. After receiving the trigger signal, the audio generation circuit 305 generates an audio signal based on the sound source obtained through the sound source interface 304.

[0027] The audio generation circuit 305 and the audio driving circuit 306 are electrically connected. The headphone interface 307, the audio driving circuit 306, and the control circuit 310 are electrically connected in sequence. The audio driving circuit 306 is used to receive audio signals and generate audio driving signals containing audio signals based on the audio signals. The control circuit 310 is used to control the audio driving circuit 306 to output audio driving signals of a set duration through the headphone interface 307, so that the headphones 200 output sound stimuli of a set duration to act on the collector and realize auditory evoked potentials.

[0028] The audio driving circuit 306 and the signal acquisition circuit 309 are electrically connected. The EEG electrodes 101, the signal acquisition interface 308, the signal acquisition circuit 309, and the control circuit 310 are electrically connected in sequence. The audio driving circuit 306 is used to generate a synchronization signal based on the audio driving signal and transmit it to the signal acquisition circuit 309. The signal acquisition circuit 309 is used to acquire the multi-channel EEG signals sensed by multiple EEG electrodes through the signal acquisition interface 308 and transmit the multi-channel EEG signals to the control circuit 310.

[0029] Both the storage circuit 311 and the communication circuit 313 are electrically connected to the control circuit 310. The control circuit 310 is used to store the multi-channel EEG signals of the collector in the storage circuit 311 and upload them to the host computer through the communication circuit 313.

[0030] The operation indicator circuit 312 is electrically connected to the control circuit 310. The control circuit 310 is used to control the operation indicator circuit 312 to light up when the device is operating normally.

[0031] Among them, such as Figure 5 As shown, the power supply circuit 303 includes a main power switch circuit, a first DC-DC circuit, a first protection circuit, a first voltage regulator circuit, a first switching circuit, a second switching circuit, a third switching circuit, a fourth switching circuit, a filter circuit, a second DC-DC circuit, a second voltage regulator circuit, and a third voltage regulator circuit.

[0032] The input terminal of the main power switch circuit is electrically connected to the power supply interface 302 (such as a Type-C interface), and the output terminal of the main power switch circuit is electrically connected to the control circuit 310 through the first DC-DC circuit. The main power switch circuit is used to control the circuit 310 to turn on and adjust the output of the first power supply voltage VCC_5V based on the input voltage. The first DC-DC circuit is used to convert the first power supply voltage into the second power supply voltage VCC_3.3V and provide the second power supply voltage VCC_3.3V to the control circuit 310.

[0033] The output of the main power switch circuit is electrically connected to the communication circuit 313 through the first protection circuit to provide the VBUS voltage to the communication circuit 313. The output of the first DC-DC circuit is electrically connected to the communication circuit 313 to provide the second power supply voltage VCC_3.3V to the communication circuit 313.

[0034] The output of the main power switch circuit is electrically connected to the audio driver circuit 306 through the first voltage regulator circuit. The first voltage regulator circuit is used to regulate the first supply voltage VCC_5V to the regulated supply voltage VCC1_3V3A and provide the audio driver circuit 306 with a regulated supply voltage of 3.3V VCC1_3V3A. The output of the first DC-DC circuit is electrically connected to the audio driver circuit 306 through the first switch circuit and is used to provide the audio driver circuit 306 with a 3.3V supply voltage VCC1_3V3.

[0035] The output of the first DC-DC circuit is electrically connected to the audio generation circuit 305 through the second switching circuit to provide the audio generation circuit 305 with a 3.3V power supply voltage VCC2_3V3.

[0036] The output of the first DC-DC circuit is electrically connected to the storage circuit 311 through the third switching circuit to provide the storage circuit 311 with a 3.3V power supply voltage VCC3_3V3.

[0037] The output of the first DC-DC circuit is electrically connected to the input of the fourth switching circuit. The output of the fourth switching circuit is electrically connected to the signal acquisition circuit 309 through a filter circuit to provide the filtered voltage DVDD_33 to the signal acquisition circuit 309. The output of the fourth switching circuit is also electrically connected to the signal acquisition circuit 309 through the second DC-DC circuit and the second voltage regulator circuit, and also through the third voltage regulator circuit to provide the signal acquisition circuit with bipolar power supply voltages (AVSS and AVDD, respectively).

[0038] Among them, such as Figure 6As shown, the power switch circuit includes: a main switch K3 (model K8-5854P-L1) and a power switch chip U4 (model TPS2553DRVR). The switching terminal of the main switch K3 is embedded in the housing 301. The IN pin (pin 6) of the power switch chip U4 is electrically connected to the power supply interface 302, and also electrically connected to pin 2 of the main switch K3, and grounded through capacitor C30. The EN pin (pin 4) of the power switch chip U4 is electrically connected to pin 3 of the main switch K3 through resistor R14, and also grounded through resistor R77, and grounded through capacitor C32. The GND pin (pin 4) of the power switch chip U4 is also connected to the main switch K3.

[0039] Pin 5 and EP pin (pin 7) are both grounded, FAULT (pin 3) is electrically connected to the power supply interface 302 through the power status indicator D2 and resistor R17, ILIM pin (pin 2) is grounded through resistor R15, and the OUT pin (pin 1) of the power switch chip U4 is used to output the first supply voltage VCC_5V and is also grounded through capacitor C31.

[0040] like Figure 7 As shown, the first DC-DC circuit includes: a power management chip U1 (TPS62140RGTR). The two PVIN pins (pins 11 and 12), AVIN pin (pin 10), and EN pin (pin 13) of the power management chip U1 are electrically connected to the OUT pin (pin 1) of the power switch chip U4 to receive the first supply voltage VCC_5V. It is also grounded through series resistors R9 and R12, capacitors C105, C24, and C23. The FSW pin (pin 7) of the power management chip U1 is grounded through resistor R12, the DEF pin (pin 8) is grounded through resistor R11, and the SS / TR pin (pin 9) is grounded through capacitor C2. 9. Grounding; the two PGND pins (pins 15 and 16), AGND pin (pin 6), and EP pin (pin 17) of the power management chip U1 are all grounded; the FB pin (pin 5) of the power management chip U1 is grounded through resistor R13, and the VOS pin (pin 14) is grounded through a series of resistors R10 and R13; the three SW pins (pins 1, 2, and 3) of the power management chip U1 output the second supply voltage VCC_3.3V through inductors L1 and L8 in series. Inductors L1 and L8 are grounded through capacitors C25, C26, C27, and C28, respectively. The end of inductor L8 furthest from inductor L1 is grounded through capacitors C108 and C107, respectively.

[0041] like Figure 8As shown, the first protection circuit includes: resistor R20 and diode D5. One end of resistor R20 is electrically connected to the OUT pin (pin 1) of power switch chip U4 to access the first supply voltage VCC_5V, and the other end is electrically connected to the cathode of diode D5. The anode of diode D5 is grounded, and the cathode is electrically connected to communication circuit 313 to provide VBUS voltage.

[0042] like Figure 9 As shown, the first voltage regulator circuit includes: a linear regulator U8 (model SOT23-5), whose VIN pin (pin 1) is electrically connected to the OUT pin (pin 1) of the power switch chip U4 to receive the first supply voltage VCC_5V, and is also grounded through capacitor C45 and capacitor C46; the EN pin (pin 3) of the linear regulator U8 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit, the GND pin (pin 2) is grounded, and the BP pin (pin 4) is grounded through capacitor C49; the VOUT pin (pin 5) of the linear regulator U8 is electrically connected to the audio driver circuit 306, and is also grounded through capacitor C47 and capacitor C48, for providing a 3.3V regulated supply voltage VCC1_3V3A to the audio driver circuit 306.

[0043] like Figure 9 As shown, the first switching circuit includes a transistor Q3 (model DTC143ZE) and a field-effect transistor M2 (model SOT1220). The base of transistor Q3 is electrically connected to the PE1 pin of the main control chip U13 in the control circuit 310, and the emitter of transistor Q3 is grounded. The source of field-effect transistor M2 is electrically connected to the inductor L8 of the power management chip U1 through resistor R21 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C38 and electrically connected to the collector of transistor Q3 through resistor R22. The gate of field-effect transistor M2 is electrically connected to the collector of transistor Q3. The drain of field-effect transistor M2 is electrically connected to the audio driver circuit 306 and is also grounded through capacitor C39 and capacitor C40, which are used to provide a 3.3V voltage VCC1_3V3 to the audio driver circuit 306.

[0044] like Figure 10As shown, the second switching circuit includes: transistor Q1 (model DTC143ZE) and field-effect transistor M1 (model SOT1220). The base of transistor Q1 is electrically connected to pin PA3 of the main control chip U13 in the control circuit 310, and the emitter of transistor Q1 is grounded. The source of field-effect transistor M1 is electrically connected to inductor L8 of power management chip U1 through resistor R6 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C18 and electrically connected to the collector of transistor Q1 through resistor R7. The gate of field-effect transistor M1 is electrically connected to the collector of transistor Q1. The drain of field-effect transistor M1 is electrically connected to pin 3V3 (pin 1) of audio generation chip U2 in audio generation circuit 305, and is also grounded through capacitor C19 and capacitor C20, to provide 3.3V voltage VCC2_3V3 to audio generation circuit 305.

[0045] like Figure 11 As shown, the third switching circuit includes: transistor Q4 (model DTC143ZE) and field-effect transistor M3 (model SOT1220). The base of transistor Q4 is electrically connected to pin PA7 of the main control chip U13 in the control circuit 310, and the emitter of transistor Q4 is grounded. The source of field-effect transistor M3 is electrically connected to inductor L8 of power management chip U1 through resistor R29 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C50 and electrically connected to the collector of transistor Q4 through resistor R30. The gate of field-effect transistor M3 is electrically connected to the collector of transistor Q4. The drain of field-effect transistor M3 is electrically connected to storage circuit 311 and is also grounded through capacitor C95 and capacitor C51, which are used to provide 3.3V voltage VCC3_3V3 to storage circuit 311.

[0046] like Figure 12 As shown, the fourth switching circuit includes: transistor Q5 (model DTC143ZE) and field-effect transistor M4 (model SOT1220). The base of transistor Q5 is electrically connected to pin PI9 of the main control chip U13 in control circuit 310, and the emitter of transistor Q5 is grounded. The source of field-effect transistor M4 is electrically connected to inductor L8 of power management chip U1 through resistor R52 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C71 and electrically connected to the collector of transistor Q5 through resistor R53. The gate of field-effect transistor M4 is electrically connected to the collector of transistor Q5. The drain of field-effect transistor M4 is electrically connected to the filter circuit, the second DC-DC circuit and the third voltage regulator circuit respectively, and is also grounded through capacitor C72 to provide a 3.3V voltage VCC4_3V3.

[0047] like Figure 12As shown, the filter circuit includes: inductor L2, capacitor C73, capacitor C74 and capacitor C75. One end of inductor L2 is electrically connected to the drain of field-effect transistor M4, and is also grounded through capacitor C73 and capacitor C74. The other end of inductor L2 is electrically connected to the signal acquisition circuit and is also grounded through capacitor C75, which is used to provide the filtered 3.3V voltage DVDD_33 to the signal acquisition circuit.

[0048] like Figure 12 As shown, the second DC-DC circuit includes: a switching regulator chip U11 (model TPS60403DBVR), the IN pin (pin 2) of the switching regulator chip U11 is electrically connected to the drain of the field-effect transistor M4 through inductor L5, and is also grounded through inductor L5 and capacitor C84 connected in series, and is also grounded through capacitor C85 and capacitor C86; the GND pin (pin 4) of the switching regulator chip U11 is grounded, and capacitor C83 is connected between the CFLY- pin (pin 3) and the CFLY+ pin (pin 5); the OUT pin (pin 1) of the switching regulator chip U11 is electrically connected to the second voltage regulator circuit through inductor L6, and is also grounded through capacitors C87 and C88 respectively.

[0049] like Figure 12 As shown, the second voltage regulator circuit includes: a negative linear regulator chip U12 (model LT3094EMSE). The IN1 pin (pin 1), IN2 pin (pin 2), EP pin (pin 13), PGFB pin (pin 5), and EN / UV pin (pin 3) of the negative linear regulator chip U12 are all electrically connected to inductor L6 and grounded through capacitors C89 and C90 respectively. The ILIM pin (pin 6) of the negative linear regulator chip U12 is grounded through resistor R57, and the GND pin (pin 9) is grounded through resistor R57. The SET pin (pin 8) is grounded through a parallel resistor R56 and a capacitor C94. The OUTS pin (pin 10), OUT1 pin (pin 11), and OUT2 pin (pin 12) of the negative linear regulator chip U12 are all electrically connected to the signal acquisition circuit 309 through inductor L7, and are also grounded through inductor L7 and capacitor C93, capacitor C91, and capacitor C92, respectively, to provide the -2.5V voltage AVSS in the bipolar power supply voltage for the signal acquisition circuit.

[0050] like Figure 12As shown, the third voltage regulator circuit includes: a linear regulator chip U10 (model GM1200ACPZ). The IN pin (pin 1), IN1 pin (pin 2), PGFB pin (pin 6), and EN / UV pin (pin 3) of the linear regulator chip U10 are all electrically connected to the drain of the field-effect transistor M4 through inductor L3, and are also grounded in sequence through inductor L3 and capacitor C76, and also grounded through capacitors C77 and C78 respectively; the ILIM pin (pin 5) of the linear regulator chip U10 is connected to... The ground and two GND pins (pin 8 and pin 11) are grounded, and the SET pin (pin 7) is grounded through a parallel resistor R55 and a capacitor C82, respectively. The OUTS pin (pin 9) and OUT pin (pin 10) of the linear regulator chip U10 are both electrically connected to the signal acquisition circuit 309 through inductor L4, and are also grounded through inductor L4 and capacitor C81, capacitor C79, and capacitor C80, respectively, to provide the +2.5V voltage AVDD in the bipolar power supply voltage to the signal acquisition circuit.

[0051] In this plan, such as Figure 13As shown, the control circuit 310 includes: a main control chip U13, which is an STM32H743IIK6. The PA0, PA1, PA2, PA3, PE11, PE12, PE13, PE14, PC10, and PC11 pins of the main control chip U13 are all electrically connected to the audio generation circuit; the PE4, PE5, PE3, PE6, PE2, PB8, PB9, and PE1 pins of the main control chip U13 are also connected to the audio generation circuit. All are electrically connected to the audio driver circuit; pins PB3, PA15, PB5, PG9, PG13, PC13, PI8, PI7, PC9, and PI9 of the main control chip U13 are all electrically connected to the signal acquisition circuit; pins PB14, PB15, PG11, PB4, PC1, PD7, PA7, and PD8 of the main control chip U13 are all electrically connected to the storage circuit; pins PB11, PB12, and P... Pins D6 and PD5 are both electrically connected to the communication circuit; pins PA9, PA10, PA13, and PA14 of the main control chip U13 are all electrically connected to the debug printer interface; pins VDDA, VBAT, VREF+, and VDD1-VDD14 of the main control chip U13 are all connected to the second power supply voltage VCC_3.3V; pins VSSA, VREF-, and VSS1-VSS37 of the main control chip U13 are all grounded; and pin BOOT0 of the main control chip U13 is connected to... Resistor R67 is grounded, VCAP1 pin is grounded through capacitor C14, VCAP2 pin is grounded through capacitor C17, PDR_ON pin is grounded through resistor R68, the NRST pin of the main control chip U13 is electrically connected to pin 2 of the tactile switch K1 (model KMR221NGLFS), and is also connected to the second power supply voltage VCC_3.3V through resistor R2 and grounded through capacitor C16. Pins 1 and 4 of the tactile switch K1 are both grounded, and a crystal oscillator circuit is connected between the PH0 and PH1 pins of the main control chip U13.

[0052] In this plan, such as Figure 10As shown, the audio generation circuit includes: an audio generation chip U2 (model ESP32-C3); the 3V3 pin (pin 1) of the audio generation chip U2 is electrically connected to the drain of the field-effect transistor M1 to receive a 3.3V voltage VCC2_3V3; the EN pin (pin 2) of the audio generation chip U2 is electrically connected to the drain of the field-effect transistor M1 through resistor R74, and is also electrically connected to pin 2 of the tactile switch K4 (model KMR221NGLFS), and is also grounded through capacitor C106; the tactile switch K4... Pins 1 and 4 are grounded; pin IO6 (pin 5) of audio generation chip U2 is electrically connected to pin PE12 of main control chip U13, and pin IO7 (pin 6) is electrically connected to pin PE14 of main control chip U13; pin IO8 (pin 7) of audio generation chip U2 is electrically connected to pin PA0 of main control chip U13, and is also electrically connected to the drain of field-effect transistor M1 through resistor R75; pin IO9 (pin 8) of audio generation chip U2 is electrically connected to pin PA1 of main control chip U13, and is also electrically connected to the drain of field-effect transistor M1 through resistor R75. The audio source interface J2 (i.e., audio source interface 304) is electrically connected to pin 3; the IO10 pin (pin 10) of the audio generation chip U2 is electrically connected to the PE11 pin of the main control chip U13; the RXD0 pin (pin 11) and TXD0 pin (pin 12) of the audio generation chip U2 are electrically connected to pins 1 and 2 of the audio source interface J2, respectively. The audio source interface J2 is a USB communication interface or a serial communication interface, and pin 4 is grounded; the IO3 pin (pin 15) of the audio generation chip U2 is connected to the main control chip... The PA2 pin of chip U13 is electrically connected, the IO2 pin (pin 15) is electrically connected to the PE13 pin of the main control chip U13, the IO1 pin (pin 17) is electrically connected to the PC11 pin of the main control chip U13, and the IO0 pin (pin 18) is electrically connected to the PC10 pin of the main control chip U13; all GND pins (pins 9, 19, 20, 21, 22, 23, 24, 25, 26, and 27) of audio generation chip U2 are grounded.

[0053] In this plan, such as Figure 9As shown, the audio driver circuit includes: an audio driver chip U7 (model WM8978), whose LRC pin (pin 7) is electrically connected to the PE4 pin of the main control chip U13, its BCLK pin (pin 8) is electrically connected to the PE5 pin of the main control chip U13, its ADCDAT pin (pin 9) is electrically connected to the PE3 pin of the main control chip U13, its DDACAT pin (pin 10) is electrically connected to the PE6 pin of the main control chip U13, and its MCLK pin (pin 11) is electrically connected to the PE2 pin of the main control chip U13; the SCLK pin (pin 16) of the audio driver chip U7 is connected to the main control chip... The PB8 pin of U13 is electrically connected and also connected to a 3.3V voltage VCC1_3V3 via resistor R23; the SDIN pin (pin 17) of the audio driver chip U7 is electrically connected to the PB9 pin of the main control chip U13 and also connected to a 3.3V voltage VCC1_3V3 via resistor R24; the MODE pin (pin 18) of the audio driver chip U7 is grounded via resistor R27; the EP pin (pin 33), DGND pin (pin 12), SPKGND pin (pin 24), and AGND pin (pin 28) of the audio driver chip U7 are all grounded, and the DGND pin (pin 12) and SPKGND pin are also grounded. A resistor R28 is connected between pin D (pin 24); the VMID pin (pin 27) of the audio driver chip U7 is grounded through capacitor C103; the ROUT1 pin (pin 29) of the audio driver chip U7 is electrically connected to the headphone jack J6 (i.e., headphone jack 307) through capacitor C43, the LOUT1 pin (pin 30) is electrically connected to the headphone jack J6 through capacitor C44, and the LOUT1 pin (pin 30) is also electrically connected to the signal acquisition circuit 309 through capacitor C44 and resistor R25 to send a synchronization signal; the SPKVDD pin (pin 26) and AVDD pin (pin 3) of the audio driver chip U7 are also connected to the signal acquisition circuit 309 through capacitor C44 and resistor R25. 1) Both are electrically connected to the VOUT pin (pin 5) of the linear regulator U8; the SPKVDD pin (pin 26) of the audio driver chip U7 is grounded through parallel capacitors C36 and C41, and the AVDD pin (pin 31) is grounded through parallel capacitors C37 and C42, respectively, to provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driver chip U7; the DBVDD pin (pin 14) and DCVDD pin (pin 13) of the audio driver chip U7 are both electrically connected to the drain of the field-effect transistor M2, to provide a 3.3V voltage VCC1_3V3 for the audio driver chip U7.

[0054] In this design, the EEG cap 100 has eight EEG electrodes 101 arranged from front to back. The shell 301 also integrates an EEG acquisition and protection circuit. All eight EEG electrodes 101 are electrically connected to the signal acquisition circuit 309 through the signal acquisition interface 308 and the EEG acquisition and protection circuit.

[0055] Among them, such as Figure 14 As shown, the EEG acquisition protection circuit includes ESD protection circuit D6, ESD protection circuit D7 and ESD protection circuit D8.

[0056] Pin 2 of ESD protection circuit D6 is connected to a -2.5V voltage AVSS and grounded through capacitor C99. Pin 3 of ESD protection circuit D6 receives the reference signal EEG_SRB1 through signal acquisition interface J8 and is electrically connected to the signal acquisition circuit through resistor R40 to output the reference signal SRB1. Pin 4 of ESD protection circuit D6 receives the EEG signal EEG_IN2_P induced by the second EEG electrode through signal acquisition interface J8 and is electrically connected to the signal acquisition circuit through resistor R33 to output the EEG signal IN2_P. Pin 5 of ESD protection circuit D6 is connected to a +2.5V voltage AVDD and grounded through capacitor C96. Pin 6 of ESD protection circuit D6 receives the EEG signal EEG_IN1_P induced by the first EEG electrode through signal acquisition interface J8 and is electrically connected to the signal acquisition circuit through resistor R32 to output the EEG signal IN1_P.

[0057] Pin 1 of the ESD protection circuit D7 receives the EEG signal EEG_IN3_P sensed by the third EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R34 to output the EEG signal IN3_P. Pin 2 of the ESD protection circuit D7 is connected to a -2.5V voltage AVSS and is also grounded through capacitor C100. Pin 3 of the ESD protection circuit D7 receives the EEG signal EEG_IN4_P sensed by the fourth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R35 to output the EEG signal IN4_P. Pin 4 of the ESD protection circuit D7 receives the EEG signal EEG_IN5_P induced by the fifth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R36 to output the EEG signal IN5_P. Pin 5 of the ESD protection circuit D7 is connected to a +2.5V voltage AVDD and is also grounded through capacitor C97. Pin 6 of the ESD protection circuit D7 receives the EEG signal EEG_IN6_P induced by the sixth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R37 to output the EEG signal IN6_P.

[0058] Pin 1 of the ESD protection circuit D8 receives the EEG signal EEG_IN7_P induced by the seventh EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R38 to output the EEG signal IN7_P. Pin 2 of the ESD protection circuit D8 is connected to a -2.5V voltage AVSS and is also grounded through capacitor C101. Pin 3 of the ESD protection circuit D8 receives the EEG signal EEG_IN8_P induced by the eighth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R39 to output the EEG signal IN8_P. Pin 4 of the ESD protection circuit D8 receives the bias signal EEG_BIAS through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R41 to output the bias signal BIAS. Pin 5 of the ESD protection circuit D8 is connected to a +2.5V voltage AVDD and is also grounded through capacitor C98.

[0059] like Figure 15 As shown, the signal acquisition circuit 309 includes: a signal acquisition chip U9 (model ADS1299-4PAG). The SRB1 pin (pin 17) of the signal acquisition chip U9 is connected to the reference signal SRB1; the IN1P pin (pin 16) is connected to the EEG signal IN1_P; the IN2P pin (pin 14) is connected to the EEG signal IN2_P; the IN3P pin (pin 12) is connected to the EEG signal IN3_P; the IN4P pin (pin 10) is connected to the EEG signal IN4_P; the IN5P pin (pin 8) is connected to the EEG signal IN5_P; the IN6P pin (pin 6) is connected to the EEG signal IN6_P; the IN7P pin (pin 4) is connected to the EEG signal IN7_P; and the IN8P pin (pin 2) is connected to the EEG signal IN8_P. A capacitor C55 and a resistor R49 are connected in parallel between the BIASINV pin (pin 61) and the BIASIOUT pin (pin 62) of the signal acquisition chip U9, and then connected through a resistor R5. The bias signal BIAS is connected to the signal acquisition chip U9. The VCAP1 pin (pin 28) is connected to the -2.5V voltage AVSS through capacitor C67, the VCAP2 pin (pin 30) is connected to the -2.5V voltage AVSS through capacitor C59, the VCAP3 pin (pin 55) is connected to the -2.5V voltage AVSS through capacitors C60 and C61 connected in parallel, and the VCAP4 pin (pin 26) is connected to the -2.5V voltage AVSS through capacitor C62. The RESV1 pin (pin 31) and the three DGND pins (pins 33, 49 and 51) of the signal acquisition chip U9 are all grounded. The VREFP pin (pin 24) of the signal acquisition chip U9 is connected to the reference voltage VREFP, the VREFN pin (pin 25) is connected to the -2.5V voltage AVSS, and capacitors C56 and C57 are connected in parallel between the VREFP pin (pin 24) and the VREFN pin (pin 25).

[0060] The GPIO1 pin (pin 42) of the signal acquisition chip U9 is grounded through resistor R47, the GPIO2 pin (pin 44) is grounded through resistor R46, the GPIO3 pin (pin 45) is grounded through resistor R45, the GPIO4 pin (pin 46) is grounded through resistor R44, and the CLKSEL pin (pin 52) is grounded through resistor R48.

[0061] The CLK pin (pin 37) of the signal acquisition chip U9 and the PC9 pin of the main control chip U13

[0062] Electrical connections: PWDN pin (pin 35) is electrically connected to PI7 pin of the main control chip U13; RESET pin (pin 36) is electrically connected to PI8 pin of the main control chip U13; START pin (pin 38) is electrically connected.

[0063] — The DRDY pin (pin 47) is electrically connected to the PC13 pin of the main control chip U13, the DOUT pin (pin 43) is electrically connected to the PG13 pin of the main control chip U13, and the DOUT pin (pin 43) is electrically connected to the PG9 pin of the main control chip U13.

[0064] —Pin electrical connections: DIN pin (pin 34) is electrically connected to PB5 pin of the main control chip U13; CS pin (pin 39) is electrically connected to PA15 pin of the main control chip U13; SCLK pin (pin 40) is electrically connected to PB3 pin of the main control chip U13.

[0065] The two DVDD pins (pins 48 and 50) of the signal acquisition chip U9 are connected to the filtered voltage DVDD_33 and are also grounded through capacitors C52 and C53 respectively; all AVSS pins (pins 20, 23, 32, 58 and 57) and AVSS1 pin (pin 53) of the signal acquisition chip U9 are connected to the -2.5V voltage AVSS, and all AVDD pins (pins 19, 21, 22, 59 and 56) and AVSS1 pin (pin 54) are connected to the +2.5V voltage AVDD.

[0066] like Figure 11As shown, the storage circuit 311 includes: a storage chip J7 (model TF-01A); pin D0 (pin 7) of storage chip J7 is electrically connected to pin PB14 of main control chip U13 and is also connected to a 3.3V voltage VCC3_3V3 through resistor R66; pin D1 (pin 8) of storage chip J7 is electrically connected to pin PB15 of main control chip U13 and is also connected to a 3.3V voltage VCC3_3V3 through resistor R65; pin D2 (pin 1) of storage chip J7 is electrically connected to pin PG11 of main control chip U13 and is also connected to a 3.3V voltage VCC3_3V3 through resistor R64; pin D3 (pin 2) of storage chip J7 is electrically connected to pin PB4 of main control chip U13 and is also connected to a 3.3V voltage through resistor R63. The J7 memory chip's CLK pin (pin 5) is electrically connected to the U13 main control chip's PC1 pin; the J7 memory chip's CMD pin (pin 3) is electrically connected to the U13 main control chip's PD7 pin, and is also connected to a 3.3V voltage VCC3_3V3 through resistor R62; the J7 memory chip's CD pin (pin 9) is electrically connected to the U13 main control chip's PD8 pin, and is also connected to a second supply voltage VCC_3.3V through resistor R31; the J7 memory chip's VDD pin (pin 4) is connected to a 3.3V voltage VCC3_3V3; the J7 memory chip's VSS pin (pin 6), NC1 (pin 11), NC2 (pin 12), NC3 (pin 13), and G# pin (pin 10) are all grounded;

[0067] like Figure 8As shown, the communication circuit 313 includes a USB-to-serial chip U6 (model CH343) and a Type-C interface U5; the VIO pin (pin 1) and VDDS pin of the USB-to-serial chip U6 are both connected to the second power supply voltage VCC_3.3V and are also grounded through capacitor C35; the GND pin (pin 2) and EP pin (pin 17) of the USB-to-serial chip U6 are grounded; the TXD pin (pin 4) of the USB-to-serial chip U6 is electrically connected to the PD6 pin of the main control chip U13 through resistor R18, and the RXD pin (pin 5) is electrically connected to the PD5 pin of the main control chip U13 through resistor R19; the V3 pin (pin 5) of the USB-to-serial chip U6 is also grounded. 6) The second power supply voltage VCC_3.3V is connected and grounded through capacitor C33; the UD+ pin (pin 7) of the USB to serial port chip U6 is electrically connected to the DP1 and DP2 pins of the Type-C interface U5 through resistor R58, and the UD- pin (pin 8) is electrically connected to the DN1 and DN2 pins of the Type-C interface U5 through resistor R59; the VBUS pin (pin 9) of the USB to serial port chip U6 is electrically connected to the first protection circuit; the DP1 and DP2 pins of the Type-C interface U5 are grounded through electrostatic protection diode D4, the DN1 and DN2 pins are grounded through electrostatic protection diode D3, and the GND pin is grounded.

[0068] like Figure 16 As shown, the operation indicator circuit 312 includes a resistor R16, a light-emitting diode D1, and a transistor Q2. The base of the transistor Q2 is electrically connected to the PD10 pin of the main control chip U13, the emitter is grounded, and the collector is electrically connected to the cathode of the light-emitting diode D1. The anode of the light-emitting diode D1 is connected to a 3.3V voltage VCC3_3V3 through the resistor R16.

[0069] While specific embodiments of this utility model have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this utility model is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this utility model, but all such changes and modifications fall within the scope of protection of this utility model.

Claims

1. A wearable electroencephalogram (EEG) monitoring device, characterized in that, It includes an EEG cap and earphones for the collector to wear, and an EEG acquisition device. The EEG cap is equipped with multiple EEG electrodes, and the EEG acquisition device is installed on the EEG cap. The EEG acquisition device includes a housing, which integrates a power supply interface, a power circuit, an audio source interface, an audio generation circuit, an audio drive circuit, an earphone interface, a signal acquisition interface, a signal acquisition circuit, a control circuit, a storage circuit, an operation indicator circuit, and a communication circuit. The power supply circuit is electrically connected to the power supply interface, control circuit, audio generation circuit, audio drive circuit, signal acquisition circuit, storage circuit, operation indicator circuit, and communication circuit to supply power to the circuit. The sound source interface, audio generation circuit, and control circuit are electrically connected in sequence to generate audio signals for the audio generation circuit. The audio generation circuit and audio drive circuit are electrically connected to generate audio drive signals for the audio drive circuit. The headphone interface, audio drive circuit, and control circuit are electrically connected in sequence to emit sound stimulation through the headphone interface for the audio drive circuit. The audio drive circuit and signal acquisition circuit are electrically connected to generate synchronization signals for the signal acquisition circuit. The EEG electrodes, signal acquisition interface, signal acquisition circuit, and control circuit are electrically connected in sequence to acquire multi-channel EEG signals sensed by multiple EEG electrodes through the signal acquisition interface for the signal acquisition circuit. The storage circuit, operation indicator circuit, and communication circuit are all electrically connected to the control circuit.

2. The wearable EEG monitoring device as described in claim 1, characterized in that, The power supply circuit includes a main power switch circuit, a first DC-DC circuit, a first protection circuit, a first voltage regulator circuit, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a filter circuit, a second DC-DC circuit, a second voltage regulator circuit, and a third voltage regulator circuit. The input terminal of the main power switch circuit is electrically connected to the power supply interface, and the output terminal of the main power switch circuit is electrically connected to the control circuit through the first DC-DC circuit. The main power switch circuit is used to turn on the control circuit and adjust the output of the first power supply voltage based on the input voltage. The first DC-DC circuit is used to convert the first power supply voltage into a second power supply voltage and provide the second power supply voltage to the control circuit. The output terminal of the main power switch circuit is electrically connected to the communication circuit through the first protection circuit to provide VBUS voltage to the communication circuit, and the output terminal of the first DC-DC circuit is electrically connected to the communication circuit to provide a second power supply voltage to the communication circuit. The output terminal of the power main switch circuit is electrically connected to the audio driver circuit through the first voltage regulator circuit. The first voltage regulator circuit is used to regulate the first power supply voltage to a regulated power supply voltage and provide a regulated power supply voltage to the audio driver circuit. The output terminal of the first DC-DC circuit is electrically connected to the audio driver circuit through the first switch circuit to provide a second power supply voltage to the audio driver circuit. The output terminal of the first DC-DC circuit is electrically connected to the audio generation circuit through the second switching circuit to provide a second power supply voltage to the audio generation circuit. The output of the first DC-DC circuit is electrically connected to the storage circuit through a third switching circuit to provide a second power supply voltage to the storage circuit. The output terminal of the first DC-DC circuit is electrically connected to the input terminal of the fourth switching circuit. The output terminal of the fourth switching circuit is electrically connected to the signal acquisition circuit through a filter circuit to provide a filtered voltage for the signal acquisition circuit. The output terminal of the fourth switching circuit is also electrically connected to the signal acquisition circuit through a second DC-DC circuit and a second voltage regulator circuit, and also through a third voltage regulator circuit to provide a bipolar power supply voltage for the signal acquisition circuit.

3. The wearable EEG monitoring device as described in claim 2, characterized in that, The main power switch circuit includes: a main switch K3 and a power switch chip U4. The switching terminal of the main switch K3 is embedded in the housing. The IN pin of the power switch chip U4 is electrically connected to the power supply interface, and also electrically connected to pin 2 of the main switch K3, and is also grounded through capacitor C30. The EN pin of the power switch chip U4 is electrically connected to pin 3 of the main switch K3 through resistor R14, and is also grounded through resistor R77, and is also grounded through capacitor C32. The GND pin and EP pin of the power switch chip U4 are both grounded. The FAULT pin is electrically connected to the power supply interface through the power status indicator D2 and resistor R17. The ILIM pin is grounded through resistor R15. The OUT pin of the power switch chip U4 is used to output the first power supply voltage VCC_5V, and is also grounded through capacitor C31. The first DC-DC circuit includes: a power management chip U1, whose two PVIN pins, AVIN pin, and EN pin are all electrically connected to the OUT pin of the power switch chip U4, and are also grounded through series resistors R9 and R12, capacitors C105, C24, and C23. The FSW pin of the power management chip U1 is grounded through resistor R12, the DEF pin is grounded through resistor R11, and the SS / TR pin is grounded through capacitor C29. The PGND, AGND, and EP pins are all grounded. The FB pin of the power management chip U1 is grounded through resistor R13, and the VOS pin is grounded through a series of resistors R10 and R13. The three SW pins of the power management chip U1 output the second supply voltage VCC_3.3V through inductors L1 and L8 in series. Inductors L1 and L8 are grounded through capacitors C25, C26, C27, and C28, respectively. The end of inductor L8 furthest from inductor L1 is grounded through capacitors C108 and C107, respectively.

4. The wearable EEG monitoring device as described in claim 3, characterized in that, The first protection circuit includes: a resistor R20 and a diode D5. One end of the resistor R20 is electrically connected to the OUT pin of the power switch chip U4, and the other end is electrically connected to the cathode of the diode D5. The anode of the diode D5 is grounded, and the cathode is electrically connected to the communication circuit to provide VBUS voltage. The first voltage regulator circuit includes: a linear regulator U8, whose VIN pin is electrically connected to the OUT pin of the power switch chip U4, and is also grounded through capacitor C45 and capacitor C46; the EN pin of the linear regulator U8 is electrically connected to the control circuit, the GND pin is grounded, and the BP pin is grounded through capacitor C49; the VOUT pin of the linear regulator U8 is electrically connected to the audio driver circuit, and is also grounded through capacitor C47 and capacitor C48, for providing a 3.3V regulated power supply voltage VCC1_3V3A to the audio driver circuit; The first switching circuit includes: transistor Q3 and field-effect transistor M2. The base of transistor Q3 is electrically connected to the control circuit, and the emitter of transistor Q3 is grounded. The source of field-effect transistor M2 is electrically connected to the inductor L8 of power management chip U1 through resistor R21 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C38 and electrically connected to the collector of transistor Q3 through resistor R22. The gate of field-effect transistor M2 is electrically connected to the collector of transistor Q3. The drain of field-effect transistor M2 is electrically connected to the audio driver circuit and is also grounded through capacitor C39 and capacitor C40, in order to provide a 3.3V voltage VCC1_3V3 to the audio driver circuit. The second switching circuit includes: transistor Q1 and field-effect transistor M1. The base of transistor Q1 is electrically connected to the control circuit, and the emitter of transistor Q1 is grounded. The source of field-effect transistor M1 is electrically connected to the inductor L8 of power management chip U1 through resistor R6 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C18 and electrically connected to the collector of transistor Q1 through resistor R7. The gate of field-effect transistor M1 is electrically connected to the collector of transistor Q1. The drain of field-effect transistor M1 is electrically connected to the audio generation chip generation circuit and is also grounded through capacitor C19 and capacitor C20, in order to provide a 3.3V voltage VCC2_3V3 to the audio generation circuit. The third switching circuit includes: transistor Q4 and field-effect transistor M3. The base of transistor Q4 is electrically connected to the control circuit, and the emitter of transistor Q4 is grounded. The source of field-effect transistor M3 is electrically connected to the inductor L8 of power management chip U1 through resistor R29 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C50 and electrically connected to the collector of transistor Q4 through resistor R30. The gate of field-effect transistor M3 is electrically connected to the collector of transistor Q4. The drain of field-effect transistor M3 is electrically connected to the storage circuit and is also grounded through capacitor C95 and capacitor C51, in order to provide a 3.3V voltage VCC3_3V3 to the storage circuit. The fourth switching circuit includes: transistor Q5 and field-effect transistor M4. The base of transistor Q5 is electrically connected to the control circuit, and the emitter of transistor Q5 is grounded. The source of field-effect transistor M4 is electrically connected to the inductor L8 of power management chip U1 through resistor R52 to access the second supply voltage VCC_3.3V. The source is also grounded through capacitor C71 and electrically connected to the collector of transistor Q5 through resistor R53. The gate of field-effect transistor M4 is electrically connected to the collector of transistor Q5. The drain of field-effect transistor M4 is electrically connected to the filter circuit, the second DC-DC circuit, and the third voltage regulator circuit, respectively, and is also grounded through capacitor C72 to provide a 3.3V voltage VCC4_3V3. The filtering circuit includes an inductor L2, a capacitor C73, a capacitor C74, and a capacitor C75. One end of the inductor L2 is electrically connected to the drain of the field-effect transistor M4 and is also grounded through capacitor C73 and capacitor C74. The other end of the inductor L2 is electrically connected to the signal acquisition circuit and is also grounded through capacitor C75. It is used to provide the filtered voltage DVDD_33 to the signal acquisition circuit. The second DC-DC circuit includes: a switching regulator chip U11, the IN pin of the switching regulator chip U11 is electrically connected to the drain of the field-effect transistor M4 through inductor L5, and is also grounded through inductor L5 and capacitor C84 connected in series, and is also grounded through capacitor C85 and capacitor C86; the GND pin of the switching regulator chip U11 is grounded; capacitor C83 is connected between the CFLY- pin and the CFLY+ pin; the OUT pin of the switching regulator chip U11 is electrically connected to the second voltage regulator circuit through inductor L6, and is also grounded through capacitors C87 and C88 respectively; The second voltage regulator circuit includes: a negative linear regulator chip U12. The IN1, IN2, EP, PGFB, and EN / UV pins of the negative linear regulator chip U12 are all electrically connected to inductor L6 and are also grounded through capacitors C89 and C90, respectively. The ILIM pin of the negative linear regulator chip U12 is grounded through resistor R57, the GND pin is grounded, and the SET pin is grounded through parallel resistor R56 and capacitor C94, respectively. The OUTS, OUT1, and OUT2 pins of the negative linear regulator chip U12 are all electrically connected to the signal acquisition circuit through inductor L7 and are also grounded through inductor L7 and capacitor C93, capacitor C91, and capacitor C92, respectively, to provide the -2.5V voltage AVSS in the bipolar power supply voltage to the signal acquisition circuit. The third voltage regulator circuit includes: a linear voltage regulator chip U10. The IN, IN1, PGFB, and EN / UV pins of the linear voltage regulator chip U10 are all electrically connected to the drain of the field-effect transistor M4 through inductor L3, and are also grounded through inductor L3 and capacitor C76, and through capacitors C77 and C78 respectively. The ILIM pin of the linear voltage regulator chip U10 is grounded through resistor R54, the two GND pins are grounded, and the SET pin is grounded through parallel resistor R55 and capacitor C82 respectively. The OUTS and OUT pins of the linear voltage regulator chip U10 are both electrically connected to the signal acquisition circuit through inductor L4, and are also grounded through inductor L4 and capacitor C81, and through capacitor C79 and C80 respectively, and are used to provide the +2.5V voltage AVDD in the bipolar power supply voltage to the signal acquisition circuit.

5. The wearable EEG monitoring device as described in claim 4, characterized in that, The control circuit includes a main control chip U13, which is an STM32H743IIK6. The PA0, PA1, PA2, PA3, PE11, PE12, PE13, PE14, PC10 and PC11 pins of the main control chip U13 are all electrically connected to the audio generation circuit. The PE4, PE5, PE3, PE6, PE2, PB8, PB9 and PE1 pins of the main control chip U13 are all electrically connected to the audio driver circuit. The PB3, PA15, PB5, PG9, PG13, PC13, PI8, PI7, PC9 and PI9 pins of the main control chip U13 are all electrically connected to the signal acquisition circuit. The PB14, PB15, PG11, PB4, PC1, PD7, PA7 and PD8 pins of the main control chip U13 are all electrically connected to the storage circuit. The PB11, PB12, PD6 and PD5 pins of the main control chip U13 are all electrically connected to the communication circuit. The PA9, PA10, PA13 and PA14 pins of the main control chip U13 are all electrically connected to the debug printer interface. The VDDA, VBAT, VREF+, and VDD1-VDD14 pins of the main control chip U13 are all connected to the second power supply voltage VCC_3.3V. The VSSA, VREF-, and VSS1-VSS37 pins of the main control chip U13 are all grounded. The BOOT0 pin of the main control chip U13 is grounded through resistor R67, the VCAP1 pin is grounded through capacitor C14, the VCAP2 pin is grounded through capacitor C17, and the PDR_ON pin is grounded through resistor R68. The NRST pin of the main control chip U13 is electrically connected to pin 2 of the tactile switch K1, is also connected to the second power supply voltage VCC_3.3V through resistor R2, and is also grounded through capacitor C16. Pins 1 and 4 of the tactile switch K1 are both grounded. A crystal oscillator circuit is connected between the PH0 and PH1 pins of the main control chip U13.

6. The wearable EEG monitoring device as described in claim 5, characterized in that, The audio generation circuit includes: an audio generation chip U2, whose 3V3 pin is electrically connected to the drain of the field-effect transistor M1 to receive a 3.3V voltage VCC2_3V3; the EN pin of the audio generation chip U2 is electrically connected to the drain of the field-effect transistor M1 through a resistor R74, and also to pin 2 of the tactile switch K4, and grounded through a capacitor C106; pins 1 and 4 of the tactile switch K4 are grounded; the IO6 pin of the audio generation chip U2 is electrically connected to the PE12 pin of the main control chip U13, and the IO7 pin is electrically connected to the PE14 pin of the main control chip U13; the IO8 pin of the audio generation chip U2 is electrically connected to the PA0 pin of the main control chip U13, and also to the drain of the field-effect transistor M1 through a resistor R75; the IO... Pin 9 is electrically connected to pin PA1 of the main control chip U13 and pin 3 of the audio source interface J2. Pin IO10 of the audio generation chip U2 is electrically connected to pin PE11 of the main control chip U13. Pins RXD0 and TXD0 of the audio generation chip U2 are electrically connected to pins 1 and 2 of the audio source interface J2, respectively. The audio source interface J2 is a USB communication interface or a serial communication interface, and pin 4 is grounded. Pin IO3 of the audio generation chip U2 is electrically connected to pin PA2 of the main control chip U13. Pin IO2 is electrically connected to pin PE13 of the main control chip U13. Pin IO1 is electrically connected to pin PC11 of the main control chip U13. Pin IO0 is electrically connected to pin PC10 of the main control chip U13. All GND pins of the audio generation chip U2 are grounded.

7. The wearable EEG monitoring device as described in claim 6, characterized in that, The audio driver circuit includes: an audio driver chip U7, whose LRC pin is electrically connected to the PE4 pin of the main control chip U13, its BCLK pin is electrically connected to the PE5 pin of the main control chip U13, its ADCDAT pin is electrically connected to the PE3 pin of the main control chip U13, its DCDAT pin is electrically connected to the PE6 pin of the main control chip U13, its MCLK pin is electrically connected to the PE2 pin of the main control chip U13, its SCLK pin is electrically connected to the PB8 pin of the main control chip U13, and is also connected via resistor R2.

3. Connect to a 3.3V voltage VCC1_3V3. The SDIN pin of the audio driver chip U7 is electrically connected to the PB9 pin of the main control chip U13. It is also connected to a 3.3V voltage VCC1_3V3 through resistor R24. The MODE pin of the audio driver chip U7 is grounded through resistor R27. The EP pin, DGND pin, SPKGND pin and AGND pin of the audio driver chip U7 are all grounded. A resistor R28 is connected between the DGND pin and the SPKGND pin. The VMID pin of the audio driver chip U7 is grounded through capacitor C103. The ROUT1 pin of the audio driver chip U7 is electrically connected to the headphone jack J6 through capacitor C43, the LOUT1 pin is electrically connected to the headphone jack J6 through capacitor C44, and the LOUT1 pin is also electrically connected to the signal acquisition circuit through capacitor C44 and resistor R25 to emit a synchronization signal. The SPKVDD and AVDD pins of the audio driver chip U7 are both electrically connected to the VOUT pin of the linear regulator U8. The SPKVDD pin of the audio driver chip U7 is grounded through parallel capacitors C36 and C41, and the AVDD pin is grounded through parallel capacitors C37 and C42, respectively, to provide a 3.3V regulated power supply voltage VCC1_3V3A for the audio driver chip U7. The DBVDD and DCVDD pins of the audio driver chip U7 are both electrically connected to the drain of the field-effect transistor M2 to provide a 3.3V voltage VCC1_3V3 to the audio driver chip U7.

8. The wearable EEG monitoring device as described in claim 5, characterized in that, The EEG cap has eight EEG electrodes arranged from front to back. The shell integrates an EEG acquisition and protection circuit. All eight EEG electrodes are electrically connected to the signal acquisition circuit through a signal acquisition interface and the EEG acquisition and protection circuit.

9. The wearable EEG monitoring device as described in claim 8, characterized in that, The EEG acquisition protection circuit includes ESD protection circuit D6, ESD protection circuit D7 and ESD protection circuit D8. Pin 2 of ESD protection circuit D6 is connected to a -2.5V voltage AVSS and is also grounded through capacitor C99. Pin 3 of ESD protection circuit D6 receives the reference signal EEG_SRB1 through signal acquisition interface J8 and is also electrically connected to the signal acquisition circuit through resistor R40 to output the reference signal SRB1. Pin 4 of ESD protection circuit D6 receives the EEG signal EEG_IN2_P induced by the second EEG electrode through signal acquisition interface J8 and is also electrically connected to the signal acquisition circuit through resistor R33 to output the EEG signal IN2_P. Pin 5 of ESD protection circuit D6 is connected to a +2.5V voltage AVDD and is also grounded through capacitor C96. Pin 6 of ESD protection circuit D6 receives the EEG signal EEG_IN1_P induced by the first EEG electrode through signal acquisition interface J8 and is also electrically connected to the signal acquisition circuit through resistor R32 to output the EEG signal IN1_P. Pin 1 of the ESD protection circuit D7 receives the EEG signal EEG_IN3_P sensed by the third EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R34 to output the EEG signal IN3_P. Pin 2 of the ESD protection circuit D7 is connected to a -2.5V voltage AVSS and is also grounded through capacitor C100. Pin 3 of the ESD protection circuit D7 receives the EEG signal EEG_IN4_P sensed by the fourth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R35 to output the EEG signal IN4_P. Pin 4 of ESD protection circuit D7 receives the EEG signal EEG_IN5_P sensed by the fifth EEG electrode through signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R36 to output the EEG signal IN5_P. Pin 5 of ESD protection circuit D7 is connected to +2.5V voltage AVDD and is also grounded through capacitor C97. Pin 6 of ESD protection circuit D7 receives the EEG signal EEG_IN6_P sensed by the sixth EEG electrode through signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R37 to output the EEG signal IN6_P. Pin 1 of the ESD protection circuit D8 receives the EEG signal EEG_IN7_P induced by the seventh EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R38 to output the EEG signal IN7_P. Pin 2 of the ESD protection circuit D8 is connected to a -2.5V voltage AVSS and is also grounded through capacitor C101. Pin 3 of the ESD protection circuit D8 receives the EEG signal EEG_IN8_P induced by the eighth EEG electrode through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R39 to output the EEG signal IN8_P. Pin 4 of the ESD protection circuit D8 receives the bias signal EEG_BIAS through the signal acquisition interface J8, and is also electrically connected to the signal acquisition circuit through resistor R41 to output the bias signal BIAS. Pin 5 of the ESD protection circuit D8 is connected to a +2.5V voltage AVDD and is also grounded through capacitor C98.

10. The wearable EEG monitoring device as described in claim 9, characterized in that, The signal acquisition circuit includes a signal acquisition chip U9. The SRB1 pin of the signal acquisition chip U9 is connected to the reference signal SRB1; the IN1P pin is connected to the EEG signal IN1_P; the IN2P pin is connected to the EEG signal IN2_P; the IN3P pin is connected to the EEG signal IN3_P; the IN4P pin is connected to the EEG signal IN4_P; the IN5P pin is connected to the EEG signal IN5_P; the IN6P pin is connected to the EEG signal IN6_P; the IN7P pin is connected to the EEG signal IN7_P; and the IN8P pin is connected to the EEG signal IN8_P. A capacitor C55 and a resistor R49 are connected in parallel between the BIASINV pin and the BIASOUT pin of the signal acquisition chip U9, and then the bias signal is connected through a resistor R50. The signal acquisition chip U9 has the following pins connected to the BIAS: VCAP1 pin is connected to a -2.5V voltage AVSS via capacitor C67; VCAP2 pin is connected to a -2.5V voltage AVSS via capacitor C59; VCAP3 pin is connected to a -2.5V voltage AVSS via parallel capacitors C60 and C61; and VCAP4 pin is connected to a -2.5V voltage AVSS via capacitor C62. The signal acquisition chip U9 has the RESV1 pin and three DGND pins grounded. The signal acquisition chip U9 has the VREFP pin connected to the reference voltage VREFP and the VREFN pin connected to a -2.5V voltage AVSS. Capacitors C56 and C57 are connected in parallel between the VREFP and VREFN pins. The CLK pin of the signal acquisition chip U9 is electrically connected to the PC9 pin of the main control chip U13. The pin is electrically connected to the PI7 pin of the main control chip U13. The START pin is electrically connected to the PI8 pin of the main control chip U13, and the START pin is electrically connected to the PC13 pin of the main control chip U13. The pin is electrically connected to the PG13 pin of the main control chip U13, and the DOUT pin is connected to the PG13 pin of the main control chip U13. The PG9 pin is electrically connected, the DIN pin is electrically connected to the PB5 pin of the main control chip U13, the CS pin is electrically connected to the PA15 pin of the main control chip U13, and the SCLK pin is electrically connected to the PB3 pin of the main control chip U13. The two DVDD pins of the signal acquisition chip U9 are connected to the filtered voltage DVDD_33, and are also grounded through capacitors C52 and C53 respectively. All AVSS pins and AVSS1 pins of the signal acquisition chip U9 are connected to the -2.5V voltage AVSS, and all AVDD pins and AVSS1 pins are connected to the +2.5V voltage AVDD.

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