High-side split charging scheme based on PMOS (P-channel Metal Oxide Semiconductor)

Abstract

The utility model discloses a PMOS (P-channel Metal Oxide Semiconductor)-based high-side split charging scheme, which belongs to the technical field of BMS (Battery Management System), and comprises a high-side split charging module and a high-side PMOS module. According to the utility model, the high-side split charging module is used to control the on-off of the charging current, and the high-side PMOS module is a path through which the large charging current passes, thereby avoiding the loss of the charging voltage. And safe implementation of large-current charging in a high-side split charging scene is realized.

Description

Technical Field

[0001] This utility model relates to the field of battery management systems, and specifically provides a high-side split-port charging scheme based on PMOS. Background Technology

[0002] With the development of the new energy industry and the widespread application of battery packs, the application scenarios of high-side charging in BMS (Battery Management System) are gradually increasing. Among high-side charging systems, split-port systems are increasingly favored by manufacturers because they can use fewer charging MOSFETs compared to mono-port systems. However, how to ensure that the charging current of the high-side split-port charging terminal C+ can be maximized and the voltage loss to the charger voltage can be reduced when it is not charged has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a safe high-side split-port charging scheme that allows for a large charging current and has low voltage loss in the charger.

[0004] The technical solution of this utility model is: a high-side split-port charging scheme based on PMOS, comprising a high-side split-port charging module and a high-side PMOS module; the high-side split-port charging module controls whether charging is performed, and the high-side PMOS module implements intelligent control to ensure that when there is charging current, the PMOS is in the open state, with its internal resistance at the milliΩ level, so as not to affect the flow of charging current, avoid heat generation caused by large current, and avoid damage to the charger voltage. When there is no charging current, the PMOS is in the closed state, so C+ is not charged, improving the overall system safety level.

[0005] A further technical solution includes a high-side charging module comprising the battery pack's positive B+ terminal, an enhancement-mode NMOS transistor Q1, resistors R2 and R1, a Zener diode Z1, and a high-side charging control signal CHG. The battery pack's positive B+ terminal is connected to the gate of Q1 and the positive terminals of R1 and Z1. The source of the enhancement-mode NMOS transistor Q1 is connected to the battery pack's positive B+ terminal, its gate is connected to R2, and its drain is connected to the source of Q2 and the negative terminals of R3 and Z2. R2 is connected to the gate of Q1 and the negative terminals of R1 and Z1. R1 is connected to the negative terminals of R2 and Z1, as well as the battery pack's positive B+ terminal and the positive terminal of Z1. The positive terminal of the Zener diode Z1 is connected to R1 and the battery pack's positive B+ terminal, and its negative terminal is connected to R1, R2, and the high-side charging control signal CHG. The high-side charging control signal CHG is connected to the negative terminals of R2, R1, and Z1.

[0006] A further technical solution includes an enhancement-mode PMOS module comprising an enhancement-mode PMOS transistor Q2, a high-side charging terminal C+, resistor R3, a Zener diode Z2, resistor R4, and a high-side PMOS control signal P-CHG. The drain of the enhancement-mode PMOS transistor Q2 is connected to the high-side charging terminal C+, its gate is connected to R3, the positive terminal of Z2, and R4, and its source is connected to the negative terminals of R3 and Z2 and the drain of Q1. The high-side charging terminal C+ is connected to the drain of Q2. R3 is connected to the drain of Q1, the negative terminal of Z2, the source of Q2, the positive terminal of Z2, R4, and the gate of Q2. The negative terminal of the Zener diode Z2 is connected to the drain of R3 and Q1 and the source of Q2, and its positive terminal is connected to R3, R4, and the gate of Q2. R4 is connected to the positive terminal of R3 and Z2, the gate of Q2, and the high-side PMOS control signal P-CHG, which is connected to R4.

[0007] The beneficial effects of this invention are as follows: In the high-side split-port charging module, flexible and intelligent control is achieved using a high-side PMOS module. When there is no charging current, the PMOS is turned off, and C+ is not charged, meeting the system's hard safety requirements. When charging is required, the PMOS is turned on, reducing charging losses. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the implementation of a battery adaptive circuit in this utility model. Detailed Implementation

[0009] This utility model is a high-side split-port charging scheme based on PMOS, such as... Figure 1 It includes a high-side split-port charging module and a high-side PMOS module. The high-side split-port charging module controls the NMOS to turn on or off through the CHG signal, thereby managing the charging current. The reverse cutoff characteristic of the diode in the high-side split-port charging module ensures that the C+ port of the high-side split-port charging is not energized, while the forward conduction characteristic of the diode is used to enable freewheeling of the charging current, thus ensuring the safety of the high-side split-port charging scheme.

[0010] like Figure 1 The high-side charging module shown includes: a battery pack positive B+, an enhancement-mode NMOS transistor Q1, resistors R2, R1, and R3, a Zener diode Z1, and a high-side charging control signal CHG. The battery pack positive B+ is connected to the gate of Q1 and the positive terminals of R1 and Z1. The source of the enhancement-mode NMOS transistor Q1 is connected to the battery pack positive B+, its gate is connected to R2, and its drain is connected to the negative terminal of D1. R2 is connected to the gate of Q1, as well as the negative terminals of R1, R3, and Z1. R1 is connected to the negative terminals of R2, R3, and Z1, as well as the battery pack positive B+ and Z1. R3 is connected to the high-side charging control signal CHG, as well as the negative terminals of R2, R1, and Z1. The positive terminal of the Zener diode Z1 is connected to R1 and the battery pack positive B+, and its negative terminal is connected to R1, R2, and R3. The high-side charging control signal CHG is connected to R3.

[0011] The high-side charging control signal CHG is connected to the gate of the enhancement-mode NMOS transistor Q1 through a current-limiting resistor R3 and a matching resistor R2. When the voltage of the high-side charging control signal CHG rises to the sum of the total positive B+ voltage of the battery pack and the turn-on voltage of the enhancement-mode NMOS transistor Q1, the enhancement-mode NMOS transistor Q1 turns on, and charging current flows into the battery pack. When the voltage of the high-side charging control signal CHG drops to the sum of the total positive B+ voltage of the battery pack and the turn-on voltage of the enhancement-mode NMOS transistor Q1, the enhancement-mode NMOS transistor Q1 turns on, and the charging current is cut off. This successfully controls the charging current. The current-limiting resistor R3 ensures that the high-side charging control signal CHG does not output excessive current that could cause damage, while the matching resistor R2 ensures that the gate-source voltage waveform of the enhancement-mode NMOS transistor Q1 remains intact and does not produce spikes or distortions. The pull-down resistor R1 ensures that when the high-side charging control signal CHG has no output, the gate voltage of the enhancement-mode NMOS transistor Q1 is pulled down to the source voltage of the enhancement-mode NMOS transistor Q1, ensuring that the enhancement-mode NMOS transistor Q1 does not turn on unexpectedly. The voltage regulator Z1 utilizes its reverse operating characteristic to control the gate-source voltage of the enhancement-mode NMOS transistor Q1, absorbing potential unexpected surges and protecting Q1. This circuit achieves control over the high-side charging current while ensuring safety and reliability, meeting current mainstream safety requirements.

[0012] The high-side PMOS module includes diode D1 and a high-side charging terminal C+. The anode of diode D1 is connected to the high-side charging terminal C+, and the cathode is connected to the drain of enhancement-mode NMOS transistor Q1. The high-side charging terminal C+ is also connected to the anode of diode D1. Connecting the cathode of diode D1 to the drain of NMOS transistor Q1 establishes the link between the two modules. Combined with the forward conduction characteristic of the diode, this allows for freewheeling of the charging current required by the system, ensuring unimpeded charging and achieving the charging purpose. Simultaneously, the reverse cutoff characteristic of the diode prevents the high-side charging terminal C+ from being pulled up to the battery pack voltage by the battery pack's total positive B+ through the body diode of Q1. Therefore, the battery pack's total positive B+ remains uncharged, meeting current mainstream safety requirements.

[0013] It will be apparent to those skilled in the art that this invention is not limited to the details of the above-described exemplary embodiments, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0014] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This description is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other ways that can be understood by those skilled in the art.

Claims

1. A high-side split-port charging scheme based on PMOS, characterized in that, This system includes a high-side split-port charging module and a high-side PMOS module. The high-side split-port charging module controls the charging state, while the high-side PMOS module improves the overall system safety level and can handle high current. In high-side split-port charging scenarios, the charging terminal C+ is not charged when not charging. The high-side split-port charging module includes: a battery pack positive B+, an enhancement-mode NMOS transistor Q1, resistors R2 and R1, a Zener diode Z1, and a high-side charging control signal CHG. The battery pack positive B+ is connected to the gate of Q1 and the positive terminals of R1 and Z1. The source of the enhancement-mode NMOS transistor Q1 is connected to the battery pack positive B+, its gate is connected to R2, and its drain is connected to the source of Q2 and the negative terminals of R3 and Z2. R2 is connected to the gate of Q1 and the negative terminals of R1 and Z1. R1 is connected to the negative terminals of R2 and Z1, as well as the battery pack positive B+ and Z1. The positive terminal of the Zener diode Z1 is connected to R1 and the battery pack positive B+, and its negative terminal is connected to R1 and R2. The high-side PMOS module consists of an enhancement-mode PMOS transistor Q2, a high-side charging terminal C+, R3, a Zener diode Z2, R4, and a high-side PMOS control signal P-CHG. The drain of the enhancement-mode PMOS transistor Q2 is connected to the high-side charging terminal C+, its gate is connected to the positive terminals of R3 and Z2 and R4, its source is connected to the negative terminals of R3 and Z2 and the drain of Q1, the high-side charging terminal C+ is connected to the drain of Q2, R3 is connected to the drain of Q1, the negative terminal of Z2, the source of Q2, the positive terminal of Z2, R4, and the gate of Q2, the negative terminal of the Zener diode Z2 is connected to the drain of R3 and Q1 and the source of Q2, its positive terminal is connected to R3, R4, and the gate of Q2, R4 is connected to the positive terminal of R3 and Z2 and the gate of Q2, and the high-side PMOS control signal P-CHG is connected to R4.

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