Array substrate, liquid crystal display panel and display device
By designing a cuttable extension on the scan line, the problem of G-line extinction caused by particulate matter in the liquid crystal display panel is solved, improving repair efficiency and yield, and ensuring the integrity of the scan line.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SDP GLOBAL (CHINA) CO LTD
- Filing Date
- 2025-05-08
- Publication Date
- 2026-04-28
AI Technical Summary
In existing liquid crystal display panels, when particles fall onto thin-film transistors and penetrate the protective layer of the array substrate, they cause a short circuit between the scan line and the common electrode layer of the color filter substrate, forming a G-type quench line. As a result, the pixels on the entire scan line cannot be turned on normally, creating a defect.
An extension that can be physically cut off is designed on the scan line to isolate the problematic TFT without interrupting the conductivity of the main body. By cutting off the extension, the electrical connection between the gate and the main body is broken, which is converted into a single pixel defect.
It improves the repair yield and efficiency, avoids the transformation of defects along the entire scan line into defects in a single pixel, and enhances the operability and safety of the repair process.
Smart Images
Figure CN224176854U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to an array substrate, a liquid crystal display panel, and a display device. Background Technology
[0002] In current liquid crystal display panels, when a particle of a certain height falls onto a thin film transistor (TFT) and penetrates the protective layer of the array substrate, if the liquid crystal display panel is pressed, the particle will come into contact with the common electrode layer on one side of the color filter (CF) substrate and short-circuit. This causes the pixels on the entire gate line to turn off because the TFT cannot be turned on normally, forming a G-extinguishing line. Utility Model Content
[0003] Therefore, it is necessary to provide an array substrate and a display panel to solve the technical problem of G-line quenching in existing liquid crystal display panels.
[0004] This application provides an array substrate. The array substrate includes multiple scan lines, multiple data lines, multiple pixel electrodes, and multiple TFTs. Each scan line includes a body portion. Any two adjacent data lines intersect with the body portions of two adjacent scan lines to define a pixel region. Each pixel region contains one pixel electrode and one TFT. Each TFT includes a gate, a source, and a drain. The gate of each TFT is electrically connected to a corresponding scan line, the source of each TFT is electrically connected to a corresponding data line, and the drain of each TFT is electrically connected to a corresponding pixel electrode. Each scan line further includes at least one extension portion extending from the body portion and connecting to the gate of a corresponding TFT. The extension portion is configured to be physically cut off to disconnect the electrical connection between the gate and the body portion without interrupting the conductivity of the body portion.
[0005] In this array substrate, each scan line includes a physically cut-off extension. When a problem occurs with the gate of a TFT (such as particulate matter causing a short circuit between the TFT gate and the common electrode layer on one side of the CF substrate), the TFT can be isolated by cutting off this extension, while the main body of the scan line (responsible for driving other pixels in that row) remains intact. This transforms a problem that would otherwise lead to a defect in the entire scan line into a defect in a single pixel, improving repair yield and efficiency.
[0006] In some embodiments, the main body portion of each TFT and the scan line to which it is electrically connected does not overlap.
[0007] In some embodiments, each scan line includes a plurality of extensions, each extension being disposed within a corresponding pixel region, and each TFT overlapping with the extension to which it is connected.
[0008] In some embodiments, the main body extends along a first direction, and the data line and the extension both extend along a second direction, the first direction intersecting the second direction; each extension includes a connecting portion and a carrier portion, the connecting portion connecting between the main body and the carrier portion along the second direction; the TFT is disposed on the carrier portion, and the connecting portion is configured to be physically cut off to disconnect the electrical connection between the carrier portion and the main body without interrupting the conductivity of the main body, thereby disconnecting the electrical connection between the gate and the main body.
[0009] In some embodiments, along the first direction, the size of the support portion is larger than the size of the connecting portion, such that a gap is formed between the support portion and the main body portion, and the size of the gap along the second direction is not less than 3 micrometers.
[0010] In some embodiments, along the first direction, the connecting portion is connected to the central region of the carrier portion; along the first direction, the carrier portion includes a first protrusion and a second protrusion protruding relative to the connecting portion; the first protrusion is closer to the data line connected to the TFT than the second protrusion; the TFT is disposed on the first protrusion.
[0011] In some embodiments, the distance between the TFT and the connection portion along the first direction is not less than 5 micrometers.
[0012] In some embodiments, the main body and the extension are formed from the same conductive layer.
[0013] A second aspect of this application provides a liquid crystal display panel. The liquid crystal display panel includes an array substrate, a color filter substrate, and a liquid crystal layer, as provided in the first aspect of this application. The color filter substrate is disposed opposite to the array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate.
[0014] The liquid crystal display panel of the second aspect of this application has at least the same advantages as the array substrate of the first aspect of this application, which will not be repeated here.
[0015] A third aspect of this application provides a display device. The display device includes a liquid crystal display panel and a backlight module as provided in the second aspect of this application. The backlight module is disposed on one side of the liquid crystal display panel to provide backlighting for the liquid crystal display panel.
[0016] The display device of the third aspect of this application has at least the same advantages as the array substrate of the first aspect of this application, which will not be repeated here. Attached Figure Description
[0017] Figure 1 This is a partial structural diagram of the array substrate of the related technology.
[0018] Figure 2 For application Figure 1 A schematic diagram of the structure of the liquid crystal display panel on the array substrate before pressing.
[0019] Figure 3 For application Figure 1 A schematic diagram of the structure of the liquid crystal display panel on the array substrate after being pressed.
[0020] Figure 4 This is a schematic diagram of the structure of an array substrate according to an embodiment of this application.
[0021] Figure 5 for Figure 4 A schematic diagram of the equivalent circuit of the array substrate.
[0022] Figure 6 For when Figure 4 A schematic diagram illustrating the repair process when the array substrate is at risk of crushing lines.
[0023] Figure 7 This is a schematic diagram of the structure of a display device according to an embodiment of this application.
[0024] Explanation of main component symbols -
[0025] Display device - 100; Liquid crystal display panel - 110, 110'; Array substrate - 10, 10'; Scan lines - 11, 11'; Main body - 11a; Extension - 11b; Connecting part - 111; Supporting part - 112; First protrusion - 112a; Second protrusion - 112b; Data lines - 12, 12'; First metal layer - M1; Second metal layer - M2; Insulating protective layer - IL; Gap - G; Pixel area - P; TFT - 13, 13'; Gate - 13g; Source - 13s; Drain - 13d; Pixel electrode - 14; Color filter substrate - 20, 20'; Color filter layer - 21, 21'; Common electrode layer - 22'; Liquid crystal layer - 30'; First polarizer - 40; Second polarizer - 50; Backlight module - 120; First direction - X; Second direction - Y; Particles - Q.
[0026] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation
[0027] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.
[0028] In the description of the embodiments of this application, the terms "middle", "width", "thickness", "upper", "lower", "inner", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the implementation of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0029] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.
[0030] In the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.
[0031] In the description of the embodiments of this application, unless otherwise stated, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that allows communication between the two components; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two components or the interaction between two components.
[0032] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0033] Figure 1 This is a partial structural diagram of the array substrate of the related technology. Figure 1 Figure (a) shows a partial structural diagram of the array substrate. Figure 1 In Figure (a), the array substrate 10' includes a scan line 11', a data line 12' that intersects the scan line 11', and a TFT 13' that connects the scan line 11' and the data line 12'. Figure 1 Figure (b) shows a schematic diagram of particulate matter Q falling onto TFT 13' of array substrate 10'.
[0034] Figure 2 For application Figure 1A schematic diagram of the liquid crystal display panel 110' of the array substrate 10' before pressing. (See diagram below.) Figure 2 As shown, the liquid crystal display panel 110' includes an array substrate 10', a color filter substrate 20' disposed opposite to the array substrate 10', and a liquid crystal layer 30' sandwiched between the array substrate 10' and the color filter substrate 20'.
[0035] The array substrate 10' includes a first metal layer M1 for forming scan lines 11', a second metal layer M2 for forming data lines 12' and the source electrodes of TFTs 13', and an insulating protective layer IL covering the second metal layer M2. The first metal layer M1 and the second metal layer M2 are disposed at an insulating interval.
[0036] The color filter substrate 20' includes a color filter layer 21' and a common electrode layer 22' located on the side of the color filter layer 21' facing the array substrate 10'.
[0037] The particle Q falls onto TFT13', contacts the second metal layer M2 and passes through the insulating protective layer IL. Before the liquid crystal display panel 110' is pressed, the particle Q has a certain distance from the common electrode layer 22' and does not make contact.
[0038] Figure 3 For application Figure 1 A schematic diagram of the liquid crystal display panel 110' of the array substrate 10' after being pressed. Figure 3 As shown, when the liquid crystal display panel 110' is pressed, the particle Q comes into contact with the common electrode layer 22' and short-circuits, causing the pixels on the entire scan line connected to the TFT to fail to turn on normally and turn off, forming a G-shaped de-energized line. In addition, it also causes an S-shaped dark line, which disappears after the pressure is released.
[0039] To improve the problem of voltage drop lines caused by particulate matter falling on the TFT, the array substrate of the present application embodiment will be described in detail below with reference to the accompanying drawings.
[0040] Figure 4 This is a schematic diagram of the structure of an array substrate 10 according to an embodiment of this application. Figure 5 for Figure 4 A schematic diagram of the equivalent circuit of the array substrate 10. Please refer to the following: Figure 4 and Figure 5 The array substrate 10 includes multiple scan lines 11, multiple data lines 12, and multiple pixel electrodes 14 (illustrated in...). Figure 7 (in the middle) and multiple TFT13.
[0041] Each scan line 11 includes a main body portion 11a. Any two adjacent data lines 12 intersect with the main body portions 11a of the two adjacent scan lines 11 to define a pixel region P. Each pixel region P is provided with a pixel electrode 14 and a TFT 13.
[0042] Each TFT 13 includes a gate 13g, a source 13s, and a drain 13d. The gate 13g of each TFT 13 is electrically connected to a corresponding scan line 11, the source 13s of each TFT 13 is electrically connected to a corresponding data line 12, and the drain 13d of each TFT 13 is electrically connected to a corresponding pixel electrode 14.
[0043] TFT13 acts as a video signal switch. Scan lines 11 are sequentially activated one by one via different potentials. Data lines 12 supply a set voltage to the pixel electrodes 14 of the activated column, and the video signal is transmitted as follows: Figure 5 The dashed lines in the diagram indicate the capacitors provided to the corresponding pixels and the storage capacitors, thus completing the image display.
[0044] Each scan line 11 also includes at least one extension 11b. The extension 11b extends from the main body 11a and connects to the gate 13g of a corresponding TFT 13. The extension 11b is configured to be physically cut off to disconnect the electrical connection between the gate 13g and the main body 11a without interrupting the conductivity of the main body 11a.
[0045] Figure 6 For when Figure 4 This diagram illustrates the structure for repairing the array substrate 10 when there is a risk of a crush line. Please refer to the attached diagram. Figure 4 and Figure 6 It should be noted that Figure 6 Each black-filled strip in the diagram represents a laser cut.
[0046] When a particle Q of a certain height falls on TFT13 and poses a risk of voltage drop (or short circuit), the extension 11b can be cut off, the connection line between the drain 13d of TFT13 and the pixel electrode can be cut off, causing the connection capacitor to fail. The connection between the source 13s of TFT13 and the data line 12 can also be cut off, so that TFT13 no longer receives the original scan line 11 signal and becomes a passive signal metal, and the pixel can be repaired into a dark spot.
[0047] In the array substrate 10, each scan line 11 includes a physically cut-off extension 11b. When a problem occurs with the gate 13g of a TFT 13 (such as the presence of particulate matter Q causing a short circuit between the gate 13g of the TFT 13 and the common electrode layer on one side of the CF substrate), the TFT 13 can be isolated by cutting off this extension 11b, allowing the problematic structure to be isolated from the main circuit, while the main body 11a of the scan line 11 (responsible for driving other pixels in that row) remains intact. This transforms a problem that would otherwise lead to a defect in the entire scan line 11 into a defect in a single pixel, improving repair yield and repair efficiency.
[0048] In some embodiments, the physical cutting method includes, but is not limited to, laser cutting.
[0049] In some embodiments, each TFT 13 does not overlap with the main body 11a of the scan line 11 to which it is electrically connected. Therefore, by positioning each TFT 13 relative to the main body 11a of the scan line 11, physical separation between the TFT 13 and the main body 11a of the scan line 11 is ensured, providing clearer space for cutting the extension 11b, reducing the risk of accidentally damaging the main body 11a of the scan line 11 or the TFT 13 itself during cutting, and enhancing the operability and safety of the repair.
[0050] In some embodiments, each scan line 11 includes multiple extensions 11b. Each extension 11b is disposed within a corresponding pixel region P, and each TFT 13 overlaps with its connected extension 11b. Alternatively, multiple extensions 11b are spaced apart, with each extension 11b located between two adjacent data lines 12.
[0051] In some embodiments, the gate 13g of the TFT 13 is part of the extension 11b or is formed directly on the extension 11b.
[0052] In some embodiments, the main body 11a extends along a first direction X, and both the data line 12 and the extension 11b extend along a second direction Y. The first direction X intersects the second direction Y.
[0053] Each extension 11b includes a connecting portion 111 and a carrier portion 112. Along the second direction Y, the connecting portion 111 connects the main body portion 11a and the carrier portion 112. The TFT 13 is disposed on the carrier portion 112, and the connecting portion 111 is configured to be physically disconnected to break the electrical connection between the carrier portion 112 and the main body portion 11a without interrupting the conductivity of the main body portion 11a, thereby breaking the electrical connection between the gate 13g and the main body portion 11a.
[0054] Therefore, the extension 11b is divided into two parts: the connecting part 111 and the carrier part 112, which makes the cutting target clear, easy to position and operate, further improving the cutting accuracy and success rate, while protecting the carrier part 112 where the TFT13 is located.
[0055] In some embodiments, the carrier portion 112 of the extension portion 11b is also referred to as a line connected in parallel with the main body portion 11a of the scan line 11. The TFT 13 is not on the main body portion 11a of the scan line 11, but is disposed on one side of the main body portion 11a.
[0056] In some embodiments, the dimension of the carrier portion 112 along the first direction X is larger than the dimension of the connecting portion 111 along the first direction X, such that a gap G is formed between the carrier portion 112 and the main body portion 11a, and the dimension W1 of the gap G along the second direction Y is not less than 3 micrometers. Alternatively, the after-development inspection (ADI) dimension of the gap G along the second direction Y is not less than 3 micrometers.
[0057] Therefore, the specific dimensional relationship between the connecting portion 111 and the carrier portion 112, as well as the size of the gap G, provides a sufficient process window for physical cutting (especially laser cutting). The TFT 13 is set on the wider carrier portion 112, the narrower connecting portion 111 serves as the cutting point, and the gap G of 3 micrometers or more is beneficial to the exposure accuracy requirements in the preparation process.
[0058] In some embodiments, the connecting portion 111 is connected to the central region of the carrier portion 112 along the first direction X. The extension portion 11b is generally T-shaped. The carrier portion 112 includes a first protrusion 112a and a second protrusion 112b that protrude relative to the connecting portion 111 along the first direction X. The first protrusion 112a is closer to the data line 12 connected to the TFT 13 than the second protrusion 112b. The TFT 13 is disposed on the first protrusion 112a.
[0059] Therefore, by defining the shape of the extension 11b and the specific position of the TFT 13 thereon, it is beneficial to optimize the layout space utilization or electrical performance within the pixel. For example, placing the TFT 13 near the first protrusion 112a of the data line 12 helps with wiring or reduces parasitic capacitance.
[0060] In some embodiments, the distance W2 between TFT13 and connection portion 111 along the first direction X is not less than 5 micrometers, which helps to ensure sufficient space for laser cutting.
[0061] In some embodiments, the edge of TFT 13 furthest from the data line 12 it is connected to is aligned with the edge of connector 111 near TFT 13, and the distance W2 between TFT 13 and connector 111 along the first direction X is the size of connector 111 in the first direction X. That is, the size of connector 111 in the first direction X is not less than 5 micrometers.
[0062] In some embodiments, the main body 11a and the extension 11b are formed from the same conductive layer. This simplifies the fabrication process.
[0063] Understandably, the array substrate 10 may also include, but is not limited to, output modules, gate start signal lines, clock signal lines, and gate drivers (GOAs) integrated on the array substrate 10.
[0064] Figure 7 This is a schematic diagram of the structure of a display device 100 according to an embodiment of this application. Figure 7 As shown, the display device 100 includes a liquid crystal display panel 110 and a backlight module 120. The backlight module 120 is disposed on one side of the liquid crystal display panel 110 to provide backlight for the liquid crystal display panel 110.
[0065] The liquid crystal display panel 110 includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer (not shown) according to any of the above embodiments. The color filter substrate 20 is disposed opposite to the array substrate 10. The liquid crystal layer is disposed between the array substrate 10 and the color filter substrate 20. The color filter substrate 20 may include a light-transmitting substrate, a color filter layer 21, a black matrix, etc.
[0066] The liquid crystal display panel 110 also includes a first polarizing plate 40 and a second polarizing plate 50. The first polarizing plate 40 is located on the side of the array substrate 10 opposite to the color filter substrate 20. The second polarizing plate 50 is located on the side of the color filter substrate 20 opposite to the array substrate 10. The polarization directions of the first polarizing plate 40 and the second polarizing plate 50 are perpendicular.
[0067] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.
Claims
1. An array substrate, characterized in that, include- Multiple scan lines, each scan line including a main body portion; Multiple data lines, wherein any two adjacent data lines intersect with the main body portion of two adjacent scan lines to define a pixel region; Multiple pixel electrodes, with one pixel electrode disposed in each pixel region; as well as Multiple TFTs are provided, with one TFT disposed in each pixel region. Each TFT includes a gate, a source, and a drain. The gate of each TFT is electrically connected to a corresponding scan line, the source of each TFT is electrically connected to a corresponding data line, and the drain of each TFT is electrically connected to a corresponding pixel electrode. Each scan line further includes at least one extension, each extension extending from the main body and connecting to a corresponding gate of the TFT, and is configured to be physically cut off to disconnect the electrical connection between the gate and the main body without interrupting the conductivity of the main body.
2. The array substrate according to claim 1, characterized in that, The main body of each TFT and the scan line to which it is electrically connected do not overlap.
3. The array substrate according to claim 2, characterized in that, Each scan line includes a plurality of extensions, each extension being disposed within a corresponding pixel region, and each TFT overlapping with the extension to which it is connected.
4. The array substrate according to claim 3, characterized in that, The main body extends along a first direction, and the data line and the extension both extend along a second direction, with the first direction intersecting the second direction. Each of the extensions includes a connecting portion and a supporting portion, wherein the connecting portion connects the main body portion and the supporting portion along the second direction; The TFT is disposed on the carrier portion, and the connection portion is configured to be physically cut off to disconnect the electrical connection between the carrier portion and the main body portion without interrupting the conductivity of the main body portion, thereby disconnecting the electrical connection between the gate portion and the main body portion.
5. The array substrate according to claim 4, characterized in that, Along the first direction, the size of the supporting part is larger than the size of the connecting part, such that a gap is formed between the supporting part and the main body, and the size of the gap along the second direction is not less than 3 micrometers.
6. The array substrate according to claim 5, characterized in that, Along the first direction, the connecting portion is connected to the middle region of the bearing portion; Along the first direction, the bearing portion includes a first protrusion and a second protrusion that protrude relative to the connecting portion; The first protrusion is closer to the data line connected to the TFT than the second protrusion; The TFT is disposed on the first protrusion.
7. The array substrate according to claim 5 or 6, characterized in that, The distance between the TFT and the connection portion along the first direction is not less than 5 micrometers.
8. The array substrate according to any one of claims 1 to 6, characterized in that, The main body and the extension are formed by the same conductive layer.
9. A liquid crystal display panel, characterized in that, include- The array substrate according to any one of claims 1 to 8; A color filter substrate is disposed opposite to the array substrate; as well as A liquid crystal layer is disposed between the array substrate and the color filter substrate.
10. A display device, characterized in that, include- The liquid crystal display panel according to claim 9; and A backlight module is disposed on one side of the liquid crystal display panel to provide backlight for the liquid crystal display panel.