Zener chip and LED packaging structure with Zener chip
By setting through-holes and parallel pads on the bottom pads of the Zener chip, the problem of difficult wire bonding caused by the Zener chip occupying pad space was solved, and the wire bonding area was expanded and the reliability of electrostatic protection was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- DONGGUAN FURIYUANLEI TECH CO LTD
- Filing Date
- 2025-04-25
- Publication Date
- 2026-04-28
AI Technical Summary
In existing LED packaging structures with Zener chips, the vertical structure of the Zener chip occupies pad space, making wire bonding difficult and posing risks such as cold solder joints and false solder joints.
Vertical vias are set on the bottom pads of the Zener chip, and parallel pads cover the vias and connect them to the bottom pads. The vias are etched using thin-film blocking and photolithography techniques, and a conductive material layer is electroplated on the inner wall of the vias to increase the bonding area.
It improves the convenience of wire bonding operations, reduces the risk of wire bonding, ensures that Zener chips can still maintain electrostatic protection when conductive silver paste falls off, and enhances the reliability of the packaging structure.
Smart Images
Figure CN224178516U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of LED technology, and in particular to a Zener chip and an LED packaging structure with a Zener chip. Background Technology
[0002] Existing LED packaging structures connect Zener chips in parallel across both ends of the LED chip to prevent electrostatic discharge (ESD) damage during operation, thus protecting the LED from ESD and effectively extending its lifespan. However, because the Zener chip is vertically mounted, it needs to be die-bonded to the positive pad at the bottom of the mounting bracket using conductive silver paste, occupying space that would otherwise be used for wire bonding. Furthermore, due to the diffusion of the conductive silver paste, the Zener chip further encroaches on the original positive pad area for wire bonding, reducing the available bonding area. This leads to difficulties in wire bonding, cold solder joints, and other issues associated with LED packaging structures incorporating Zener chips.
[0003] Therefore, existing technologies still need to be improved and developed. Utility Model Content
[0004] In view of the shortcomings of the prior art, the purpose of this utility model is to provide a Zener chip and an LED packaging structure with a Zener chip, so as to solve the problems of small wire bonding area of the light-emitting chip, difficult wire bonding operation, and wire bonding risk in the existing LED packaging structure with Zener chip.
[0005] The technical solution of this utility model is as follows:
[0006] A Zener chip includes: a Zener structure, Zener pads, parallel pads, and a bottom pad; wherein,
[0007] A Zener structure is disposed on the bottom pad, the Zener structure having a vertical through-hole, the Zener structure being used to form a Zener diode;
[0008] The Zener pads and parallel pads are respectively fixedly disposed on the upper surface of the Zener structure. The parallel pads cover the through holes and are connected to the bottom pads through the through holes.
[0009] In a further embodiment of this invention, the Zener structure includes: a first N-type semiconductor layer, a P-type semiconductor layer, a protective layer, and Zener pads; wherein,
[0010] The first N-type semiconductor layer is disposed on the bottom pad. The top of the first N-type semiconductor layer is provided with a first upper surface and a second upper surface formed by a downward indentation. The via is located at the first upper surface of the first N-type semiconductor layer and is used to electrically connect the parallel pad and the bottom pad in the vertical direction.
[0011] The P-type semiconductor layer is embedded in the second upper surface on top of the first N-type semiconductor layer;
[0012] The protective layer is disposed on the first upper surface of the first N-type semiconductor layer and the upper surface of the P-type semiconductor layer. The protective layer has pad contact holes at the via locations and on the upper surface of the P-type semiconductor layer, respectively. The Zener pads are connected to the P-type semiconductor layer through the pad contact holes.
[0013] In a further embodiment of this invention, the Zener structure includes: a first N-type semiconductor layer, a P-type semiconductor layer, a second N-type semiconductor layer, and a protective layer; wherein,
[0014] The first N-type semiconductor layer is disposed on the bottom pad, and the top of the first N-type semiconductor layer is provided with a first upper surface and a second upper surface formed by downward indentation; the via is located at the first upper surface of the first N-type semiconductor layer and is used to electrically connect the parallel pad and the bottom pad in the vertical direction;
[0015] The top of the P-type semiconductor layer is provided with a third upper surface and a fourth upper surface formed by downward indentation, and the P-type semiconductor layer is embedded in the second upper surface of the top of the first N-type semiconductor layer.
[0016] The second N-type semiconductor layer is embedded in the fourth upper surface on top of the P-type semiconductor layer;
[0017] The protective layer is disposed on the first upper surface of the first N-type semiconductor layer, the third upper surface of the P-type semiconductor layer, and the upper surface of the second N-type semiconductor layer;
[0018] The protective layer has pad contact holes at the via locations and on the upper surface of the second N-type semiconductor layer, respectively.
[0019] A further feature of this invention is that a conductive material layer is electroplated onto the inner wall of the through hole.
[0020] In a further improvement of this invention, an impedance material layer is electroplated onto the inner wall of the through hole.
[0021] Based on the same concept, this utility model also provides an LED packaging structure with a Zener chip, which includes a support, a Zener chip as described above, and a light-emitting chip; wherein, the support includes a positive electrode functional area and a negative electrode functional area;
[0022] The light-emitting chip is die-bonded in the negative electrode functional region. The positive terminal of the light-emitting chip is connected to the parallel pad of the Zener chip through a lead. The negative terminal of the light-emitting chip is connected to the negative electrode functional region through a lead.
[0023] The Zener chip is die-bonded in the positive functional area of the support and connected to the negative functional area via leads.
[0024] Based on the same concept, this utility model also provides an LED packaging structure with a Zener chip, which includes a support, a Zener chip as described above, and a light-emitting chip; wherein, the support includes a positive electrode functional area and a negative electrode functional area;
[0025] The light-emitting chip is flip-chip configured such that the positive terminal of the light-emitting chip is die-bonded in the positive electrode functional region, and the negative terminal of the light-emitting chip is die-bonded in the negative electrode functional region;
[0026] The Zener chip is die-bonded in the positive functional region of the substrate, the Zener structure of the Zener chip is connected to the negative functional region via leads, and the parallel pads of the Zener chip are connected to the negative functional region via leads.
[0027] In a further improvement of this invention, the lead wire is a gold wire.
[0028] In a further embodiment of this invention, the Zener chip is fixed to the bracket by conductive silver paste.
[0029] This invention discloses a Zener chip and an LED packaging structure with a Zener chip. The Zener chip includes a Zener structure, Zener pads, parallel pads, and a bottom pad. The Zener structure is disposed on the bottom pad and has a vertical through-hole for electrically connecting the parallel pads and the bottom pad. The Zener structure is used to form a Zener diode. The Zener pads and parallel pads are fixedly disposed on the upper surface of the Zener structure. The parallel pads cover the through-holes and are connected to the bottom pads through the through-holes. This invention increases the area of the positive electrode pads available for wire bonding when the Zener chips are connected in parallel by providing parallel pads connected to the bottom pads through through-holes on the upper surface of the Zener chip, thus reducing the wire bonding risk of the LED packaging structure with a Zener chip. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the structure of a Zener chip in the prior art.
[0032] Figure 2 This is an equivalent circuit diagram of an LED package structure with a Zener chip, in which the Zener chip and the light-emitting chip are connected in parallel.
[0033] Figure 3 This is a schematic diagram of an existing LED packaging structure with a Zener chip.
[0034] Figure 4 This is a schematic diagram of the structure of a unidirectional Zener chip in a preferred embodiment of this utility model.
[0035] Figure 5 This is a schematic diagram of the structure of a bidirectional Zener chip in another preferred embodiment of the present invention.
[0036] Figure 6 This is a schematic diagram of the structure of a unidirectional Zener chip in another preferred embodiment of the present invention.
[0037] Figure 7 This is a schematic diagram of the structure of a bidirectional Zener chip in another preferred embodiment of the present invention.
[0038] Figure 8 This is an equivalent circuit diagram showing the Zener chip and the light-emitting chip connected in parallel in another preferred embodiment of the present invention.
[0039] Figure 9 This is a schematic diagram of an LED package structure with a Zener chip in some preferred embodiments of this utility model.
[0040] Figure 10 This is a schematic diagram of an existing LED packaging structure with a Zener chip.
[0041] Figure 11 This is a schematic diagram of an LED package structure with a Zener chip in another preferred embodiment of the present invention.
[0042] The labels in the attached diagram are as follows: 1. Zener chip; 11. Zener structure; 111. First N-type semiconductor layer; 112. P-type semiconductor layer; 113. Protective layer; 114. Second N-type semiconductor layer; 12. Zener pad; 13. Parallel pad; 14. Bottom pad; 2. Light-emitting chip; 3. Support; 31. Positive electrode functional area; 32. Negative electrode functional area. Detailed Implementation
[0043] This utility model provides a Zener chip and an LED packaging structure with a Zener chip. To make the purpose, technical solution, and effects of this utility model clearer and more explicit, the following describes this utility model in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of this utility model and are not intended to limit this utility model.
[0044] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of this utility model involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.
[0045] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.
[0046] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.
[0047] Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0048] Figure 1-3 The prior art Zener chip 1 and its corresponding LED packaging structure are disclosed, specifically, Figure 1 This is a schematic diagram of the structure of a Zener chip 1 in the prior art. Wherein, Figure 1 The image above is a top view of the structure of a unidirectional Zener chip. Figure 1The figure below is a front view of a unidirectional Zener chip. The unidirectional Zener chip includes a bottom pad 14, and a Zener structure 11 is disposed above the bottom pad 14. When in use, the Zener pad 12 on the upper surface of the Zener chip 1 and the bottom pad 14 are respectively connected to an external circuit. When current flows through the Zener structure 11 located between the Zener pad 12 and the bottom pad 14, a Zener diode is formed inside the Zener structure 11. The Zener structure 11 can be used to form a unidirectional Zener diode or a bidirectional Zener diode. The working principle of the Zener diode is prior art and will not be described in detail here.
[0049] Furthermore, please refer to the following: Figure 2 and Figure 3 LEDs are semiconductor devices sensitive to electrostatic discharge (ESD), which can reach tens of thousands of volts. When an ESD voltage strikes the electrodes of the LED's internal light-emitting chip (LED 2), the reverse current rapidly melts the internal structure of the LED package along the path of lowest resistance, damaging the LED 2. To protect the LED 2 from ESD damage and improve its anti-static capability, a Zener diode is built into the LED package. This Zener diode is connected in parallel across the LED 2 in chip form. When the input voltage exceeds the Zener voltage, the Zener diode breaks down in reverse, clamping the voltage at the Zener voltage value and preventing damage to the LED 2 due to overvoltage, thus providing ESD discharge. The circuit diagram of an LED package with a Zener diode is shown below. Figure 2 As shown, Figure 2 The left figure shows the circuit diagram of LED chip 2 connected in parallel with a unidirectional Zener diode. Figure 2The right figure is a circuit diagram of a parallel bidirectional Zener diode connected to a light-emitting chip 2. For example, when a unidirectional Zener diode structure is formed inside the Zener chip 1, the light-emitting chip can be equivalent to a first light-emitting diode LED1, and the unidirectional Zener diode structure can be equivalent to a first Zener diode ZD1. The anode of the first light-emitting diode LED1 is considered to be connected to the cathode of the Zener diode ZD1, and the cathode of the first light-emitting diode LED1 is connected to the anode of the first Zener diode ZD1. The first Zener diode ZD1 is connected in reverse parallel across the first light-emitting diode LED1, and the breakdown direction of the first Zener diode ZD1 is opposite to the conduction direction of the first light-emitting diode LED1, clamping the reverse voltage at the Zener voltage value. When the Zener chip 1 forms a bidirectional Zener diode structure, its internal circuit can be equivalent to a second forward Zener diode ZD2 and a third reverse Zener diode ZD3 connected in series and then connected in parallel with the second light-emitting diode LED2. Specifically, the cathode of the second light-emitting diode LED2 is connected to the cathode of the second forward Zener diode ZD2, the anode of the second forward Zener diode ZD2 is connected to the anode of the third reverse Zener diode ZD3, and the cathode of the third reverse Zener diode ZD3 is connected to the anode of the second light-emitting diode LED1. Thus, regardless of whether there is a forward or reverse overvoltage, the bidirectional Zener diode can break down and conduct, clamping the voltage within a safe range and achieving bidirectional overvoltage protection.
[0050] Figure 3The diagram shows a prior art LED packaging structure with a Zener chip. The Zener chip 1 is die-bonded in the positive electrode functional area 31 at the bottom of the support 3, and the light-emitting chip 2 is die-bonded in the negative electrode functional area 32 of the support 3. The positive electrode functional area 31 also includes a positive electrode pad for wire bonding to the positive terminal of the light-emitting chip 2. After die bonding, an LED wire bonding machine is used to press the wire bonded to the pads on the support 3 and chip surface using a ceramic nozzle, and then ultrasonically bonded. Specifically, the positive terminal of the light-emitting chip 2 is connected to the positive electrode functional area 31 via a wire bond, and the negative terminal of the light-emitting chip 2 and the Zener pad 12 of the Zener chip 1 are connected to the negative electrode functional area 32 via wire bondes. The inventors have discovered that in the prior art, because the Zener chip 1 is vertically oriented, conductive silver paste must be used to die-bond the Zener chip 1 in the positive electrode pad to achieve reverse electrostatic discharge of the Zener diode, thus occupying the pad space in the positive electrode functional area 31 originally used for wire bonding. Meanwhile, during the curing process of the conductive silver paste, due to the different surface energies of the materials, the organic components in the conductive silver paste will migrate along the substrate surface at the bottom of the support 3, causing diffusion. This diffusion may then cover the positive electrode pads of adjacent positions used for bonding the wire-light chip 2. Deviation in the solderable area of the pads causes the ceramic nozzle and the wire to easily come into contact with the cup wall of the support 3 during the wire bonding process, resulting in phenomena such as ceramic nozzle breakage and wire breakage. This makes wire bonding operations difficult during processing, and thus poses risks of wire bonding such as cold solder joints and false solder joints.
[0051] To address the aforementioned technical problems, this utility model proposes a Zener chip, comprising: a Zener structure 11, a Zener pad 12, a parallel pad 13, and a bottom pad 14; wherein, the Zener structure 11 is disposed on the bottom pad 14, the Zener structure 11 has a through hole in the vertical direction, and the Zener structure 11 is used to form a Zener diode; the Zener pad 12 and the parallel pad 13 are respectively fixedly disposed on the upper surface of the Zener structure 11, the parallel pad 13 covers the through hole and is connected to the bottom pad 14 through the through hole.
[0052] Specifically, the bottom pad 14 of the Zener chip 1 is connected to the Zener pad 12 via the Zener structure 11 and to the parallel pad 13 via a via. When the Zener pad 12 of the Zener chip 1 is connected to an external circuit, its internal Zener structure 11 forms a Zener diode to realize the original electrostatic discharge function of the Zener chip 1. The parallel pad 13 of the Zener chip 1 is connected in parallel to the bottom pad 14 via a via. The parallel pad 13 needs to be etched with vias using thin-film blocking and photolithography techniques, and then a conductive material layer is coated on the inner surface of the via using vapor deposition or via plating. The material of the metal layer can be at least one of aluminum, copper, and tungsten. The via can be regarded as a wire, so the bottom pad 14 and the parallel pad 13 are electrically connected, and the potential difference between them is zero, and they are at the same potential. The branch formed by the conductive connection of the bottom pad 14, the through hole and the parallel pad 13 is connected in parallel with the Zener structure 11, thereby reserving a parallel pad 13 with the same potential as its lower surface on the upper surface of the Zener chip 1, increasing the solderable area of the pad and facilitating wire bonding.
[0053] Furthermore, such as Figure 4 As shown, in some preferred embodiments of this utility model, the Zener structure 11 includes: a first N-type semiconductor layer 111, a P-type semiconductor layer 112, a protective layer 113, and a Zener pad 12; wherein, the first N-type semiconductor layer 111 is disposed on the bottom pad 14, and the top of the first N-type semiconductor layer 111 is provided with a first upper surface and a second upper surface formed by downward indentation, and the through hole is located at the first upper surface of the first N-type semiconductor layer for vertically electrically connecting the parallel pad and the bottom pad; the P-type semiconductor layer 112 is embedded in the second upper surface at the top of the first N-type semiconductor layer 111; the protective layer 113 is disposed on the first upper surface of the first N-type semiconductor layer 111 and the upper surface of the P-type semiconductor layer 112, and the protective layer 113 is provided with pad contact holes at the through hole position and on the upper surface of the P-type semiconductor layer 112 respectively; the Zener pad 12 is connected to the P-type semiconductor layer 112 through the pad contact holes.
[0054] Specifically, doping is performed on the upper surface of the first N-type semiconductor layer 111, which has a first upper surface, thereby fusing a pn junction between the second upper surface of the first N-type semiconductor layer 111 and the P-type semiconductor layer 112 to form a unidirectional Zener diode. The fabrication method and specific operation mode of the Zener diode are existing technologies and will not be described in detail here. A through-hole is formed on the first upper surface of the first N-type semiconductor layer 111 by thin film blocking and photolithography, and then a metal layer is deposited on the surface inside the through-hole by vapor deposition.
[0055] Furthermore, such as Figure 5As shown, the Zener structure 11 includes: a first N-type semiconductor layer 111, a P-type semiconductor layer 112, a second N-type semiconductor layer 114, and a protective layer 113; wherein, the first N-type semiconductor layer 111 is disposed on the bottom pad 14, and the top of the first N-type semiconductor layer 111 is provided with a first upper surface and a second upper surface formed by downward indentation; the via is located at the first upper surface of the first N-type semiconductor layer and is used for vertically electrically connecting the parallel pad and the bottom pad; the top of the P-type semiconductor layer 112 is provided with a third upper surface. The P-type semiconductor layer 112 is embedded in the second upper surface on top of the first N-type semiconductor layer 111, and the second N-type semiconductor layer 114 is embedded in the fourth upper surface on top of the P-type semiconductor layer 112. The protective layer 113 is disposed on the first upper surface of the first N-type semiconductor layer 111, the third upper surface of the P-type semiconductor layer 112, and the upper surface of the second N-type semiconductor layer 114. The protective layer 113 has pad contact holes at the via positions and on the upper surface of the second N-type semiconductor layer 114, respectively.
[0056] Specifically, a PN junction is formed between the second upper surface of the first N-type semiconductor layer 111 and the P-type semiconductor layer 112, thereby forming a unidirectional Zener diode. Further, a PN junction is formed between the P-type semiconductor layer 112 and the second N-type semiconductor layer 114, constituting another unidirectional Zener diode. The two unidirectional Zener diodes are oriented in opposite directions. A via is formed at the first upper surface of the first N-type semiconductor layer 111 using thin-film blocking and photolithography techniques, and then a metal layer is deposited on the surface within the via using vapor deposition. Regardless of forward or reverse overvoltage (such as reverse power connection, inductive load backflash, or AC interference), the bidirectional Zener diode can quickly clamp the voltage, preventing damage to the light-emitting chip 2 due to overvoltage or reverse voltage, thus providing electrostatic discharge protection. This application adds parallel pads 13 to the upper surface of the Zener chip 1 to ensure sufficient soldering space during actual soldering.
[0057] Furthermore, please refer to the following: Figures 6 to 8 In a further embodiment of a preferred embodiment of this utility model, an impedance material layer may be provided on the inner wall of the through hole. One end of the impedance material layer is connected to the parallel pad through a conductive material layer, and the other end of the impedance material layer is connected to the bottom pad through another conductive material layer. The conductive material layer and the impedance material layer on the inner wall of the through hole are obtained by hole electroplating. The preparation method can also be to fill the through hole with conductive material and impedance material, which is not limited here.
[0058] The equivalent circuit of the light-emitting chip 2 and the Zener chip 1 with a unidirectional Zener diode structure connected in parallel is as follows: Figure 8As shown in the left figure, the equivalent circuit of the light-emitting chip 2 and the Zener chip 1 with a bidirectional Zener diode structure connected in parallel is as follows: Figure 8 As shown in the right figure. Exemplarily, when a unidirectional Zener diode structure is formed inside the Zener chip 1, the light-emitting chip can be equivalent to a third light-emitting diode LED3, and the unidirectional Zener diode structure can be equivalent to a fourth Zener diode ZD4. The impedance material layer is considered as a first equivalent resistance R1. The anode of the third light-emitting diode LED3 is connected to one end of the first equivalent resistance R1, and the other end of the first equivalent resistance R1 is connected to an external voltage and to the cathode of the fourth Zener diode ZD4; the cathode of the third light-emitting diode LED3 is connected to the anode of the fourth Zener diode ZD4. The fourth Zener diode ZD4 is connected in reverse parallel across the third light-emitting diode LED3 and the first equivalent resistance. The breakdown direction of the fourth Zener diode ZD4 is opposite to the conduction direction of the third light-emitting diode LED3, thereby clamping the reverse voltage to the Zener voltage value, which is then divided by the first equivalent resistance R1. When the Zener chip 1 forms a bidirectional Zener diode structure, its equivalent circuit consists of a fifth forward Zener diode ZD5 (forward-biased) and a sixth reverse Zener diode ZD6 (reverse-biased) connected in series, then connected in parallel with a second equivalent resistor R2 and a fourth light-emitting diode LED4. Specifically, one end of the second equivalent resistor is connected to an external voltage and to the cathode of the sixth reverse Zener diode ZD6, while the other end of the second equivalent resistor R2 is connected to the anode of the fourth light-emitting diode LED4. The cathode of the fourth light-emitting diode LED4 is connected to the outside. The electrical connection between the fifth Zener diode ZD5, the sixth Zener diode ZD6, and the fourth light-emitting diode LED4 is such that, regardless of whether there is a forward or reverse overvoltage, the bidirectional Zener diode can break down and conduct, clamping the voltage within a safe range and achieving bidirectional overvoltage protection. A predetermined impedance R1 is established between the through pad and the bottom pad 14 of the Zener chip 1. This allows the Zener chip 1 to be connected in parallel with an external circuit, enabling current limiting while maintaining the parallel connection, without requiring an additional external resistor at the front end of the external circuit. This simplifies the circuit and saves on-chip space. Specific implementation details are described in the Zener chip example and will not be repeated here.
[0059] like Figure 9As shown, based on the same inventive concept, this utility model also provides an LED packaging structure with a Zener chip, which includes a support 3, a Zener chip as described above, and a light-emitting chip 2; wherein, the support 3 includes a positive electrode functional region 31 and a negative electrode functional region 32; the light-emitting chip 2 is die-bonded in the negative electrode functional region 32, the positive terminal of the light-emitting chip 2 is connected to the parallel pad 13 of the Zener chip through a lead, and the negative terminal of the light-emitting chip 2 is connected to the negative electrode functional region 32 through a lead; the Zener chip is die-bonded in the positive electrode functional region 31 of the support 3 and connected to the negative electrode functional region 32 through a lead. The lead is a gold wire, and the Zener chip is fixed to the support 3 with conductive silver paste.
[0060] Specifically, the support 3 is provided with a bowl-shaped cup, the bottom of which includes a positive electrode functional area 31 and a negative electrode functional area 32, which are respectively a positive electrode pad and a negative electrode pad. The bottom pad 14 of the Zener chip 1 is die-bonded to the positive electrode functional area 31 by conductive silver paste. When the Zener chip is working, one current flows from the bottom pad 14 through the Zener structure 11, through the unidirectional Zener diode formed between the first N-type semiconductor layer 111 and the P-type semiconductor layer 112, and flows out from the Zener pad 12 to the negative electrode pad, and the Zener diode works normally. The other current is connected to the positive terminal of the light-emitting chip 2 through the parallel pad 13 of the Zener chip 1, and the negative terminal of the light-emitting chip 2 is connected to the negative electrode pad. The positive terminal of LED 2 is at the same potential as the bottom pad 14 of Zener chip 1, and the negative terminal of LED 2 is at the same potential as the Zener pad 12 of Zener chip 1. LED 2 and Zener chip 1 are connected in parallel, and Zener chip 1 provides electrostatic discharge protection. By adding a parallel pad 13 to the upper surface of Zener chip 1, the bonding wires of Zener chip 1 and LED 2 can be connected even when the width of the bracket 3 is very narrow or when there is a lack of bonding wire positions, thus achieving a parallel connection between Zener chip 1 and LED 2.
[0061] Furthermore, please refer to the following: Figure 10 and Figure 11 In another preferred embodiment of this utility model, another LED packaging structure with a Zener chip is also provided.
[0062] Specifically, another existing LED packaging structure with a Zener chip is as follows: Figure 11As shown, the light-emitting chip 2 is flip-chip mounted in a bowl. The positive terminal of the light-emitting chip 2 is die-bonded in the positive electrode functional region 31, and the negative terminal is die-bonded in the negative electrode functional region 32. The positive and negative terminals of the light-emitting chip 2 are connected to the positive and negative electrode pads on the bottom of the chip, respectively. One end of the Zener chip 1 is fixed and electrically connected to the positive electrode pad on the bottom through conductive silver paste, and the other end of the Zener chip 1 is connected to the negative electrode functional region 32 through a bonding wire, thus achieving parallel connection between the Zener chip 1 and the light-emitting chip 2. However, when the LED packaging structure experiences drastic temperature changes in a short period of time, these temperature changes can cause the conductive silver paste to expand or contract, thereby generating thermal stress, which can easily lead to detachment and delamination from the support 3. Specifically, the conductive silver paste is mainly composed of silver powder and matrix resin. The matrix resin can be selected from adhesive systems such as epoxy resin, acrylic resin, silicone resin, polyimide resin, phenolic resin, polyurethane, and acrylic resin, which have good adhesion and plasticity. After the conductive silver paste cures, the silicone inside the bracket 3 is subjected to temperature changes, and the internal silicone stress will compress the contact surface between the conductive silver paste and the Zener chip 1. After the LED chip undergoes a certain degree of aging or environmental temperature changes, the conductive silver paste at the bottom of the Zener chip 1 will delaminate, causing the conductive silver paste to peel off from the bottom of the bracket 3, resulting in an open circuit in the Zener chip 1. This leads to the failure of electrostatic discharge protection, and the performance and reliability of the LED packaging structure with Zener chip in the existing technology decrease in extreme environments.
[0063] For the above technical issues, please refer to the following: Figure 4-7 and Figure 11 In another preferred embodiment, the present invention also provides another LED packaging structure with a Zener chip, including: a support 3, a Zener chip 1 as described above, and a light-emitting chip 2; wherein, the support 3 includes a positive electrode functional region 31 and a negative electrode functional region 32; the light-emitting chip 2 is flip-chip mounted on the support 3, with its positive end die-bonded in the positive electrode functional region 31 and its negative end die-bonded in the negative electrode functional region 32; the Zener chip is die-bonded in the positive electrode functional region 31, the Zener pads 12 of the Zener chip are connected to the negative electrode functional region 32 through leads, and the parallel pads 13 of the Zener chip are connected to the positive electrode functional region 31 through leads.
[0064] Specifically, both the parallel pad 13 and the bottom pad 14 maintain the same potential as the positive pad on the support 3. When the Zener chip 1 is securely connected to the support 3 via conductive silver paste, current flows through the bottom pad 14 through the Zener structure 11 and exits from the Zener pad 12 to the negative pad in the negative characteristic region. The Zener chip 1 and the light-emitting chip 2 are connected in parallel. Its operation is as described in the Zener chip 1 with parallel pad 13, and will not be repeated here. When the conductive silver paste at the bottom of the Zener chip 1 falls off, the bottom pad 14 of the Zener chip 1 is considered an open circuit. At this time, the Zener chip 1 is connected to the positive pad via the parallel pad 13. Since the parallel pad 13 is connected to the bottom pad 14 through a via, and the via is located in the first N-type semiconductor layer 111, the potential inside the via and the bottom pad 14 remains the same as the positive pad. Furthermore, the Zener chip 1 is connected to the through pad and the bracket 3 pad using wire bonding. The Zener chip 1 with the through pad is fixed to the bottom of the chip with conductive silver paste. Even if the conductive silver paste falls off, the Zener chip 1 will still maintain effective electrostatic protection because it is conductively connected to the bracket 3 pad, thus achieving secondary protection for the circuit structure of the Zener chip 1 connected in parallel.
[0065] In summary, the Zener chip and LED packaging structure with Zener chip provided by this utility model have the following beneficial effects:
[0066] By improving the pad structure of the Zener chip and adding through pads, and by setting parallel pads on the upper surface of the Zener chip that are connected to the bottom pads via vias, the area of the positive electrode pads that can be used for wire bonding when the Zener chips are connected in parallel is increased, thereby reducing the wire bonding risk of LED packaging structures with Zener chips and reducing the difficulty of wire bonding operations.
[0067] The Zener chip with through-pads uses conductive silver paste to fix the chip to conductivity. Even if the conductive silver paste detaches, the Zener chip can still function, providing secondary protection for circuit structures connected in parallel with the Zener chip. It can be used in products with certain thermal shock requirements, preventing Zener chip failure after the conductive silver paste and the bracket detach, thus providing dual protection.
[0068] It should be understood that the application of this utility model is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A Zener chip for parallel connection with a light-emitting chip, characterized in that, include: Zener structure, Zener pads, parallel pads, and bottom pads; among which... A Zener structure is disposed on the bottom pad, the Zener structure having a vertical through-hole for electrically connecting the parallel pad and the bottom pad; the Zener structure is used to form a Zener diode; The Zener pads and parallel pads are respectively fixedly disposed on the upper surface of the Zener structure. The parallel pads cover the through holes and are connected to the bottom pads through the through holes.
2. The Zener chip according to claim 1, characterized in that, The Zener structure includes: a first N-type semiconductor layer, a P-type semiconductor layer, and a protective layer; wherein... The first N-type semiconductor layer is disposed on the bottom pad. The top of the first N-type semiconductor layer is provided with a first upper surface and a second upper surface formed by a downward indentation. The via is located at the first upper surface of the first N-type semiconductor layer and is used to electrically connect the parallel pad and the bottom pad in the vertical direction. The P-type semiconductor layer is embedded in the second upper surface on top of the first N-type semiconductor layer; The protective layer is disposed on the first upper surface of the first N-type semiconductor layer and the upper surface of the P-type semiconductor layer. The protective layer has pad contact holes at the via locations and on the upper surface of the P-type semiconductor layer, respectively. The Zener pads are connected to the P-type semiconductor layer through the pad contact holes.
3. The Zener chip according to claim 1, characterized in that, The Zener structure includes: a first N-type semiconductor layer, a P-type semiconductor layer, a second N-type semiconductor layer, and a protective layer; wherein... The first N-type semiconductor layer is disposed on the bottom pad, and the top of the first N-type semiconductor layer is provided with a first upper surface and a second upper surface formed by downward indentation; the via is located at the first upper surface of the first N-type semiconductor layer and is used to electrically connect the parallel pad and the bottom pad in the vertical direction; The top of the P-type semiconductor layer is provided with a third upper surface and a fourth upper surface formed by downward indentation, and the P-type semiconductor layer is embedded in the second upper surface of the top of the first N-type semiconductor layer. The second N-type semiconductor layer is embedded in the fourth upper surface on top of the P-type semiconductor layer; The protective layer is disposed on the first upper surface of the first N-type semiconductor layer, the third upper surface of the P-type semiconductor layer, and the upper surface of the second N-type semiconductor layer; The protective layer has pad contact holes at the via locations and on the upper surface of the second N-type semiconductor layer, respectively.
4. The Zener chip according to claim 2 or 3, characterized in that, The inner wall of the through hole is electroplated with a conductive material layer.
5. The Zener chip according to claim 4, characterized in that, The inner wall of the through hole is also electroplated with an impedance material layer.
6. An LED packaging structure with a Zener chip, characterized in that, Includes the Zener chip, light-emitting chip, and bracket as described in any one of claims 1-5; wherein the bracket includes a positive electrode functional region and a negative electrode functional region; The light-emitting chip is die-bonded in the negative electrode functional region. The positive terminal of the light-emitting chip is connected to the parallel pad of the Zener chip through a lead. The negative terminal of the light-emitting chip is connected to the negative electrode functional region through a lead. The Zener chip is die-bonded in the positive functional area of the support and connected to the negative functional area via leads.
7. An LED packaging structure with a Zener chip, characterized in that, Includes the Zener chip, light-emitting chip, and bracket as described in any one of claims 1-5; wherein the bracket includes a positive electrode functional region and a negative electrode functional region; The light-emitting chip is flip-chip configured such that the positive terminal of the light-emitting chip is die-bonded in the positive electrode functional region, and the negative terminal of the light-emitting chip is die-bonded in the negative electrode functional region; The Zener chip is die-bonded in the positive functional region of the substrate, the Zener structure of the Zener chip is connected to the negative functional region via leads, and the parallel pads of the Zener chip are connected to the negative functional region via leads.
8. The LED packaging structure with Zener chip according to claim 6 or 7, characterized in that, The lead wire is gold wire.
9. The LED packaging structure with Zener chip according to claim 6 or 7, characterized in that, The Zener chip is fixed to the bracket with conductive silver paste.