Super junction power semiconductor device

Abstract

The present description provides a super junction power semiconductor device. An example super junction power semiconductor device has a die of semiconductor material including a structural layer having a first doping type, the die having an active region forming an active cell and an edge region surrounding the active region at a periphery of the die. An edge termination arrangement at the edge region has a plurality of edge termination trenches extending through the structural layer, the plurality of edge termination trenches being filled with a dielectric material and having respective doping layers of the second doping type at sidewalls thereof. The edge termination arrangement has an electrical connection structure to electrically connect together the respective doped layers at sidewalls of the edge termination trench.

Description

[0001] Cross-references to (one or more) related applications

[0002] This application claims priority to Italian patent application No. 102024000005977, filed on March 18, 2024, entitled “DISPOSITIVO SEMICONDUTTORE DIPOTENZA A SUPERGIUNZIONE CON TERMINAZIONE DI BORDO PERFEZIONATA”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This solution relates to a superjunction power semiconductor device with improved edge termination. Background Technology

[0004] Superjunction power semiconductor devices, such as MOSFET devices, are based on the principle of charge balance or charge compensation, according to which the charge in a structural layer of a first conductivity or doping type (e.g., an n-type epitaxial layer) is compensated or balanced by doped pillars or struts formed in the same layer and having a second conductivity or doping type (in this example, p-type doping). This technique is advantageous, for example, because it allows for a trade-off between the breakdown voltage and on-resistance of the power semiconductor device.

[0005] However, the manufacturing cost of this technology is quite high because the formation of doped pillars requires complex manufacturing steps, such as multiple implantation and epitaxial growth steps, or complete filling (no voids) of deep trenches with high aspect ratios, for example, up to 20 (depth): 1 (width).

[0006] Moreover, as with all power devices, edge termination is required to achieve the desired breakdown voltage performance, and for these superjunction power semiconductor devices, proper edge termination design is generally not a simple process.

[0007] Recently, a system architecture for charge-balanced dual-trench superjunction MOSFET devices has been proposed, which allows for overcoming at least some of the above problems, see, for example, US 2023 / 0107611 A1.

[0008] Advantageously, in order to form a columnar charge-balanced structure for the MOSFET cell, the fabrication of this superjunction MOSFET device does not require multiple epitaxial processing steps or epitaxial filling of deep trenches.

[0009] However, such superjunction MOSFET devices must also address the issue of providing efficient edge termination, especially considering that the charge balance structure of the last MOSFET cell shows a high voltage difference between the reference (ground) potential of the corresponding body region and source region and the high voltage at the edge of the same device (corresponding to the drain-source voltage of superjunction MOSFET device 1), which may cause an undesirable distribution of electric field lines.

[0010] One known solution for edge termination is to provide a deep and wide trench filled with dielectric as a protection around the active area of ​​the device and to place a field plate on top.

[0011] For example, this technique is disclosed in the article "Design optimization of the deeptrench termination for superjunction power devices" in the International Journal of microelectronics and computer science, Vol. 6, No. 4, 2015, by Noblecourt, S. et al.

[0012] However, the drawback of this solution is that it is difficult to control the depth of this larger trench while creating the charge-balancing trench in the active region; and it also involves the complexity of achieving complete filling (no voids) of this last trench. Utility Model Content

[0013] This solution is generally designed to overcome the limitations of known superjunction power devices, particularly regarding the problem of providing efficient edge termination regions.

[0014] According to this solution, a superjunction power device is thus provided as defined in the appended claims. The superjunction power semiconductor device has a die of semiconductor material, the die including a substrate and a structural layer formed on the substrate and having a first doping type, wherein the die has an active region forming active cells and an edge region surrounding the active region at the periphery of the die, and the die includes a plurality of charge-balanced deep trenches filled with a dielectric in the active region, the plurality of charge-balanced deep trenches extending through the structural layer and reaching the substrate between corresponding pairs of active cells, each charge-balanced deep trench having a doped layer of a second doping type at its sidewalls; the superjunction power semiconductor device further includes an edge-termination arrangement located at the edge region, the edge-termination arrangement including a plurality of edge-termination trenches extending through the structural layer and reaching the substrate, filled with a dielectric, and having a corresponding doped layer of the second doping type at its sidewalls; wherein the edge-termination arrangement includes an electrical connection structure configured to electrically connect the corresponding doped layers at the sidewalls of the plurality of edge-termination trenches together.

[0015] In one embodiment, the first electrical connection structure closest to the active region is electrically connected to the last active unit of the active region, and all other electrical connection structures are at a floating potential.

[0016] In one embodiment, the electrical connection structure includes corresponding bridging conductive portions, each bridging conductive portion being disposed above and across the corresponding edge termination trench, and electrically short-circuiting the corresponding doped layer at the sidewall of the corresponding edge termination trench.

[0017] In one embodiment, a superjunction power semiconductor device includes a dielectric layer on the top surface of the structural layer; wherein each of the electrical connection structures includes: a pair of contacts disposed at one or more sides of a corresponding edge-terminating trench, traversing the dielectric layer and designed to electrically contact a corresponding doped layer; and a blocking portion disposed on the dielectric layer and contacting the pair of contacts from above.

[0018] In one embodiment, the edge termination arrangement includes a doped region located on the top surface of the structural layer and having the same doping type as the doped layer, the doped region being arranged transversely to the plurality of edge termination trenches to contact the respective doped layer; wherein a pair of contacts is configured to reach the doped region in the structural layer.

[0019] In one embodiment, the edge termination arrangement includes a shallow trench located at the top surface of the structural layer, the shallow trench being arranged between the pair of contacts and including a polysilicon region separated from the doped region by a dielectric layer.

[0020] In one embodiment, the electrical connection structure further includes: additional contacts that traverse the dielectric layer and are configured to electrically contact the polysilicon region of the corresponding shallow trench; wherein the blocking portion of the electrical connection structure is configured to also contact the corresponding additional contacts from above.

[0021] In one embodiment, the doped region is separated by a separation portion of the epitaxial layer disposed between the pair of contacts.

[0022] In one embodiment, the electrical connection structure includes a conductive bridging portion disposed on the top surface of the structural layer and closing the corresponding edge-terminating trench at the top; and a doped region in the structural layer that contacts the bridging portion and one or more thin doped layers at the sidewalls of the corresponding edge-terminating trench.

[0023] In one embodiment, the electrical connection structure is discontinuous along the extension direction of the deep trench terminating at the corresponding edge, but is instead regularly distributed along the extension direction at a given separation distance.

[0024] In one embodiment, the superjunction power semiconductor device is a trench-gate power MOSFET device. Attached Figure Description

[0025] To better understand this disclosure, preferred embodiments thereof will now be described by way of non-limiting example and with reference to the accompanying drawings, in which:

[0026] Figure 1 A cross-section of a portion of a superjunction power device is shown;

[0027] Figure 2 A portion of a superjunction power device according to one aspect of this solution and a cross-section of the corresponding edge termination region are shown;

[0028] Figure 3 This is a diagram of the potential distribution in the edge region of a superjunction power device;

[0029] Figures 4A-4K A cross-section of a power semiconductor device associated with a first embodiment of an edge-terminating arrangement is shown in successive steps of the manufacturing process;

[0030] Figure 5 The following are illustrated in possible embodiments. Figure 4K A plan view of the edge portion of a power semiconductor device;

[0031] Figure 6A An alternative embodiment is shown. Figure 4K A plan view of the edge portion of a power semiconductor device;

[0032] Figure 6B It shows Figure 6A The cross-section of a power semiconductor device;

[0033] Figures 7A-7K A cross-section of a power semiconductor device associated with a second embodiment of edge-terminating arrangement is shown in successive steps of the manufacturing process;

[0034] Figure 8 Illustrations are shown according to possible embodiments Figure 7K A plan view of the edge portion of the power semiconductor device; and

[0035] Figures 9A-9H A cross-section of a power semiconductor device associated with a third embodiment of edge-termination arrangement is shown in successive steps of the manufacturing process. Detailed Implementation

[0036] As will be discussed below, one aspect of this solution relates to an improved edge termination for superjunction power semiconductor devices (particularly MOSFET devices), comprising dielectric-filled trenches with doped sidewalls disposed in the periphery of the active region of the device. Specifically, the sidewalls of adjacent trenches are electrically connected and maintained at a floating potential, thereby achieving a gradual distribution of voltage potential in the edge region of the superjunction power semiconductor device and appropriate confinement of electric field lines.

[0037] like Figure 1 As shown, the superjunction power semiconductor device, generally represented by 1, particularly a MOSFET device, includes a die 20' of a semiconductor material such as silicon (or other semiconductor materials, such as silicon carbide), which includes a substrate 29 having a low thickness (approximately 20-200 µm) and a high concentration of a first doping type, such as n ++ (For example, doping concentrations as high as 4e) 16 cm -3 ).

[0038] Epitaxial layer 27 is formed on substrate 29 and has a first doping type and a low concentration (e.g., n-type).

[0039] MOSFET cells 5 are formed on the top surface 27a of the epitaxial layer 27 opposite to the substrate 29. Each trench-gate type MOSFET cell 5 includes: a gate region 6, made of doped polysilicon, disposed in a corresponding gate trench 7 formed through a shallow portion of the epitaxial layer 27; a body region 8, having a second doping type (p-type), laterally surrounding the gate trench 7 and separated from the gate trench 7 by a thin dielectric layer 9; and a source region 10, having a first doping type (n-type), disposed on the body region 8 laterally opposite the corresponding gate trench 7.

[0040] The power semiconductor device 1 also includes a plurality of charge-balancing deep trenches 12, which are filled with a dielectric, particularly an oxide, extending through the epitaxial layer 27 and reaching the underlying substrate 29. In the active region of the MOSFET device, each MOSFET cell 5 is arranged between an adjacent pair of charge-balancing deep trenches 12.

[0041] Specifically, the power semiconductor device 1 includes a thin doped layer 14 of a second doping type (p-type) at the sidewalls of each charge-balancing deep trench 12, for example, with a width ranging from ten nanometers to two hundred nanometers, designed to compensate for epitaxial n-type charge under depletion and achieve charge balance. These thin doped layers 14 form p-doped pillars, thereby allowing corresponding narrow and heavily doped n-type epitaxial drift regions, thus improving the tradeoff between on-resistance and breakdown voltage (generally, the smaller the width, the better the performance in terms of on-resistance).

[0042] The power semiconductor device 1 also includes a drain contact layer 15 on the back side of the substrate 29; and a source contact layer 16 above the top surface 27a of the epitaxial layer 27 (which represents the drift region of the device), the source contact layer 16 contacting both the body region 8 and the source region 10 via contact elements (or "plugs") 18, extending vertically through the dielectric region 19, covering the top surface 27a, and traversing the source region 10 to reach the body region 8 (the source contact layer 16 is typically held at a reference voltage potential, e.g., ground GND).

[0043] Figure 2 An improved edge termination arrangement 22 of a power semiconductor device 1 according to one aspect of the present solution is shown.

[0044] An edge termination arrangement 22 is formed in the edge region 28 of the power semiconductor device 1, located around the die 20'. The edge termination arrangement surrounds the active region (referred to here as 26), where the active cell 5 is formed.

[0045] Figure 2 Only one active unit 5 is shown, which is the one closest to the edge region 28; as described Figure 2In a manner not shown, the power semiconductor device 1 includes a plurality of charge-balancing deep trenches in the active region 26. These deep trenches are formed in the epitaxial layer 27 and extend to the substrate 29, and include dielectric-filled regions and thin doped layers located at the sidewalls of the trenches (as shown above). Figure 1 (As discussed).

[0046] According to one aspect of this solution, the edge termination arrangement 22 includes a plurality of edge termination deep trenches 30 arranged in a regular pattern in the edge region 28. Each edge termination deep trench 30 traverses the epitaxial layer 27 and reaches the substrate 29 and includes a dielectric-filled region 31 and a thin doped layer (also indicated by 14) located at its sidewalls.

[0047] Edge termination arrangement 22 also includes electrical connection structure 34 ( Figure 2 (Schematably shown in the diagram), the electrical connection structure 34 is configured to electrically connect (i.e., short-circuit) the thin doped layers 14 at the sidewalls of each edge-terminating deep trench 30 together. Specifically, the first of these electrical connection structures 34 (closest to the active region 26) is connected to the source region and body region of the last active cell 5 in the active region 26 and connected to the source contact layer 16 (so that it is at a reference or ground potential); all other electrical connection structures 34 remain floating (i.e., not connected to any particular voltage potential).

[0048] like Figure 3 As schematically shown, the effect is that the potential in the edge region 28 of the power semiconductor device 1 gradually shifts from the reference potential (GND, 0V) to the drain-source voltage, for example, at 180-190V (each increasing voltage step corresponds to one of the electrical connection structures 34).

[0049] Above Figure 2 As not shown, the edge-terminated deep trench 30 has a ring-shaped structure surrounding the active region 26 of the power semiconductor device 1, with the radius increasing with distance from the active region 26. Furthermore, the electrical connection structures 34 may be discontinuous along the ring of the respective edge-terminated deep trench 30, but rather distributed regularly along the ring at a given separation distance (as will be disclosed in more detail below).

[0050] First refer to Figure 4A Now we will discuss a first embodiment of the process for manufacturing the power semiconductor device 1, with particular reference to the manufacturing of the edge termination arrangement 22 in the edge region 28 (simultaneously with the manufacturing of the active cell 5 in the active region 26).

[0051] Figure 4AA substrate 29 and an epitaxial layer 27 of a power semiconductor device 1 are shown, both located in the active region 26 and the edge region 28 of the power semiconductor device 1. In the following discussion, unless otherwise specified, the steps to be performed are intended to be performed simultaneously in both the active region 26 and the edge region 28 of the semiconductor device 1.

[0052] The first step of the manufacturing process envisions forming a shallow trench 40 starting from the top surface 27a of the epitaxial layer 27. For example, the trench has a width of 0.1 to 1 µm along a first axis x of the horizontal plane xy (parallel to the top surface 27a) and a depth of 0.5 to 2 µm in the vertical direction along a vertical axis z orthogonal to the horizontal plane xy. In the active region 26, the shallow trench 40 is designed to form a gate trench for the active cell 5 of the power semiconductor device 1.

[0053] like Figure 4B As shown, a thin dielectric layer 41 is formed, for example, by thermal oxidation on the top surface 27a and in the shallow trench 40 (coating its transverse walls and bottom).

[0054] Then, a polycrystalline silicon region 42 is formed within the shallow trench 40. Figure 4C Specifically, the polysilicon region 42 is separated from the epitaxial layer 27 by the dielectric layer 41.

[0055] like Figure 4D As shown, in the surface portion of the epitaxial layer 27, a doped layer 43 of the second doping type (p-type) is formed at its top surface 27a; in the active region 26, this doped layer 43 is designed to form the body region of the active cell 5 for the power semiconductor device 1.

[0056] Then, the manufacturing process is designed. Figure 4E The thin dielectric layer 41 is removed from the top surface 27a of the epitaxial layer 27, and then shallow doping is performed only in the active region 26 of the power semiconductor device 20 to form a shallow doped layer 44 having a first doping type (n-type); in the active region 26, this shallow doped layer 44 is designed to form the source region of the active cell 5 for the power semiconductor device 1.

[0057] after, Figure 4F The deep trenches are etched through the epitaxial layer 27 and reach the substrate 29, with each deep trench formed between a corresponding pair of shallow trenches 40. In particular, these deep trenches are designed to form a plurality of charge-balanced deep trenches 12 in the active region 26 and a plurality of edge-terminated deep trenches 30 in the edge region 28.

[0058] Subsequently, as described Figure 4FAs shown, the sidewalls of the deep trench are doped to form a thin doped layer (also denoted as 14) having a second doping type (p-type). In particular, these thin doped layers 14 are continuous with and in contact with the doped regions 43' of the previously formed doped layer 43 (also having a second doping type).

[0059] Then, the manufacturing process continues. Figure 4G The deep trench 46 is filled with a dielectric filling region 47 (e.g., silicon oxide). This step also results in the formation of a dielectric layer 48 on the top surface 27a of the epitaxial layer 27.

[0060] like Figure 4H As shown, contact openings 49 are then opened through the dielectric layer 48 and the underlying doped region 43' (and the shallow doped layer 44 in the active region 26). Specifically, a pair of contact openings 49 are formed on the side of each shallow trench 40, the pair of contact openings being separated from the corresponding thin dielectric layer 41 by a certain distance.

[0061] like Figure 4I As shown, the contact opening 49 is then filled with a conductive material (e.g., tungsten) to form a contact (or "plug") 50 within the contact opening 49.

[0062] Then a thin barrier layer 52 of a conductive material, such as TiN, is deposited on the dielectric layer 48. Figure 4J As shown, the thin barrier layer contacts the contact 50 from above.

[0063] The barrier layer 52 is continuous in the active region 26.

[0064] According to a specific aspect of this solution, the barrier layer 52 is patterned in the edge region 28 to define barrier portions 54, which are configured to electrically connect in pairs to the thin doped layers 14 of the corresponding edge-terminating deep trenches 30. Specifically, each barrier portion 54 contacts a pair of contacts 50 disposed above on the side of the corresponding edge-terminating deep trench 30 and reaching the doped region 43' of the doped layer 43; thus, these barrier portions 54, together with the corresponding contacts 50, define the above-described electrical connection structure 34 of the edge-terminating arrangement 22.

[0065] like Figure 4K As shown, the manufacturing process then continues to form a thick top metal layer 56 separately on the barrier layer 52 in the active region 26 to define the source contact layer of the power semiconductor device 1.

[0066] As discussed above, in a possible embodiment of the edge termination arrangement 22, the contact structure 34 is not continuous along the ring surrounding the active region 26.

[0067] in this regard, Figure 5A top view of the edge portion of the power semiconductor device 1 is shown, wherein the electrical connection structure 34 is not continuous along the extension direction of the corresponding edge-terminating deep trench 30, but rather along the extension direction (in Figure 5 In the middle, along the second axis y of the horizontal plane xy, it is regularly distributed with a given separation distance.

[0068] Specifically, the blocking portion 54 of the electrical connection structure 34 has a much smaller longitudinal extension than the corresponding edge-terminating deep trench 30, and is arranged at a certain separation distance along the extension direction of the edge-terminating deep trench 30 (in Figure 5 In the example, the blocking portion 54 has a substantially rectangular shape in the horizontal plane xy).

[0069] The contact 50 coupled to the corresponding blocking portion 54 also has substantially the same longitudinal extension as the blocking portion 54.

[0070] In this case, the electrical continuity between the electrical connection structures 34 is guaranteed by the underlying doped region 43', which is continuous along the ring surrounding the active region 26.

[0071] Furthermore, in the illustrated embodiment, the blocking portions 54 associated with adjacent edge-terminating deep trenches 30 are staggered in the aforementioned extending direction, causing the electrical connection structures 34 of adjacent edge-terminating deep trenches 30 to be misaligned (in... Figure 5 In the middle, along the first axis x of the horizontal plane xy). Figure 5 In the embodiment shown, the blocking portion 54 of any given edge-terminating deep trench 30 and the next non-adjacent edge-terminating deep trench 30 is instead aligned along the first axis x.

[0072] This embodiment of the electrical connection structure 34 can be particularly advantageous in all cases where a reduction in the width of the edge-terminating deep trench 30 may cause problems when manufacturing the contact 50 transverse to the trench.

[0073] According to yet another embodiment of this solution, reference is now made to... Figure 6A and Figure 6B In this embodiment, the electrical connection structure 34 in the edge region 28 is also electrically connected (short-circuited) to the polysilicon regions 42 formed within the shallow trench 40, such that these polysilicon regions 42 also remain floating and are at the same voltage potential as the corresponding electrical connection structure 34. This solution can be advantageous, allowing for further improvement in control of the confinement of electric field lines in the edge region 28.

[0074] In this respect, additional contacts (denoted as 50') are thus formed through the dielectric layer 48 to reach the polysilicon region 42 of the corresponding bottom shallow trench 40; and in addition to the contacts 50 defined above, the blocking portion 54 of the electrical connection structure 34 is configured to electrically contact the corresponding contacts among these additional contacts 50'.

[0075] In particular, Figure 6A and Figure 6B In the embodiment shown, additional contacts 50' are arranged locally at the corner areas of the corresponding blocking portions 54. As described... Figure 6A and Figure 6B As shown, a localized enlargement of the shallow groove 40 can be provided in the corner region to accommodate additional contact 50'.

[0076] First refer to Figure 7A Now we will discuss a second embodiment of the edge termination arrangement 22 of the power semiconductor device 1, which differs from the embodiment discussed above because there is no shallow trench 40 in the edge region 28.

[0077] In fact, such as Figure 7A As shown, the first step of the manufacturing process envisions forming shallow trenches 40 only in the active region 26, wherein the shallow trenches 40 are designed to form gate trenches for the active cells 5 of the power semiconductor device 1; while no shallow trenches are formed in the edge region 28.

[0078] like Figure 7B As shown, a thin dielectric layer 41 is then formed, for example, by thermal oxidation on the top surface 27a of the epitaxial layer 27 and in the shallow trenches 40 in the active region 26 (coating their lateral walls and bottom).

[0079] Subsequently, a doped polysilicon region 42 is formed within the shallow trench 40 in the active region 26. Figure 7C .

[0080] like Figure 7D As shown, a second doping type (p-type) doped layer 43 is then formed on the surface portion of the epitaxial layer 27 at its top surface 27a to form a body region of the active cell 5 for the power semiconductor device 1 in the active region 26.

[0081] Specifically, the doped layer 43 is appropriately patterned in the edge region 28 so as not to exist in the separation portion 27' of the epitaxial layer 27; in other words, the doped layer 43 has corresponding doped regions 43' in the edge region 28, which are separated in the horizontal plane by the separation portion 27' of the epitaxial layer 27.

[0082] The manufacturing process is then envisioned. Figure 7EFirst, the thin dielectric layer 41 is removed from the top surface 27a of the epitaxial layer 27, and then shallow doping is performed only in the active region 26 of the power semiconductor device 1 to form a shallow doped layer 44 with a first doping type (n-type) to form the source region for the active cell 5.

[0083] after, Figure 7F Deep trenches are etched through the epitaxial layer 27 and reach the substrate 29. In the active region 26, each resulting charge-balanced deep trench 12 is formed between a corresponding pair of shallow trenches 40; in the edge region 28, the resulting edge-terminating deep trench 30 is formed at the doped region 43' of the doped layer 43.

[0084] Subsequently, the sidewalls of the deep trench 46 are doped to form a thin doped layer 14, as described above. Figure 7F As shown in the diagram. In particular, the thin doped layer 14 of each edge-terminating deep trench 30 is continuous with the corresponding doped region 43' of the doped layer 43.

[0085] Then, the manufacturing process continues. Figure 7G The deep trench 46 is filled with dielectric filling region 47, and a dielectric layer 48 is formed on the top surface 27a of the epitaxial layer 27.

[0086] like Figure 7H As shown, contact openings 49 are then opened through the dielectric layer 48 and the underlying doped layer 43 (and the shallow doped layer 44 in the active region 26). Specifically, in the active region 26, a pair of contact openings 49 are formed on the side of each shallow trench 40; in the edge region 28, instead, a pair of contact openings 49 are formed on the side of the corresponding separation portion 27' of the epitaxial layer 27, reaching the corresponding doped region 43' of the doped layer 43.

[0087] like Figure 7I As shown, the contact opening 49 is then filled with a conductive material, such as tungsten, to form a contact (or "plug") 50.

[0088] Then a thin barrier layer 52 made of a conductive material such as TiN is deposited on the dielectric layer 48, such as... Figure 7J As shown, the thin barrier layer contacts the contact 50 from above.

[0089] The barrier layer 52 is continuous in the active region 26. As discussed above, the barrier layer 52 is patterned in the edge region 28 to define a barrier portion 54, which is configured to electrically connect the thin doped layer 14 at the sidewalls of each adjacent edge-terminating deep trench 30. In particular, each barrier portion 54 contacts from above a pair of contacts 50 disposed on the sidewalls of the corresponding edge-terminating deep trench 30; thus, these barrier portions 54, together with the corresponding contacts 50, define the electrical connection structure 34 of the edge-terminating arrangement 22 discussed above.

[0090] like Figure 7K As shown, the manufacturing process then continues, forming a thick top metal layer 56 separately on the barrier layer 52 in the active region 26 to define the source contact layer 16 of the power semiconductor device 1.

[0091] The advantage of this embodiment is that it eliminates the need to form shallow trenches in the edge region 28. However, by arranging polysilicon-filled shallow trenches 40 between the contacts 50, the previously discussed embodiments allow for better confinement of electric field lines in the edge region 28.

[0092] Moreover, in this embodiment, such as Figure 8 As shown in the figure (which relates to the edge portion of the power semiconductor device 1), the electrical connection structure 34 may be discontinuous along the extension direction of the corresponding edge terminating the deep trench 30, but rather along the extension direction (in Figure 8 In the middle, along the second axis y), it is regularly distributed with a given separation distance.

[0093] In this case, the blocking portion 54 of the connecting structure 34 is continuous along the extending direction; instead, the contact element 50 (in this example, having a substantially rectangular shape in the horizontal plane xy) is arranged in a localized manner along the extending direction (in Figure 8 In the middle, along the second axis y) are arranged at a certain separation distance.

[0094] Furthermore, the contacts 50 are staggered in the extending direction, causing the contacts 50 of adjacent edge-terminating deep grooves 30 to be misaligned (in Figure 8 In the middle, along the first axis x of the horizontal plane xy). Figure 8 In the embodiment shown, the contacts 50 of any given edge-terminating deep trench 30 and the next non-adjacent edge-terminating deep trench 30 are instead aligned along the first axis x.

[0095] First refer to Figure 9AWe will now discuss a third embodiment of the edge termination arrangement 22 of the power semiconductor device 1, which envisions forming the electrical connection structure 34 of the edge termination arrangement 22 using a self-alignment process. This process will be discussed with particular reference to the formation of the edge termination arrangement 22 in the edge region 28 (the formation of the active cell 5 in the active region 26 will not be disclosed).

[0096] like Figure 9A As shown, the process first forms a thin dielectric layer (also indicated by 41) on the top surface 27a of the epitaxial layer 27, and in this case, a thin passivation layer 60, such as a nitride, is formed on the thin dielectric layer 41.

[0097] Then, deep trenches are etched through the epitaxial layer 27 (and the thin dielectric layer 41 and passivation layer 60) and reach the substrate 29 (not shown here) to form edge-terminated deep trenches 30 in the edge region 28. The sidewalls of the edge-terminated deep trenches 30 are doped to form a thin doped layer 14.

[0098] Subsequently, the edge termination deep trench 30 is filled with dielectric filling region 47, and a dielectric layer 48 is also formed on the top surface 27a of the epitaxial layer 27.

[0099] like Figure 9B As shown, a planarization step is then performed (e.g., CMP - chemical mechanical polishing), which results in the removal of a portion of the dielectric layer 48 above the thin passivation layer 60.

[0100] after, Figure 9C The surface portion of the dielectric-filled region 47 is etched, resulting in the formation of contact holes 62 at the top of each edge-terminating deep trench 30 on the top surface 27a of the epitaxial layer 27. As described Figure 9C As shown, the etching also results in the removal of a portion of the thin dielectric layer 41 beneath the thin passivation layer 60 in the horizontal plane xy relative to the contact hole 62.

[0101] Then, as Figure 9D As shown, a polysilicon deposition step is performed, in which the polysilicon is doped with a second doping type (p-type), resulting in the formation of a polysilicon layer 64 on the thin passivation layer 60 and within the contact hole 62 at the top of the edge-terminating deep trench 30.

[0102] like Figure 9E As shown, the polysilicon layer 64 is then recessed (e.g., using CMP technology) to the level of the thin passivation layer 60, leaving only the bridging portion 64' of the polysilicon layer 64, filling the corresponding contact holes 62, thereby closing the corresponding edge termination deep trench 30 at the top.

[0103] These bridging portions 64' here constitute an electrical connection between the thin doped layers 14 of the corresponding edge-terminating deep trenches 30.

[0104] Then remove the thin passivation layer 60, such as Figure 9F As shown, a thick dielectric layer (again denoted by 48) is formed above the top surface 27a of the epitaxial layer 27 and on the bridging portion 64', as... Figure 9G As shown in the image.

[0105] According to one aspect of this solution, an annealing step (e.g., RTA, rapid thermal annealing) is then performed, such as... Figure 9H As shown, this causes the dopant to diffuse laterally from the doped polysilicon of the bridging portion 64', resulting in the formation of a doped region 68 in the epitaxial layer 27, which contacts the bridging portion 64' and the thin doped layer 14 at the sidewall of the edge-terminating deep trench 30.

[0106] Therefore, in this embodiment, the bridging portion 64' and the doped region 68 define the electrical connection structure 34 of the edge termination arrangement 22 discussed above.

[0107] Advantageously, in this case, the electrical connection structure 34 is obtained in a self-aligned manner with respect to the thin doped layer 14 at the sidewall of the edge-terminated deep trench 30, thus having a simplified process flow.

[0108] The advantages of the proposed solution are clear from the preceding description.

[0109] The disclosed solution provides an edge-termination arrangement for power semiconductor devices, particularly charge-balanced superjunction types, wherein a charge-balanced deep trench with a thin doped layer at its sidewalls in the edge region allows for a corresponding narrow and heavily doped n-type epitaxial drift region, which improves the tradeoff between on-resistance and breakdown voltage.

[0110] In particular, these thin doped layers are short-circuited by appropriate interconnect structures to keep the charge-balanced deep trenches at a floating potential, thereby allowing potential distribution at the edge regions and preventing equipotential lines from escaping near the surface of the epitaxial layer.

[0111] Finally, it is clear that modifications and changes may be made to the content described and illustrated herein without departing from the scope of this disclosure as defined in the appended claims.

[0112] In particular, it should be emphasized that the solutions discussed can be applied to different types of power semiconductor devices, such as power diodes or JFETs.

[0113] Furthermore, it is conceivable not to provide an electrical connection structure 34 for the last edge-terminating deep trench 30 (i.e., the trench furthest from the active region 26), because this last deep trench can withstand a certain amount of potential drop, while reducing the impact on the termination balance.

[0114] According to one aspect of this disclosure, a process for manufacturing a superjunction power semiconductor device is provided, comprising: forming an active region having active cells and an edge region surrounding the active region at the periphery of the die in a die of semiconductor material having a substrate and a structural layer of a first doping type thereon; forming the active region comprising forming a plurality of charge-balanced deep trenches filled with a dielectric, the plurality of charge-balanced deep trenches extending through the structural layer and reaching the substrate between corresponding pairs of active cells, each charge-balanced deep trench having a doped layer of a second doping type at its sidewall; forming an edge termination arrangement having a plurality of edge-terminating trenches extending through the structural layer and reaching the substrate at the edge region, the plurality of edge-terminating trenches being filled with a dielectric material and having a corresponding doped layer of a second doping type at its sidewall; and wherein forming the edge termination arrangement comprises forming an electrical connection structure configured to electrically connect the corresponding doped layers at the sidewalls of the plurality of edge-terminating trenches together.

[0115] In one embodiment, forming the electrical connection structure includes forming bridging conductive portions, each bridging conductive portion being disposed above and across a corresponding edge termination trench, and electrically short-circuiting the corresponding doped layer.

[0116] In one embodiment, the process for manufacturing a superjunction power semiconductor device further includes: forming a dielectric layer on the top surface of the structural layer; and wherein forming the electrical connection structure includes forming: a pair of contacts disposed at one or more sides of a corresponding edge-terminating trench, traversing the dielectric layer and designed to electrically contact a corresponding doped layer of the corresponding edge-terminating trench; and a blocking portion disposed on the dielectric layer and contacting the pair of contacts from above.

[0117] In one embodiment, the process for manufacturing a superjunction power semiconductor device further includes: forming shallow trenches in the structural layer at a top surface of the structural layer prior to forming the plurality of edge-terminating trenches, the shallow trenches including polysilicon regions separated from the epitaxial layer by a dielectric layer; forming a doped layer in a surface portion of the epitaxial layer at the top surface; and wherein forming the electrical connection structure includes: forming a pair of contact openings through the dielectric layer and the underlying doped layer at one or more sides of each shallow trench; filling the contact openings with a conductive material to form the pair of contacts; and patterning a barrier layer of conductive material deposited on the dielectric layer to define the barrier portion.

[0118] In one embodiment, forming the electrical connection structure further includes: forming additional contacts traversing the dielectric layer to electrically contact the polysilicon region of the corresponding shallow trench; and wherein the blocking portion of the electrical connection structure is configured to also contact the corresponding additional contacts from above.

[0119] In one embodiment, the process for manufacturing a superjunction power semiconductor device further includes: patterning a doped layer in a surface portion of an epitaxial layer at the top surface before forming the plurality of edge-terminating trenches to define doped regions separated by separation portions of the epitaxial layer; wherein the plurality of edge-terminating trenches are formed at the doped regions of the doped layer; and wherein forming the electrical connection structure includes: forming a pair of contact openings at one or more sides of the respective separation portions of the epitaxial layer, the pair of contact openings reaching the respective doped regions of the doped layer; filling the contact openings with a conductive material to define the pair of contacts; and patterning a barrier layer of conductive material deposited on the dielectric layer to define the barrier portions.

[0120] In one embodiment, forming the electrical connection structure includes: forming a contact hole at the top surface of the epitaxial layer on top of the plurality of edge-terminating trenches; depositing and patterning a doped polysilicon layer to form a bridging portion within the contact hole that closes the plurality of edge-terminating trenches at the top; and performing an annealing step to cause dopant to diffuse laterally from the doped polysilicon layer of the bridging portion and form a doped region in the structural layer, the doped region contacting the bridging portion and contacting one or more thin doped layers at the sidewalls of the respective edge-terminating trenches in the plurality of edge-terminating trenches.

Claims

1. A superjunction power semiconductor device, characterized in that, The superjunction power semiconductor device has a die made of semiconductor material, the die comprising a substrate and a structural layer formed on the substrate and having a first doping type. The die has an active region forming active cells and an edge region surrounding the active region at the periphery of the die. The active region includes a plurality of charge-balanced deep trenches filled with a dielectric material. These charge-balanced deep trenches extend through the structural layer and reach the substrate between corresponding pairs of active cells. Each charge-balanced deep trench has a doped layer of a second doping type on its sidewalls. The superjunction power semiconductor device further includes an edge termination arrangement located at the edge region, the edge termination arrangement including a plurality of edge termination trenches extending through the structural layer and reaching the substrate, being filled with a dielectric and having a corresponding doped layer of a second doping type at its sidewalls; The edge termination arrangement includes an electrical connection structure configured to electrically connect the corresponding doped layers at the sidewalls of the plurality of edge termination trenches together.

2. The superjunction power semiconductor device according to claim 1, characterized in that, The first electrical connection structure closest to the active region is electrically connected to the last active unit in the active region, and all other electrical connection structures are at a floating potential.

3. The superjunction power semiconductor device according to claim 1, characterized in that, The electrical connection structure includes corresponding bridging conductive portions, each bridging conductive portion being disposed above and across the corresponding edge termination trench, and electrically short-circuiting the corresponding doped layer at the sidewall of the corresponding edge termination trench.

4. The superjunction power semiconductor device according to claim 1, characterized in that, Includes a dielectric layer located on the top surface of the structural layer; Each of the electrical connection structures includes: a pair of contacts arranged at one or more sides of a corresponding edge-terminating trench, traversing the dielectric layer and designed to electrically contact the corresponding doped layer; And a blocking portion, which is disposed on the dielectric layer and contacts the pair of contacts from above.

5. The superjunction power semiconductor device according to claim 4, characterized in that, The edge termination arrangement includes a doped region located on the top surface of the structural layer and having the same doping type as the doped layer, the doped region being arranged laterally to the plurality of edge termination trenches to contact the corresponding doped layer; The pair of contacts are configured to reach the doped regions in the structural layer.

6. The superjunction power semiconductor device according to claim 5, characterized in that, The edge termination arrangement includes a shallow trench located on the top surface of the structural layer, the shallow trench being arranged between the pair of contacts and including a polysilicon region separated from the doped region by a dielectric layer.

7. The superjunction power semiconductor device according to claim 6, characterized in that, The electrical connection structure further includes: additional contacts that traverse the dielectric layer and are configured to electrically contact the polysilicon region of the corresponding shallow trench; wherein the blocking portion of the electrical connection structure is configured to also contact the corresponding additional contacts from above.

8. The superjunction power semiconductor device according to claim 5, characterized in that, The doped region is separated by a separation portion of the epitaxial layer disposed between the pair of contacts.

9. The superjunction power semiconductor device according to claim 1, characterized in that, The electrical connection structure includes a conductive bridging portion disposed on the top surface of the structural layer and having a corresponding edge-terminating trench closed at the top. And the doped regions in the structural layer, the doped regions being in contact with the bridging portion and with one or more thin doped layers at the sidewalls of the corresponding edge-terminating trench.

10. The superjunction power semiconductor device according to claim 1, characterized in that, The electrical connection structures are discontinuous along the extension direction of the corresponding edge-terminating trenches, but are instead regularly distributed along the extension direction at a given separation distance.

11. The superjunction power semiconductor device according to claim 1, characterized in that, The superjunction power semiconductor device is a trench-gate power MOSFET device.

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