Trench capacitor structure and semiconductor device

Abstract

The utility model provides a semiconductor device comprising a trench capacitor structure and a forming method thereof. Using a multi-electrode connection including the use of conductive sidewall layers, the interconnect structure may be connected with a plurality of vertically arranged electrode layers of the trench capacitor structure. The connection of a plurality of vertically arranged electrode layers can increase the effective thickness of the connection pad for the interconnect structure compared to the connection using a single electrode layer. The increased effective thickness can reduce the likelihood that vertical interconnect access is generated in the metal structure of the trench capacitor structure to induce metal island corrosion defects.

Description

Technical Field

[0001] This utility model relates to a trench capacitor structure and a semiconductor device. Background Technology

[0002] Semiconductor devices may include trench capacitor regions, comprising a multilayer structure of conductive material layers dispersed with dielectric material layers conforming to the sidewalls of trenches perpendicularly extending into the semiconductor substrate. Trench capacitor regions can increase the capacitance of the semiconductor device while preserving area for integrated device structures within the semiconductor device. Utility Model Content

[0003] This utility model provides a structure. The structure includes a first conductive layer. The structure includes a dielectric layer on the first conductive layer. The structure includes a second conductive layer on the dielectric layer, the second conductive layer having a gap region above a portion of the first conductive layer. The structure includes a third conductive layer, the third conductive layer including a portion of the gap region. The structure includes an interconnect structure that passes through the portion of the third conductive layer in the gap region, passes through the dielectric layer, and enters the first conductive layer. The structure includes a sidewall layer surrounding the interconnect structure, passing through the portion of the third conductive layer in the gap region, passing through the dielectric layer, and entering the first conductive layer.

[0004] This invention provides a semiconductor device. The semiconductor device includes a metallization layer comprising a first portion and a second portion. The semiconductor device includes a trench capacitor structure comprising at least two vertically arranged positive capacitor electrode layers and at least two vertically arranged negative capacitor electrode layers. The semiconductor device includes a first interconnect structure connecting the at least two vertically arranged positive capacitor electrode layers to the first portion. The semiconductor device includes a second interconnect structure connecting the at least two vertically arranged negative capacitor electrode layers to the second portion. Attached Figure Description

[0005] The best understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0006] Figure 1 This is a diagram of an example environment in which the systems and / or methods described in this paper can be implemented.

[0007] Figure 2A and Figure 2B This is a diagram of an example semiconductor die package that includes the trench capacitor structure described herein.

[0008] Figure 3This is a diagram of an example embodiment of the trench capacitor structure described herein.

[0009] Figures 4A to 4G This is a diagram illustrating an example embodiment of the trench capacitor structure described herein.

[0010] Figures 5A to 5D This is a diagram illustrating an example embodiment of the semiconductor die described herein.

[0011] Figures 6A to 6E This is a diagram illustrating an example embodiment of the semiconductor die described herein.

[0012] Figures 7A to 7G This is a diagram of an example embodiment that forms part of the semiconductor die package described herein.

[0013] Figure 8A and Figure 8B This is a graph of data related to the corrosion defects of metal islands induced by accessing vertical interconnects as described in this article.

[0014] Figure 9 This is a diagram of an example component of the device described in this article.

[0015] Figure 10 This is a flowchart of an example process associated with forming the trench capacitor structure described in this article. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate any relationship between the various embodiments or configurations discussed.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," or similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly.

[0018] Performance improvements of trench capacitor structures (e.g., increased charge storage capacity, increased charge storage duration) can be achieved by increasing the density of the capacitor electrode layers (e.g., conductive material layers) and capacitor dielectric layers (e.g., dielectric material layers) to form the trench capacitor structure. Increasing the density may include increasing the number of capacitor electrode layers and / or capacitor dielectric layers in a given region of a semiconductor device including the trench capacitor structure.

[0019] In some cases, increasing the density of trench capacitor structures may exceed the spacing limitations of the interconnect structures connected to the capacitor electrode layers (e.g., the processing capabilities of developing and / or etching tools). Exceeding these spacing limitations may lead to an increase in the size of the semiconductor device including the trench capacitor structure. Alternatively, in some cases, increasing the density of trench capacitor structures may reduce the thickness of the capacitor electrode layers, resulting in a reduction in the process margin for cleaning operations used to form the trench capacitor structure. A reduced process margin may increase the likelihood of vertical interconnect access induced metalisland corrosion (VIMIC) defects forming in the metal structures contained within the trench capacitor structure. The increased likelihood of VIMIC defects may reduce the manufacturing yield and / or reliability of the semiconductor device.

[0020] Some embodiments described herein provide a semiconductor device including a trench capacitor structure and a method for forming the same. Using multi-electrode connections including conductive sidewall layers, the interconnect structure can be connected to multiple vertically aligned electrode layers of the trench capacitor structure. Using multiple vertically aligned electrode layers increases the effective thickness of the connection pads for the interconnect structure compared to connections using a single electrode layer. This increased effective thickness increases etching and cleaning process margins, reducing the likelihood of VIMIC defects in the metal structure of the trench capacitor structure.

[0021] In this way, the performance of the trench capacitor structure (e.g., charge storage capacity and / or charge storage duration) is increased, while improving the quality and / or reliability of the semiconductor device. Additionally, reducing the number of interconnect structures within the trench capacitor structure reduces its size (and thus the size of the semiconductor device). By improving the performance of the trench capacitor structure, increasing the yield and / or reliability of the semiconductor device, or reducing the size of the semiconductor device, the amount of resources used to support the market consuming semiconductor devices can be reduced (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources can be decreased).

[0022] Figure 1 This is a diagram of an example environment 100 in which the systems and / or methods described herein can be implemented. (See diagram 100 for example environment 100.) Figure 1 As shown, example environment 100 may include multiple semiconductor processing tools 102-114 and wafer / die transfer tools 116. The multiple semiconductor processing tools 102-112 may include deposition tools 102, exposure tools 104, developing tools 106, etching tools 108, planarization tools 110, electroplating tools 112, bonding tools 114, and / or other types of semiconductor processing tools. Among other examples, the tools included in example environment 100 may be located in semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities, and / or manufacturing facilities.

[0023] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin-coating tool capable of depositing a photoresist layer on a substrate such as a chip. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a subatmospheric pressure CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, deposition tool 102 includes an epitaxial tool configured to form layers and / or regions through an epitaxial growth apparatus. In some embodiments, example environment 100 includes multiple types of deposition tools 102.

[0024] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep ultraviolet (EUV) source, an extreme ultraviolet (EUV) source, and / or the like), an X-ray source, an electron beam source, and / or the like. Exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, and so on. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0025] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source, thereby developing a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the photoresist layer. The pattern is formed by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0026] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, chips, or semiconductor devices. For example, etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific time period to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to etch the one or more portions in the same or directional manner.

[0027] Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing the layers of a chip or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing layers or surfaces of deposited or electroplated material. Planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free-grinding polishing) to polish or planarize the surface of the semiconductor device. Planarization tool 110 may be used in conjunction with a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device) using abrasives and corrosive chemical slurries. The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and plan any irregularities in the topography of the semiconductor device, making the semiconductor device flat or planar.

[0028] Electroplating tool 112 is a semiconductor processing tool capable of electroplating substrates (e.g., chips, semiconductor devices, etc.) or portions thereof with one or more metals. For example, electroplating tool 112 may include copper electroplating apparatus, aluminum electroplating apparatus, nickel electroplating apparatus, tin electroplating apparatus, compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating apparatus, and / or electroplating apparatus for one or more other types of conductive materials, metals and / or similar types of materials.

[0029] Bonding tool 114 is a semiconductor processing tool capable of bonding two or more workpieces (e.g., two or more semiconductor substrates, two or more semiconductor devices, two or more semiconductor dies) together. For example, bonding tool 114 can be a direct bonding tool, which is a type of bonding tool configured to directly bond semiconductor dies together via a copper-to-copper (or other direct metal) connection. As another example, bonding tool 114 can include a eutectic bonding tool capable of forming a eutectic bond between two or more chips. In these examples, bonding tool 114 can heat two or more chips to form a eutectic system between the materials of the two or more chips.

[0030] Wafer / die transfer tool 116 includes a mobile robot, robotic arm, tram or railcar, overhead crane transport (OHT) system, automated material handling system (AMHS), and / or is configured to transfer substrates and / or semiconductor devices between semiconductor processing tools 102-114, configured to transfer substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or configured to transfer substrates and / or semiconductor devices to and from other locations, such as chip racks, storage chambers, etc. In some embodiments, wafer / die transfer tool 116 may be a programmed device configured to travel a specific path and / or capable of semi-autonomous or autonomous operation. In some embodiments, example environment 100 includes multiple wafer / die transfer tools 116.

[0031] For example, wafer / die transfer tool 116 may be included in a clustering tool or another type of tool comprising multiple processing chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple processing chambers, to transfer substrates and / or semiconductor devices between processing chambers and buffers, to transfer substrates and / or semiconductor devices between processing chambers and interface tools such as equipment front end modules (EFEMs), and / or to transfer substrates and / or semiconductor devices between processing chambers and transport carriers (e.g., front opening unified pods, FOUPs), etc. In some embodiments, wafer / die transfer tool 116 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidation and / or deposits), a deposition processing chamber (e.g., a processing chamber for depositing different types of materials, a processing chamber for performing different types of deposition operations). In these embodiments, the wafer / die transfer tool 116 is configured to transfer substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without disrupting or removing the processing chambers and / or the vacuum (or at least a partial vacuum) during processing operations in the deposition tool 102.

[0032] In some implementations, and as in combination Figures 2A to 10In more detail, one or more of semiconductor processing tools 102-114 and / or wafer / die transport tool 116 can be used to perform a series of semiconductor processing operations. This series of semiconductor processing operations includes forming a stack of trench capacitor structures on a substrate, the trench capacitor structures including a first capacitor electrode layer, a capacitor dielectric layer on the first capacitor electrode layer, and a second capacitor electrode layer above the first capacitor electrode layer. This series of semiconductor processing operations includes forming one or more dielectric layers above the stack. This series of semiconductor processing operations includes forming cavities through one or more dielectric layers, through the second capacitor electrode layer, through the capacitor dielectric layer, and into the first capacitor electrode layer. This series of semiconductor processing operations includes using the cavities to form multi-electrode connections.

[0033] Figure 1 The number and arrangement of the devices shown are provided as one or more examples. In practice, there may be more... Figure 1 The diagram shows more devices, fewer devices, different devices, or devices arranged differently. Furthermore, Figure 1 The two or more devices shown can be implemented in a single device, or within a single device. Figure 1 The apparatus shown can be implemented as multiple distributed apparatuses. Alternatively, a set of apparatuses (e.g., one or more apparatuses) of example environment 100 can be used to perform one or more functions described as being performed by another set of apparatuses of example environment 100.

[0034] Figure 2A and Figure 2B This is a diagram of an example semiconductor die package 200 incorporating the trench capacitor structure described herein. The semiconductor die package 200 includes examples of a wafer-on-wafer (WoW) semiconductor die package, a wafer-on-die semiconductor die package, a die-on-die semiconductor die package, or another type of semiconductor die package in which semiconductor dies are placed. These are either directly bonded and vertically aligned or stacked. Figure 2A A top view of a portion of a semiconductor die package 200 is shown, including the combination of Figure 2B The reference profile line AA used.

[0035] Multiple trench capacitor regions 204a-204n in the first semiconductor die 202. The trench capacitor regions 204a-204n may be arranged horizontally and may include various sizes and / or shapes to provide sufficient decoupling capacitance for the circuitry and semiconductor devices of the semiconductor die package 200.

[0036] like Figure 2B As shown (e.g., along) Figure 2A(A cross-sectional view of AA), the semiconductor die package 200 includes a first semiconductor die 202 and a second semiconductor die 206. In some embodiments, the semiconductor die package 200 includes additional semiconductor dies. The first semiconductor die 202 may include a SoC die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, and / or other types of SoC dies. Additionally and / or alternatively, the first semiconductor die 202 may include a memory chip, an input / output (I / O) chip, a pixel sensor chip, and / or another type of semiconductor die. The memory chip may include a static random access memory (SRAM) chip, a dynamic random access memory (DRAM) chip, a NAND chip, a high-bandwidth memory (HBM) chip, and / or other types of memory chips. The second semiconductor die 206 may include a semiconductor die of the same type as the first semiconductor die 202, or may include a semiconductor die of a different type.

[0037] The first semiconductor die 202 and the second semiconductor die 206 may be bonded together at a bonding interface 208 (e.g., direct bonding). In some embodiments, one or more layers may be included between the first semiconductor die 202 and the second semiconductor die 206. At the bonding interface 208, for example, one or more passivation layers, one or more bonding films, and / or one or more layers of another type.

[0038] The second semiconductor die 206 may include a device region 210 and an interconnect region 212 adjacent to and / or above the device region 210. In some embodiments, the second semiconductor die 206 may include additional regions. Similarly, the first semiconductor die 202 may include a device region 214 and an interconnect region 216 adjacent to and / or below the device region 214. In some embodiments, the first semiconductor die 202 may include additional regions. The first semiconductor die 202 and the second semiconductor die 206 may be joined at the interconnect regions 212 and 216. A joining interface 208 may be located on a first side of the interconnect region 216 facing the interconnect region 212 and corresponding to a first side of the second semiconductor die 206.

[0039] Device regions 210 and 214 may each include a semiconductor substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or other types of semiconductor substrates. Device region 210 of the second semiconductor die 206 may include one or more semiconductor devices 218 contained within the semiconductor substrate of device region 210. Semiconductor devices 218 may include one or more transistors (e.g., planar transistors, FinFETs), nanosheet transistors (e.g., gate-around-ahead (GAA) transistors), memory cells, capacitors, inductors, resistors, pixel sensors, circuitry (e.g., integrated circuits (ICs)), and / or other types of semiconductor devices. In some embodiments, device region 210 includes logic circuitry.

[0040] like Figure 2B As further shown, the device region 214 of the first semiconductor die 202 (e.g., an IC device) may include the semiconductor substrate of the device region 214 (e.g., in...). Figure 2A A trench capacitor structure 220 is formed within the trench capacitor region 204b. The depth of the trench capacitor structure 220 can be selected to provide sufficient capacitance to meet the circuit decoupling parameters of the semiconductor device 218 included in the circuitry of the semiconductor die package 200, while reducing the likelihood of warping, breakage, and / or cracking of the semiconductor die package 200. Some circuits in the semiconductor die package 200 may have larger decoupling capacitance requirements than others in order to operate correctly at the desired performance parameters. Therefore, a deeper trench capacitor structure can be formed for these circuits relative to the depth of the trench capacitor structure formed for other circuits with smaller decoupling capacitance requirements. This achieves a balance between meeting the capacitance requirements in the semiconductor die package 200.

[0041] In some embodiments, interconnect regions 212 and 216 are referred to as back-end line online (BEOL) regions. Interconnect region 212 may include one or more dielectric layers 222, which may include silicon nitride (SiNx), oxides (e.g., silicon oxide (SiOx) and / or another oxide material), low-k dielectric materials, and / or another type of dielectric material. In some embodiments, one or more etch stop layers (ESLs) may be included between the layers of dielectric layer 222. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and / or silicon oxide (SiOx), etc.

[0042] The interconnect region 212 may also include one or more metallization layers 224 in the dielectric layer 222. The semiconductor device 218 in the device region 210 may be electrically and / or physically connected to one or more metallization layers 224. The metallization layer 224 may include wires, trenches, vias, pillars, interconnects, and / or another type of metallization layer. Contacts 226 may be included in the dielectric layer 222 of the interconnect region 212. Contacts 226 may be electrically and / or physically connected to one or more of the metallization layers 224. Contacts 226 may include conductive terminals, conductive pads, conductive pillars, under-bump metallization (UBM) structures, and / or another type of contact. The metallization layer 224 and contact 226 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0043] Interconnect region 216 may include one or more dielectric layers 228, which may include silicon nitride (SiNx), oxides (e.g., silicon oxide (SiOx) and / or another oxide material), low-k dielectric materials, undoped silicate glass (USG), and / or another type of dielectric material. In some embodiments, one or more etch stop layers (ESLs) may be included between the layers of dielectric layer 228. The one or more ESLs may include aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), silicon oxynitride (SiOxNy), aluminum oxynitride (AlON), and / or silicon oxide (SiOx), etc.

[0044] The interconnect region 216 may also include one or more metallization layers 230 in the dielectric layer 228. The trench capacitor structures 220a-220c in the device region 214 may be electrically and / or physically connected to one or more of the metallization layers 230. The metallization layer 230 may include wires, trenches, vias, pillars, interconnects, and / or another type of metallization layer. Contacts 232 may be included in the dielectric layer 228 of the interconnect region 216. Contacts 232 may be electrically and / or physically connected to one or more of the metallization layers 230. Contacts 232 may be electrically and / or physically connected to contacts 226 of the second semiconductor die 206. Contacts 232 may include conductive terminals, conductive pads, conductive pillars, UBM structures, and / or another type of contact. The metallization layer 230 and the contact 232 may each include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0045] Interconnect region 216 may include one or more interconnect structures 234. Interconnect structures 234 (e.g., vertical interconnect structures or vias) may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another conductive material. Interconnect structures 234 may provide electrical connections between one or more metallization layers 230. Alternatively or concurrently, interconnect structures 234 may connect trench capacitor structures 220 to the metallization layers of one or more metallization layers.

[0046] like Figure 2B As further shown, the semiconductor die package 200 may include a redistribution structure 236. The redistribution structure 236 may include a redistribution layer (RDL) structure, an interposer, a silicon-based interposer, a polymer-based interposer, and / or another type of redistribution structure. The redistribution structure 236 may be configured to fan out and / or connect signals and I / O of the semiconductor dies 202 and 206.

[0047] The redistribution circuit structure 236 may include one or more dielectric layers 238 and a plurality of metallization layers 240 disposed in the one or more dielectric layers 238. The dielectric layer 238 may include polybenzoxazole (PBO), polyimide, low-temperature polyimide (LTPI), epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), one or more dielectric layers, and / or another suitable dielectric material.

[0048] The metallization layer 240 of the redistributed circuit structure 236 may include one or more materials, such as gold (Au), copper (Cu), silver (Ag), nickel (Ni), tin (Sn), and / or palladium (Pd). The metallization layer 240 of the redistributed circuit structure 236 may include metal lines, vias, interconnects, and / or another type of metallization layer.

[0049] like Figure 2B As further shown, the semiconductor die package 200 may include one or more back-side through-silicon via (BTSV) structures 242 that pass through device region 214 and enter a portion of interconnect region 216 of the first semiconductor die 202. The BTSV structure 242 includes vertically elongated conductive structures (e.g., conductive pillars, conductive vias) that can electrically connect one or more metallization layers 230 in interconnect region 216 of the first semiconductor die 202 to one or more metallization layers 240 located in redistribution wiring structure 236. The BTSV structure 242 may be referred to as a through-silicon via (TSV) structure because the BTSV structure 242 extends completely through the semiconductor substrate (e.g., silicon substrate) of device region 214, as opposed to extending completely through a dielectric or insulating layer. The BTSV structure 242 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0050] An under-bump metallization (UBM) layer 244 may be included on the top surface of one or more dielectric layers 238. The UBM layer 244 may be electrically and / or physically connected to one or more metallization layers 240 in the redistribution wiring structure 236. The UBM layer 244 may be included in a recess in the top surface of one or more dielectric layers 238. The UBM layer 244 may include one or more conductive materials, such as copper (Cu), gold (Au), silver (Ag), nickel (Ni), tin (Sn), ruthenium (Ru), cobalt (Co), tungsten (W), titanium (Ti), one or more metals, one or more conductive ceramics, and / or another type of conductive material.

[0051] like Figure 2BAs further shown, the semiconductor die package 200 may include conductive terminals 246. Conductive terminals 246 may be electrically and / or physically connected to a UBM layer 244. The UBM layer 244 may be included to facilitate attachment to one or more metallization layers 240 in the redistribution structure 236, and / or to provide increased structural rigidity to the conductive terminals 246 (e.g., by increasing the surface area to which the conductive terminals 246 are connected). Conductive terminals 246 may include ball gate array (BGA) balls, pad gate array (LGA) pads, pin gate array (PGA) pins, and / or other types of conductive terminals. Conductive terminals 246 may enable the semiconductor die package 200 to be mounted to interposers or redistribution structures of circuit boards, sockets (e.g., LGA sockets), semiconductor device packages (e.g., chip-on-wafer-on-substrate (CoWoS) packages, integrated fan-out (InFO) packages, and / or other types of mounting structures).

[0052] As mentioned above, Figure 2A and Figure 2B This is provided as an example. Other examples may be provided in conjunction with [the relevant information]. Figure 2A and Figure 2B The descriptions are different.

[0053] Figure 3 This is a figure of an example embodiment 300 of the trench capacitor structure described herein. The trench capacitor structure can correspond to including... Figure 2B The trench capacitor structure 220 is in the substrate of the device region 214 of the semiconductor die 202.

[0054] like Figure 3 As shown, and in some embodiments, the trench capacitor structure 220 is a multilayer structure (e.g., a stack). In such embodiments, the trench capacitor structure 220 may include a liner 302 (e.g., a "glue" layer) located on a trench in the substrate of the device region 214. The liner 302 may include a dielectric material, such as silicon oxide (SiO2) or silicon nitride (SiN), etc.

[0055] The trench capacitor structure 220 may also include a stack comprising one or more conductive layers 304 (e.g., capacitor electrode layers) and one or more dielectric layers 306 (e.g., capacitor dielectric layers). The conductive layers 304 and dielectric layers 306 may be arranged alternately and / or staggered vertically and dispersed among each other within the trench capacitor structure 220.

[0056] The conductive layer 304 may include one or more conductive materials, such as conductive metals (e.g., copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), conductive ceramics (e.g., tantalum nitride (TaN), titanium nitride (TiN)), and / or another type of conductive material. The dielectric layer 306 may include one or more dielectric materials, such as oxides (e.g., silicon oxide (SiOx)), nitrides (e.g., silicon nitride (SixNy)), and / or another suitable dielectric material.

[0057] like Figure 3 As shown, the conductive layer 304 includes a conductive layer 304a (e.g., the negative (-) polarity capacitor electrode layer of the trench capacitor structure 220), a conductive layer 304b (e.g., the positive (+) polarity capacitor electrode layer of the trench capacitor structure 220), a conductive layer 304c (e.g., the negative (-) polarity capacitor electrode layer of the trench capacitor structure 220), and a conductive layer 304d (e.g., the positive (+) polarity capacitor electrode layer of the trench capacitor structure 220).

[0058] like Figure 3 As shown, dielectric layer 306a is located between conductive layers 304a and 304b (e.g., dispersed between conductive layers 304a and 304b). Alternatively, dielectric layer 306b is located between conductive layers 304b and 304c (e.g., dispersed between conductive layers 304b and 304c). Alternatively, dielectric layer 306c is located between conductive layers 304c and 304d (e.g., dispersed between conductive layers 304c and 304d).

[0059] like Figure 3 As shown, the trench capacitor structure 220 includes a dielectric layer 308 (e.g., a "merged" layer). The dielectric layer 308 may include an oxide material, such as alumina (Al₂O₃), zirconium oxide (ZrO₂), or silicon dioxide (SiO₂). Figure 3 In the trench capacitor structure, dielectric layer 308 is located in the vertically oriented merging region 310 between the co-facing surface of the top layer and conductive layer 304d.

[0060] In some embodiments, one or more additional dielectric layers are located above the trench capacitor structure 220. For example, in addition to bonding... Figure 2B In addition to the described dielectric layer 228, dielectric layer 312 (e.g., silicon nitride) and dielectric layer 314 (e.g., undoped silicon glass (USG) material) may be located above trench capacitor structure 220.

[0061] like Figure 3As shown, metallization layer 230 (e.g., metallization layer 230a and metallization layer 230b) is surrounded by dielectric layers 312 and 314. In some embodiments, metallization layer 230 is connected to trench capacitor structure 220 using interconnect structure 234 (e.g., interconnect structure 234a and / or interconnect structure 234b), wherein interconnect structure 234 is surrounded by one or more sidewall layers (e.g., sidewall layer 316a and / or sidewall layer 316b).

[0062] In some embodiments, the sidewall layer acts as a stress buffer layer (e.g., absorbing stress and / or strain within the trench capacitor structure 220 during its formation) and can prevent delamination of the conductive layer 304 and / or the dielectric layer 306.

[0063] Alternatively or in some embodiments, the sidewall layer electrically couples two or more conductive layers 304 and / or couples two or more conductive layers 304 to the substrate of the device region 214. In this case, the sidewall layer may comprise a conductive material, such as titanium nitride (TiN) or tantalum nitride (TaN). If the interconnect structure 234 comprises copper (Cu), the sidewall layer may act as a copper barrier layer.

[0064] Interconnect structure 234 and sidewall layer connect metallization layer 230 to trench capacitor structure 220. Connecting metallization layer 230 to trench capacitor structure 220 may include using one or more multi-electrode connections (e.g., multi-electrode connections 318a and / or multi-electrode connections 318b) for connection to two or more conductive layers (e.g., two or more capacitor electrode layers) having the same polarity. Figure 8A and Figure 8B As described in more detail, the use of multi-electrode connections can increase the effective thickness of the junction region of the interconnect structure 234. The increased effective thickness (e.g., the combined thickness of conductive layers of the same polarity) can further enhance the effective thickness of the interconnect structure 234. This increases the etch and cleaning process margin, reducing the likelihood of VIMIC defects occurring during the formation of the trench capacitor structure 220.

[0065] To accommodate multi-electrode connections, and as combined Figures 4A to 4G As described in more detail, forming the conductive layer 304 may include forming one or more gap regions (e.g., gap region 320a corresponding to a discontinuity in conductive layer 304c and / or gap region 320b corresponding to a discontinuity in conductive layer 304b) within the one or more conductive layers 304. Furthermore, one or more dielectric layers 306 may coincide with the edges of the gap regions to isolate the one or more conductive layers 304.

[0066] Depending on the selected configuration, the interconnect structure 234 and the sidewall layer may extend through one or more dielectric layers above the gap region. Alternatively, the interconnect structure 234 and the sidewall layer may extend through portions of one or more conductive layers filling the gap region. Alternatively, the interconnect structure 234 and the sidewall layer may extend through one or more dielectric layers 306 on the conductive layer below the gap region. Alternatively, the interconnect structure 234 and the sidewall layer may extend to and / or through the conductive layer below the gap region. Alternatively, the interconnect structure 234 and the sidewall layer may extend into the substrate of the device region 214.

[0067] As an example, such as Figure 3 As shown, the metallization layer 230a is connected to the conductive layers 304b and 304d using a multi-electrode connection 318a (e.g., connected to multiple positive (+) polarity capacitor electrode layers). The multi-electrode connection 318a includes an interconnect structure 234a and a sidewall layer 316a. Furthermore, the interconnect structure 234a and the sidewall layer 316a pass through the dielectric layer 228, through the dielectric layer 308, through the dielectric layer 306d, through a portion of the conductive layer 304d located in the gap region 320a, through the dielectric layer 306c and / or the dielectric layer 306b (e.g., the dielectric layers 306c and 306b may be incorporated on the conductive layer 304b), and enter the conductive layer 304b.

[0068] Alternatively or alternatively, such as Figure 3 As shown, the metallization layer 230b is connected to the conductive layers 304a and 304c via a multi-electrode connection 318b (e.g., connected to multiple negative (-) polarity capacitor electrode layers). The multi-electrode connection 318b includes an interconnect structure 234b and a sidewall layer 316b. Furthermore, the interconnect structure 234b and the sidewall layer 316b pass through the dielectric layer 228, through the dielectric layer 306c, through a portion of the conductive layer 304c located in the gap region 320b, through the dielectric layer 306b and / or the dielectric layer 306a (e.g., the dielectric layers 306b and 306a may be merged on the conductive layer 304a), through the conductive layer 304a, and into the substrate of the device region 214.

[0069] As mentioned above, providing Figure 3 As an example. Other examples may be related to... Figure 3 The descriptions are different.

[0070] Such as combination Figure 2A , Figure 2B and Figure 3As described, and in some embodiments, the structure (e.g., trench capacitor structure 220) includes a first conductive layer (e.g., conductive layer 304b). The structure includes a dielectric layer (e.g., dielectric layer 306b) on the first conductive layer. The structure includes a second conductive layer (e.g., conductive layer 304c) on the dielectric layer, having a gap region (e.g., gap region 320a) over a portion of the first conductive layer. The structure includes a third conductive layer (e.g., conductive layer 304c) including a portion within the gap region. This structure includes an interconnect structure (e.g., interconnect structure 234a) that extends through the portion of the third conductive layer in the gap region, through the dielectric layer, and into the first conductive layer. The structure includes a sidewall layer (e.g., sidewall layer 316a) that surrounds the interconnect structure and extends through the portion of the third conductive layer in the gap region, through the dielectric layer, and into the first conductive layer.

[0071] Alternatively or concurrently, and in some embodiments, the semiconductor device (e.g., a semiconductor die package 200 including a semiconductor die 202) includes a metallization layer comprising a first portion (e.g., metallization layer 230a) and a second portion (e.g., metallization layer 230b). The semiconductor device includes a trench capacitor structure (e.g., trench capacitor structure 220) comprising at least two vertically aligned positive capacitor electrode layers (e.g., conductive layers 304b and 304d) and at least two vertically aligned negative capacitor electrode layers (e.g., conductive layers 304a and 304c). The semiconductor device includes a first interconnect structure (e.g., interconnect structure 234a) connecting the at least two vertically aligned positive capacitor electrode layers to the first portion. The semiconductor device includes a second interconnect structure (e.g., interconnect structure 234b) connecting the at least two vertically aligned negative capacitor electrode layers to the second portion.

[0072] In these ways, the performance of trench capacitor structures is improved (e.g., by increasing the density of capacitor electrode layers and / or capacitor dielectric layers to increase charge storage capacity and / or charge storage duration), while also improving the performance of trench capacitor structures, including the quality and / or reliability of semiconductor devices with trench capacitor structures (e.g., by reducing VIMIC defects in semiconductor devices, thus improving the quality and / or reliability of semiconductor devices). Additionally, reducing the number of interconnect structures in trench capacitor structures (e.g., a single interconnect structure can connect to two or more capacitor electrode layers) reduces the size of trench capacitor structures, thereby reducing the size of semiconductor devices. By improving the performance of trench capacitor structures, increasing the yield and / or reliability of semiconductor devices, or reducing the size of semiconductor devices, the amount of resources used to support markets consuming semiconductor devices can be reduced (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources can be reduced).

[0073] Figures 4A to 4G This is a diagram of an example embodiment 400 for forming the trench capacitor structure described herein. The trench capacitor structure may correspond to trench capacitor structure 220. Furthermore, example embodiment 400 may include a combination of... Figure 1 One or more of the described semiconductor processing tools 102-114 are used to perform one or more semiconductor processing operations.

[0074] like Figure 4A As shown, and as part of embodiment 400, a cavity 402 is formed in the substrate of device region 214. In some embodiments, a pattern in a photoresist layer is used to etch the substrate to form the cavity 402. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the substrate. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch the substrate based on the pattern to form the cavity 402. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the substrate.

[0075] In addition, such as Figure 4A As shown, a liner 302 is formed over and / or on the substrate of device region 214 and cavity 402. Deposition tool 102 can be used with CVD, PVD, ALD, oxidation, or other methods combined with the substrate. Figure 1 Another deposition technique described herein, and / or another suitable deposition technique, is used to deposit the liner 302. The liner 302 may be deposited in one or more deposition operations. In some embodiments, a planarization tool 110 may be used to planarize the liner 302 and / or deposit the liner 302.

[0076] In addition, such as Figure 4A As shown, a conductive layer 304a is formed on and / or above the substrate 302. A deposition tool 102 and / or an electroplating tool 112 can be used to deposit the conductive layer 304a. For example, CVD, PVD, ALD, electroplating, or other methods can be used to deposit the conductive layer 304a. Figure 1 Another deposition technique described, and / or another suitable deposition technique. The conductive layer 304a can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the conductive layer 304a is deposited on the seed layer. In some embodiments, a planarization tool 110 can be used to planarize the conductive layer 304a after deposition.

[0077] The thickness D1 of the conductive layer 304a (and / or the subsequently formed conductive layer) can range from about 100 angstroms to about 200 angstroms. If the thickness D1 is less than about 100 angstroms, the equivalent series resistance of the trench capacitor structure including the conductive layer 304a may increase and cause the effective capacitance of the trench capacitor structure to fail to meet the performance threshold. If the thickness D1 is in the range of about 100 angstroms to about 200 angstroms, the effective capacitance of the trench capacitor structure may meet the performance threshold and / or the size of the trench capacitor structure may meet the layout threshold (e.g., size requirements). If the thickness D1 is greater than about 200 angstroms, the size of the trench capacitor structure may increase and fail to meet the layout threshold. However, other values ​​and ranges of thickness D1 are also within the scope of this disclosure.

[0078] like Figure 4B As shown, and as part of embodiment 400, portions of the conductive layer 304a are removed to expose the substrate 302. To remove these portions, a photoresist layer 404 can be deposited on and / or over the conductive layer 304a using a deposition tool 102. An exposure tool 104 can be used to expose the photoresist layer 404 to a radiation source to pattern the photoresist layer 404. A development tool 106 can be used to develop and remove portions of the photoresist layer 404 to expose the pattern (e.g., the removed conductive layer 304a). An etching tool 108 can be used to etch these portions and expose the substrate 302. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of portions.

[0079] like Figure 4C As shown, and as part of embodiment 400, dielectric layer 306a is formed on a portion of conductive layer 304a and substrate 302 (e.g., through...). Figure 4B The semiconductor operation described above and / or over a portion of the exposed substrate 302. In some embodiments, the deposition tool 102 can be used to deposit the dielectric layer 306a using ALD technology. Alternatively, the deposition tool can be used using PVD technology, CVD technology, oxidation technology, bonding technology, etc. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit dielectric layer 306a. Dielectric layer 306a may be deposited in one or more deposition operations. In some embodiments, planarization tool 110 may be used to planarize dielectric layer 306a after deposition.

[0080] like Figure 4DAs shown, and as part of embodiment 400, additional conductive layers 304b-304d and additional dielectric layers 306c and 306d are formed. Forming the additional conductive layers 304b-304d and / or the additional dielectric layers 306c and 306d may include repeating as in combination. Figures 4A to 4C One or more semiconductor processing operations are described. Furthermore, forming conductive layers 304b-304d includes forming gap regions 320a (e.g., discontinuities between the edges of conductive layers 304c may define gap regions 320a) and gap regions 320b (e.g., discontinuities between the edges of conductive layers 304c may define gap regions 320b).

[0081] like Figure 4D As shown, after the dielectric layer 306d is formed, a gap 406 with a width D2 exists between the common facing surfaces of the dielectric layer 306d. In some embodiments, the width D2 is greater than about 10 nanometers (nm). If the width D2 is greater than about 10 nm, filling the gap 406 with photoresist during subsequent patterning operations will not be suppressed by degassing, which can lead to bubbles in the photoresist and manufacturing defects. If the width D2 is less than about 10 nm, filling the gap 406 with photoresist during subsequent patterning operations may be suppressed by degassing, and bubbles may form in the photoresist, leading to manufacturing defects. Furthermore, although shown as being between the common facing surfaces of the top layer serving as the dielectric layer of the top capacitor, in other embodiments, the gap 406 may be between the surfaces of the top layer serving as the electrode layer of the top capacitor.

[0082] like Figure 4E As shown, and as part of embodiment 400, dielectric layer 308 is formed on and / or over dielectric layer 306d. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, bonding technology, etc. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit 306d. The dielectric layer 308 can be deposited in one or more deposition operations. In some embodiments, a planarization tool 110 can be used to planarize 308 after the dielectric layer 308 has been deposited.

[0083] like Figure 4F As shown, and as part of embodiment 400, dielectric layer 228 is formed on and / or over dielectric layer 308. Deposition tool 102 can be used with PVD technology, ALD technology, CVD technology, oxidation technology, bonding technology, etc. Figure 1 Another type of deposition technique, and / or another suitable deposition technique, is described to deposit the dielectric layer 228. The dielectric layer 228 may be deposited in one or more deposition operations. In some embodiments, a planarization tool 110 may be used to planarize the dielectric layer 228 after deposition.

[0084] like Figure 4F As further shown, a cavity 410a is formed through dielectric layer 228, dielectric layer 308, dielectric layer 306d, a portion of conductive layer 304d located in gap region 320a, dielectric layer 306c and / or dielectric layer 306b (e.g., dielectric layers 306c and 306b may be merged on conductive layer 304b), and enters conductive layer 304b. Furthermore, a cavity 410b is formed through dielectric layer 228, dielectric layer 306c, a portion of conductive layer 304c located in gap region 320b, dielectric layer 306b and / or dielectric layer 306a (e.g., dielectric layers 306b and 306a may be merged on conductive layer 304a), and enters the substrate of device region 214.

[0085] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 228, dielectric layer 308, dielectric layers 306a-306d, conductive layers 304a-304d, and / or the substrate of the device region 214 to form cavities 410a and 410b. In these embodiments, a deposition tool 102 can be used to form the photoresist layer on and / or over the dielectric layer 228. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layer 228, dielectric layer 308, dielectric layers 306a-306d, conductive layers 304a-304d, and / or the substrate to form cavities 410a and 410b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used based on a pattern to etch dielectric layer 228, dielectric layer 308, dielectric layers 306a-306d, conductive layers 304a-304d, and / or the substrate.

[0086] In addition, such as Figure 4F As shown, a sidewall layer 316a is formed on the surface of cavity 410a, and a sidewall layer 316b is formed on the surface of cavity 410b. The deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and in combination. Figure 1Another type of deposition technique, and / or another suitable deposition technique, is described to deposit sidewall layers 316a and / or 316b. Sidewall layers 316a and / or 316b can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and sidewall layers 316a and / or 316b are deposited on the seed layer. In some embodiments, a planarization tool 110 can be used to planarize sidewall layers 316a and / or 316b after deposition.

[0087] Sidewall layers 316a (and / or 316b) may include a thickness D3. As an example, the thickness D3 may range from about 50 angstroms to about 1000 angstroms. Taking sidewall layer 316a as an example, if the thickness D3 is less than about 50 angstroms, the effectiveness of sidewall layer 316a in preventing delamination and / or breakage in conductive layer 304b, dielectric layer 306b, dielectric layer 306c, conductive layer 304d, and / or dielectric layer 306d is reduced, potentially causing mechanical defects in the trench capacitor structure 220. If the thickness D3 is in the range from about 50 angstroms to about 1000 angstroms, the sidewall layer 316a can prevent such delamination and / or breakage, and the dimensions of the trench capacitor structure 220 can meet layout thresholds (e.g., dimensional requirements). If the thickness D3 is greater than about 1000 angstroms, the dimensions of the trench capacitor structure 220 may not meet layout thresholds. However, other values ​​and ranges of thickness D3 are also within the scope of this disclosure.

[0088] like Figure 4G As shown, and as part of embodiment 400, interconnect structures 234a and 234b are formed. The deposition tool 102 and / or electroplating tool 112 can be used with PVD technology, ALD technology, CVD technology, electroplating technology, oxidation technology, and bonding technology. Figure 1 Another type of deposition technique, and / or another suitable deposition technique, is described to deposit the interconnect structure 234a (e.g., above and / or on the sidewall layer 316a in the cavity 410a). Alternatively or concurrently, deposition tool 102 and / or electroplating tool 112 may be used with PVD, ALD, CVD, electroplating, oxidation, or bonding techniques. Figure 1 Another type of deposition technique, and / or another suitable deposition technique, is described to deposit the interconnect structure 234b (e.g., above and / or on the sidewall layer 316b in the cavity 410b). The interconnect structure 234a and / or the interconnect structure 234b may be deposited in one or more deposition operations. In some embodiments, a planarization tool 110 may be used to planarize the interconnect structure 234a and / or the interconnect structure 234b after deposition.

[0089] When forming the interconnect structure 234a, the multi-electrode connection 318a electrically couples multiple capacitor electrode layers (e.g., conductive layers 304b and 304d) to the sidewall layer 316a and the interconnect structure 234a. Furthermore, when forming the interconnect structure 234b, the multi-electrode connection 318b electrically couples multiple capacitor electrode layers (e.g., conductive layers 304a and 304c), the sidewall layer 316b, the interconnect structure 234b, and the substrate of the device region 214.

[0090] like Figure 4G As further shown, dielectric layers 312 and 314 are formed on and / or above dielectric layer 228. Deposition tool 102 can be used with PVD, ALD, CVD, oxidation, and bonding technologies. Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit dielectric layer 312 and / or dielectric layer 314. Dielectric layer 312 and / or dielectric layer 314 may be deposited in one or more deposition operations. In some embodiments, planarization tool 110 may be used to planarize dielectric layer 312 and / or dielectric layer 314 after deposition.

[0091] In addition, such as Figure 4G As shown, metallization layers 230a and 230b are formed. In some embodiments, and as part of forming metallization layers 230a and 230b, the dielectric layers 314 and 312 are etched using a pattern in the photoresist layer to form cavities in the dielectric layers 314 and 312. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the dielectric layer 314. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool 108 can be used to etch the dielectric layers 314 and 312 based on the pattern to form cavities in the dielectric layers 314 and 312. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-etched dielectric layers 314 and 312.

[0092] After the cavity is formed, the deposition tool 102 and / or the electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and the above-mentioned bonding. Figure 1Another deposition technique, and / or another suitable deposition technique, is described to deposit metallization layers 230a and / or 230b. Metallization layers 230a and / or 230b can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and metallization layers 230a and / or 230b are deposited on the seed layer. In some embodiments, a planarization tool 110 can be used to planarize metallization layers 230a and / or 230b after deposition.

[0093] As mentioned above, Figures 4A to 4G Provided as an example. Other examples may be provided with reference to [the relevant information]. Figures 4A to 4G The descriptions are different.

[0094] Figures 5A to 5D This is a diagram illustrating an exemplary embodiment 500 of forming the semiconductor die described herein. In some embodiments, exemplary embodiment 500 includes an exemplary process for forming a portion of a second semiconductor die 206. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may be used to perform one or more operations described in conjunction with exemplary embodiment 500. In some embodiments, one or more operations described in conjunction with exemplary embodiment 500 may be performed by another semiconductor processing tool.

[0095] refer to Figure 5A In example implementation 500, one or more operations can be performed in conjunction with the semiconductor substrate of the device region 210 of the second semiconductor die 206. The semiconductor substrate of the device region 210 can be provided in the form of a semiconductor chip or other type of substrate.

[0096] like Figure 5B As shown, one or more semiconductor devices 218 may be formed in device region 210. For example, one or more of semiconductor processing tools 102-114 may be used to perform photolithography patterning operations, etching operations, deposition operations, CMP operations, and / or another type of operation to form one or more transistors, one or more capacitors, one or more memory cells, one or more circuits (e.g., one or more ICs), and / or one or more other types of semiconductor devices. In some embodiments, one or more regions of the semiconductor substrate of device region 210 may be doped in an ion implantation operation to form one or more p-wells, one or more n-wells, and / or one or more deep n-wells. In some embodiments, deposition tool 102 may be used to deposit one or more source / drain regions, one or more gate structures, and / or one or more STI regions, etc.

[0097] like Figure 5CAs shown, a portion of the interconnect region 212 of the second semiconductor die 206 may be formed on and / or over the semiconductor substrate of the device region 210. One or more of the semiconductor processing tools 102-114 may form the interconnect region 212 by forming a dielectric layer 222 and forming a plurality of metallization layers 224 in the dielectric layer 222. For example, a deposition tool 102 may be used to deposit a first layer of the interconnect region 212 (e.g., using CVD, ALD, PVD, and / or another type of deposition technique), and an etching tool 108 may be used to remove a portion of the first layer to form a trench in the dielectric layer 222. The deposition tool 102 and / or the electroplating tool 112 may form a first metallization layer of a plurality of metallization layers 224 in the trench (e.g., using CVD, ALD, PVD, electroplating, and / or another type of deposition technique). At least a portion of the first metallization layer may be electrically and / or physically connected to the semiconductor device 218. The deposition tool 102, etching tool 108, electroplating tool 112 and / or another semiconductor processing tool may continue to perform similar processing operations to form the interconnect region 212 until the metallization layer 224 is adequately or as desired arranged.

[0098] like Figure 5D As shown, one or more of the semiconductor processing tools 102-114 can form another layer of dielectric layer 222, and can form one or more contacts 226 in said layer, such that the contacts 226 dielectric layer 224 are electrically connected and / or physically connected to one or more metallization layers 224. For example, deposition tool 102 can be used to deposit a layer of dielectric layer 222 (e.g., using CVD technology, ALD technology, PVD technology and / or another type of deposition technology), etching tool 108 can be used to remove a portion of the layer to form a groove in the layer, and deposition tool 102 and / or electroplating tool 112 can form contacts 226 in the groove (e.g., using CVD technology, ALD technology, PVD technology, electroplating technology and / or another type of deposition technology).

[0099] As mentioned above, Figures 5A to 5D Provided as an example. Other examples may be provided with reference to [the relevant information]. Figures 5A to 5D The descriptions are different.

[0100] Figures 6A to 6EThis is a diagram illustrating an exemplary embodiment 600 of forming the semiconductor die described herein. In some embodiments, exemplary embodiment 600 includes an exemplary process for forming a portion of a first semiconductor die 202. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may be used to perform one or more operations described in conjunction with exemplary embodiment 600. In some embodiments, one or more operations described in conjunction with exemplary embodiment 600 may be performed by another semiconductor processing tool.

[0101] refer to Figure 6A In example implementation 600, one or more operations can be performed in conjunction with the semiconductor substrate of device region 214 of the first semiconductor die 202. The semiconductor substrate of device region 214 can be provided in the form of a semiconductor chip or other type of substrate.

[0102] like Figure 6B As shown, the trench capacitor structure 220 can be formed in the device region 214. For example... Figures 4A to 4E As shown elsewhere in this document, one or more semiconductor processing tools 102-114 may form a trench capacitor structure 220, including a liner 302, conductive layers 304a-304b, dielectric layers 306a-306d, and dielectric layer 308.

[0103] like Figure 6C As shown, a portion of the interconnect region 216 of the first semiconductor die 202 may be formed on and / or above the semiconductor substrate of the device region 214. Figure 4F , 4G As shown elsewhere in this document, one or more semiconductor processing tools 102-114 may form interconnect structures 234a, interconnect structures 234b, sidewall layers 316a, sidewall layers 316b, metallization layers 230a and 230b, multi-electrode connections 318a, and / or multi-electrode connections 318b.

[0104] like Figure 6D As shown, deposition tool 102, etching tool 108, electroplating tool 112 and / or another semiconductor processing tool can continue to perform similar processing operations to continue forming dielectric layer 228 and / or metallization layer 230 located in interconnect region 216.

[0105] like Figure 6EAs shown, one or more of the semiconductor processing tools 102-114 can be used to form another layer of dielectric layer 228, and can be used to form one or more contacts 232 in said layer, such that the contacts 232 are electrically and / or physically connected to one or more of the metallization layers 230. For example, deposition tool 102 can be used to deposit dielectric layer 228 (e.g., using CVD technology, ALD technology, PVD technology and / or another type of deposition technology), etching tool 108 can be used to remove a portion of said layer to form a groove in said layer, and deposition tool 102 and / or electroplating tool 112 can be used to form contacts 232 in the groove (e.g., using CVD technology, ALD technology, PVD technology, electroplating technology and / or another type of deposition technology).

[0106] As mentioned above, Figures 6A to 6E Provided as an example. Other examples may be provided with reference to [the relevant information]. Figures 6A to 6E The descriptions are different.

[0107] Figures 7A to 7G This is a diagram of an example embodiment 700 that forms part of the semiconductor die package 200 described herein. In some embodiments, combined with Figures 7A to 7G The described one or more operations can be performed by one or more of semiconductor processing tools 102-114 and / or wafer / die transfer tools 116. In some embodiments, Figures 7A to 7G One or more of the operations described can be performed by another semiconductor processing tool.

[0108] like Figure 7A As shown, a first semiconductor die 202 and a second semiconductor die 206 can be bonded at a bonding interface 208, such that the first semiconductor die 202 and the second semiconductor die 206 are vertically aligned or stacked. The first semiconductor die 202 and the second semiconductor die 206 can be vertically aligned or stacked in a WoW configuration, a wafer-on-die configuration, a die-on-die configuration, and / or another direct bonding configuration. A bonding tool 114 can be used to perform a bonding operation to bond the first semiconductor die 202 and the second semiconductor die 206 at the bonding interface 208. The bonding operation can include a direct bonding operation, wherein the bonding of the first semiconductor die 202 and the second semiconductor die 206 is achieved through a physical connection between contact 226 and contact 232. At the bonding interface 208, a direct metal bond is formed between contact 226 and contact 232, and a dielectric bond is formed between the two dielectric layers.

[0109] like Figure 7BAs shown, one or more grooves 702 may be formed as part of the dielectric layer 228 extending through the semiconductor substrate of the device region 214 and into the interconnect region 216. The grooves 702 may be formed to expose one or more portions of the metallization layer 230 in the interconnect region 216. Therefore, the grooves 702 may be formed over one or more portions of the metallization layer 230.

[0110] In some embodiments, the pattern in the photoresist layer is used to form the recess 702. In these embodiments, a deposition tool 102 forms a photoresist layer over a silicon substrate of device region 214. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches through the semiconductor substrate of device region 214 and into a portion of the dielectric layer 228 of interconnect region 216 to form the recess 702. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the recess 702.

[0111] like Figure 7C As shown, the BTSV structure 242 can be formed in the recess 702. In this way, the BTSV structure 242 extends through the semiconductor substrate of the device region 214 and into the interconnect region 216. The BTSV structure 242 can be electrically and / or physically connected to one or more portions of the metallization layer 230 exposed through the recess 702.

[0112] Deposition tool 102 and / or electroplating tool 112 can be used with CVD technology, PVD technology, ALD technology, electroplating technology, and above-ground bonding. Figure 1 The deposition techniques and / or other combinations shown above are used. Figure 1 An alternative deposition technique, other than the aforementioned deposition technique, is used to deposit the BTSV structure 242. In some embodiments, a planarization tool 110 may be used to perform a CMP operation to planarize the BTSV structure(s)242 after it.

[0113] like Figure 7DAs shown, a redistribution structure 236 of the semiconductor die package 200 can be formed on the first semiconductor die 202. One or more of the semiconductor processing tools 102-114 can be used to form the redistribution structure 236 by depositing one or more dielectric layers 238 and forming multiple metallization layers 240 in the dielectric layers 238. For example, the deposition tool 102 can be used to deposit a first layer of one or more dielectric layers 238 (e.g., using CVD, ALD, PVD, and / or another type of deposition technique), the etching tool 108 can be used to remove a portion of the first layer to form a groove in the first layer, and the deposition tool 102 and / or the electroplating tool 112 can be used to form a first metallization layer of multiple metallization layers 240 in the groove (e.g., using CVD, ALD, PVD, electroplating, and / or another type of deposition technique). At least a portion of the first metallization layer can be electrically and / or physically connected to the BTSV structure 242. The deposition tool 102, etching tool 108, electroplating tool 112 and / or another semiconductor processing tool may continue to perform similar processing operations to form the redistributed circuit structure 236 until the metallization layer 240 is adequately or as desired arranged.

[0114] like Figure 7E As shown, the groove 704 can be formed in one or more dielectric layers 238. The groove 704 can be formed to expose a portion of the metallization layer 240 in the redistribution circuit structure 236. Therefore, the groove 704 can be formed in one or more portions of the metallization layer 240.

[0115] In some embodiments, a pattern in a photoresist layer is used to form the groove 704. In these embodiments, a deposition tool 102 forms a photoresist layer on one or more dielectric layers 238. An exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 develops and removes portions of the photoresist layer to expose the pattern. An etching tool 108 etches one or more dielectric layers 238 to form the groove 704. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the groove 704.

[0116] like Figure 7F As shown, the UBM layer 244 can be formed in the groove 704. The deposition tool 102 and / or electroplating tool 112 can be used to utilize CVD technology, PVD technology, ALD technology, electroplating technology, and the above-mentioned bonding... Figure 1 Another deposition technique described, and / or in addition to the above combination Figure 1Deposition techniques other than those described are used to deposit the UBM layer 244. In some embodiments, a continuous layer of conductive material is deposited on the top surface of the redistributed circuit structure 236, including deposition in the groove 702. The continuous layer of conductive material is then patterned (e.g., through a deposition tool 102, an exposure tool 104, and a development tool 106) to form a patterned continuous layer of conductive material on the continuous layer, and an etching tool 108 removes portions of the continuous layer of conductive material based on the pattern. The remaining portions of the continuous layer of conductive material may correspond to the UBM layer 244.

[0117] like Figure 7G As shown, conductive terminals 246 can be formed in grooves 704 above UBM layer 244. In some embodiments, electroplating tool 112 uses electroplating technology to form conductive terminals 246. In some embodiments, solder is applied to grooves 704 to form conductive terminals 246.

[0118] As mentioned above, Figures 7A to 7G Provided as an example. Other examples may be provided with reference to [the relevant information]. Figures 7A to 7G The descriptions are different.

[0119] Figure 8A and Figure 8B This is a diagram related to the corrosion defects of metal islands induced by access to vertical interconnects as described in this article. Figure 8A An example circuit 802 is shown, which includes a trench capacitor structure 220, conductive layers 304a, 304b, 304c, and 304d, and an interconnect structure 234b connected to the substrate of device region 214. During the formation of the trench capacitor structure 220, conductive layers 304a and / or 304c (e.g., negative (-) polarity capacitor electrode layers) may be exposed to potential 804. Alternatively, during the formation of the trench capacitor structure 220, conductive layers 304b and / or 304d (e.g., positive (+) polarity capacitor electrode layers) may be exposed to potential 806.

[0120] In some implementations, and in cleaning operations (e.g., may be combined with...) Figures 4A to 4GDuring the wet etching operation (combined with a cleaning operation as described), a potential 808 can accumulate in the trench capacitor structure 220. A voltage drop 810 may occur on the interconnect structure 234b that electrically couples the circuit 802 to the substrate of the device region 214, with a suppression potential 808 discharging from the trench capacitor structure 220 to the conductive layers 304a-304d. By discharging the suppression potential 808, potential superposition (e.g., potential 808 combined with potentials 804 and / or 806) can be avoided, reducing the likelihood of damage to one or more features of the trench capacitor structure 220. Within the circuit 802, the voltage drop 810 can correspond to a voltage divider effect conforming to Kirchhoff's law.

[0121] Figure 8B An example comparison of defect distribution on a wafer-based substrate is shown. Figure 8B In this example, Example 812 may correspond to a wafer-based substrate (e.g., a silicon semiconductor chip) comprising multiple semiconductor dies, the semiconductor dies not including the configuration of multi-electrode connections 318a and / or multi-electrode connections 318b described herein. Conversely, Example 814 may correspond to a wafer-based substrate comprising multiple semiconductor dies, the semiconductor dies including the configuration of multi-electrode connections 318a and / or multi-electrode connections 318b.

[0122] In some embodiments, and as shown in Example 812, the defect density may increase near the periphery of the wafer-based substrate due to the increased potential near the periphery within the trench capacitor (e.g., trench capacitor structure 220) during wet cleaning operations (e.g., during wet cleaning operations involving rotation of the wafer-based substrate, where local velocities near the periphery may be greater than those near the center, resulting in additional charge accumulation near the periphery within the trench capacitor structure 220). However, and as shown in Example 814, the defect distribution (e.g., the amount of vertical interconnect access-induced metal island corrosion (VIMIC) defects across the wafer-based substrate and / or the defect density near the periphery of the wafer-based substrate) is much smaller than the defect distribution in Example 812.

[0123] like Figure 8B As shown, since the semiconductor die includes multi-electrode connections 318a and / or multi-electrode connections 318b, the likelihood of VIMIC defects within the wafer substrate (e.g., VIMIC defects within the semiconductor die) can be reduced. By reducing the likelihood of such defects, the yield of the semiconductor die can be increased, thereby reducing the amount of resources (e.g., semiconductor manufacturing tools, raw materials, human and / or computing resources) required to manufacture a given volume of semiconductor die.

[0124] As mentioned above, Figure 8A and Figure 8BProvided as an example. Other examples may be provided with reference to [the relevant information]. Figure 8A and Figure 8B The descriptions are different.

[0125] Figure 9 This is a diagram of example components of the device 900 described herein. In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transport tool 116 may include one or more devices 900 and / or one or more components of device 900. Figure 9 As shown, the device 900 may include a bus 910, a processor 920, a memory 930, an input component 940, an output component 950, and / or a communication component 960.

[0126] Bus 910 may include one or more components enabling wired and / or wireless communication between components of device 900. Bus 910 can... Figure 9 Two or more components are coupled together, for example via operational coupling, communication coupling, electronic coupling, coupling, and / or electrical coupling. For example, bus 910 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless connections. Processor 920 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing component. Processor 920 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0127] Memory 930 may include volatile and / or non-volatile memory. For example, memory 930 may include random access memory (RAM), read-only memory (ROM), hard disk, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 930 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus). Memory 930 may be a non-transitory computer-readable medium. Memory 930 may store information related to the operation of device 900, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 930 may include one or more memory modules coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 920) via bus 910. The communicative coupling between processor 920 and memory 930 enables processor 920 to read and / or process information stored in processor 920 and / or store information in memory 930.

[0128] Input component 940 enables device 900 to receive input, such as user input and / or sensed input. For example, input component 940 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator. Output component 950 enables device 900 to provide output, such as via a display, speaker, and / or light-emitting diode. Communication component 960 enables device 900 to communicate with other devices via wired and / or wireless connections. For example, communication component 960 may include a receiver, transmitter, transceiver, modem, network adapter, and / or antenna.

[0129] Device 900 may be used to perform one or more of the operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 930) may store a set of instructions (e.g., one or more instructions or program code) for execution by processor 920. Processor 920 may execute this group of instructions to perform one or more of the operations or processes described herein. In some embodiments, execution of the group of instructions by one or more processors 920 causes one or more processors 920 and / or device 900 to perform one or more of the operations or processes described herein. In some embodiments, hard-wired circuitry may be used in place of or in combination with instructions to perform one or more of the operations or processes described herein. Alternatively or additionally, processor 920 may be configured to perform one or more of the operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0130] Figure 9 The number and arrangement of components shown are provided as an example. Device 900 may include components related to... Figure 9 The components shown are those with more components, fewer components, different components, or different arrangements. Alternatively, one or more functions described as being performed by another set of components of device 900 may be performed using one set of components of device 900 (e.g., one or more components).

[0131] Figure 10 This is a flowchart of an example process 1000 associated with forming the trench capacitor structure described herein. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-114) are used to perform the process. Figure 10 One or more processing blocks. Alternatively, Figure 10 One or more processing blocks can be executed using one or more devices of device 900, such as processor 920, memory 930, input device 940, output device 950 and / or communication device 960.

[0132] like Figure 10 As shown, process 1000 may include a stack of layers forming a trench capacitor structure on a substrate, the trench capacitor structure including a first capacitor electrode layer, a capacitor dielectric layer on the first capacitor electrode layer, and a second capacitor electrode layer (block 1010) located on the first capacitor electrode layer. For example, one or more of semiconductor processing tools 102-114 may be used to form a stack of layers of trench capacitor structures (e.g., trench capacitor structure 220) on a substrate (e.g., the substrate of device region 214), including a first capacitor electrode layer (e.g., conductive layer 304b), a capacitor dielectric layer on the first capacitor electrode layer (e.g., dielectric 306b), and a second capacitor electrode layer (e.g., conductive layer 304c) above the first capacitor electrode layer, as described herein.

[0133] like Figure 10 As further shown, process 1000 may include forming one or more dielectric layers over the stack (block 1020). For example, one or more of semiconductor processing tools 102-114 may be used to form one or more dielectric layers (e.g., dielectric layer 308, dielectric layer 312, and / or dielectric layer 314) over the stack, as described herein.

[0134] like Figure 10 As further shown, process 1000 may include forming a cavity (block 1030) that passes through one or more dielectric layers, through a second capacitor electrode layer, through a capacitor dielectric layer, and into a first capacitor electrode layer. For example, one or more of semiconductor processing tools 102-114 may be used to form a cavity (e.g., cavity 410a) that passes through one or more dielectric layers, through a second capacitor electrode layer, through a capacitor dielectric layer, and into a first capacitor electrode layer, as described herein.

[0135] like Figure 10 As further shown, process 1000 may include forming a multi-electrode connection using a cavity (block 1040). For example, one or more of semiconductor processing tools 102-114 may be used to form a multi-electrode connection using a cavity (e.g., multi-electrode connection 318a), as described herein.

[0136] Process 1000 may include other implementations, such as any single implementation or any combination of implementations described below and / or combined with one or more other processes described elsewhere herein.

[0137] In a first embodiment, forming the stack further includes forming a third capacitor electrode layer (e.g., conductive layer 304d) on the capacitor dielectric layer. In some embodiments, forming the third capacitor electrode layer includes forming a gap region (e.g., gap region 320a) in the third capacitor electrode layer above a portion of the first capacitor electrode layer.

[0138] In the second embodiment, forming the third capacitor electrode layer, alone or in combination with the first embodiment, includes depositing the third capacitor electrode layer on the capacitor dielectric layer and using an etching operation to remove portions of the third capacitor electrode layer to form discontinuous segments in the third capacitor electrode layer corresponding to the gap region.

[0139] In the third embodiment, forming the stack, alone or in combination with one or more of the first and second embodiments, includes using a conformal deposition process to form a second capacitor electrode layer, wherein the conformal deposition process forms a portion of the second capacitor electrode layer in the gap region.

[0140] In the fourth embodiment, a cavity is formed, either alone or in combination with one or more of the first to third embodiments, that passes through one or more dielectric layers, through the second capacitor electrode layer, through the capacitor dielectric layer and into the first capacitor dielectric layer, including a portion of the second capacitor electrode layer passing through the gap region to form the cavity.

[0141] In the fifth embodiment, forming a multi-electrode connection, alone or in combination with one or more of the first to fourth embodiments, includes forming a sidewall layer (e.g., sidewall layer 316a) along the inner surface of the cavity.

[0142] In the sixth embodiment, forming the sidewall layer, alone or in combination with one or more of the first to fifth embodiments, includes forming the sidewall layer by depositing a conductive material that electrically couples the first capacitor electrode layer and the second capacitor electrode layer.

[0143] In the seventh embodiment, forming a multi-electrode connection, either alone or in combination with one or more of the first to sixth embodiments, further includes forming an interconnect structure (e.g., interconnect structure 234a) in a cavity on the sidewall layer.

[0144] In the eighth embodiment, forming an interconnect structure, alone or in combination with one or more of the first to seventh embodiments, includes forming the interconnect structure by depositing conductive material in cavities on the sidewall layer.

[0145] In the ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, process 1000 includes forming a metallization layer (e.g., metallization layer 230) over one or more dielectric layers and performing a cleaning operation. In some embodiments, by using multi-electrode connections to reduce the voltage drop between the metallization layer and the substrate, the likelihood of vertical interconnect access-induced metal island corrosion defects caused by cleaning operations on at least one of the metallization layer, interconnect structures, first capacitor electrode layer, or second capacitor electrode layer is reduced.

[0146] although Figure 10 An example block of process 1000 is shown, but in some embodiments, process 1000 includes... Figure 10 The blocks depicted in the diagram can be more, fewer, different, or arranged differently. Alternatively, two or more blocks in process 1000 can be executed in parallel.

[0147] Some embodiments described herein provide a semiconductor device including a trench capacitor structure and a method for forming the same. Using multi-electrode connections including conductive sidewall layers, the interconnect structure can be connected to multiple vertically aligned electrode layers of the trench capacitor structure. Compared to connections using a single electrode layer, connections using multiple vertically aligned electrode layers can increase the effective thickness of the connection pads for the interconnect structure. This increased effective thickness can increase etching and cleaning process margins, thereby reducing the likelihood of VIMIC defects in the metal structure of the trench capacitor structure.

[0148] In this way, the performance of the trench capacitor structure (e.g., charge storage capacity and / or charge storage duration) is increased, while improving the quality and / or reliability of the semiconductor device. Additionally, reducing the number of interconnect structures within the trench capacitor structure reduces its size (and thus the size of the semiconductor device). By improving the performance of the trench capacitor structure, increasing the yield and / or reliability of the semiconductor device, or reducing the size of the semiconductor device, the amount of resources needed to support the market for consumer semiconductor devices can be reduced (e.g., semiconductor processing tools, labor, raw materials, and / or computing resources can be reduced).

[0149] As described in more detail above, some embodiments described herein provide a structure. The structure includes a first conductive layer. The structure includes a dielectric layer on the first conductive layer. The structure includes a second conductive layer on the dielectric layer, the second conductive layer having a gap region over a portion of the first conductive layer. The structure includes a third conductive layer, the third conductive layer including a portion of the gap region. The structure includes an interconnect structure passing through the portion of the third conductive layer in the gap region, through the dielectric layer, and into the first conductive layer. The structure includes a sidewall layer surrounding the interconnect structure, passing through the portion of the third conductive layer in the gap region, through the dielectric layer, and into the first conductive layer.

[0150] In some embodiments, the sidewall layer includes a conductive material that electrically couples the interconnect structure to the first conductive layer and the third conductive layer.

[0151] In some embodiments, the thicknesses of the first conductive layer and the second conductive layer are in the range of about 100 angstroms to about 200 angstroms.

[0152] In some embodiments, the thickness of the sidewall layer is in the range of about 50 angstroms to about 1000 angstroms.

[0153] In some embodiments, the dielectric layer is a first dielectric layer, and the structure further includes a second dielectric layer on the second conductive layer, wherein the second dielectric layer coincides with the edge of the second conductive layer defining the gap region to electrically isolate the second conductive layer from the third conductive layer, the interconnect structure, and the sidewall layer.

[0154] In some embodiments, the second dielectric layer is merged with the first dielectric layer beneath the gap region.

[0155] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a metallization layer comprising a first portion and a second portion. The semiconductor device includes a trench capacitor structure comprising at least two vertically aligned positive capacitor electrode layers and at least two vertically aligned negative capacitor electrode layers. The semiconductor device includes a first interconnect structure connecting the at least two vertically aligned positive capacitor electrode layers to the first portion. The semiconductor device includes a second interconnect structure connecting the at least two vertically aligned negative capacitor electrode layers to the second portion.

[0156] In some embodiments, the trench capacitor structure further includes a dielectric layer incorporated in a vertically oriented merging region between the common facing surfaces of the top layer of the trench capacitor structure, wherein the first interconnect structure passes through the dielectric layer above the at least two vertically aligned positive capacitor electrode layers.

[0157] In some embodiments, the trench capacitor structure further includes: a dielectric layer that merges in a vertically oriented merging region between the common facing surfaces of the top capacitor electrode layers of the trench capacitor structure, and a gap region in the dielectric layer through which the second interconnect structure passes over the at least two vertically aligned negative capacitor electrode layers.

[0158] In some embodiments, the second interconnect structure passes through the at least two vertically aligned negative capacitor electrode layers to the substrate beneath the at least two vertically aligned negative capacitor electrode layers.

[0159] As described in more detail above, some embodiments described herein provide a method. The method includes forming a stack of trench capacitor structures on a substrate, the trench capacitor structure including a first capacitor electrode layer, a capacitor dielectric layer on the first capacitor electrode layer, and a second capacitor electrode layer above the first capacitor electrode layer. The method includes forming one or more dielectric layers above the stack. This method includes forming cavities through the one or more dielectric layers, through the second capacitor electrode layer, through the capacitor dielectric layer, and into the first capacitor electrode layer. The method includes using the cavities to form multi-electrode connections.

[0160] In some embodiments, forming the stack further includes forming a third capacitor electrode layer on the capacitor dielectric layer, wherein forming the third capacitor electrode layer includes forming a gap region in the third capacitor electrode layer above a portion of the first capacitor electrode layer.

[0161] In some embodiments, forming the third capacitor electrode layer includes: depositing the third capacitor electrode layer on the capacitor dielectric layer; and removing portions of the third capacitor electrode layer using an etching operation to form discontinuous segments in the third capacitor electrode layer corresponding to the gap region.

[0162] In some embodiments, forming the stack includes: using a conformal deposition process to form a second capacitor electrode layer, the conformal deposition process forming a portion of the second capacitor electrode layer in the gap region.

[0163] In some embodiments, forming the cavity through the one or more dielectric layers, through the second capacitor electrode layer, through the capacitor dielectric layer and into the first capacitor electrode layer includes: forming the cavity through the portion of the second capacitor electrode layer in the gap region.

[0164] In some embodiments, forming the multi-electrode connection includes forming a sidewall layer along the inner surface of the cavity.

[0165] In some embodiments, forming the sidewall layer includes forming the sidewall layer by depositing a conductive material that electrically couples the first capacitor electrode layer and the second capacitor electrode layer.

[0166] In some embodiments, forming the multi-electrode connection further includes forming an internal interconnect structure in the cavity on the sidewall layer.

[0167] In some embodiments, forming the interconnect structure includes forming the interconnect structure by depositing a conductive material in the cavity on the sidewall layer.

[0168] In some embodiments, the method further includes: forming a metallization layer over the one or more dielectric layers; and performing a cleaning operation, wherein the voltage drop between the metallization layer and the substrate is reduced by using the multi-electrode connection to reduce the likelihood of metal island corrosion defects induced by vertical interconnect access to at least one of the metallization layer, the interconnect structure, the first capacitor electrode layer, or the second capacitor electrode layer due to the cleaning operation.

[0169] As used herein, the term "and / or" when used in conjunction with multiple items is intended to cover each of the multiple items individually, as well as any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A and not B", and "B and not A".

[0170] As used in this article, "meeting the threshold" can refer to a value greater than, greater than or equal to, less than, less than or equal to, or equal to the threshold, depending on the context.

[0171] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A trench capacitor structure, characterized in that, include: First conductive layer; A dielectric layer is disposed on the first conductive layer; The second conductive layer has a gap region located above a portion of the first conductive layer on the dielectric layer; The third conductive layer includes a portion located in the gap region; An interconnect structure passes through the portion of the third conductive layer in the gap region, passes through the dielectric layer, and enters the first conductive layer; as well as The sidewall layer surrounds the interconnect structure and passes through the portion of the third conductive layer in the gap region, through the dielectric layer, and into the first conductive layer.

2. The trench capacitor structure of claim 1, wherein, The sidewall layer includes a conductive material that electrically couples the interconnect structure to the first conductive layer and the third conductive layer.

3. The trench capacitor structure according to claim 1, characterized in that, The thicknesses of the first conductive layer and the second conductive layer are in the range of about 100 angstroms to about 200 angstroms.

4. The trench capacitor structure according to claim 1, characterized in that, The thickness of the sidewall layer is in the range of about 50 angstroms to about 1000 angstroms.

5. The trench capacitor structure of claim 1, wherein, The dielectric layer is a first dielectric layer, and the structure further includes: The second dielectric layer is located on the second conductive layer. The second dielectric layer coincides with the edge of the second conductive layer that defines the gap region, so as to electrically isolate the second conductive layer from the third conductive layer, the interconnect structure and the sidewall layer.

6. The trench capacitor structure of claim 5, wherein, The second dielectric layer merges with the first dielectric layer beneath the gap region.

7. A semiconductor device, characterized by comprising: include: Metallization layer, including: Part One; and Part Two; The trench capacitor structure includes: Two vertically arranged positive polarity capacitor electrode layers, including a first conductive layer and a second conductive layer; A dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer and having a gap region located above a portion of the first conductive layer; and Two vertically arranged negative polarity capacitor electrode layers, including a third conductive layer and a fourth conductive layer, wherein the third conductive layer includes a portion located in the gap region; A first interconnect structure connects the two vertically arranged positive capacitor electrode layers to the first portion; and The second interconnect structure connects the two vertically arranged negative capacitor electrode layers to the second part.

8. The semiconductor device according to claim 7, characterized in that, The trench capacitor structure also includes: The merging layer is located in a vertically oriented merging region between the common facing surfaces of the top layer of the trench capacitor structure. The first interconnect structure passes through the merged layer above the two vertically arranged positive capacitor electrode layers.

9. The semiconductor device according to claim 7, characterized in that, The trench capacitor structure also includes: A merging layer, which merges in a vertically oriented merging region between the common facing surfaces of the top capacitor electrode layers of the trench capacitor structure, and The second interconnect structure passes through the gap region in the merged layer above the two vertically arranged negative capacitor electrode layers.

10. The semiconductor device according to claim 7, wherein The second interconnect structure passes through the two vertically arranged negative capacitor electrode layers to reach the substrate below the two vertically arranged negative capacitor electrode layers.

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