Network-to-JTAG / URAT circuit, radar assembly and radar system

Abstract

The utility model discloses a network to JTAG / URAT circuit, radar assembly and radar system, the circuit comprises a network interface, a USB to Ethernet controller chip, a USB to JTAG / URAT chip, a first clock circuit and a second clock circuit, the network interface is connected with the USB to Ethernet controller chip, the USB to Ethernet controller chip is connected with the USB to JTAG / URAT chip, the first clock circuit is connected with the USB to JTAG / URAT chip, and the second clock circuit is connected with the USB to JTAG / URAT chip. The first clock circuit is connected with the USB to Ethernet controller chip, and the second clock circuit is connected with the USB to JTAG / URAT chip. According to the utility model, remote JTAG debugging and serial port communication of the radar assembly can be realized, time resources and manpower resources are saved, and the debugging efficiency of a radar system is improved.

Description

Technical Field

[0001] This utility model belongs to the field of communication technology, and in particular relates to a network to JTAG / URAT circuit, radar components and radar system. Background Technology

[0002] A dual-polarization phased array weather radar system comprises numerous components, such as transceiver components, waveform generation components, timing generation components, frequency synthesis components, and A / D conversion components. These components may be designed by different engineers. During the commissioning of subsystems and the entire radar system, cross-component joint diagnostics are frequently required. This necessitates collaboration among designers of multiple components to pinpoint the problem, making the diagnostic process serial. Furthermore, during routine maintenance, frontline maintenance personnel often only possess basic fault-handling skills; specialized faults require on-site intervention by expert teams (e.g., component designers). Additionally, to meet the demands of upgrading meteorological target recognition algorithms and enhancing anti-interference capabilities, appropriate radar systems are selected for program verification. This verification process frequently necessitates program modifications, also requiring on-site intervention by expert teams. These on-site interventions result in low commissioning efficiency and high costs for both subsystems and the entire radar system. Utility Model Content

[0003] The purpose of this invention is to provide a network-to-JTAG / URAT circuit, radar components, and radar system to solve the problems of low debugging efficiency and high debugging costs caused by the need for on-site processing in traditional radar debugging methods.

[0004] This utility model solves the above-mentioned technical problems through the following technical solution: A network to JTAG / URAT circuit includes a network interface, a USB to Ethernet controller chip, a USB to JTAG / URAT chip, a first clock circuit, and a second clock circuit. The network interface is connected to the USB to Ethernet controller chip, the USB to Ethernet controller chip is connected to the USB to JTAG / URAT chip, the first clock circuit is connected to the USB to Ethernet controller chip, and the second clock circuit is connected to the USB to JTAG / URAT chip.

[0005] Each radar component integrates a network-to-JTAG / URAT circuit, and the radar component is connected to the JTAG and URAT interfaces in the network-to-JTAG / URAT circuit. When on-site troubleshooting is required, the expert team can remotely debug the radar component through the network-to-JTAG / URAT circuit, avoiding the problems of low debugging efficiency and high debugging costs caused by sending an expert team to handle most special faults on-site.

[0006] Furthermore, the network-to-JTAG / URAT circuit also includes an electrostatic discharge (ESD) protection chip, which is located between the network interface and the USB-to-Ethernet controller chip.

[0007] Furthermore, the network-to-JTAG / URAT circuit also includes a first memory, which is connected to the USB-to-Ethernet controller chip.

[0008] Furthermore, the network-to-JTAG / URAT circuit also includes a second memory, which is connected to the USB-to-JTAG / URAT chip.

[0009] Based on the same concept, this utility model also provides a radar component, in which a network to JTAG / URAT circuit as described above is integrated, and the radar component is connected to the USB to JTAG / URAT chip in the network to JTAG / URAT circuit.

[0010] Currently, there are no readily available network-to-JTAG / URAT circuits on the market. This invention designs a network-to-JTAG / URAT circuit and integrates it into the radar assembly, thus avoiding the problem of a significant increase in radar assembly size due to the addition of the network-to-JTAG / URAT circuit.

[0011] Based on the same concept, this utility model also provides a radar system, which includes multiple radar components. Each radar component integrates the network-to-JTAG / URAT circuit as described above, and the radar component is connected to the USB-to-JTAG / URAT chip in the network-to-JTAG / URAT circuit.

[0012] Compared with the prior art, the advantages of this utility model are:

[0013] The network-to-JTAG / URAT circuit provided by this invention can be integrated into the radar assembly, enabling expert teams to directly perform remote JTAG debugging and serial communication via the network. This facilitates remote positioning, debugging, troubleshooting, and fault resolution, saving time and manpower, improving the debugging efficiency of the radar system, and avoiding the problem of a significant increase in size caused by adding a network-to-JTAG / URAT circuit. Attached Figure Description

[0014] To more clearly illustrate the technical solution of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a structural block diagram of the network-to-JTAG / URAT circuit in an embodiment of this utility model;

[0016] Figure 2 This is a circuit diagram of the network interface in an embodiment of this utility model;

[0017] Figure 3 This is a schematic diagram of the peripheral circuit of the USB to Ethernet controller chip in this embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of the peripheral circuit of the USB to JTAG / URAT chip in this embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of remote debugging in an embodiment of this utility model. Detailed Implementation

[0020] The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0021] like Figures 1 to 4 As shown, the network-to-JTAG / URAT circuit provided in this embodiment includes a network interface P2, a USB-to-Ethernet controller chip U1, a USB-to-JTAG / URAT chip U3, a first clock circuit, and a second clock circuit. The network interface P2 is connected to the USB-to-Ethernet controller chip U1, the USB-to-Ethernet controller chip U1 is connected to the USB-to-JTAG / URAT chip U3, the first clock circuit is connected to the USB-to-Ethernet controller chip U1, and the second clock circuit is connected to the USB-to-JTAG / URAT chip U3.

[0022] Network interface P2 is used for wired network access; the USB to JTAG / URAT chip U3 is a dual-channel USB, enabling hardware conversion between local USB and URAT interfaces, and between USB and JTAG interfaces. Network interface P2 connects to the Ethernet PHY interface of the USB to Ethernet controller chip U1, conforming to the IEEE 802.3 protocol specification, compatible with IEEE 802.3 10Base-T and 100Base-TX protocol standards, and supporting auto-negotiation and Auto-MDIX.

[0023] like Figure 3As shown, the first clock circuit includes an external crystal oscillator X1, which is connected to the XI and XO pins of the USB-to-Ethernet controller chip U1. It generates a 480MHz clock required for the USB physical layer interface, a 125MHz clock required for the Ethernet physical layer interface, and the clock for the core of the USB-to-Ethernet controller chip U1 via a phase-locked loop. Figure 4 As shown, the second clock includes an external crystal oscillator X2, which is connected to the OSCI and OSCO pins of the USB to JTAG / URAT chip U3, providing the 12MHz clock required by the USB to JTAG / URAT chip U3.

[0024] In a specific embodiment of this utility model, such as Figure 2 As shown, the network to JTAG / URAT circuit also includes an electrostatic discharge (ESD) protection chip T1, which is located between the network interface P2 and the USB to Ethernet controller chip U1 to provide ESD protection.

[0025] In a specific embodiment of this invention, the network-to-JTAG / URAT circuit further includes a first memory U2, which is connected to the USB-to-Ethernet controller chip U1. The first memory U2 is an SPI Flash. The USB-to-Ethernet controller chip U1 has two user configuration loading modes: manufacturer configuration and loading from SPI Flash. This invention supports external SPI Flash and the use of manufacturer-preset configuration data, including MAC configuration information and USB configuration information, etc.

[0026] In a specific embodiment of this utility model, the network-to-JTAG / URAT circuit further includes a second memory U4, which is connected to the USB-to-JTAG / URAT chip U3. The second memory U4 is an EEPROM. The EEPROM can be programmed via USB using FT_PROG (software tool).

[0027] In a specific embodiment of this utility model, the USB-to-Ethernet controller chip U1 is selected from models CH397F, AX88179A, or RTL8153; the USB-to-JTAG / URAT chip U3 is selected from models FT2232, FT232H, or CH347. The USB-to-Ethernet controller chip U1 integrates a USB high-speed device controller and a USB-PHY transceiver, supporting high-speed and full-speed operation according to the USB 2.0 / USB 2.1 specifications. Its UDP (Data Plus) and UDM (Data Minus) are connected to the DP (Data Plus) and DM (Data Minus) of the USB-to-JTAG / URAT chip U3 for USB communication. The USB-to-JTAG / URAT chip U3 has two Multiprotocol Synchronous Serial Engines (MPSSE), enabling simultaneous USB-to-URAT data transmission and USB-to-JTAG functionality.

[0028] like Figure 5 As shown, the radar component provided by this utility model integrates a network-to-JTAG / URAT circuit as described in this embodiment. The JTAG debugging interface of the radar component is connected to the JTAG terminal of the USB-to-JTAG / URAT chip U3 in the network-to-JTAG / URAT circuit, and the URAT debugging interface of the radar component is connected to the URAT terminal of the USB-to-JTAG / URAT chip U3 in the network-to-JTAG / URAT circuit. When an expert team needs to debug the radar component, the expert team can directly achieve remote JTAG debugging and serial communication via the network, eliminating the need for on-site processing by the expert team. This avoids the problems of long travel time and high costs for the expert team and improves debugging efficiency.

[0029] like Figure 5 As shown, the radar system provided by this utility model includes multiple radar components. Each radar component integrates a network-to-JTAG / URAT circuit as described in this embodiment. The JTAG debugging interface of the radar component is connected to the JTAG terminal of the USB-to-JTAG / URAT chip U3 in the network-to-JTAG / URAT circuit, and the URAT debugging interface of the radar component is connected to the URAT terminal of the USB-to-JTAG / URAT chip U3 in the network-to-JTAG / URAT circuit. Each radar component can achieve remote JTAG debugging and serial communication. Through the cooperation of an expert team and on-site maintenance personnel, in most cases, accurate and rapid fault location and resolution can be achieved without dispatching an expert team. Simultaneously, program verification for algorithm upgrades and improved anti-interference capabilities is also more convenient.

[0030] The above description only discloses specific embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or modifications that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model should be included within the protection scope of the present utility model.

Claims

1. A network-to-JTAG / URAT circuit, characterized in that, The network-to-JTAG / URAT circuit includes a network interface, a USB-to-Ethernet controller chip, a USB-to-JTAG / URAT chip, a first clock circuit, and a second clock circuit. The network interface is connected to the USB-to-Ethernet controller chip, the USB-to-Ethernet controller chip is connected to the USB-to-JTAG / URAT chip, the first clock circuit is connected to the USB-to-Ethernet controller chip, and the second clock circuit is connected to the USB-to-JTAG / URAT chip.

2. The network-to-JTAG / URAT circuit according to claim 1, characterized in that, The network-to-JTAG / URAT circuit also includes an electrostatic discharge (ESD) protection chip, which is located between the network interface and the USB-to-Ethernet controller chip.

3. The network-to-JTAG / URAT circuit according to claim 1, characterized in that, The network-to-JTAG / URAT circuit also includes a first memory, which is connected to the USB-to-Ethernet controller chip.

4. The network-to-JTAG / URAT circuit according to claim 1, characterized in that, The network-to-JTAG / URAT circuit also includes a second memory, which is connected to the USB-to-JTAG / URAT chip.

5. A radar assembly, characterized in that, The radar assembly integrates a network-to-JTAG / URAT circuit as described in any one of claims 1 to 4, and the radar assembly is connected to a USB-to-JTAG / URAT chip in the network-to-JTAG / URAT circuit.

6. A radar system comprising a plurality of radar components, characterized in that, Each radar component integrates a network-to-JTAG / URAT circuit as described in any one of claims 1 to 4, and the radar component is connected to a USB-to-JTAG / URAT chip in the network-to-JTAG / URAT circuit.

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