A multi-interface solution board suitable for a HAPS prototype verification platform

Abstract

The utility model provides a kind of multi-interface scheme board suitable for HAPS prototype verification platform, the scheme board of the utility model is based on the interface condition of HAPS-100 platform, using HapsTrak 3 connector and expands multiple external interfaces, the connection of different interface types external device and HAPS-100 platform is realized, the diversified demand under different application scenarios is satisfied, and development cost is reduced.The scheme board of the utility model has multiple lapping modes on HAPS-100 platform, has greater degree of freedom when selecting interface resources, improves the debugging efficiency of HAPS-100 platform.Scheme board uses the HapsTrak 3 connector of HT3 standard protocol to ensure good adaptability with HAPS-100 platform, guarantee the stability and reliability of signal transmission, also use standard MGB2 interface and connect with HAPS-100 platform through cable line, provide flexible connection mode.

Description

Technical Field

[0001] This utility model relates to the field of prototype verification technology, and in particular to a multi-interface solution board suitable for the HAPS prototype verification platform. Background Technology

[0002] Currently, Synopsys provides a variety of powerful tools to support the HAPS-100 platform, such as Synplify, Identity, and Protocompiler. These tools are natively compatible with the HAPS-100 platform, greatly improving the ease of use of the EDA (Electronic Design Automation) workflow. Simultaneously, Synopsys has built a comprehensive ecosystem, providing users with abundant supporting resources, among which the IP Prototyping Package (IPK) is particularly crucial. This package helps developers quickly integrate and verify various interface IPs, effectively shortening the debugging cycle of interface IPs, improving development efficiency, reducing development costs, and providing strong support for complex integrated circuit designs.

[0003] The HAPS-100 platform utilizes numerous HapsTrak 3 connectors, providing a foundation for its scalability and connectivity, and meeting device connectivity needs in certain scenarios. However, with the increasing diversity of electronic device interfaces, developers often face diverse interface debugging requirements when verifying and debugging devices under test (DUTs). In practical applications, due to the limitations of the existing connector design on the HAPS-100 platform, it cannot directly adapt to various DUTs with different interfaces. Developers must design and manufacture adapter boards separately for each different interface to achieve connection and debugging with the HAPS-100 platform. This approach not only significantly increases development costs, including material and labor costs, but also significantly extends the project cycle, increasing time costs. Utility Model Content

[0004] In view of the shortcomings of the prior art, this utility model provides a multi-interface solution board suitable for the HAPS prototype verification platform, which solves the problem that the HAPS-100 platform cannot directly adapt to various types of devices under test with different interfaces, thus increasing development costs.

[0005] To achieve the above and other related objectives, the first aspect of this utility model provides a multi-interface solution board suitable for the HAPS prototype verification platform, comprising:

[0006] Several HapsTrak 3 connectors for connecting to the HAPS prototyping platform;

[0007] The first MGB2 interface is used to connect to the HAPS prototype verification platform via a cable.

[0008] Multiple external interfaces for connecting to corresponding external devices;

[0009] The plurality of HapsTrak 3 connectors are respectively connected to the plurality of external interfaces and the first MGB2 interface.

[0010] In some embodiments of the first aspect of this utility model, the plurality of external interfaces include a JTAG interface, an NVMe M.2 interface, a GPIO interface, an I2C interface, a UART2USB interface, an RJ45 interface, an SD interface, a UART interface, a QSPI interface, and an SPI interface.

[0011] In some embodiments of the first aspect of this utility model, the multi-interface solution board is further provided with LEDs and buttons.

[0012] In some embodiments of the first aspect of this utility model, the multi-interface solution board is further provided with a DC interface; the DC interface is used to connect to an external power source.

[0013] In some embodiments of the first aspect of this utility model, the multi-interface solution board is further provided with a memory.

[0014] In some embodiments of the first aspect of this utility model, the memory employs an eMMC memory chip.

[0015] In some embodiments of the first aspect of this utility model, the plurality of HapsTrak 3 connectors are adapted to connect to the HapsTrak interface of the HAPS prototype verification platform.

[0016] In some embodiments of the first aspect of this utility model, the first MGB2 interface is adapted and connected to the second MGB2 interface of the HAPS prototype verification platform.

[0017] In some embodiments of the first aspect of this utility model, the first MGB2 interface is also used to connect to a corresponding external device.

[0018] In some embodiments of the first aspect of this utility model, the number of HapsTrak 3 connectors is three.

[0019] As described above, the multi-interface solution board for the HAPS prototype verification platform provided by this utility model has the following beneficial effects:

[0020] This utility model's solution board, based on the interface configuration of the HAPS-100 platform, utilizes a HapsTrak 3 connector and expands with various external interfaces, enabling connections between external devices of different interface types and the HAPS-100 platform. This meets diverse needs in various application scenarios and reduces development costs. The solution board offers multiple connection methods on the HAPS-100 platform, providing greater flexibility in interface resource selection and improving debugging efficiency. The use of the HT3 standard protocol HapsTrak 3 connector ensures good compatibility with the HAPS-100 platform, guaranteeing stable and reliable signal transmission. It also employs a standard MGB2 interface and connects to the HAPS-100 platform via a cable, providing flexible connection options. Attached Figure Description

[0021] Figure 1 The diagram shown is a structural schematic of a multi-interface solution board suitable for the HAPS prototype verification platform according to an embodiment of this utility model.

[0022] Figure 2 The diagram shown is a structural schematic of a specific embodiment of a multi-interface solution board suitable for the HAPS prototype verification platform according to one embodiment of the present invention.

[0023] Component designation explanation

[0024] 100 Solution Board

[0025] 110 HapsTrak 3 connector

[0026] 120 First MGB2 interface

[0027] 1301 JTAG Interface

[0028] 1302 NVMe M.2 interface

[0029] 1303 GPIO interface

[0030] 1304 I2C interface

[0031] 1305 UART2USB interface

[0032] 1306 RJ45 interface

[0033] 1307 SD Interface

[0034] 1308 UART interface

[0035] 1309 QSPI interface

[0036] 1310 SPI interface

[0037] 140 LED

[0038] 150 Button

[0039] 160 DC interface

[0040] 170 Memory

[0041] 200 HAPS Prototype Verification Platform

[0042] 210 HapsTrak Interface

[0043] 220 Second MGB2 Interface Detailed Implementation

[0044] The following specific embodiments illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification.

[0045] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation of this utility model. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this utility model, should still fall within the scope of the technical content disclosed in this utility model. The following detailed description should not be considered restrictive, and the scope of the embodiments of this application is limited only by the claims of the published patents. The terminology used herein is for describing specific embodiments only and is not intended to limit this application. Spatial terms such as "upper," "lower," "left," "right," "below," "below," "lower part," "above," "upper part," etc., may be used in the text to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0046] In this utility model, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0047] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0048] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions in the embodiments of this utility model are further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this utility model and are not intended to limit the utility model.

[0049] like Figures 1 to 2 The diagram shows a structural schematic of a multi-interface solution board 100 suitable for a HAPS prototype verification platform according to an embodiment of the present invention. The multi-interface solution board 100 for a HAPS prototype verification platform in this embodiment includes:

[0050] Several HapsTrak 3 connectors 110 are used for connection to the HAPS prototype verification platform 200;

[0051] The first MGB2 interface 120 is used to connect to the HAPS prototype verification platform 200 via a cable;

[0052] Multiple external interfaces for connecting to corresponding external devices;

[0053] The plurality of HapsTrak 3 connectors 110 are respectively connected to the plurality of external interfaces and the first MGB2 interface 120.

[0054] The multi-interface solution board 100 in this embodiment can be used to connect multiple external devices to the HAPS prototype verification platform 200. The solution board 100 is equipped with several HapsTrak 3 connectors 110, which are used to connect to the HAPS prototype verification platform 200. The solution board 100 also has multiple external interfaces, which are used to connect to corresponding external devices.

[0055] The connection relationships on the solution board 100 are as follows: several HapsTrak 3 connectors 110 are connected to each external interface, and several HapsTrak 3 connectors 110 are connected to the first MGB2 interface 120. Further, the external interfaces connect to external devices, and the several HapsTrak 3 connectors 110 connect to the HAPS prototype verification platform 200, thereby realizing the connection between the external devices and the solution board 100, and between the solution board 100 and the HAPS prototype verification platform 200. Therefore, by connecting the external devices and the HAPS prototype verification platform 200 through the solution board 100, the solution board 100 can transmit signals and data from the external devices to the HAPS prototype verification platform 200, and vice versa.

[0056] The external devices include FPGAs, microcontrollers, NVMe solid-state drives, GPIO interface devices, EEPROM memory, serial port devices, Ethernet devices, SD memory cards, microcontroller development boards, QSPI Flash memory, SPI Flash memory, etc. In this embodiment, the type of external device is not limited; the corresponding external interface is selected and configured according to the actual situation.

[0057] In this embodiment, the solution board 100 is connected to the HAPS prototype verification platform 200 through several HapsTrak 3 connectors 110, and connects to corresponding external devices through multiple external interfaces, thereby enabling various types of external devices to connect and interact with the HAPS prototype verification platform 200 through the solution board 100. The number and type of external interfaces in this embodiment can be configured according to actual needs to meet the connection requirements of different types of external devices.

[0058] The solution board 100 also features a first MGB2 interface 120, which connects to the HAPS prototype verification platform 200 via a cable. This indicates that the solution board 100 can connect to the HAPS prototype verification platform 200 not only through several HapsTrak 3 connectors 110, but also through the first MGB2 interface 120. The solution board 100 offers two connection methods to the HAPS prototype verification platform 200, increasing the flexibility and reliability of the connection.

[0059] In some examples, the model of the first MGB2 interface is ARF6-16-S-RA-TR.

[0060] In some examples, several HapsTrak 3 connectors 110 are disposed on the bottom side of the solution board 100, and the first MGB2 interface 120 and multiple external interfaces are disposed on the top side of the solution board 100.

[0061] It should be noted that the solution board 100 has a bottom surface and a top surface. Several HapsTrak 3 connectors are located on the bottom surface of the solution board 100, while the first MGB2 interface and multiple external interfaces are located on the top surface. This layout design effectively optimizes the space utilization of the solution board, making the connectors more compact and reasonable within a limited space, reducing space waste. Furthermore, this layout facilitates the connection operation between the solution board and the FPGA platform or related boards.

[0062] In one embodiment, the plurality of HapsTrak 3 connectors 110 are adapted to connect to the HapsTrak interface (HT interface in the figure) of the HAPS prototype verification platform 200.

[0063] In this embodiment, the HAPS prototyping platform is the HAPS-100, an FPGA-based prototyping system particularly suitable for prototyping large-scale chip designs requiring FPGA expansion. The HAPS-100 allows chip designers, software developers, and verification engineers to communicate across regions and job categories, resulting in greater scale, higher performance, higher debugging efficiency, and lower cost. The HAPS-100 platform includes multiple HapsTrak interfaces, which are HapsTrak 3 connectors; that is, the HAPS-100 platform includes multiple HapsTrak 3 connectors.

[0064] like Figure 2 As shown, in this embodiment, the number of HapsTrak 3 connectors on the solution board 100 is three. The spacing between each adjacent HapsTrak 3 connector on the solution board 100 is the same as the spacing between each adjacent HapsTrak 3 connector on the HAPS-100 platform, achieving structural adaptation and ensuring the stability of the connection between the solution board and the HAPS-100 platform.

[0065] Because the spacing between adjacent HapsTrak 3 connectors is the same, the three HapsTrak 3 connectors on the solution board 100 can overlap with any three adjacent HapsTrak 3 connectors on the HAPS-100 platform. This embodiment does not limit the specific overlap method; it can be selected according to actual needs. For example, if there are ten HapsTrak 3 connectors on the HAPS-100 platform, the three HapsTrak 3 connectors on the solution board 100 can overlap with any three adjacent HapsTrak 3 connectors among those ten. This flexible overlap method can meet different application scenarios and requirements.

[0066] In some examples, the HapsTrak 3 connector on solution board 100 is model number SEAM-20-020-L-08-1-AK-TR.

[0067] In one embodiment, the first MGB2 interface 120 is adapted to and connected to the second MGB2 interface 220 of the HAPS prototype verification platform 200.

[0068] It should be noted that the interfaces on the HAPS-100 platform include not only the HapsTrak interface 210, but also the second MGB2 interface 220. Therefore, the solution board 100 can be connected to the HAPS prototype verification platform 200 not only through several HapsTrak 3 connectors 110, but also through the first MGB2 interface 120. A cable connects the first MGB2 interface 120 on the solution board 100 and the second MGB2 interface 220 on the HAPS prototype verification platform 200, enabling connection between the solution board 100 and the HAPS prototype verification platform 200.

[0069] The external interface on the solution board 100 is connected to an external device. The first MGB2 interface 120 on the solution board 100 is connected to the HAPS prototype verification platform 200. The external interface and the first MGB2 interface 120 are connected through the HapsTrak 3 connector 110, thereby enabling the external device to connect to the HAPS prototype verification platform 200 through the solution board 100.

[0070] In one embodiment, the first MGB2 interface 120 is also used to connect to a corresponding external device.

[0071] It needs to be explained that, such as Figure 1As shown, the first MGB2 interface 120 can be connected to the second MGB2 interface 220 of the HAPS prototype verification platform 200 via a cable, thereby enabling the connection between the solution board 100 and the HAPS prototype verification platform 200. In addition, the first MGB2 interface 120 can also be used to connect external devices. Specifically, the first MGB2 interface 120 is connected to several HapsTrak 3 connectors 110 on the solution board 100, the several HapsTrak 3 connectors 110 are connected to the HAPS prototype verification platform 200, and the first MGB2 interface 120 is connected to the corresponding external device. This external device communicates with the HAPS prototype verification platform 200 through the solution board 100.

[0072] For example, when an external device with an MGB2 interface is present, the first MGB2 interface 120 on the solution board 100 is connected to the external device with the MGB2 interface, and several HapsTrak 3 connectors 110 are connected to the HAPS prototype verification platform 200. Thus, the solution board 100 can enable the connection between the external device with the MGB2 interface and the HAPS prototype verification platform 200. In one embodiment, as... Figure 1 and Figure 2 As shown, the multiple external interfaces include a JTAG interface 1301, an NVMe M.2 interface 1302, a GPIO interface 1303, an I2C interface 1304, a UART2USB interface 1305, an RJ45 interface 1306, an SD interface 1307, a UART interface 1308, a QSPI interface 1309, and an SPI interface 1310.

[0073] It should be noted that the external devices include FPGAs, microcontrollers, NVMe solid-state drives, GPIO interface devices, EEPROM memory, serial port devices, Ethernet devices, SD memory cards, microcontroller development boards, QSPI Flash memory, SPI Flash memory, etc.

[0074] In this embodiment, the JTAG interface 1301 can be connected to an FPGA or microcontroller, the NVMe M.2 interface 1302 can be connected to an NVMe solid-state drive, the GPIO interface 1303 can be connected to a GPIO interface device, the I2C interface 1304 can be connected to an EEPROM memory, the UART2USB interface 1305 can be connected to a serial port device, the RJ45 interface 1306 can be connected to an Ethernet device, the SD interface 1307 can be connected to an SD memory card, the UART interface 1308 can be connected to a microcontroller development board, the QSPI interface 1309 can be connected to a QSPI Flash memory, and the SPI interface 1310 can be connected to an SPI Flash memory.

[0075] The JTAG interface uses the Jianniu 2.54-2x10P model.

[0076] The NVMe M.2 interface supports the NVMe protocol and is a high-speed storage interface. The model number of the NVMe M.2 interface is 91302-55-067R2M, ​​which supports both 2240 and 2280 M.2 cards.

[0077] The GPIO interface can control external devices through high and low voltage levels.

[0078] The I2C interface consists of four groups, model number XFCN PZ254V-11-10P.

[0079] The UART2USB interface consists of three sets, used to convert between the UART protocol and the USB protocol.

[0080] The RJ45 interface consists of an RJ45 connector and a PHY chip. The RJ45 connector is a HANRUN HR911130C, and the PHY chip is a REALTEK RTL8211F-CG. The RJ45 connector, as the physical interface, is responsible for inserting the network cable and connecting it to external devices to achieve the physical transmission of Ethernet signals. The PHY chip, as a physical layer transceiver, is responsible for converting the analog signals received by the RJ45 connector into digital signals and transmitting them to several HapsTrak 3 connectors on the solution board.

[0081] The SD interface consists of an SD connector and a TF card chip. The SD connector is an ATOM MR01A-01211, and the TF card chip is a TI LSF0108PWR.

[0082] The UART interface consists of three groups, used for sending or receiving serial data.

[0083] The QSPI interface is used to access data in the QSPI flash memory, enabling data storage and retrieval.

[0084] Multiple external interfaces are set on the solution board 100, and communication and interaction between the HAPS prototype verification platform 200 and various types of external devices can be realized through the solution board 100 alone.

[0085] In one embodiment, the multi-interface solution board 100 is further provided with LEDs 140 and Buttons 150. There are four groups of LEDs 140 and four groups of Buttons 150.

[0086] In one embodiment, the multi-interface solution board 100 is further provided with a DC interface 160; the DC interface 160 is used to connect an external power source to supply power to the solution board 100.

[0087] In one embodiment, the multi-interface solution board 100 is further provided with a memory 170. The memory 170 is connected to a plurality of HapsTrak 3 connectors 110.

[0088] In one embodiment, the memory 170 uses an eMMC memory chip. The eMMC memory chip is a Samsung KLM8G1GETF-B041.

[0089] In summary, this utility model provides a multi-interface solution board suitable for the HAPS prototype verification platform. It includes: a plurality of HapsTrak 3 connectors for connecting to the HAPS prototype verification platform; a first MGB2 interface for connecting to the HAPS prototype verification platform via a cable; and multiple external interfaces for connecting to corresponding external devices; wherein the plurality of HapsTrak 3 connectors are respectively connected to the multiple external interfaces and the first MGB2 interface.

[0090] This invention's solution board, based on the interface configuration of the HAPS-100 platform, utilizes a HapsTrak 3 connector and expands with various external interfaces, enabling connections between external devices of different interface types and the HAPS-100 platform. This meets diverse needs in various application scenarios and reduces development costs. The solution board offers multiple connection methods on the HAPS-100 platform, providing greater flexibility in interface resource selection and improving debugging efficiency. The use of the HT3 standard protocol HapsTrak 3 connector ensures good compatibility with the HAPS-100 platform, guaranteeing stable and reliable signal transmission. It also employs a standard MGB2 interface and connects to the HAPS-100 platform via a cable, providing flexible connection options. Therefore, this invention effectively overcomes the shortcomings of existing technologies and possesses high industrial applicability.

[0091] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A multi-interface solution board suitable for the HAPS prototype verification platform, characterized in that, include: Several HapsTrak 3 connectors for connecting to the HAPS prototyping platform; The first MGB2 interface is used to connect to the HAPS prototype verification platform via a cable. Multiple external interfaces for connecting to corresponding external devices; The plurality of HapsTrak 3 connectors are respectively connected to the plurality of external interfaces and the first MGB2 interface.

2. The multi-interface solution board for the HAPS prototype verification platform according to claim 1, characterized in that, The multiple external interfaces include JTAG interface, NVMe M.2 interface, GPIO interface, I2C interface, UART2USB interface, RJ45 interface, SD interface, UART interface, QSPI interface, and SPI interface.

3. The multi-interface solution board suitable for the HAPS prototype verification platform according to claim 1, characterized in that, The multi-interface solution board is also equipped with LEDs and buttons.

4. The multi-interface solution board suitable for the HAPS prototype verification platform according to claim 1, characterized in that, The multi-interface solution board is also equipped with a DC interface; the DC interface is used to connect to an external power source.

5. The multi-interface solution board suitable for the HAPS prototype verification platform according to claim 1, characterized in that, The multi-interface solution board is also equipped with a memory.

6. The multi-interface solution board suitable for the HAPS prototype verification platform according to claim 5, characterized in that, The memory uses an eMMC storage chip.

7. The multi-interface solution board suitable for the HAPS prototype verification platform according to claim 1, characterized in that, The plurality of HapsTrak 3 connectors are adapted and connected to the HapsTrak interface of the HAPS prototype verification platform.

8. The multi-interface solution board for the HAPS prototype verification platform according to claim 1, characterized in that, The first MGB2 interface is adapted and connected to the second MGB2 interface of the HAPS prototype verification platform.

9. The multi-interface solution board for the HAPS prototype verification platform according to claim 1, characterized in that, The first MGB2 interface is also used to connect to a corresponding external device.

10. The multi-interface solution board for the HAPS prototype verification platform according to claim 1, characterized in that, The number of HapsTrak 3 connectors is three.

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