Bias circuit and chip

Abstract

The utility model discloses a bias circuit and a chip, the bias circuit comprises: a first current mirror image unit, a first isolation tube, a second isolation tube and a current compensation unit, the first current mirror image unit mirrors an input current proportionally to generate a first mirror image current and a second mirror image current, the first isolation tube generates a first working current based on the first mirror current, the second isolation tube generates a second working current based on the second mirror current, and the current compensation unit generates a compensation current based on the second working current and a second leakage current generated by the second isolation tube. And the current compensation unit compensates the first leakage current generated by the first isolation tube through the compensation current. According to the biasing circuit and the chip, the first leakage current generated by the first isolation tube is compensated through the compensation current, so that the influence of the first leakage current of the first isolation tube on the output current of the biasing circuit is greatly reduced or even eliminated.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to a bias circuit and chip. Background Technology

[0002] Many chips are now used in high-voltage systems, such as power chips. The application of high-voltage devices is particularly important in these chips, as it affects their main functions and reliability. Compared to low-voltage devices, the PN junctions of high-voltage devices can withstand higher voltages, but this comes at the cost of greater leakage current, especially in high-temperature environments. This non-ideal leakage current is something chip designers want to avoid, and its impact needs to be carefully considered. Many chip failures are often caused by leakage current from high-voltage devices.

[0003] The bias circuit is the reference of the chip. Whether it is a high-voltage circuit or a low-voltage circuit, a stable and accurate bias source is required. The high-voltage chip circuit is often divided into high-voltage domain circuit and low-voltage domain circuit. The bias circuit of the chip is generally made in the low-voltage domain. The bias current needs to be provided to the high-voltage domain circuit through the conversion circuit. The leakage current brought by the high-voltage device used in the conversion circuit will affect the accuracy of the bias current, and thus affect the function of the chip, especially in high-temperature environments or under different process corners. In severe cases, it can cause chip failure.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide a bias circuit and chip that can eliminate the influence of leakage current on the circuit.

[0006] To achieve the above objectives, a specific embodiment of this utility model provides the following technical solution: a bias circuit, comprising: a first current mirror unit, a first isolation transistor, a second isolation transistor, and a current compensation unit. The first current mirror unit is used to proportionally mirror the input current to generate a first mirror current and a second mirror current. The first isolation transistor is connected to the first current mirror unit to generate a first operating current based on the first mirror current. The second isolation transistor is connected to the first current mirror unit to generate a second operating current based on the second mirror current. The current compensation unit is connected to the second isolation transistor to generate a compensation current based on the second operating current and the second leakage current generated by the second isolation transistor. The current compensation unit is connected to the first isolation transistor to compensate for the first leakage current generated by the first isolation transistor through the compensation current.

[0007] In one or more embodiments of the present invention, the bias circuit further includes a second current mirror unit, which is connected to the first isolation tube to proportionally mirror the compensated current to generate an output current.

[0008] In one or more embodiments of the present invention, the first current mirror unit includes a first transistor, a second transistor, and a third transistor. The control terminals of the first transistor, the second transistor, and the third transistor are connected together. The first terminals of the first transistor, the second transistor, and the third transistor are connected to ground voltage. The second terminal of the first transistor is connected to the control terminal of the first transistor to receive input current. The second terminal of the second transistor is connected to the first terminal of the first isolation transistor. The second terminal of the third transistor is connected to the first terminal of the second isolation transistor.

[0009] In one or more embodiments of the present invention, the current mirror ratio of the first transistor, the second transistor and the third transistor is 1:M:N, and M>N>0.

[0010] In one or more embodiments of the present invention, the current compensation unit includes a fourth transistor and a fifth transistor. The control terminal of the fourth transistor, the second terminal of the fourth transistor, and the control terminal of the fifth transistor are connected to the second terminal of the second isolation tube. The first terminal of the fourth transistor and the first terminal of the fifth transistor are connected to the power supply voltage. The second terminal of the fifth transistor is connected to the second terminal of the first isolation tube.

[0011] In one or more embodiments of the present invention, the second current mirror unit includes a sixth transistor and a seventh transistor. The first terminals of the sixth transistor and the seventh transistor are connected to the power supply voltage. The second terminals of the sixth transistor, the control terminal of the sixth transistor, and the control terminal of the seventh transistor are connected to the second terminal of the first isolation transistor. The second terminal of the seventh transistor is used to generate an output current.

[0012] In one or more embodiments of this utility model, the first current mirror unit and / or current compensation unit is a Cascode current mirror.

[0013] In one or more embodiments of this utility model, the second current mirror unit is a Cascode current mirror.

[0014] In one or more embodiments of this invention, the current mirror ratio of the fourth transistor and the fifth transistor is 1:1.

[0015] This utility model also discloses a chip, including the aforementioned bias circuit.

[0016] Compared with the prior art, the bias circuit and chip of this utility model generate a compensation current based on the second operating current of the second isolation tube and the second leakage current generated by the second isolation tube through the current compensation unit. The compensation current compensates for the first leakage current generated by the first isolation tube, thereby greatly reducing or even eliminating the influence of the first leakage current of the first isolation tube on the output current of the bias circuit. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a circuit diagram of the bias circuit in one embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0020] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0021] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0022] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0023] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0024] Various components and devices may be referred to or shown in the singular (e.g., “MOS transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0025] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0026] like Figure 1 As shown, a bias circuit in one embodiment of the present invention includes: a first current mirror unit 10, a first isolation transistor G1, a second isolation transistor G2, a current compensation unit 20, and a second current mirror unit 30.

[0027] The first current mirror unit 10 is used to proportionally mirror the input current Iin to generate a first mirror current and a second mirror current. The first isolation tube G1 is connected to the first current mirror unit 10 to generate a first operating current based on the first mirror current. The first mirror current and the first operating current are equal. The second isolation tube G2 is connected to the first current mirror unit 10 to generate a second operating current based on the second mirror current. The second mirror current and the second operating current are equal.

[0028] The current compensation unit 20 is connected to the second isolation transistor G2 to generate a compensation current based on the second operating current and the second leakage current Ig2 generated by the second isolation transistor G2. The current compensation unit 20 is also connected to the first isolation transistor G1 to compensate for the first leakage current Ig1 generated by the first isolation transistor G1 through the compensation current. The second current mirroring unit 30 is connected to the first isolation transistor G1 to proportionally mirror the compensated current to generate an output current Iout.

[0029] In one embodiment, a second isolation tube G2 is selected based on the first isolation tube G1, and the second leakage current Ig2 generated by the second isolation tube G2 is equal to the first leakage current Ig1 generated by the first isolation tube G1.

[0030] Specifically, such as Figure 1 As shown, the first current mirror unit 10 includes a first transistor M1, a second transistor M2, and a third transistor M3. The control terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are connected. The first terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are connected to ground voltage. The second terminal of the first transistor M1 is connected to the control terminal of the first transistor M1 to receive the input current Iin. The second terminal of the second transistor M2 is connected to the first terminal of the first isolation transistor G1. The second terminal of the third transistor M3 is connected to the first terminal of the second isolation transistor G2.

[0031] In one embodiment, the current mirror ratio of the first transistor M1, the second transistor M2, and the third transistor M3 is 1:M:N, and M>N>0.

[0032] like Figure 1 As shown, the current compensation unit 20 includes a fourth transistor M4 and a fifth transistor M5. The control terminal of the fourth transistor M4, the second terminal of the fourth transistor M4, and the control terminal of the fifth transistor M5 are connected to the second terminal of the second isolation transistor G2. The first terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5 are connected to the power supply voltage. The second terminal of the fifth transistor M5 is connected to the second terminal of the first isolation transistor G1.

[0033] The second current mirror unit 30 includes a sixth transistor M6 and a seventh transistor M7. The first terminal of the sixth transistor M6 and the first terminal of the seventh transistor M7 are connected to the power supply voltage. The second terminal of the sixth transistor M6, the control terminal of the sixth transistor M6, and the control terminal of the seventh transistor M7 are connected to the second terminal of the first isolation transistor G1. The second terminal of the seventh transistor M7 is used to generate the output current Iout.

[0034] In other embodiments, the first current mirror unit 10 and / or the current compensation unit 20 and / or the second current mirror unit 30 are Cascode current mirrors.

[0035] In one embodiment, the current mirror ratio of the fourth transistor M4 and the fifth transistor M5 is 1:1, and the current mirror ratio of the seventh transistor M7 and the sixth transistor M6 is 1:K, where K>0.

[0036] In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the first isolation transistor G1, and the second isolation transistor G2 are N-channel MOSFETs, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are P-channel MOSFETs. In other embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the first isolation transistor G1, and the second isolation transistor G2 are P-channel MOSFETs, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are N-channel MOSFETs.

[0037] The first terminal of the first transistor M1, the first terminal of the second transistor M2, the first terminal of the third transistor M3, the first terminal of the fourth transistor M4, the first terminal of the fifth transistor M5, the first terminal of the sixth transistor M6, the first terminal of the seventh transistor M7, the first terminal of the first isolation transistor G1, and the first terminal of the second isolation transistor G2 are the sources; the second terminals of the first transistor M1, the second terminal of the second transistor M2, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the second terminal of the fifth transistor M5, the second terminal of the sixth transistor M6, the second terminal of the seventh transistor M7, the second terminal of the first isolation transistor G1, and the second terminal of the second isolation transistor G2 are the drains; the control terminals of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the first isolation transistor G1, and the second isolation transistor G2 are the gates.

[0038] The first transistor M1, the second transistor M2, the first isolation transistor G1, the sixth transistor M6, and the seventh transistor M7 form a bias switching circuit, where the first transistor M1, the second transistor M2, the sixth transistor M6, and the seventh transistor M7 are low-voltage transistors. The control terminals of the first isolation transistor G1 and the second isolation transistor G2 receive the control voltage LVDD. The first isolation transistor G1 and the second isolation transistor G2 are high-voltage transistors. The function of the first isolation transistor G1 is to clamp the voltage at its first terminal to LVDD-VGS (VGS is the voltage between the control terminal and the first terminal of the first isolation transistor G1), so that the second transistor M2 is in the low-voltage domain. The side effect of the first isolation transistor G1 is the introduction of a first leakage current Ig1. For this bias switching circuit, the output current Iout = 1 / K*(M*Iin+Ig1).

[0039] The third transistor M3, the fourth transistor M4, and the fifth transistor M5 are low-voltage transistors. The current IM4 on the fourth transistor M4 is equal to the current IM5 on the fifth transistor M5, IM4 = IM5 = N*Iin + Ig2. When the fifth transistor M5 cuts off the branch where the first isolation transistor G1 is located, the output current Iout = 1 / K*(M*Iin + Ig1 - N*Iin - Ig2) = 1 / K*Iin(MN), where M > N, so that Iout is independent of the first leakage current Ig1, thus achieving the purpose of leakage current compensation.

[0040] It should be noted that in this embodiment, the leakage current of the first isolation tube G1 flows from the drain of the first isolation tube G1 through the substrate to ground. In other scenarios, the direction of leakage current is from ground through the substrate to the source of the tube, then the current compensation unit 20 needs to be connected to the source of the first isolation tube G1 to perform leakage current compensation.

[0041] This invention also provides a chip, including the aforementioned bias circuit.

[0042] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0043] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A bias circuit, characterized in that, include: The system comprises a first current mirror unit, a first isolation transistor, a second isolation transistor, and a current compensation unit. The first current mirror unit is used to proportionally mirror the input current to generate a first mirror current and a second mirror current. The first isolation transistor is connected to the first current mirror unit to generate a first operating current based on the first mirror current. The second isolation transistor is connected to the first current mirror unit to generate a second operating current based on the second mirror current. The current compensation unit is connected to the second isolation transistor to generate a compensation current based on the second operating current and the second leakage current generated by the second isolation transistor. The current compensation unit is also connected to the first isolation transistor to compensate for the first leakage current generated by the first isolation transistor through the compensation current.

2. The bias circuit according to claim 1, characterized in that, The bias circuit further includes a second current mirror unit, which is connected to the first isolation tube to proportionally mirror the compensated current to generate an output current.

3. The bias circuit according to claim 1, characterized in that, The first current mirror unit includes a first transistor, a second transistor, and a third transistor. The control terminals of the first transistor, the second transistor, and the third transistor are connected together. The first terminals of the first transistor, the second transistor, and the third transistor are connected to ground voltage. The second terminal of the first transistor is connected to the control terminal of the first transistor to receive input current. The second terminal of the second transistor is connected to the first terminal of the first isolation transistor. The second terminal of the third transistor is connected to the first terminal of the second isolation transistor.

4. The bias circuit according to claim 3, characterized in that, The current mirror ratio of the first transistor, the second transistor, and the third transistor is 1:M:N, and M>N>0.

5. The bias circuit according to claim 1, characterized in that, The current compensation unit includes a fourth transistor and a fifth transistor. The control terminal of the fourth transistor, the second terminal of the fourth transistor, and the control terminal of the fifth transistor are connected to the second terminal of the second isolation transistor. The first terminal of the fourth transistor and the first terminal of the fifth transistor are connected to the power supply voltage. The second terminal of the fifth transistor is connected to the second terminal of the first isolation transistor.

6. The bias circuit according to claim 2, characterized in that, The second current mirror unit includes a sixth transistor and a seventh transistor. The first terminals of the sixth transistor and the seventh transistor are connected to the power supply voltage. The second terminal of the sixth transistor, the control terminal of the sixth transistor, and the control terminal of the seventh transistor are connected to the second terminal of the first isolation transistor. The second terminal of the seventh transistor is used to generate the output current.

7. The bias circuit according to claim 1, characterized in that, The first current mirror unit and / or current compensation unit is a Cascode current mirror.

8. The bias circuit according to claim 2, characterized in that, The second current mirror unit is a Cascode current mirror.

9. The bias circuit according to claim 5, characterized in that, The current mirror ratio of the fourth transistor and the fifth transistor is 1:

1.

10. A chip, characterized in that, Includes the bias circuit as described in any one of claims 1 to 9.

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