Processor mainboard and computer equipment

Abstract

The embodiment of the utility model provides a processor mainboard and computer equipment, and the processor mainboard comprises a processor; at least one external device; the processor comprises a high-speed Serdes port used for being connected with the at least one external device, the high-speed Serdes port comprises at least one communication interface mapped by a port bit width range, and one communication interface is connected with one external device; the port bit width range comprises a plurality of port bits, and the port bits are divided into independent connection bits and non-independent connection bits; wherein one communication interface maps one independent connection bit or one connection bit range, the connection bit range comprises continuous independent connection bits and / or continuous non-independent connection bits, and the different connection bit ranges do not have repeated port bits. The embodiment of the utility model improves the flexible configuration of the processor.

Description

Technical Field

[0001] This application relates to the field of processor technology, specifically to a processor motherboard and a computer device. Background Technology

[0002] With the rapid advancement of technology, the electronic equipment industry is booming. As the functions of electronic devices continue to increase, the processor, as the core component, is also becoming increasingly diversified. Processors not only need to handle massive amounts of data processing but also need to support the connection and communication of various external devices to meet diverse user needs. However, the interface design of current processor motherboards is relatively simple, limiting the flexible configuration of the processor.

[0003] Therefore, how to provide a processor motherboard that improves the flexible configuration of the processor has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] In view of this, embodiments of this application provide a processor motherboard and a computer device to improve the flexible configuration of the processor.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a processor motherboard, comprising:

[0007] processor;

[0008] At least one external device;

[0009] The processor includes a high-speed SerDes port for connecting the at least one external device. The high-speed SerDes port includes at least one communication interface mapped by a port bit width range, and one communication interface connects to one external device. The port bit width range includes multiple port bits, which are divided into independent connection bits and non-independent connection bits.

[0010] In this context, a communication interface maps to an independent connection bit or a range of connection bits, wherein the range of connection bits includes consecutive independent connection bits and / or consecutive non-independent connection bits, and different ranges of connection bits do not have overlapping port bits.

[0011] Optionally, the independent connection bit is lower in bit order than the non-independent connection bit within the port bit width range; the bit range of the non-independent connection bit supports a first bus type to support connection to external devices corresponding to the first bus type; the bit range of the independent connection bit supports multiple bus types to support connection to external devices corresponding to the multiple bus types, wherein the multiple bus types include the first bus type.

[0012] Optionally, the at least one communication interface is specifically a single communication interface that maps multiple port bits of the port bit width range;

[0013] Alternatively, the at least one communication interface may specifically be two communication interfaces of the same bus type, with one communication interface mapping consecutive non-independent connection bits in order from high bit to low bit, and the other communication interface mapping the remaining non-independent connection bits and independent connection bits.

[0014] Optionally, the at least one communication interface supports the first bus type.

[0015] Optionally, all independent connection bits form a connection bit range, and all non-independent connection bits form multiple connection bit ranges;

[0016] The number of at least one communication interface is greater than two, and one communication interface maps to one connection bit range.

[0017] Optionally, the number of the at least one communication interface is greater than two, with one independent connection bit mapping to one communication interface; consecutive non-independent connection bits form multiple connection bit ranges, and each connection bit range maps to a communication interface.

[0018] Optionally, the number of the at least one communication interface is greater than two, all independent connection bits form multiple connection bit ranges, all non-independent connection bits form multiple connection bit ranges, and one communication interface maps to one connection bit range.

[0019] Optionally, the first bus type is a PCIe bus.

[0020] Optionally, the port bit width range includes a total of 16 port bits, which are divided into 4 independent connection bits and 12 non-independent connection bits.

[0021] Secondly, embodiments of this application provide a computer device including a processor motherboard as described in the first aspect above.

[0022] This application provides a processor motherboard and a computer device. The processor motherboard includes: a processor; at least one external device; the processor includes a high-speed SerDes port for connecting the at least one external device, the high-speed SerDes port includes at least one communication interface mapped by a port bit width range, and one communication interface connects to one external device; the port bit width range includes multiple port bits, the port bits are divided into independent connection bits and non-independent connection bits; wherein, one communication interface maps to one independent connection bit or a range of connection bits, the range of connection bits includes consecutive independent connection bits and / or consecutive non-independent connection bits, and different ranges of connection bits do not have overlapping port bits.

[0023] As can be seen, the processor in the processor motherboard provided in this application embodiment includes a high-speed SerDes port. The port width range of the high-speed SerDes port includes multiple port bits, and these port bits are divided into independent connection bits and non-independent connection bits. By flexibly mapping the port width range of the high-speed SerDes port in the processor to a communication interface, and with one communication interface mapping one independent connection bit or a range of connection bits, the processor can flexibly configure the communication interface according to the number and type of external devices and the required data transmission bandwidth, thereby enabling the processor to better adapt to different application scenarios and system requirements. Furthermore, since the processor's high-speed SerDes port supports mapping multiple ranges of connection bits, including consecutive independent connection bits and / or consecutive non-independent connection bits, the processor can be compatible with various types of external devices, thereby enabling the processor to better adapt to different application scenarios and system requirements. Therefore, the processor motherboard provided in this application embodiment can achieve support for different numbers and types of external devices through the flexible configuration of the processor's high-speed SerDes port, thereby enabling the processor to better adapt to different application scenarios and system requirements. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a first structural schematic diagram of the processor motherboard provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the second structure of the processor motherboard provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the third structure of the processor motherboard provided in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the fourth structure of the processor motherboard provided in the embodiments of this application;

[0029] Figure 5 This is a fifth structural schematic diagram of the processor motherboard provided in the embodiments of this application;

[0030] Figure 6 This is a sixth structural schematic diagram of the processor motherboard provided in the embodiments of this application;

[0031] Figure 7 This is a seventh structural schematic diagram of the processor motherboard provided in the embodiments of this application;

[0032] Figure 8 This is an eighth structural schematic diagram of the processor motherboard provided in the embodiments of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] As described in the background section, the processor interface design in a processor motherboard is relatively simple, which limits the flexible configuration of the processor. Therefore, embodiments of this application provide a processor motherboard and a computer device using the processor motherboard to improve the flexible configuration of the processor.

[0035] The processor motherboard provided in this application embodiment includes: a processor; at least one external device; the processor includes a high-speed SerDes port for connecting the at least one external device, the high-speed SerDes port includes at least one communication interface mapped by a port bit width range, and one communication interface connects to one external device; the port bit width range includes multiple port bits, the port bits are divided into independent connection bits and non-independent connection bits; wherein, one communication interface maps to one independent connection bit or one connection bit range, the connection bit range includes consecutive independent connection bits, and / or consecutive non-independent connection bits, and different connection bit ranges do not have overlapping port bits.

[0036] As can be seen, the processor in the processor motherboard provided in this application embodiment includes a high-speed SerDes port. The port width range of the high-speed SerDes port includes multiple port bits, and these port bits are divided into independent connection bits and non-independent connection bits. By flexibly mapping the port width range of the high-speed SerDes port in the processor to a communication interface, and with one communication interface mapping one independent connection bit or a range of connection bits, the processor can flexibly configure the communication interface according to the number and type of external devices and the required data transmission bandwidth, thereby enabling the processor to better adapt to different application scenarios and system requirements. Furthermore, since the processor's high-speed SerDes port supports mapping multiple ranges of connection bits, including consecutive independent connection bits and / or consecutive non-independent connection bits, the processor can be compatible with various types of external devices, thereby enabling the processor to better adapt to different application scenarios and system requirements. Therefore, the processor motherboard provided in this application embodiment can achieve support for different numbers and types of external devices through the flexible configuration of the processor's high-speed SerDes port, thereby enabling the processor to better adapt to different application scenarios and system requirements.

[0037] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0038] refer to Figure 1 , Figure 1 This is a first structural schematic diagram of the processor motherboard provided in an embodiment of this application. For example... Figure 1 As shown, the processor motherboard provided in this application embodiment may include:

[0039] Processor 100;

[0040] At least one external device; for example, multiple external devices, such as... Figure 1 The external devices shown are 201...20N. These external devices refer to devices that transmit and interact with the processor, and can be connected to the processor via a high-speed SerDes port to achieve high-speed, efficient data communication. These external devices may include, but are not limited to, storage devices, network interface devices, and high-performance input / output devices.

[0041] Combination Figure 1 As shown, the processor 100 includes a high-speed Serdes port P0 for connecting the at least one external device. The high-speed Serdes port P0 includes at least one communication interface mapped by a port bit width range, and each communication interface connects to an external device.

[0042] The port bit width range includes multiple port bits, which are divided into independent connection bits and non-independent connection bits; wherein, a communication interface maps to an independent connection bit or a range of connection bits, and the range of connection bits includes consecutive independent connection bits and / or consecutive non-independent connection bits, and there are no duplicate port bits in different ranges of connection bits.

[0043] In an optional implementation, if a communication interface maps an independent connection bit, then for the x-th independent connection bit, the communication interface mapping the x-th independent connection bit can be represented as P0[x]; if a communication interface maps a range of connection bits, assuming a range of connection bits contains consecutive connection bits n to connection bits m, then the communication interface mapping the range of connection bits n to connection bits m can be represented as P0[n:m].

[0044] As can be seen, the processor in the processor motherboard provided in this application embodiment includes a high-speed SerDes port. The port width range of the high-speed SerDes port includes multiple port bits, and these port bits are divided into independent connection bits and non-independent connection bits. By flexibly mapping the port width range of the high-speed SerDes port in the processor to a communication interface, and with one communication interface mapping one independent connection bit or a range of connection bits, the processor can flexibly configure the communication interface according to the number and type of external devices and the required data transmission bandwidth, thereby enabling the processor to better adapt to different application scenarios and system requirements. Furthermore, since the processor's high-speed SerDes port supports mapping multiple ranges of connection bits, including consecutive independent connection bits and / or consecutive non-independent connection bits, the processor can be compatible with various types of external devices, thereby enabling the processor to better adapt to different application scenarios and system requirements. Therefore, the processor motherboard provided in this application embodiment can achieve support for different numbers and types of external devices through the flexible configuration of the processor's high-speed SerDes port, thereby enabling the processor to better adapt to different application scenarios and system requirements.

[0045] In one optional implementation, the independent connection bit is positioned below the non-independent connection bit within the port bit width range; the bit range of the non-independent connection bit supports a first bus type to support connection to external devices corresponding to the first bus type; the bit range of the independent connection bit supports multiple bus types to support connection to external devices corresponding to the multiple bus types, wherein the multiple bus types include the first bus type. The first bus type may be, for example, a PCIe (Peripheral Component Interconnect Express) bus; the multiple bus types supported by the bit range of the independent connection bit may be, for example, a PCIe bus or a SATA (Serial Advanced Technology Attachment) bus.

[0046] In an optional implementation example, the port bit width range may specifically include 16 port bits. Further, taking the 16 port bits as divided into 4 independent connection bits and 12 non-independent connection bits as an example, the position order of the 4 independent connection bits in the port bit width range can be the zeroth, first, second, and third bits, respectively. The position order of the 12 non-independent connection bits in the port bit width range can be the fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth bits, respectively. It can be understood that the 4 independent connection bits occupy the lower bits from the zeroth to the third bit, while the 12 non-independent connection bits occupy the higher bits from the fourth to the fifteenth bit.

[0047] The following describes in detail the solutions provided in this application embodiment by using the high-speed SerDes port in the processor to connect different numbers of external devices as different application scenarios.

[0048] Scenario 1: A high-speed SerDes port in the processor is connected to an external device.

[0049] Taking the port width range as an example, which includes 16 port bits, and these port bits are divided into 4 independent connection bits (e.g., connection bits 0 to 3) and 12 non-independent connection bits (e.g., connection bits 4 to 15), Figure 2 An exemplary schematic diagram of the second structure of the processor motherboard is shown, with reference to... Figure 2The high-speed Serdes port P0 in the processor 100 is connected to an external device 201. At this time, the at least one communication interface is specifically a communication interface. The communication interface maps multiple port bits of the port bit width range, such as the connection bit range being connection bit 0 to connection bit 15. The corresponding mapped communication interface can be represented as P0[0:15].

[0050] The communication interface P0[0:15] supports the first bus type, such as a PCIe bus. Correspondingly, the external device 201 can be a PCIe device.

[0051] Scenario 2: The high-speed SerDes port in the processor connects two external devices.

[0052] Taking the port width range as an example, which includes 16 port bits, and these port bits are divided into 4 independent connection bits (e.g., connection bits 0 to 3) and 12 non-independent connection bits (e.g., connection bits 4 to 15), Figure 3 An exemplary schematic diagram of the third structure of the processor motherboard is shown, with reference to... Figure 3 The high-speed Serdes port P0 in the processor 100 connects to two external devices, namely external device 201 and external device 202. At this time, the at least one communication interface is specifically two communication interfaces with the same bus type. In order from high bit to low bit, one of the two communication interfaces maps a continuous part of the non-independent connection bits, and the other communication interface maps the remaining non-independent connection bits and independent connection bits.

[0053] For example, one communication interface maps connection bits ranging from connection bit 8 to connection bit 15, and another communication interface maps connection bits ranging from connection bit 0 to connection bit 7. The two communication interfaces can be represented as P0[8:15] and P0[0:7], respectively, and both communication interfaces P0[8:15] and P0[0:7] support the first bus type, such as a PCIe bus. Correspondingly, external devices 201 and 202 can be PCIe devices.

[0054] Scenario 3: The high-speed SerDes port in the processor is connected to three external devices.

[0055] Taking the port width range as an example, which includes 16 port bits, and these port bits are divided into 4 independent connection bits (e.g., connection bits 0 to 3) and 12 non-independent connection bits (e.g., connection bits 4 to 15), Figure 4 An exemplary schematic diagram of the fourth structure of the processor motherboard is shown, with reference to... Figure 4The high-speed Serdes port P0 in the processor 100 connects to three external devices, namely external device 201, external device 202 and external device 203. All independent connection bits of the high-speed Serdes port P0 form a connection bit range, and all non-independent connection bits form multiple connection bit ranges. One communication interface maps to one connection bit range.

[0056] For example, the connection bit range mapped to a communication interface is connection bit 0 to connection bit 3; the connection bit range mapped to a communication interface is connection bit 4 to connection bit 7; and the connection bit range mapped to a communication interface is connection bit 8 to connection bit 15. The communication interfaces connected to external devices 201, 202, and 203 can be represented as P0[8:15], P0[4:7], and P0[0:3], respectively. Communication interfaces P0[8:15] and P0[4:7] support the first bus type, such as a PCIe bus; communication interface P0[0:3] supports either the first bus type (e.g., PCIe bus) or other bus types (e.g., SATA bus). Correspondingly, external devices 201 and 202 can be PCIe devices; external device 203 can be either a PCIe device or a SATA device.

[0057] Scenario 4: The high-speed SerDes port in the processor connects to four external devices.

[0058] Taking the port width range as an example, which includes 16 port bits, and these port bits are divided into 4 independent connection bits (e.g., connection bits 0 to 3) and 12 non-independent connection bits (e.g., connection bits 4 to 15), Figure 5 The fifth structural diagram of the processor motherboard shown as an example is referred to... Figure 5 The high-speed Serdes port P0 in the processor 100 connects to four external devices, namely external device 201, external device 202, external device 203 and external device 204. All independent connection bits of the high-speed Serdes port P0 form a connection bit range, and all non-independent connection bits form multiple connection bit ranges. One communication interface maps to one connection bit range.

[0059] For example, the connection bit range mapped by a communication interface is connection bit 0 to connection bit 3; the connection bit range mapped by a communication interface is connection bit 4 to connection bit 7; the connection bit range mapped by a communication interface is connection bit 8 to connection bit 11; and the connection bit range mapped by a communication interface is connection bit 12 to connection bit 15. The communication interfaces connected to the external devices 201, 202, 203, and 204 can be represented as P0[12:15], P0[8:11], P0[4:7], and P0[0:3], respectively. The bus types supported by communication interfaces P0[12:15], P0[8:11], and P0[4:7] are all the first bus type, such as a PCIe bus. The bus type supported by communication interface P0[0:3] can be the first bus type (e.g., PCIe bus) or other bus types (e.g., SATA bus). Correspondingly, external devices 201, 202, and 203 can be PCIe devices; external device 204 can be either a PCIe device or a SATA device.

[0060] Scenario 5: The high-speed SerDes port in the processor connects to six external devices.

[0061] Taking the port width range as an example, which includes 16 port bits, and these port bits are divided into 4 independent connection bits (e.g., connection bits 0 to 3) and 12 non-independent connection bits (e.g., connection bits 4 to 15), Figure 6 The exemplary sixth structural diagram of the processor motherboard is shown below, with reference to... Figure 6 The high-speed Serdes port P0 in the processor 100 connects to six external devices, namely external device 201, external device 202, external device 203, external device 204, external device 205 and external device 206. One independent connection bit of the high-speed Serdes port P0 maps to one communication interface; consecutive non-independent connection bits form multiple connection bit ranges, and each connection bit range maps to one communication interface.

[0062] For example, a communication interface may be mapped to connection bit 0; a communication interface may be mapped to connection bit 1; a communication interface may be mapped to connection bit 2; a communication interface may be mapped to connection bit 3; a communication interface may be mapped to connection bit range 4 to 7; a communication interface may be mapped to connection bit range 8 to 15.

[0063] The communication interfaces connected to external devices 201, 202, 203, 204, 205, and 206 can be represented as P0[8:15], P0[4:7], P0[3], P0[2], P0[1], and P0[0], respectively. Communication interfaces P0[8:15] and P0[4:7] support the first bus type, such as a PCIe bus. Communication interfaces P0[3], P0[2], P0[1], and P0[0] support either the first bus type (e.g., PCIe bus) or other bus types (e.g., SATA bus). Correspondingly, external devices 201 and 202 can be PCIe devices; external devices 203, 204, 205, and 206 can be either PCIe devices or SATA devices.

[0064] Scenario 6: The high-speed SerDes port in the processor connects to eight external devices.

[0065] Taking the port width range as an example, which includes 16 port bits, and these port bits are divided into 4 independent connection bits (e.g., connection bits 0 to 3) and 12 non-independent connection bits (e.g., connection bits 4 to 15), Figure 7 The exemplary seventh structural diagram of the processor motherboard is shown below, with reference to... Figure 7 The high-speed Serdes port P0 in the processor 100 connects to eight external devices, namely external device 201, external device 202, external device 203, external device 204, external device 205, external device 206, external device 207 and external device 208. All independent connection bits of the high-speed Serdes port P0 form multiple connection bit ranges, and all non-independent connection bits form multiple connection bit ranges. One communication interface maps to one connection bit range.

[0066] For example, the connection bit range mapped to a communication interface is connection bit 0 and connection bit 1; the connection bit range mapped to a communication interface is connection bit 2 and connection bit 3; the connection bit range mapped to a communication interface is connection bit 4 and connection bit 5; the connection bit range mapped to a communication interface is connection bit 6 and connection bit 7; the connection bit range mapped to a communication interface is connection bit 8 and connection bit 9; the connection bit range mapped to a communication interface is connection bit 10 and connection bit 11; the connection bit range mapped to a communication interface is connection bit 12 and connection bit 13; and the connection bit range mapped to a communication interface is connection bit 14 and connection bit 15.

[0067] The communication interfaces connected to external devices 201, 202, 203, 204, 205, 206, 207, and 208 can be represented as P0[14:15], P0[12:13], P0[10:11], P0[8:9], P0[6:7], P0[4:5], P0[2:3], and P0[0:1], respectively, and the communication interface P0[14:15] is further represented as P0[12:13], P0[10:11], P0[8:9], P0[6:7], P0[4:5], P0[2:3], and P0[0:1].

[15] Communication interfaces P0[12:13], P0[10:11], P0[8:9], P0[6:7], and P0[4:5] all support the first bus type, such as PCIe bus; communication interfaces P0[2:3] and P0[0:1] can both support the first bus type (e.g., PCIe bus) or other bus types (e.g., SATA bus). Correspondingly, external devices 201, 202, 203, 204, 205, and 206 can be PCIe devices; external devices 207 and 208 can be PCIe devices or SATA devices.

[0068] In the optional implementation, Figure 8 An exemplary schematic diagram of the eighth structure of the processor motherboard is shown, with reference to... Figure 8 The processor motherboard may also have two DDR memory channels, numbered channel A and channel B respectively; each channel is connected to a memory slot, allowing each memory channel to accommodate one DIMM, supporting a maximum of two memory modules (e.g., DIMM A0 connected to memory channel A and DIMM B0 connected to memory channel B). The supported memory module type is SO-DIMM (Small Outline Dual In-line Memory Module). In other embodiments, the memory module may also support memory chips.

[0069] Furthermore, the processor motherboard may also be equipped with multiple USB connectors electrically connected to the processor 100. These multiple USB connectors include: a Type A USB composite interface (e.g., ...). Figure 8 The RJ45 (BMC) + USB Rear (as shown) and multiple Type A USB ports (such as...) Figure 8 (As shown in the USB INSIDE TYPEA).

[0070] The processor 100 supports eight USB 3.1 ports and four USB 2.0 ports. The eight USB 3.1 ports are implemented by the USB00[0], USB00[1], USB00[2], USB00[3], USB01[0], USB01[1], USB01[2] and USB01[3] ports on the processor 100, respectively. The four USB 2.0 ports are implemented by the USB00[4], USB00[5], USB01[4] and USB01[5] ports on the processor 100, respectively. At the same time, the USB00[5] port on the processor 100 can be connected to the baseboard management controller chip BMC and a Class A USB interface through a multiplexer MUX to realize data transmission.

[0071] As can be seen, the processor in the processor motherboard provided in this application embodiment includes a high-speed SerDes port. The port width range of the high-speed SerDes port includes multiple port bits, and these port bits are divided into independent connection bits and non-independent connection bits. By flexibly mapping the port width range of the high-speed SerDes port in the processor to a communication interface, and with one communication interface mapping one independent connection bit or a range of connection bits, the processor can flexibly configure the communication interface according to the number and type of external devices and the required data transmission bandwidth, thereby enabling the processor to better adapt to different application scenarios and system requirements. Furthermore, since the processor's high-speed SerDes port supports mapping multiple ranges of connection bits, including consecutive independent connection bits and / or consecutive non-independent connection bits, the processor can be compatible with various types of external devices, thereby enabling the processor to better adapt to different application scenarios and system requirements. Therefore, the processor motherboard provided in this application embodiment can achieve support for different numbers and types of external devices through the flexible configuration of the processor's high-speed SerDes port, thereby enabling the processor to better adapt to different application scenarios and system requirements.

[0072] This application also provides a computer device, which includes a processor motherboard as described above.

[0073] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0074] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A processor motherboard, characterized in that, include: processor; At least one external device; The processor includes a high-speed SerDes port for connecting the at least one external device. The high-speed SerDes port includes at least one communication interface mapped by a port bit width range, and one communication interface connects to one external device. The port bit width range includes multiple port bits, which are divided into independent connection bits and non-independent connection bits. In this context, a communication interface maps to an independent connection bit or a range of connection bits, wherein the range of connection bits includes consecutive independent connection bits and / or consecutive non-independent connection bits, and different ranges of connection bits do not have overlapping port bits.

2. The processor motherboard according to claim 1, characterized in that, The independent connection bit is in a lower bit order than the non-independent connection bit within the port bit width range; the bit range of the non-independent connection bit supports the first bus type to support connection to external devices corresponding to the first bus type. The bit range of the independent connection bit supports multiple bus types to support the connection of external devices corresponding to the multiple bus types, including the first bus type.

3. The processor motherboard according to claim 2, characterized in that, The at least one communication interface is specifically a single communication interface that maps multiple port bits within the port bit width range; Alternatively, the at least one communication interface may specifically be two communication interfaces of the same bus type, with one communication interface mapping consecutive non-independent connection bits in order from high bit to low bit, and the other communication interface mapping the remaining non-independent connection bits and independent connection bits.

4. The processor motherboard according to claim 3, characterized in that, The at least one communication interface supports the first bus type.

5. The processor motherboard according to claim 2, characterized in that, All independent connection bits form one connection bit range, and all non-independent connection bits form multiple connection bit ranges. The number of at least one communication interface is greater than two, and one communication interface maps to one connection bit range.

6. The processor motherboard according to claim 2, characterized in that, The number of at least one communication interface is greater than two, with one independent connection bit mapping to one communication interface; consecutive non-independent connection bits form multiple connection bit ranges, and each connection bit range maps to a communication interface.

7. The processor motherboard according to claim 2, characterized in that, The number of at least one communication interface is greater than two, all independent connection bits form multiple connection bit ranges, all non-independent connection bits form multiple connection bit ranges, and one communication interface maps to one connection bit range.

8. The processor motherboard according to claim 2, characterized in that, The first bus type is PCIe bus.

9. The processor motherboard according to any one of claims 1-8, characterized in that, The port bit width range includes a total of 16 port bits, which are divided into 4 independent connection bits and 12 non-independent connection bits.

10. A computer device, characterized in that, Including the processor motherboard as described in any one of claims 1-9.

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