MOS tube current sampling circuit and electronic equipment
By adjusting the gate voltages of the main MOSFET and the mirror MOSFET through a gate voltage adjustment circuit, the problems of high power loss and limited detection accuracy in existing MOSFET current sampling are solved. This achieves high-precision and wide-range mirror ratio adjustment, which is applicable to NMOS and PMOS transistors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HANGZHOU RUIMENG TECH
- Filing Date
- 2025-05-07
- Publication Date
- 2026-05-08
AI Technical Summary
Existing MOSFET current sampling methods suffer from high power loss, limited detection accuracy, and poor cost-effectiveness, especially when adjusting the mirror ratio due to limitations imposed by MOSFET process variations and layout area.
By changing the gate voltages of the main MOSFET and the mirror MOSFET through the gate voltage adjustment circuit, high-precision and wide-range mirror ratio adjustment can be achieved. The mirror ratio adjustment can be completed using only one mirror MOSFET, reducing layout area and adjustment accuracy limitations.
It achieves high-precision and wide-range mirror ratio adjustment, reduces power loss, improves economy and detection accuracy, and is suitable for NMOS and PMOS transistors.
Smart Images
Figure CN224216774U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of MOSFET current sampling technology, and in particular to a MOSFET current sampling circuit and electronic device. Background Technology
[0002] MOSFETs are commonly used switching devices in power supply products. MOS is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor. Sampling the current flowing through a MOSFET is a prerequisite for achieving closed-loop control and reliability design in power supply products. Traditional MOSFET current sampling methods include two approaches: one involves connecting a first resistor in series with the MOSFET and determining the MOSFET current through the voltage across the first resistor. For the first type of MOSFET current sampling circuit, please refer to [link to circuit description]. Figure 1 As shown in the diagram; the second method uses a main MOSFET and a mirror MOSFET connected in parallel, with the first resistor connected in series with the mirror MOSFET. The current of the main MOSFET is inferred by detecting the current of the mirror MOSFET. For the second MOSFET current sampling circuit, please refer to [link to circuit description]. Figure 2 As shown. However, in the first current sampling method, a large current flows through the first resistor, leading to increased power loss; in the second current sampling method, power loss is small, but the detection accuracy is affected by the ratio of the image.
[0003] Due to process variations in MOSFETs, the current mirror ratio needs adjustment. Existing technology uses multiple mirror MOSFETs, each connected in series with a corresponding switching transistor. By turning on the switching transistors individually, different current mirror ratios can be set. For a second type of MOSFET current sampling circuit with adjustment circuitry, please refer to [link to relevant documentation]. Figure 3 As shown. However, using this current mirror ratio adjustment method, the adjustment accuracy is limited by the minimum channel width and minimum channel length of the MOSFET, and the adjustment range is limited by the layout area of the mirror MOSFET. In particular, the larger the adjustment range, the more mirror MOSFETs are required, and the larger the layout area of the mirror MOSFETs is, resulting in poor economic efficiency. Utility Model Content
[0004] The purpose of this invention is to provide a MOSFET current sampling circuit and electronic device that can adjust the mirror ratio by changing the gate voltage of the main MOSFET and the gate voltage of the mirror MOSFET through a gate voltage adjustment circuit. This allows for high-precision and wide-range adjustment of the mirror ratio using a single mirror MOSFET, while being economical.
[0005] This utility model discloses a MOSFET current sampling circuit, including a gate voltage adjustment circuit, a mirror MOSFET, and a first resistor;
[0006] The first terminal of the gate voltage adjustment circuit is connected to the gate of the main MOSFET, and the second terminal of the gate voltage adjustment circuit is connected to the gate of the mirror MOSFET. The gate voltage adjustment circuit is used to output an adjustable gate voltage of the main MOSFET and an adjustable gate voltage of the mirror MOSFET.
[0007] The source of the mirror MOS transistor and the source of the main MOS transistor are both connected to the source voltage, and the drain of the mirror MOS transistor is connected to the first terminal of the first resistor.
[0008] The second end of the first resistor and the drain of the main MOS transistor are both connected to the drain voltage.
[0009] Optionally, the gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor;
[0010] The negative terminals of the first current source and the third current source are both connected to the power supply voltage. The common terminal of the positive terminal of the first current source, the negative terminal of the second current source, and the first terminal of the second resistor serves as the first terminal of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor.
[0011] The common terminal of the positive terminal of the third current source, the negative terminal of the fourth current source, and the second terminal of the second resistor serves as the second terminal of the gate voltage adjustment circuit and is connected to the gate of the mirror MOS transistor.
[0012] The positive terminals of the second current source and the fourth current source are both grounded.
[0013] Optionally, the second resistor is an adjustable resistor, and / or the first current source, the second current source, the third current source, and the fourth current source are all adjustable current sources.
[0014] Optionally, the adjustable resistor includes N parallel resistor branches;
[0015] Each of the aforementioned resistor branches includes a sub-resistor and a switch connected in series.
[0016] Optionally, the adjustable current source includes N parallel current source branches;
[0017] Each of the aforementioned current source branches includes a sub-current source and a switch connected in series.
[0018] Optionally, both the main MOS transistor and the mirror MOS transistor are NMOS transistors.
[0019] Optionally, it may also include an amplifier, an AD converter, and a processor;
[0020] The input terminal of the amplifier is connected to the first resistor to amplify the voltage across the first resistor to obtain an amplified voltage.
[0021] The input terminal of the AD converter is connected to the output terminal of the amplifier, and the output terminal of the AD converter is connected to the processor. The AD converter is used to convert the amplified voltage from an analog quantity to a digital quantity.
[0022] The processor is used to process the amplified digital voltage to obtain the current of the main MOSFET.
[0023] Optionally, the system further includes a filtering module, wherein a first end of the filtering module is connected to the output end of the amplifier, and a second end of the filtering module is connected to the input end of the AD converter, for filtering the amplified voltage.
[0024] Optionally, a temperature sensor is also included, which is disposed around the mirror MOS transistor to collect the ambient temperature of the mirror MOS transistor so that the processor can use the ambient temperature to correct the current of the main MOS transistor obtained based on the voltage across the first resistor.
[0025] This utility model also discloses an electronic device, including a main MOSFET and a MOSFET current sampling circuit as described above.
[0026] This application provides a MOSFET current sampling circuit, which includes a gate voltage adjustment circuit, a mirror MOSFET, and a first resistor. The first terminal of the gate voltage adjustment circuit is connected to the gate of the main MOSFET, and the second terminal is connected to the gate of the mirror MOSFET. The source of both the mirror MOSFET and the main MOSFET are connected to source voltages, and the drain of the mirror MOSFET is connected to the first terminal of the first resistor. The second terminal of the first resistor and the drain of the main MOSFET are connected to drain voltages. Therefore, this application adjusts the mirror ratio by changing the gate voltage of the main MOSFET and the gate voltage of the mirror MOSFET using the gate voltage adjustment circuit, achieving high-precision and wide-range adjustment of the mirror ratio using a single mirror MOSFET, with good economic efficiency. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1This is the first MOS transistor current sampling circuit diagram disclosed in this utility model;
[0029] Figure 2 This is a second MOS transistor current sampling circuit diagram disclosed in this utility model;
[0030] Figure 3 This is a diagram of the second type of MOS transistor current sampling circuit with adjustment circuit disclosed in this utility model;
[0031] Figure 4 This is a schematic diagram of the structure of a MOS transistor current sampling circuit disclosed in this utility model;
[0032] Figure 5 This is a gate voltage adjustment circuit diagram disclosed in this utility model;
[0033] The attached diagram is labeled as follows: 1 represents the gate voltage adjustment circuit. Detailed Implementation
[0034] The core of this invention is to provide a MOSFET current sampling circuit and electronic device, which can adjust the mirror ratio by changing the gate voltage of the main MOSFET and the gate voltage of the mirror MOSFET through a gate voltage adjustment circuit. This allows for high-precision and wide-range adjustment of the mirror ratio using a single mirror MOSFET, and is economical.
[0035] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.
[0036] Due to process variations in MOSFETs, the current mirror ratio needs adjustment. Existing technology uses multiple mirror MOSFETs, each connected in series with a corresponding switching transistor. By turning on the switching transistors individually, different current mirror ratios can be set. For a second type of MOSFET current sampling circuit with adjustment circuitry, please refer to [link to relevant documentation]. Figure 3 As shown. However, using this current mirror ratio adjustment method, the adjustment accuracy is limited by the minimum channel width and minimum channel length of the MOSFET, and the adjustment range is limited by the layout area of the mirror MOSFET. Specifically, the larger the adjustment range, the more mirror MOSFETs are required, and the larger the layout area of the mirror MOSFETs, resulting in poor economic efficiency. Therefore, this invention provides a MOSFET current sampling circuit and electronic device.
[0037] For details, please see Figure 4As shown, Figure 4 This is a schematic diagram of the structure of a MOS transistor current sampling circuit disclosed in this utility model.
[0038] The MOSFET current sampling circuit includes a gate voltage adjustment circuit 1, a mirror MOSFET M2, and a first resistor R1;
[0039] The first terminal of the gate voltage adjustment circuit 1 is connected to the gate of the main MOSFET M1, and the second terminal of the gate voltage adjustment circuit 1 is connected to the gate of the mirror MOSFET M2.
[0040] The source of mirror MOSFET M2 and the source of main MOSFET M1 are both connected to the source voltage VS, and the drain of mirror MOSFET M2 is connected to the first end of the first resistor R1.
[0041] The second terminal of the first resistor R1 and the drain of the main MOSFET M1 are both connected to the drain voltage VD.
[0042] Specifically, the formula for the saturation current of a MOSFET is as follows:
[0043] ;
[0044] in, This is the drain current of the MOSFET. Electron mobility is the electron mobility of a MOSFET, characterizing the speed at which electrons move within the semiconductor. Let W be the capacitance of the gate oxide layer of the MOSFET, W be the channel width of the MOSFET, and L be the channel length of the MOSFET. This is the voltage between the gate and source of the MOSFET. This is the threshold voltage of the MOSFET.
[0045] Once the channel length and width of the main MOSFET M1 and the channel length and width of the mirror MOSFET M2 are determined, if the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 are equal, then the current ratio through the main MOSFET M1 and the mirror MOSFET M2, i.e., the mirror ratio, is the ratio of the channel length and width of the main MOSFET M1 to the channel length and width of the mirror MOSFET M2. If the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 are equal, and the channel widths of the main MOSFET M1 and the mirror MOSFET M2 are also the same, then the mirror ratio depends on the ratio of the channel lengths of the main MOSFET M1 and the mirror MOSFET M2.
[0046] In this embodiment, the gate voltage adjustment circuit 1 outputs an adjustable gate voltage VG1 for the main MOSFET M1 and an adjustable gate voltage VG2 for the mirror MOSFET M2. The gate voltages VG1 and VG2 of the main MOSFET M1 and mirror MOSFET M2 can be the same or different. When the gate voltages VG1 and VG2 of the main MOSFET M1 and mirror MOSFET M2 are different, since the source terminals of the main MOSFET M1 and mirror MOSFET M2 are connected together, changing the gate voltages VG1 and VG2 of the main MOSFET M1 and mirror MOSFET M2 changes their gate-source voltages, thereby altering the mirror ratio. By adjusting the gate voltages VG1 and VG2 of the main MOSFET M1 and mirror MOSFET M2 output by the gate voltage adjustment circuit 1, the mirror ratio can be adjusted over a wide range using only one mirror MOSFET M2, thus reducing the layout area. Furthermore, the adjustment accuracy is not limited by the minimum channel width and minimum channel length of the MOSFET.
[0047] Considering the process variations of MOSFETs, the ratio of the mirror ratio to the ratio of the channel length and channel width of the main MOSFET M1 and the ratio of the channel length and channel width of the mirror MOSFET M2 may have errors. Therefore, this embodiment first determines the target mirror ratio of the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 in the MOSFET current sampling circuit; then, it adjusts the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 output by the gate voltage adjustment circuit 1 in the MOSFET current sampling circuit to make the mirror ratio the target mirror ratio, reducing the impact of MOSFET process variations on the mirror ratio; the ratio of the voltage across the first resistor R1 in the MOSFET current sampling circuit to the resistance value of the first resistor R1 is used as the current of the mirror MOSFET M2; finally, the current of the main MOSFET M1 is calculated based on the current of the mirror MOSFET M2 and the target mirror ratio.
[0048] As can be seen, this application adjusts the mirror ratio by changing the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 through the gate voltage adjustment circuit 1, thereby achieving high-precision and wide-range adjustment of the mirror ratio using a single mirror MOSFET M2, which is economical.
[0049] Based on the above embodiments:
[0050] For details, please see Figure 5 As shown, Figure 5 This is a gate voltage adjustment circuit diagram disclosed in this utility model.
[0051] As an optional embodiment, the gate voltage adjustment circuit 1 includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor R2;
[0052] The negative terminals of the first current source and the third current source are both connected to the power supply voltage VDD. The positive terminal of the first current source, the negative terminal of the second current source, and the common terminal of the first end of the second resistor R2 serve as the first terminal of the gate voltage adjustment circuit 1 and are connected to the gate of the main MOS transistor M1.
[0053] The positive terminal of the third current source, the negative terminal of the fourth current source, and the common terminal of the second end of the second resistor R2 serve as the second terminal of the gate voltage adjustment circuit 1 and are connected to the gate of the mirror MOS transistor M2.
[0054] The positive terminals of both the second and fourth current sources are grounded.
[0055] In this embodiment, when the gate voltage adjustment circuit 1 consists of a first current source, a second current source, a third current source, a fourth current source, and a second resistor R2, the polarity and magnitude of the voltage across the second resistor R2 can be changed by altering the current I1 of the first current source and the current I4 of the fourth current source, or by altering the current I2 of the second current source and the current I3 of the third current source, and / or the value of the second resistor R2. This changes the gate voltage VG2 of the mirror MOSFET M2, allowing for adjustment of the mirror ratio using a single mirror MOSFET M2, resulting in good economic efficiency. The relationship between the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 is shown below:
[0056] ;
[0057] in, The current is that of the second resistor R2.
[0058] For details, please see Figure 5 As shown, Figure 5Figure 1 shows a gate voltage adjustment circuit disclosed in this utility model. In this circuit, the current flows from the first end of the second resistor R2 to the second end of the second resistor R2 in reverse order. When the currents I1 and I4 of the first and fourth current sources are the same, and the currents I2 and I3 of the second and third current sources are both 0, if the currents I1 and I4 of the first and fourth current sources are increased, the current flows from the first current source through the second resistor R2 and then to the fourth current source, generating a reverse voltage difference across the second resistor R2. Therefore, the gate voltage VG2 of the mirror MOSFET M2 decreases. When the currents I2 and I3 of the second and third current sources are both the same, the current of the first current source... When both current I1 and the current I4 from the fourth current source are 0, if the current I2 from the second current source and the current I3 from the third current source are increased, the current will flow from the third current source through the second resistor R2 and then back to the second current source, generating a positive voltage difference across the second resistor R2. This will increase the value of the gate voltage VG2 of the mirror MOSFET M2. If the resistance of the second resistor R2 is increased, the value of the gate voltage VG2 of the mirror MOSFET M2 will decrease. If the resistance of the second resistor R2 is decreased, the value of the gate voltage VG2 of the mirror MOSFET M2 will increase.
[0059] It can be seen that by changing the current I1 of the first current source and the current I4 of the fourth current source, or by changing the current I2 of the second current source and the current I3 of the third current source, and / or the value of the second resistor R2, the gate voltage VG2 of the mirror MOSFET M2 can be changed to adjust the mirror ratio. This is more convenient than changing the size of the mirror MOSFET M2, which greatly improves the adjustment range and accuracy, while saving layout area and making it more economical.
[0060] As an optional embodiment, the second resistor R2 is an adjustable resistor, and / or the first current source, the second current source, the third current source, and the fourth current source are all adjustable current sources.
[0061] Specifically, as can be seen from the relationship between the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2, the relationship between the gate voltage VG1 of the main MOSFET M1 and the gate voltage VG2 of the mirror MOSFET M2 can be adjusted by changing the resistance value of the second resistor R2 and / or the current flowing through the second resistor R2, thereby adjusting the mirror ratio. Based on this, in this embodiment, the second resistor R2 is an adjustable resistor, and / or the first current source, the second current source, the third current source, and the fourth current source are all current sources with adjustable output current, thereby achieving the adjustment of the mirror ratio.
[0062] As an optional embodiment, the adjustable resistor includes N parallel resistor branches;
[0063] Each resistor branch includes a sub-resistor and a switch connected in series.
[0064] In this embodiment, the resistance value of the adjustable resistor is adjusted by controlling the opening and closing of the switches in the resistor branch. Specifically, the number of parallel sub-resistors is determined by the number of switches closed in the resistor branch, thereby adjusting the resistance value of the adjustable resistor. The sub-resistors in each resistor branch can have the same or different resistance values, and the switches can be, but are not limited to, MOSFETs.
[0065] As an optional embodiment, the adjustable current source includes N parallel current source branches;
[0066] Each current source branch includes a sub-current source and a switch connected in series.
[0067] In this embodiment, the output current of the current source branch is adjusted by controlling the closing and opening of the switches in the current source branch. Specifically, the number of parallel sub-current sources is determined by the number of switches closed in the current source branch, thereby adjusting the output current of the current source branch. The output current of the sub-current sources in each current source branch can be the same or different, and the switches can be, but are not limited to, MOSFETs.
[0068] As an optional embodiment, both the main MOSFET and the mirror MOSFET are NMOS transistors.
[0069] In this application, both the main MOSFET and the mirror MOSFET can be NMOS transistors or PMOS transistors, thereby enabling the adjustment of the mirror ratio of the NMOS transistors or PMOS transistors, which has a wide range of applications.
[0070] As an optional embodiment, a temperature sensor is also included, which is disposed around the mirror MOS transistor M2 to collect the ambient temperature of the mirror MOS transistor M2 so that the processor can correct the current of the main MOS transistor M1 based on the voltage across the first resistor R1 using the ambient temperature.
[0071] Considering that the saturation current of a MOSFET is related to its threshold voltage, It decreases as the ambient temperature rises (approximately) This causes changes in the saturation current of the MOSFET. If not compensated, the image ratio will drift with temperature; for example, the error can reach [value missing] within the range of -40℃ to 125℃. To this end, this embodiment includes a temperature sensor to monitor the ambient temperature of the mirror MOSFET M2 in real time. The controller then uses the ambient temperature to correct the current of the main MOSFET M1, which is obtained based on the voltage across the first resistor R1, ensuring the consistency and reliability of the MOSFET current sampling over a wide temperature range.
[0072] In addition, the resistance value of the first resistor R1 may also change with the ambient temperature (such as metal film resistors). This further introduces errors. Therefore, the calibration also needs to consider the error effect caused by the resistance value of the first resistor R1 under different ambient temperatures.
[0073] As can be seen, this embodiment uses a controller to perform temperature compensation based on the temperature collected by the temperature sensor, ensuring the consistency and reliability of MOSFET current sampling over a wide temperature range.
[0074] As an optional embodiment, it also includes an amplifier, an AD converter, and a processor;
[0075] The input terminal of the amplifier is connected to the first resistor R1 to amplify the voltage across the first resistor R1 to obtain the amplified voltage.
[0076] The input terminal of the AD converter is connected to the output terminal of the amplifier, and the output terminal of the AD converter is connected to the processor. The AD converter is used to convert the amplified voltage from an analog quantity to a digital quantity.
[0077] The processor is used to process the amplified digital voltage to obtain the current of the main MOSFET M1.
[0078] Considering that the voltage across the first resistor R1 is typically small (e.g., in the millivolt range), direct measurement is susceptible to noise interference and difficult to quantize effectively by the AD converter. Therefore, this embodiment incorporates an amplifier, such as an instrumentation amplifier, to amplify the small voltage to the optimal input range of the AD converter (e.g., 0 to 3.3V), improving the SNR (Signal to Interference plus Noise Ratio) and ensuring that the voltage across the first resistor R1 can be detected with high precision by the AD converter. Since analog voltage signals cannot be directly processed by a digital processor, an AD converter is needed to convert the amplified voltage into a digital quantity (e.g., 12-bit resolution) for easier mathematical calculations and logical judgments by the processor, while avoiding attenuation and interference problems associated with long-distance analog signal transmission. Finally, based on the digital voltage output by the AD converter, combined with calibration data (e.g., temperature compensation, nonlinear correction) and the mirror ratio, the processor can accurately calculate the current of the main MOSFET M1.
[0079] As can be seen, this embodiment uses an amplifier to amplify the voltage across the first resistor R1, ensuring that the voltage across the first resistor R1 can be detected with high precision by the AD converter. The amplified voltage is converted into a digital quantity for the processor to process, so as to obtain the current of the main MOSFET M1, thereby improving the accuracy of the current sampling of the main MOSFET M1.
[0080] As an optional embodiment, a filtering module is also included, with a first end connected to the output of the amplifier and a second end connected to the input of the AD converter.
[0081] Considering that the amplifier output may contain high-frequency noise such as environmental electromagnetic interference, if this high-frequency noise is not filtered out, it will be aliased into the low-frequency signal after being sampled by the AD converter, causing digital voltage errors. Furthermore, useless high-frequency noise will occupy the quantization bits of the AD converter, reducing the resolution of the effective voltage signal. Therefore, this embodiment includes a filtering module to filter the amplified voltage, enabling the AD converter to quantize the voltage signal more accurately.
[0082] As can be seen, this embodiment uses a filtering module to suppress high-frequency noise and high frequencies, ensuring the accuracy of the input data of the AD converter and making the calculation of the current of the main MOSFET M1 more accurate.
[0083] This invention also provides an electronic device, including a main MOSFET and a MOSFET current sampling circuit as described above.
[0084] Specifically, the electronic device can be any device that includes a MOSFET, such as a converter, etc., and this application does not impose any particular limitation. For a description of the MOSFET current sampling circuit in the electronic device, please refer to the above embodiments, and this application will not repeat it here.
[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0086] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0087] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A MOSFET current sampling circuit, characterized in that, Includes a gate voltage adjustment circuit, a mirror MOSFET, and a first resistor; The first terminal of the gate voltage adjustment circuit is connected to the gate of the main MOSFET, and the second terminal of the gate voltage adjustment circuit is connected to the gate of the mirror MOSFET. The gate voltage adjustment circuit is used to output an adjustable gate voltage of the main MOSFET and an adjustable gate voltage of the mirror MOSFET. The source of the mirror MOS transistor and the source of the main MOS transistor are both connected to the source voltage, and the drain of the mirror MOS transistor is connected to the first terminal of the first resistor. The second end of the first resistor and the drain of the main MOS transistor are both connected to the drain voltage.
2. The MOS transistor current sampling circuit as described in claim 1, characterized in that, The gate voltage adjustment circuit includes a first current source, a second current source, a third current source, a fourth current source, and a second resistor; The negative terminals of the first current source and the third current source are both connected to the power supply voltage. The common terminal of the positive terminal of the first current source, the negative terminal of the second current source, and the first terminal of the second resistor serves as the first terminal of the gate voltage adjustment circuit and is connected to the gate of the main MOS transistor. The common terminal of the positive terminal of the third current source, the negative terminal of the fourth current source, and the second terminal of the second resistor serves as the second terminal of the gate voltage adjustment circuit and is connected to the gate of the mirror MOS transistor. The positive terminals of the second current source and the fourth current source are both grounded.
3. The MOS transistor current sampling circuit as described in claim 2, characterized in that, The second resistor is an adjustable resistor, and / or the first current source, the second current source, the third current source, and the fourth current source are all adjustable current sources.
4. The MOS transistor current sampling circuit as described in claim 3, characterized in that, The adjustable resistor comprises N parallel resistor branches; Each of the aforementioned resistor branches includes a sub-resistor and a switch connected in series.
5. The MOS transistor current sampling circuit as described in claim 3, characterized in that, The adjustable current source includes N parallel current source branches; Each of the aforementioned current source branches includes a sub-current source and a switch connected in series.
6. The MOS transistor current sampling circuit as described in claim 1, characterized in that, Both the main MOS transistor and the mirror MOS transistor are either NMOS transistors or both are PMOS transistors.
7. The MOS transistor current sampling circuit as described in claim 1, characterized in that, It also includes amplifiers, AD converters, and processors; The input terminal of the amplifier is connected to the first resistor to amplify the voltage across the first resistor to obtain an amplified voltage. The input terminal of the AD converter is connected to the output terminal of the amplifier, and the output terminal of the AD converter is connected to the processor. The AD converter is used to convert the amplified voltage from an analog quantity to a digital quantity. The processor is used to process the amplified digital voltage to obtain the current of the main MOSFET.
8. The MOS transistor current sampling circuit as described in claim 7, characterized in that, It also includes a filtering module, the first end of which is connected to the output of the amplifier, and the second end of which is connected to the input of the AD converter, for filtering the amplified voltage.
9. The MOS transistor current sampling circuit as described in any one of claims 1 to 8, characterized in that, It also includes a temperature sensor, which is disposed around the mirror MOS transistor to collect the ambient temperature of the mirror MOS transistor, so that the processor can use the ambient temperature to correct the current of the main MOS transistor obtained based on the voltage across the first resistor.
10. An electronic device, characterized in that, It includes a main MOSFET and a MOSFET current sampling circuit as described in any one of claims 1 to 9.