Fault monitoring circuit, chip and vehicle

Abstract

The utility model is suitable for the technical field of fault monitoring, and provides a fault monitoring circuit, a chip and a vehicle. The fault monitoring circuit comprises a first voltage monitoring module, a second voltage monitoring module, a third voltage monitoring module and a storage module, and the first voltage monitoring module, the second voltage monitoring module, the third voltage monitoring module and the storage module are all arranged in the chip. The first voltage monitoring module, the second voltage monitoring module and the third voltage monitoring module are electrically connected with the storage module. The fault monitoring circuit provided by the embodiment of the utility model can monitor the change conditions of the reference voltage, the power supply voltage and the power supply voltage in real time. When the voltage in the chip is abnormal, the abnormal monitoring signal can be quickly positioned by reading the monitoring signal in the storage module, so that the module corresponding to the abnormal monitoring signal is determined, and fault positioning in the chip is realized.

Description

Technical Field

[0001] This application belongs to the field of fault monitoring technology, and in particular relates to a fault monitoring circuit, chip and vehicle. Background Technology

[0002] In modern electronic systems, the stable operation of chips is crucial. Chips typically contain multiple power modules, providing the necessary voltages to different components. To ensure system reliability and stability, chips usually integrate fault monitoring circuits to monitor the output voltage of each power module in real time. However, while existing fault monitoring circuits in chips can detect abnormal power voltages, they often cannot accurately identify the faulty power module. This makes it difficult for engineers to quickly locate the faulty power module when an abnormal power voltage is detected and the fault monitoring circuit outputs a monitoring signal. Utility Model Content

[0003] This application provides a fault monitoring circuit, chip, and vehicle, which can solve the problem that existing fault monitoring circuits cannot accurately identify faulty power modules, making it difficult for engineers to quickly locate faulty power modules.

[0004] In a first aspect, embodiments of this application provide a fault monitoring circuit, which is disposed within a chip. The fault monitoring circuit includes a first voltage monitoring module, a second voltage monitoring module, a third voltage monitoring module, and a storage module. The first voltage monitoring module, the second voltage monitoring module, and the third voltage monitoring module are electrically connected to the storage module.

[0005] The first voltage monitoring module is used to receive the reference voltage inside the chip and output a first monitoring signal according to the reference voltage; the second voltage monitoring module is used to receive the power supply voltage of the chip and output a second monitoring signal according to the power supply voltage; the third voltage monitoring module is used to receive the power supply voltage inside the chip and output a third monitoring signal according to the power supply voltage; the storage module is used to store the first monitoring signal, the second monitoring signal and the third monitoring signal.

[0006] In one possible implementation of the first aspect, the first voltage monitoring module includes at least one first voltage monitoring unit, all of which are electrically connected to the storage module, and the first monitoring signal includes at least one first monitoring sub-signal.

[0007] Each of the first voltage monitoring units is used to receive a reference voltage within the chip, and output the first monitoring sub-signal based on the reference voltage and the reference voltage corresponding to the first voltage monitoring unit.

[0008] In one possible implementation of the first aspect, the first voltage monitoring unit includes a first resistor, a first switching transistor, and an inverter. A first terminal of the first resistor is electrically connected to a first power supply, and a second terminal of the first resistor is electrically connected to the drain of the first switching transistor and the input terminal of the inverter. The gate of the first switching transistor is used to receive a reference voltage, the source of the first switching transistor is grounded, and the output terminal of the inverter is electrically connected to the storage module.

[0009] In one possible implementation of the first aspect, the second voltage monitoring module includes at least one second voltage monitoring unit, all of which are electrically connected to the storage module, and the second monitoring signal includes at least one second monitoring sub-signal.

[0010] Each of the second voltage monitoring units is used to receive a power supply voltage of the chip, and output the second monitoring sub-signal according to the power supply voltage and the reference voltage corresponding to the second voltage monitoring unit.

[0011] In one possible implementation of the first aspect, the second voltage monitoring unit includes a second resistor, a third resistor, and a first comparator. The first terminal of the second resistor is used to receive a supply voltage. The second terminal of the second resistor is electrically connected to the first terminal of the third resistor and the first input terminal of the first comparator, respectively. The second terminal of the third resistor is grounded. The second input terminal of the first comparator is used to receive a reference voltage corresponding to the second voltage monitoring unit. The output terminal of the first comparator is electrically connected to the storage module.

[0012] In one possible implementation of the first aspect, the third voltage monitoring module includes at least one third voltage monitoring unit, all of which are electrically connected to the storage module, and the third monitoring signal includes at least one third monitoring sub-signal.

[0013] Each of the third voltage monitoring units is used to receive a power supply voltage within the chip, and output the third monitoring sub-signal based on the power supply voltage and the reference voltage corresponding to the third voltage monitoring unit.

[0014] In one possible implementation of the first aspect, the third voltage monitoring unit includes a fourth resistor, a fifth resistor, and a second comparator. The first terminal of the fourth resistor is used to receive a power supply voltage. The second terminal of the fourth resistor is electrically connected to the first terminal of the fifth resistor and the first input terminal of the second comparator, respectively. The second terminal of the fifth resistor is grounded. The second input terminal of the second comparator is used to receive a reference voltage corresponding to the third voltage monitoring unit. The output terminal of the second comparator is electrically connected to the storage module.

[0015] In one possible implementation of the first aspect, the fault monitoring circuit further includes an encoding module, wherein multiple input terminals of the encoding module are electrically connected to the first voltage monitoring module, the second voltage monitoring module, and the third voltage monitoring module respectively, and the output terminal of the encoding module is electrically connected to the storage module.

[0016] The encoding module is used to receive the first monitoring signal, the second monitoring signal, and the third monitoring signal, compress and encode the first monitoring signal, the second monitoring signal, and the third monitoring signal, and transmit the compressed and encoded signal to the storage module.

[0017] Secondly, embodiments of this application provide a chip including the fault monitoring circuit described in any one of the first aspects.

[0018] Thirdly, embodiments of this application provide a vehicle that includes the chip described in the second aspect.

[0019] The beneficial effects of the embodiments in this application compared with the prior art are:

[0020] The fault monitoring circuit provided in this application includes a first voltage monitoring module, a second voltage monitoring module, a third voltage monitoring module, and a storage module. The first voltage monitoring module receives a reference voltage within the chip and outputs a first monitoring signal based on the reference voltage. The second voltage monitoring module receives the chip's supply voltage and outputs a second monitoring signal based on the supply voltage. The third voltage monitoring module receives the chip's power supply voltage and outputs a third monitoring signal based on the power supply voltage. The storage module stores the first, second, and third monitoring signals. Therefore, the fault monitoring circuit provided in this application can monitor the changes in the reference voltage, supply voltage, and power supply voltage in real time, thereby achieving comprehensive monitoring of multiple power modules within the chip. When the first voltage monitoring module outputs the first monitoring signal, it indicates an abnormality in the reference voltage. When the second voltage monitoring module outputs the second monitoring signal, it indicates an abnormality in the supply voltage. When the third voltage monitoring module outputs the third monitoring signal, it indicates an abnormality in the power supply voltage. This design allows the fault monitoring circuit to determine whether the reference voltage is normal by reading the first monitoring signal from the storage module when it outputs a monitoring signal. It also allows the determination of whether the supply voltage is normal by reading the second monitoring signal from the storage module. By reading the third monitoring signal from the storage module, it is possible to determine whether the power supply voltage is normal. Therefore, when an abnormal voltage occurs within the chip, reading the monitoring signal from the storage module can quickly pinpoint the abnormal monitoring signal, thereby identifying the module corresponding to the abnormal monitoring signal and achieving fault location within the chip. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic block diagram of a fault monitoring circuit provided in one embodiment of this application;

[0023] Figure 2 This is a circuit connection diagram of the first voltage monitoring module provided in an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the voltage waveform of the first voltage monitoring unit provided in an embodiment of this application;

[0025] Figure 4 This is a circuit connection diagram of the first voltage monitoring unit provided in an embodiment of this application;

[0026] Figure 5 This is a circuit connection diagram of the second voltage monitoring unit provided in an embodiment of this application;

[0027] Figure 6 This is a schematic block diagram of a fault monitoring circuit provided in another embodiment of this application;

[0028] Figure 7 This is a circuit connection diagram of an encoding module provided in an embodiment of this application.

[0029] In the diagram, 10 is the fault monitoring circuit; 101 is the first voltage monitoring module; 102 is the second voltage monitoring module; 103 is the third voltage monitoring module; 104 is the storage module; and 105 is the encoding module. Detailed Implementation

[0030] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0031] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0032] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0034] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0036] While existing fault monitoring circuits in chips can detect abnormal power supply voltages, they typically cannot accurately identify the faulty power module. This makes it difficult for engineers to quickly locate the faulty power module when the fault monitoring circuit outputs a monitoring signal due to an abnormal power supply voltage.

[0037] Based on the above problems, the fault monitoring circuit provided in this application includes a first voltage monitoring module, a second voltage monitoring module, a third voltage monitoring module, and a storage module. The first voltage monitoring module receives a reference voltage within the chip and outputs a first monitoring signal based on the reference voltage. The second voltage monitoring module receives the chip's supply voltage and outputs a second monitoring signal based on the supply voltage. The third voltage monitoring module receives the chip's power supply voltage and outputs a third monitoring signal based on the power supply voltage. The storage module stores the first, second, and third monitoring signals. Therefore, the fault monitoring circuit provided in this application can monitor the changes in the reference voltage, supply voltage, and power supply voltage in real time, thereby achieving comprehensive monitoring of multiple power modules within the chip. When the first voltage monitoring module outputs the first monitoring signal, it indicates an abnormality in the reference voltage. When the second voltage monitoring module outputs the second monitoring signal, it indicates an abnormality in the supply voltage. When the third voltage monitoring module outputs the third monitoring signal, it indicates an abnormality in the power supply voltage. This design allows the fault monitoring circuit to determine whether the reference voltage is normal by reading the first monitoring signal from the storage module when it outputs a monitoring signal. By reading the second monitoring signal from the storage module, it can be determined whether the power supply voltage is normal. Similarly, by reading the third monitoring signal from the storage module, it can be determined whether the power supply voltage is normal. Therefore, when an abnormal voltage occurs within the chip, reading the monitoring signals from the storage module allows for rapid identification of the abnormal monitoring signal, thereby determining the module corresponding to the abnormal monitoring signal and achieving fault location within the chip.

[0038] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0039] Figure 1 A schematic block diagram of a fault monitoring circuit 10 according to an embodiment of this application is shown. See also... Figure 1 As shown, the fault monitoring circuit 10 includes a first voltage monitoring module 101, a second voltage monitoring module 102, a third voltage monitoring module 103, and a storage module 104. The first voltage monitoring module 101, the second voltage monitoring module 102, the third voltage monitoring module 103, and the storage module 104 are all located within the chip. The first voltage monitoring module 101, the second voltage monitoring module 102, and the third voltage monitoring module 103 are electrically connected to the storage module 104.

[0040] Specifically, the first voltage monitoring module 101 receives the reference voltage within the chip and outputs a first monitoring signal based on the reference voltage. The second voltage monitoring module 102 receives the supply voltage of the chip and outputs a second monitoring signal based on the supply voltage. The third voltage monitoring module 103 receives the power supply voltage within the chip and outputs a third monitoring signal based on the power supply voltage. The storage module 104 stores the first, second, and third monitoring signals. Therefore, the fault monitoring circuit 10 provided in this embodiment can monitor the changes in the reference voltage, supply voltage, and power supply voltage in real time, thereby achieving comprehensive monitoring of multiple power modules within the chip. When the first voltage monitoring module 101 outputs the first monitoring signal, it indicates an abnormality in the reference voltage. When the second voltage monitoring module 102 outputs the second monitoring signal, it indicates an abnormality in the supply voltage. When the third voltage monitoring module 103 outputs the third monitoring signal, it indicates an abnormality in the power supply voltage. This design allows the fault monitoring circuit 10 to determine whether the reference voltage is normal by reading the first monitoring signal from the storage module 104 when it outputs a monitoring signal. By reading the second monitoring signal in storage module 104, it can be determined whether the power supply voltage is normal. By reading the third monitoring signal in storage module 104, it can be determined whether the power supply voltage is normal. Therefore, when an abnormal voltage occurs within the chip, the abnormal monitoring signal can be quickly located by reading the monitoring signals in storage module 104, thereby identifying the module corresponding to the abnormal monitoring signal and realizing fault location within the chip.

[0041] It should be noted that the storage module 104 can store monitoring signals, ensuring that engineers can use the data to analyze the cause of the fault and provide data for fault diagnosis.

[0042] For example, storage module 104 can use SRAM (Static Random Access Memory) as its hardware fault tracing storage area. SRAM has the characteristic of no storage latency and can perform data read and write operations at high frequency, ensuring that data can be written and read quickly without causing delay to the real-time monitoring and response of the fault monitoring system.

[0043] In one embodiment of this application, the first voltage monitoring module includes at least one first voltage monitoring unit, all of which are electrically connected to the storage module, and the first monitoring signal includes at least one first monitoring sub-signal.

[0044] Specifically, the first voltage monitoring unit can receive the reference voltage and the corresponding reference voltage inside the chip. That is, a first voltage monitoring unit can receive a reference voltage and a reference voltage inside the chip, perform logical operations on the reference voltage and the reference voltage, and finally output a first monitoring sub-signal.

[0045] It should be noted that the reference voltage can be provided by a reference voltage module, other external circuitry, or a dedicated control unit. In some cases, the reference voltage may be set and adjusted via a power management chip or a microcontroller (MCU). The reference voltage can be dynamically adjusted according to system requirements and operating conditions.

[0046] In one embodiment of this application, such as Figure 2 As shown, the first voltage monitoring unit includes a first resistor R1, a first switch Q1, and an inverter U1. The first end of the first resistor R1 is electrically connected to the first power supply Vdd. The second end of the first resistor R1 is electrically connected to the drain of the first switch Q1 and the input of the inverter U1, respectively. The gate of the first switch Q1 is used to receive a reference voltage. The source of the first switch Q1 is grounded. The output of the inverter U1 is electrically connected to the storage module 104.

[0047] Specifically, the first resistor R1 is used for current limiting and voltage division. The first switching transistor Q1, as a switching device, can be turned off when the reference voltage V1 is less than the reference voltage and output a high-level signal to the inverter U1. The first switching transistor Q1 can also be turned on when the reference voltage V1 is greater than or equal to the reference voltage and output a low-level signal to the inverter U1. After receiving the input voltage signal (high-level signal or low-level signal), the inverter U1 inverts the input voltage signal. That is, when the inverter U1 receives a high-level signal, the first monitoring sub-signal Vout output by the inverter U1 to the storage module 104 is a low-level signal, and when the inverter U1 receives a low-level signal, the first monitoring sub-signal Vout output by the inverter U1 to the storage module 104 is a high-level signal. At the same time, the inverter U1 is also used for filtering, which can filter the input voltage signal and improve the accuracy of the first monitoring signal Vout. Specifically, when the reference voltage V1 is greater than or equal to the reference voltage, the first switch Q1 is in the ON state, and the first power supply Vdd, the first resistor R1, and the first switch Q1 form a circuit. The input of the inverter U1 is pulled low, and the first monitoring sub-signal Vout output by the inverter U1 is a high-level signal. When the reference voltage V1 is less than the reference voltage, the first switch Q1 is in the OFF state, and the first power supply Vdd, the first resistor R1, and the first switch Q1 cannot form a circuit. The input of the inverter U1 is high, and the first monitoring sub-signal Vout output by the inverter U1 is a low-level signal.

[0048] For example, the designer can select the type of the first switch Q1 according to the actual situation, that is, it can be a fully controllable power device such as a metal-oxide-semiconductor field-effect transistor or an insulated-gate bipolar transistor. For example, the first switch Q1 can be selected as an NMOS transistor. The turn-on threshold voltage of the first switch Q1 can be set to 0.7V, that is, the reference voltage can be set to 0.7V.

[0049] It should be noted that, as Figure 3 As shown, when the reference voltage V1 is greater than or equal to the reference voltage, the first switch Q1 is in the on state, and the first monitoring signal Vout output by the inverter U1 undergoes a step change (e.g., from 0 to 1), indicating that the reference voltage V1 is in a normal state. If the reference voltage V1 is abnormal, then the reference voltage V1 is less than the reference voltage, the first switch Q1 is in the off state, and the first monitoring signal Vout output by the inverter U1 is a low-level signal (e.g., 0).

[0050] In one embodiment of this application, the second voltage monitoring module 102 includes at least one second voltage monitoring unit, all of which are electrically connected to the storage module 104, and the second monitoring signal includes at least one second monitoring sub-signal.

[0051] Specifically, the second voltage monitoring unit can receive the chip's power supply voltage and the corresponding reference voltage. That is, a second voltage monitoring unit can receive a power supply voltage and a reference voltage of the chip, perform logical operations on the power supply voltage and the reference voltage, and finally output a second monitoring sub-signal.

[0052] It should be noted that the second voltage monitoring unit can consist of a primary voltage monitoring unit and a secondary voltage monitoring unit, both of which monitor the chip's supply voltage. The primary and secondary voltage monitoring units serve as automotive-grade functional safety backup circuits for each other; that is, these two units work together to ensure high reliability in voltage monitoring. In this design, both units are responsible for monitoring the aforementioned five voltages, but they have a redundant backup relationship to ensure that if one voltage monitoring unit fails, the other can take over the monitoring task. This design improves the overall reliability of the system; even if one voltage monitoring unit fails, the other can still operate normally, thus maintaining the system's functional safety.

[0053] In one embodiment of this application, such as Figure 4As shown, the second voltage monitoring unit includes a second resistor R2, a third resistor R3, and a first comparator CMP1. The first terminal of the second resistor R2 is used to receive a supply voltage V2. The second terminal of the second resistor R2 is electrically connected to the first terminal of the third resistor R3 and the first input terminal of the first comparator CMP1. The second terminal of the third resistor R3 is grounded. The second input terminal of the first comparator CMP1 is used to receive a reference voltage Vref corresponding to the second voltage monitoring unit. The output terminal of the first comparator CMP1 is electrically connected to the storage module 104.

[0054] Specifically, the second resistor R2 and the third resistor R3 are connected in series between the input port and ground. Both resistors R2 and R3 are used for voltage division, dividing the supply voltage V2 and transmitting the divided voltage to the first input terminal of the first comparator CMP1. The voltage transmitted to the first input terminal of the first comparator CMP1 (the voltage at the second end of the second resistor R2) is equal to the supply voltage V2 minus the voltage drop across the second resistor R2. The first input terminal of the first comparator CMP1 is a positive input terminal, used to receive the voltage after the supply voltage V2 is divided by the second resistor R2 and the third resistor R3. The second input terminal of the first comparator CMP1 is a negative input terminal, used to receive the reference voltage Vref. The first comparator CMP1 can compare the magnitude of the divided voltage and the reference voltage Vref, and output a second monitoring sub-signal to the storage module 104 based on the comparison result.

[0055] It should be noted that the value of the reference voltage Vref can be adjusted. For example, the first reference voltage can be set as a high voltage threshold, and the second reference voltage can be set as a low voltage threshold. When the voltage after voltage division is greater than the first reference voltage, the first comparator CMP1 outputs a high-level signal to the storage module 104, and the storage module 104 determines an overvoltage alarm based on the high-level signal. When the voltage after voltage division is less than the second reference voltage, the first comparator CMP1 outputs a low-level signal to the storage module 104, and the storage module 104 determines an undervoltage alarm based on the low-level signal.

[0056] For example, the voltage after voltage division can be expressed as:

[0057] V 分 =V2*R3 / (R2+R3)

[0058] Among them, V 分 V1 is the voltage after voltage division, that is, the voltage transmitted to the first input terminal of the first comparator CMP1. V2 is the supply voltage. R2 is the resistance value of the second resistor R2. R3 is the resistance value of the third resistor R3.

[0059] For example, the supply voltage V2 can be VEXT (External Voltage), VDDP3 (Digital Power Supply for 3.3V Domain), VDD (Voltage DirectDrive), EVRC (External Voltage Regulator Control), or EVR3.3 (External Voltage Regulator for 3.3V).

[0060] In one embodiment of this application, the third voltage monitoring module 103 includes at least one third voltage monitoring unit, all of which are electrically connected to the storage module 104, and the third monitoring signal includes at least one third monitoring sub-signal.

[0061] Specifically, the third voltage monitoring unit can receive the chip's power supply voltage and the corresponding reference voltage. That is, a third voltage monitoring unit can receive a power supply voltage and a reference voltage of the chip, perform logical operations on the power supply voltage and the reference voltage, and finally output a third monitoring sub-signal.

[0062] In one embodiment of this application, such as Figure 5 As shown, the third voltage monitoring module 103 includes a fourth resistor R4, a fifth resistor R5, and a second comparator CMP2. The first terminal of the fourth resistor R4 is used to receive a power supply voltage V3. The second terminal of the fourth resistor R4 is electrically connected to the first terminal of the fifth resistor R5 and the first input terminal of the second comparator CMP2. The second terminal of the fifth resistor R5 is grounded. The second input terminal of the second comparator CMP2 is used to receive a reference voltage Vref corresponding to the third voltage monitoring unit. The output terminal of the second comparator CMP2 is electrically connected to the storage module 104.

[0063] Specifically, the fourth resistor R4 and the fifth resistor R5 are connected in series between the input port and ground. Both resistors R4 and R5 are used for voltage division, dividing the power supply voltage V3 and transmitting the divided voltage to the first input terminal of the second comparator CMP2. The voltage transmitted to the first input terminal of the second comparator CMP2 (the voltage at the second terminal of the fourth resistor R4) is equal to the power supply voltage V3 minus the voltage drop across the fourth resistor R4. The first input terminal of the second comparator CMP2 is a positive input terminal, used to receive the voltage from the power supply voltage V3 after being divided by the fourth resistor R4 and the fifth resistor R5. The second input terminal of the second comparator CMP2 is a negative input terminal, used to receive the reference voltage Vref. The second comparator CMP2 can compare the magnitude of the divided voltage and the reference voltage Vref, and output a third monitoring sub-signal to the storage module 104 based on the comparison result.

[0064] For example, the power supply voltage V3 can be the on-chip VDDM (Voltage Direct Drive Memory) or VAREF (Voltage Analog Reference).

[0065] For example, the reference voltage Vref can be set to an extremely low voltage value. For instance, the reference voltage Vref can be set to 0.1V. If the voltage after voltage division is less than the reference voltage Vref, the second comparator CMP2 outputs a low-level signal to the storage module 104, and the storage module 104 determines a short-to-ground alarm based on the low-level signal. The voltage after voltage division can be expressed as:

[0066] V 分 =V3*R7 / (R6+R7)

[0067] Among them, V 分 V3 is the voltage after voltage division, which is the voltage transmitted to the first input terminal of the second comparator CMP2. V4 is the power supply voltage. R6 is the resistance value of the fourth resistor R4. R7 is the resistance value of the fifth resistor R5.

[0068] In one embodiment of this application, such as Figure 6 As shown, the fault monitoring circuit 10 also includes an encoding module 105. The multiple input terminals of the encoding module 105 are electrically connected to the first voltage monitoring module 101, the second voltage monitoring module 102 and the third voltage monitoring module 103, respectively. The output terminal of the encoding module 105 is electrically connected to the storage module 104.

[0069] Specifically, the encoding module 105 receives the first monitoring signal output from the first voltage monitoring module 101, the second monitoring signal output from the second voltage monitoring module 102, and the third monitoring signal output from the third voltage monitoring module 103. It then compresses and encodes these signals and transmits the compressed signals to the storage module. This design improves the processing efficiency of fault monitoring data and the utilization rate of storage space. By compressing and encoding the monitoring signals from the first voltage monitoring module 101, the second voltage monitoring module 102, and the third voltage monitoring module 103 using the encoding module 105, data redundancy and duplication can be reduced, thereby reducing the storage space required by the storage module 104. Simultaneously, the encoded signals are easier for subsequent data analysis and processing, facilitating rapid and accurate fault diagnosis and location. Furthermore, compression encoding helps reduce the bandwidth requirements for data transmission, improving the overall system performance and response speed.

[0070] In one embodiment of this application, the encoding module includes M AND gates and N OR gates. The inputs of the M AND gates are electrically connected to the first voltage monitoring module, the second voltage monitoring module, and the third voltage monitoring module, respectively. The outputs of the M AND gates are electrically connected to the inputs of the N OR gates, and the outputs of the N OR gates are all electrically connected to the storage module. Wherein, M and N are both positive integers, M > N, M ≥ M1 + M2 + M3, M1 is the number of first monitoring signals output by the first voltage monitoring module, M2 is the number of second monitoring signals output by the second voltage monitoring module, and M3 is the number of third monitoring signals output by the third voltage monitoring module.

[0071] Specifically, the AND gate's operation logic is as follows: the AND gate will only output a high-level signal when all of its input signals are high-level signals. If one input of the AND gate is a positive input and the remaining inputs are inverting inputs (the AND gate has inverters at its inputs), when the input signal is transmitted to the positive input, the AND gate receives the original input signal. When the input signal is transmitted to the inverting input, the AND gate receives the signal inverted by the inverter, that is, the original signal after level flipping. The OR gate's operation logic is as follows: when one of the multiple input signals received by the OR gate is a high-level signal, the OR gate will output a high-level signal.

[0072] For example, with Figure 7For example, M is 8 and N is 3. The encoding module 105 includes eight AND gates and three OR gates, meaning there are eight input signals (I0~I7) and three output signals (O0~O2). If M = M1 + M2 + M3 is set, the number of first monitoring sub-signals M1 is 1, the number of second monitoring sub-signals M2 is 5, and the number of third monitoring sub-signals M3 is 2. The I0 input signal is one of the first monitoring sub-signals in the first monitoring signal, the I1~I5 input signals are 5 of the second monitoring sub-signals in the second monitoring signal, and the I6~I7 input signals are 2 of the third monitoring sub-signals in the third monitoring signal. If the reference voltage V1 in the chip is abnormal, or one of the chip's power supply voltages is abnormal, while the other voltages in the chip are normal, then the first monitoring sub-signal is 0, and the first second monitoring sub-signal is 1, that is, the I0 input signal is 0, the I1 input signal is 1, and at this time, the three output signals are 001 in sequence.

[0073] It should be noted that the number of monitoring signals can also be set to other values. In this case, the eight input signals include the first monitoring signal, the second monitoring signal, the third monitoring signal, and the monitoring signals output by other modules, thus forming a multi-channel compression encoder. Therefore, by compressing and encoding the eight input signals, three output signals are ultimately output. This design can reduce data redundancy and duplication, thereby reducing the storage space required by the storage module 104.

[0074] It should be noted that if the I0 input signal is 1 and the remaining seven input signals are all 0, then the three output signals will be 000. If the I0 input signal is 0, the I1 input signal is 1, and the remaining six input signals can take any value, then the three output signals will be 001. If the I0 input signal is 0, the I1 input signal is 0, the I2 input signal is 1, and the remaining five input signals can take any value, then the three output signals will be 010. Therefore, to prevent multiple alarm signals from being valid simultaneously, it is stipulated that only the alarm signal with the lowest sequence number is output. Designers can set the corresponding position of the monitoring signals according to the importance of the voltage detection within the chip, that is, the more important the monitoring signal, the earlier its position.

[0075] This application also discloses a chip including the above-mentioned fault monitoring circuit. When the voltage inside the chip is abnormal, the abnormal monitoring signal can be quickly located by reading the monitoring signal in the storage module of the fault monitoring circuit, thereby determining the module corresponding to the abnormal monitoring signal and realizing fault location within the chip.

[0076] This application also discloses a vehicle that includes the aforementioned chip. When the vehicle's electronic system malfunctions, the fault monitoring circuit within the chip can quickly locate the source of the fault, thereby improving the efficiency and accuracy of fault diagnosis.

[0077] Since the processing and functions implemented by the chip in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned fault monitoring circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0078] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A fault monitoring circuit, characterized in that, The fault monitoring circuit is located inside the chip. The fault monitoring circuit includes a first voltage monitoring module, a second voltage monitoring module, a third voltage monitoring module, and a storage module. The first voltage monitoring module, the second voltage monitoring module, and the third voltage monitoring module are electrically connected to the storage module. The first voltage monitoring module is used to receive the reference voltage inside the chip and output a first monitoring signal according to the reference voltage; The second voltage monitoring module is used to receive the power supply voltage of the chip and output a second monitoring signal according to the power supply voltage; the third voltage monitoring module is used to receive the power supply voltage in the chip and output a third monitoring signal according to the power supply voltage; the storage module is used to store the first monitoring signal, the second monitoring signal and the third monitoring signal.

2. The fault monitoring circuit according to claim 1, characterized in that, The first voltage monitoring module includes at least one first voltage monitoring unit, all of which are electrically connected to the storage module, and the first monitoring signal includes at least one first monitoring sub-signal. Each of the first voltage monitoring units is used to receive a reference voltage within the chip, and output the first monitoring sub-signal based on the reference voltage and the reference voltage corresponding to the first voltage monitoring unit.

3. The fault monitoring circuit according to claim 2, characterized in that, The first voltage monitoring unit includes a first resistor, a first switching transistor, and an inverter. The first end of the first resistor is electrically connected to a first power supply, and the second end of the first resistor is electrically connected to the drain of the first switching transistor and the input of the inverter. The gate of the first switching transistor is used to receive a reference voltage, the source of the first switching transistor is grounded, and the output of the inverter is electrically connected to the storage module.

4. The fault monitoring circuit according to claim 1, characterized in that, The second voltage monitoring module includes at least one second voltage monitoring unit, all of which are electrically connected to the storage module, and the second monitoring signal includes at least one second monitoring sub-signal. Each of the second voltage monitoring units is used to receive a power supply voltage of the chip, and output the second monitoring sub-signal according to the power supply voltage and the reference voltage corresponding to the second voltage monitoring unit.

5. The fault monitoring circuit according to claim 4, characterized in that, The second voltage monitoring unit includes a second resistor, a third resistor, and a first comparator. The first end of the second resistor is used to receive a supply voltage. The second end of the second resistor is electrically connected to the first end of the third resistor and the first input end of the first comparator. The second end of the third resistor is grounded. The second input end of the first comparator is used to receive a reference voltage corresponding to the second voltage monitoring unit. The output end of the first comparator is electrically connected to the storage module.

6. The fault monitoring circuit according to claim 1, characterized in that, The third voltage monitoring module includes at least one third voltage monitoring unit, all of which are electrically connected to the storage module, and the third monitoring signal includes at least one third monitoring sub-signal. Each of the third voltage monitoring units is used to receive a power supply voltage within the chip, and output the third monitoring sub-signal based on the power supply voltage and the reference voltage corresponding to the third voltage monitoring unit.

7. The fault monitoring circuit according to claim 6, characterized in that, The third voltage monitoring unit includes a fourth resistor, a fifth resistor, and a second comparator. The first terminal of the fourth resistor is used to receive a power supply voltage. The second terminal of the fourth resistor is electrically connected to the first terminal of the fifth resistor and the first input terminal of the second comparator. The second terminal of the fifth resistor is grounded. The second input terminal of the second comparator is used to receive a reference voltage corresponding to the third voltage monitoring unit. The output terminal of the second comparator is electrically connected to the storage module.

8. The fault monitoring circuit according to any one of claims 1-7, characterized in that, The fault monitoring circuit further includes an encoding module, wherein multiple input terminals of the encoding module are electrically connected to the first voltage monitoring module, the second voltage monitoring module, and the third voltage monitoring module respectively, and the output terminal of the encoding module is electrically connected to the storage module. The encoding module is used to receive the first monitoring signal, the second monitoring signal, and the third monitoring signal, compress and encode the first monitoring signal, the second monitoring signal, and the third monitoring signal, and transmit the compressed and encoded signal to the storage module.

9. A chip, characterized in that, Includes the fault monitoring circuit as described in any one of claims 1-8.

10. A vehicle, characterized in that, Includes the chip described in claim 9.

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