Memory

Abstract

A memory includes a logic circuit having a first input, a second input, and an output, and a memory circuit, the memory circuit including: a transistor coupled to the logic circuit, the transistor having a semiconductor layer including a source and a drain; and the storage node is provided with a first connecting piece, a second connecting piece and a third connecting piece. The logic circuit includes one or more transistors in an active region of a substrate, the one or more transistors being front-end-of-line (FEOL) devices, and the semiconductor layer and the storage node being located in a back-end-of-line (BEOL) layer over the substrate.

Description

Technical Field

[0001] This disclosure relates to a memory, and more particularly to a memory having a stacked substrate. Background Technology

[0002] Recent advancements in artificial intelligence have spawned a variety of products and / or applications, including speech recognition, image processing, machine learning, and natural language processing. These products and / or applications frequently move large amounts of data to and from data processors for learning, training, cognitive computation, and other purposes. Utility Model Content

[0003] One embodiment of this disclosure includes a memory, comprising: a logic circuit having a first input, a second input, and an output; and a memory circuit including a transistor coupled to the logic circuit, the transistor having a semiconductor layer including a source and a drain; and a storage node having a first connector, a second connector, and a third connector, wherein the source or drain of the transistor is coupled to the first connector of the storage node, the logic circuit including a transistor in an active region of a substrate, the transistor being a front-end process (FEOL) device, and the semiconductor layer and the storage node being located in a back-end process (BEOL) layer above the substrate.

[0004] One embodiment of this disclosure includes a memory, comprising: a logic circuit having a first input, a second input, and an output; and a memory circuit including a storage capacitor and a transistor, wherein: the transistor and the logic circuit are located on a first substrate, and the storage capacitor is located on a second substrate, the storage capacitor having a first terminal and a second terminal, the transistor having a source and a drain, and the source or drain being coupled to the first terminal of the storage capacitor via a conductor, the conductor including an interconnect connecting the first substrate and the second substrate, and the first input of the logic circuit being coupled to the first terminal of the storage capacitor.

[0005] One embodiment of this disclosure includes a memory, comprising: a logic circuit having a first input, a second input, and an output; a substrate having an active region, the active region including: one or more first transistors, the one or more first transistors being front-end process devices; a second transistor having a semiconductor layer including a source and a drain; a storage node electrically connected to one of the source and the drain; and a capacitor, the terminals of the capacitor being electrically connected to the other of the source and the drain, wherein the semiconductor layer and the storage node are located in a back-end process layer above the substrate. Attached Figure Description

[0006] When with attachment Figure 1When reading this document, the following detailed description is the best way to understand the various features disclosed. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 A block diagram of a memory according to one embodiment;

[0008] Figure 2 This is a schematic diagram of a memory according to one embodiment;

[0009] Figure 3 This is a schematic diagram of a neural network according to one embodiment;

[0010] Figure 4 This is a schematic diagram of an integrated circuit (IC) device according to an embodiment;

[0011] Figure 5A This is a circuit diagram of a single-chip 3D digital CIM DRAM bit cell according to an embodiment;

[0012] Figure 5B A cross-sectional view of an apparatus comprising a monolithic 3D digital CIM DRAM bit cell according to an embodiment;

[0013] Figure 5C This is a flowchart of a method for manufacturing a monolithic 3D digital CIM DRAM bit cell according to an embodiment;

[0014] Figure 6A A circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to an embodiment;

[0015] Figure 6B A cross-sectional view of an apparatus comprising a heterogeneous 3D digital CIM DRAM bit cell according to an embodiment;

[0016] Figure 6C This is a flowchart of a method for manufacturing a monolithic 3D digital CIM DRAM bit cell according to an embodiment;

[0017] Figure 6D A circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to an embodiment;

[0018] Figure 6E A circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to an embodiment;

[0019] Figure 7 A circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to an embodiment;

[0020] Figure 8A A circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell according to an embodiment;

[0021] Figure 8B This is a flowchart of a method for manufacturing a monolithic 3D digital CIM DRAM bit cell using active and passive substrates according to an embodiment;

[0022] Figure 9 This is a schematic diagram of a memory macro according to one embodiment;

[0023] Figure 10 This is a flowchart of a method for operating a circuit according to an embodiment.

[0024] [Symbol Explanation]

[0025] 100: Memory

[0026] 105: First memory segmentation

[0027] 107: Second Memory Segmentation

[0028] 110: Memory Macros

[0029] 112: Memory Array

[0030] 113: Memory Unit

[0031] 114: Weight Buffer

[0032] 115: Output Circuit

[0033] 117: Memory Unit

[0034] 117a: Storage section

[0035] 117b: Arithmetic Section

[0036] 120: Memory controller

[0037] 122: Character line driver

[0038] 124: Bit line driver

[0039] 126: Control Circuit

[0040] 128: Input Buffer

[0041] 200: Memory

[0042] 202: Memory Macros

[0043] 204: Memory Macros

[0044] 206: Memory Macros

[0045] 208: Memory Macros

[0046] 211: Input Data

[0047] 212: Matrix

[0048] 214: Matrix

[0049] 216: Matrix

[0050] 218: Matrix

[0051] 219: Output Data

[0052] 220: Memory controller

[0053] 232: Processor

[0054] 234: Memory Device

[0055] 236: Bus

[0056] 300: Neural Networks

[0057] 400: Integrated Circuit Device

[0058] 500: Single-chip 3D digital CIM DRAM bit unit

[0059] 505: Bit Unit Device

[0060] 510: Semiconductor substrate

[0061] 512: Front Layer

[0062] 514: Rear Layer

[0063] 518: Active Zone

[0064] 520: Contact

[0065] 522: Conductor

[0066] 524: Through hole

[0067] 526: Conductor

[0068] 528: Through hole

[0069] 530: Access Transistor

[0070] 532: Semiconductor layer

[0071] 534: Gate

[0072] 540: Storage capacitor

[0073] 542: First capacitor electrode

[0074] 544: Second capacitor electrode

[0075] 546: Capacitor dielectric layer

[0076] 600: Heterogeneous 3D Digital CIM DRAM Bit Unit

[0077] 600': Heterogeneous 3D Digital CIM DRAM Bit Unit

[0078] 600”: Heterogeneous 3D Digital CIM DRAM Bit Unit

[0079] 605: Bit Unit Device

[0080] 610: First substrate

[0081] 618: Active Zone

[0082] 620: Second substrate

[0083] 628: Active Zone

[0084] 650: Hybrid Joint Structure

[0085] 652: First dielectric layer

[0086] 654: First interconnect element

[0087] 656: Connecting bump

[0088] 658: Silicon Through-Hole

[0089] 682: Second dielectric layer

[0090] 684: Second interconnect element

[0091] 700: 3D Digital CIM DRAM Bit Unit

[0092] 800: 3D Digital CIM DRAM Bit Unit

[0093] 900: Memory Macro

[0094] 905: MAC Array

[0095] 905_1, 905_2, 905_3~905_n: MAC array

[0096] 910: Bit cell array

[0097] 920: Adder Tree

[0098] 930: Bit shifter and accumulator

[0099] 1000: Method

[0100] 1010: First Operation

[0101] 1012: Operation

[0102] 1014: Operation

[0103] 1020: Second Operation

[0104] 1022: Operation

[0105] 1024: Operation

[0106] 1026: Operation

[0107] 5000: Method

[0108] 5012: Operation

[0109] 5014: Operation

[0110] 5016: Operation

[0111] 5018: Operation

[0112] 6000: Method

[0113] 6012: Operation

[0114] 6013: Operation

[0115] 6014: Operation

[0116] 6015: Operation

[0117] 6016: Operation

[0118] 6018: Operation

[0119] 8000: Method

[0120] 8002: Operation

[0121] 8003: Operation

[0122] 8004: Operation

[0123] 8005: Operation

[0124] 8006: Operation

[0125] 8008: Operation

[0126] A1: Node

[0127] B1: Node

[0128] BL: Bitline

[0129] BL1, BL2~BLt: Bit lines

[0130] BS1: Back side of the first substrate 610

[0131] BS2: Back side of the second substrate 620

[0132] C_d: Second capacitor

[0133] C_s: Storage capacitor

[0134] D: Storage Node

[0135] D[1], D[2]~D[i]: Output

[0136] D_IN: Input data

[0137] D_IN2: Input data

[0138] D_IN4: Input data

[0139] D_IN6: Input data

[0140] D_IN8: Input data

[0141] D_O: Data

[0142] D_OUT: Output data / output signal

[0143] D_OUT1: Output signal

[0144] D_OUT2: Output data

[0145] D_OUT4: Output data

[0146] D_OUT6: Output data

[0147] D_OUT8: Output data

[0148] FS1: Front side of the first substrate 610

[0149] FS2: Front side of the second substrate 620

[0150] IN: Input signal

[0151] IN[M:0]: Input signal

[0152] LO: Logic Circuit

[0153] LO': Logic circuit

[0154] M0~Mn: Metal layer

[0155] Mn-x: Metallic layer

[0156] OUT: Output signal

[0157] PL: Board Line

[0158] ROW[N:0]: signal

[0159] SL: Selection Logic

[0160] T_a: Access transistor

[0161] TSB: Tri-state buffer

[0162] TSB0~TSB n Tri-state buffer

[0163] W(A1,B1): Weights

[0164] W_IN: Weighted data

[0165] W1,t: fragment

[0166] WL: Character Line

[0167] WL1, WL2~WLr: Character lines Detailed Implementation

[0168] The following disclosure provides various embodiments or instances of features for implementing the provided subject matter. Specific examples of components, materials, values, steps, configurations, etc., are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not limiting. Other components, materials, values, steps, configurations, etc., may be considered. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first features are not in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0169] Furthermore, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the figures and one or more other elements or features. In addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0170] Some embodiments described herein relate to a dynamic random access memory (DRAM) bit cell implemented in a 3D structure having a stacked substrate and containing logic to perform computing-in-memory (CIM) operations. This bit cell may also be referred to herein as a 3D digital CIM DRAM bit cell, or simply a bit cell. Some embodiments described herein relate to a memory having multiple 3D digital CIM DRAM bit cells.

[0171] In at least some embodiments, when computation is performed using data, computing-in-memory (CIM) reduces the amount of data moved to and from the processor. In examples of general-purpose analog CIM (static random access memory) (SRAM) designs, the input / startup is converted to analog voltages or pulse widths.

[0172] Examples of CIM operations include mathematical operations, logical operations, and their combinations. Examples of CIM operations include NotOr (NOR), Add Or Invert (AOI), Or And Invert (OAI), and Multiply Accumulate (MAC). Another example of CIM operations is the multiplication of a multi-bit weight value with a multi-bit input data value.

[0173] In one embodiment, the CIM operation uses the value stored in the bit cell as the direct input to the CIM logic. In another embodiment, the CIM operation passes the value stored in the bit cell to intermediate logic or circuitry, such as a selector or multiplexer, which produces the input to the CIM logic as its output.

[0174] Examples of CIM applications to which the embodiments disclosed herein can be applied include artificial intelligence, image recognition, neural networks (NN) and deep neural networks (DNN) for machine learning, large language models (LLM), input and output nodes, and bitwise neural networks (BNN) with weights represented by a single bit. In one embodiment, compared to a device or system that receives data from memory via a bus or network, one or more advantages of digital CIM include reduced data transmission, reduced processing time, reduced power consumption, reduced chip area, reduced manufacturing costs, and improved performance.

[0175] A 3D digital CIM DRAM bit cell according to one embodiment has a significant reduction in computation time and / or power consumption compared to, for example, a corresponding SRAM design. A 3D digital CIM DRAM bit cell according to one embodiment has a smaller footprint (area) and / or lower leakage compared to SRAM-based digital CIM bit cells. A 3D digital CIM DRAM bit cell according to one embodiment supports applications using a large number of weighting parameters.

[0176] According to one embodiment, a 3D digital CIM DRAM bit cell has a charge storage node in the back-end (BE) or front-end (FE) of a 1T1C (single transistor single capacitor) DRAM bit, leading to a logic circuit or logic gate (e.g., NAND, NOR, AOI / OAI, etc.; see also). Figures 5A to 8A The logic circuit (LO) in the multiplexer is a direct connector to the input of the logic circuit (LO) to perform bit-by-bit computations, such as weight calculations. In one embodiment, multiple sets of bit cells store different sets of weights, and the multiplexer or equivalent logic (see [link to original text]) is used. Figure 6E The logical SL in the middle switches between different groups.

[0177] In a device according to one embodiment, logic and bit cells for performing one or more logic operations (e.g., multiplication, addition, and / or other logic operations) are stacked (e.g., positioned below the bit cells), which reduces the overall footprint or die area of ​​the device. This device is also referred to as a circuit-under-array (CuA) device.

[0178] In a bit cell according to one embodiment, CIM operations are performed without using a sense amplifier to perform bit cell readout operations, thus reducing latency and power consumption compared to a device or system that receives data from memory via a bus or network for arithmetic logic. In one embodiment, the bit cell supports general bit cell read / write operations performed concurrently with the CIM operations.

[0179] In one embodiment, the bit cell is implemented in a 3D structure having stacked substrates, wherein the first and second substrates are designed and / or manufactured at different technology nodes. In one embodiment, the second substrate is a memory die having a region substantially or primarily occupied by 1T1C memory circuitry. In one embodiment, the second substrate is manufactured using a process node that allows a higher voltage to be applied to the word lines on the second substrate relative to the voltage applied to the gates of transistors on the first substrate (e.g., logically). In one embodiment, the memory circuitry transistors on the second substrate are written at a higher voltage than the supply voltage of the logic gates on the first substrate, which helps ensure the correct functioning of the logic gates and lower leakage, even after the hold voltage drop of the memory cell's storage node.

[0180] In one embodiment, the memory cell array includes a plurality of memory cells, each memory cell including memory circuitry for storing values ​​in a storage node. In one embodiment, each memory circuitry is used to store a digital value in the storage node. In one embodiment, each memory circuitry is used to store 0 or 1 as a single bit value in the storage node. Hereinafter, a memory cell containing CIM logic and used to store digital values ​​in a storage node is referred to as a bit cell. In one embodiment, the bit cell is, and can be, a 3D DRAM bit cell, wherein the DRAM bit cell is implemented in a 3D structure having a stacked substrate. Hereinafter, a memory cell array including a plurality of bit cells is referred to as a bit cell array.

[0181] In one embodiment, each cell includes memory circuitry coupled to logic circuitry. In some embodiments, the logic circuitry is coupled to each memory circuitry in a one-to-one relationship. In some other embodiments, the logic circuitry is coupled to multiple memory circuitries.

[0182] In one embodiment, the logic circuit is coupled to a storage node of the memory circuit. In some embodiments, the logic circuit is directly connected to the storage node of the memory circuit without access transistors or other transistors in the connection. In some other embodiments, the storage node of the memory circuit is connected to (i) a corresponding access transistor and (ii) a corresponding input of the logic circuit, respectively.

[0183] In one embodiment, the logic circuit generates an output signal in response to a first signal and a second signal, the first signal representing a value stored at a storage node of the memory circuit and input to a first input of the logic circuit, and the second signal being input to a second input of the logic circuit. In another embodiment, the logic circuit generates an output signal representing the result of a computing-in-memory (CIM) operation on the first and second signals, wherein the first signal represents a value stored at a storage node of the memory circuit and input to a first input of the logic circuit, and the second signal is input to a second input of the logic circuit.

[0184] In one embodiment, each of the plurality of memory cells includes memory circuitry coupled to logic circuitry serving as a multiplier circuit. In one embodiment, the logic circuitry is a multiplier circuitry configured to generate an output signal representing the product of a first signal and a second signal, the first signal representing a value stored at a storage node of the memory circuitry and input to a first input of the logic circuitry, and the second signal being input to a second input of the logic circuitry. In one embodiment, the output signal corresponds to the product of the first signal and the second signal.

[0185] Figure 1 This is a block diagram of a memory 100 according to one embodiment.

[0186] In one embodiment, memory 100 is implemented as an integrated circuit (IC) device. In some embodiments, memory 100 is implemented as a separate IC device. In some other embodiments, memory 100 is implemented as part of a larger IC device that includes circuitry for functions other than those of memory 100.

[0187] Memory 100 includes a memory macro 110 and a memory controller 120. Memory macro 110 includes a memory array 112, a weighted buffer 114, and output circuitry 115. Memory controller 120 includes a word line driver 122, a bit line driver 124, control circuitry 126, and an input buffer 128. In one embodiment, one or more of the word line driver 122, bit line driver 124, control circuitry 126, or input buffer 128 are included in memory macro 110, and / or one or more of the weighted buffer 114 or output circuitry 115 are included in memory controller 120.

[0188] Generally, macros have reusable configurations and can be used in various types or designs of IC devices. In one instance, a macro is understood in a context similar to the architectural hierarchy of modular programming, where a main program (or other sub-common) calls a sub-common / program to perform a given computational function. In this context, the IC device uses macros to perform one or more given functions. Therefore, in this context and in terms of the architectural hierarchy, the IC device is similar to the main program, and the macro is similar to a sub-common / program. In one instance, the macro is a soft macro. In some embodiments, the macro is a hard macro. In one instance, the macro is a soft macro described numerically in register-transfer level (RTL) code. In one instance, the macro has not yet been composed, placed, and routed, allowing soft macros to be composed, placed, and routed for various process nodes. In one instance, the macro is a hard macro described digitally in a binary file format (e.g., a Graphic Database System II (GDSII) stream format), where the binary file format represents the planar geometry, text labels, and other information of one or more layout diagrams of the macro in a hierarchical manner. In one instance, composition, placement, and routing are performed on the macro to make the hard macro specific to a particular process node.

[0189] A memory macro is a macro containing memory cells that can be addressed to allow data to be written to or read from memory cells. In one example, a memory macro includes circuitry for providing access to memory cells and / or performing functions associated with memory cells (e.g., read, write, or another function). In one embodiment, memory macro 110 includes memory cells (MCs) 117 as described herein, which form circuitry for providing CIM functionality associated with memory cells 117. A memory macro used to provide CIM functionality may be referred to as a CIM macro.

[0190] In memory 100, memory cells 117 of memory macro 110 are configured in columns and rows of memory array 112. Memory controller 120 is electrically coupled to memory cells 117 and is used to control the operation of memory cells 117, including, for example, read operations, write operations, etc. Memory array 112 is coupled to word lines (also called "address lines") WL1, WL2...WLr extending along rows, and bit lines (also called "data lines") BL1, BL2...BLt extending along columns of memory cells 117 (where r and t are natural numbers). Various numbers of word lines and / or bit lines in memory array 112 are within the scope of various embodiments. Word lines are generally referred to herein as WL, and bit lines are generally referred to herein as BL.

[0191] Memory unit 117 performs CIM functions on stored data (e.g., stored weight data) and input data. In one example embodiment, memory 100 is used to simultaneously update weight data and perform CIM calculations.

[0192] exist Figure 1 In the process, weight buffer 114 transmits weight data W_IN to be stored in memory unit 117, and input buffer 128 transmits input data D_IN to memory unit 117. Figure 1 In this embodiment, the weight buffer 114 is located in the memory macro 110, and the input buffer 128 is located in the memory controller 120. In other embodiments, the weight buffer 114 is located in the memory controller 120, and the input buffer 128 is located in the memory macro 110, or both the weight buffer 114 and the input buffer 128 are located in the memory macro 120, or both the weight buffer 114 and the input buffer 128 are located in the memory controller 120.

[0193] Each of the memory cells 117 is electrically coupled to the memory controller 120 via at least one of the word lines WL and at least one of the bit lines BL. In some instances, the word lines WL are used to transmit the address of the memory cell 117 to be read, written, etc. In some instances, the bit lines BL are used to transmit data read from or written to the memory cell 117 indicated by the corresponding word line WL.

[0194] The memory types of the memory cell 117 include static random-access memory (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FERAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), phase-change RAM (PCRAM), spin-transfer torque RAM (STTRAM), floating-gate metal-oxide-semiconductor field-effect transistor (FGMOS), spintronic devices, etc. In one embodiment, the memory cell 117 is a DRAM memory cell.

[0195] In memory 100, memory cell 117 is a single-port memory cell. In one embodiment, the port of the memory cell is represented by a set of word lines WL and bit lines BL (referred to herein as the WL / BL set), which provides access to the memory cell in read operations (i.e., read access) and / or write operations (i.e., write access). A single-port memory cell has one WL / BL set used for both read and write access, but not simultaneously. In one embodiment, one or more single-port memory cells described herein are replaced by corresponding multi-port memory cells. A multi-port memory cell has several WL / BL sets, each of which is used only for read access, or only for write access, or both for read and write access.

[0196] In one embodiment, memory array 112 includes memory segments. Memory segments include memory rows, memory columns, memory groups, etc. In one embodiment, memory segments include multiple memory groups. Memory rows include memory cells 117 coupled to the same word line WL. Memory columns (also referred to as "memory strings") include memory cells 117 coupled to the same bit line BL. Memory groups include more than one memory row and / or more than one memory column. In one embodiment, a memory group includes a portion of memory array 112 having multiple memory rows and multiple memory columns. In memory 100, a first memory segment 105 includes a column of memory cells 117 coupled to bit line BL1. Furthermore, a second memory segment 107 includes a column of memory cells 117 coupled to bit line BL2.

[0197] In memory 100, each memory cell 117 includes a storage portion 117a (shown only in memory cell 117 for ease of explanation). In one embodiment, each memory cell 117 also includes an arithmetic portion 117b (shown only in one memory cell 117 for ease of explanation).

[0198] In one embodiment, each storage portion 117a corresponds to each arithmetic portion 117b in a one-to-one relationship. In other embodiments, one arithmetic portion 117b corresponds to multiple storage portions 117a. For example, a single arithmetic portion 117a is provided as a logic element that is coupled to multiple storage portions 117a using, for example, multiplexer or row selection logic.

[0199] In one embodiment, each memory unit 117 is used to store one bit of weight data W_IN, and to calculate the corresponding bit of the output signal D_OUT1 based on the CIM operation of the weight data W and the input data D_IN. For example, in Figure 1 In this memory unit 117, each storage portion 117a stores one bit of weight data W_IN, and each arithmetic portion 117b of the memory unit 117 performs CIM operations on the stored data and one bit of input data D_IN. For example, memory unit 113 (coupled to word line WL1 and bit line BLT) stores a segment W1,t of weight data W_IN, and performs CIM operations on the segment W1,t of weight data W_IN and the corresponding segment of input data D_IN. In an exemplary embodiment, the input data D_IN is serially supplied to the arithmetic portion 117b in the form of a bit stream.

[0200] In one embodiment, a combination of multiple segments or bits of weight data stored in multiple memory units constitutes a weight value to be used in the CIM operation. For simplicity, a segment or bit of weight data stored in memory unit 117, multiple segments or bits of weight data stored in multiple memory units 117, or all segments or bits of weight data stored in all memory units 117 of memory array 112 are referred to herein as weight data. In other embodiments, multiple bit memory units are provided, each of which is used to store more than one bit of weight data and to perform corresponding CIM operations on the corresponding segments of multi-bit weight data.

[0201] In one embodiment, each memory cell 117 is a unit memory cell storing a value of 0 or 1. In another embodiment, each memory cell 117 is a 3D digital CIM DRAM bit cell storing a single bit.

[0202] In memory 100, each arithmetic unit 117b of memory cell 117 is coupled to input buffer 128 to receive input data D_IN, that is, input data D_IN is supplied from input buffer 128 in memory controller 120. In other embodiments, input data D_IN is received as data output from another memory macro of memory 100 (e.g., output data D_OUT).

[0203] In memory 100, the arithmetic section 117b of memory cell 117 is used to generate output data corresponding to the CIM operation performed on the input data D_IN (received from input buffer 128) and weight data W_IN stored in memory cell 117. In one embodiment, the arithmetic section 117b is included in or incorporated into a Not Or (NOR) circuit, an Add Or Invert (AOI) circuit, or an Or And Invert (OAI) circuit. In one embodiment, the arithmetic section 117b is included in or incorporated into a Multiply Accumulate (MAC) circuit. Additional or different arithmetic sections or circuits are used to perform CIM operations other than multiplication.

[0204] In memory 100, a weight buffer 114 is coupled to memory array 112 and is used to temporarily hold new data, such as weight data, to be updated or stored in memory array 112. In another embodiment, the weight buffer 114 is located outside memory macro 110. In some embodiments, each memory segment is coupled to a corresponding weight buffer 114, or a common weight buffer 114 is coupled to several memory segments. The weight buffer 114 is coupled to memory cells 117 in memory array 112 via bit lines BL, and in a weight data update operation, new weight data is written from the weight buffer 114 to one or more memory cells 117 via the corresponding bit lines BL. Figure 1 As shown, weight buffer 114 is coupled to memory controller 120, which controls the provision of control signals specifying when and / or which memory cells 117 are updated with new weight data. In one embodiment, new weight data is received from an external circuitry system (e.g., a processor) outside of memory 100. In an example embodiment, new weight data is received via one or more input / output (I / O) circuits (not shown) of memory controller 120 and forwarded to weight buffer 114. The example weight buffer includes registers, memory cells, and other circuitry for data storage.

[0205] In one embodiment, output circuit 115 is used to latch read data received from storage portion 117a of memory cell 117 from bit line BL. In one embodiment, output circuit 115 is or includes a register, flip-flop, latch, etc. In one embodiment, output circuit 115 includes a sense amplifier that reads the state of values ​​(e.g., logic 0 or 1) stored in storage portion 117a of memory cell 117.

[0206] In memory 100, output circuit 115 receives data D_O output from arithmetic section 117b of memory cell 117. Data D_O from arithmetic section 117b is directly supplied as output signal D_OUT on the output of output circuit 115, or it is processed in output circuit 115 and then supplied as output signal D_OUT.

[0207] In one embodiment, the output data D_OUT is supplied as input data to another memory macro (not shown) of memory 100. In another embodiment, the output data D_OUT is output to an external circuit system outside memory 100, such as a processor, via one or more I / O circuits (not shown) of memory controller 120.

[0208] In memory 100, memory controller 120 includes word line driver 122, bit line driver 124, control circuitry 126, and input buffer 128. In one embodiment, memory controller 120 further includes one or more clock generators for providing clock signals to various components of memory 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations in memory 100.

[0209] In memory 100, word line driver 122 is coupled to memory array 112 via word line WL. Word line driver 122 is used to decode the row address of memory cell 117 selected for access during a read or write operation. Word line driver 122 supplies voltage to the selected word line WL corresponding to the decoded row address and supplies another voltage to the other unselected word lines WL.

[0210] In memory 100, bit line driver 124 is coupled to memory array 112 via bit line BL. Bit line driver 124 is used to decode the column address of memory cell 117 selected for access during a read or write operation. Bit line driver 124 is used to supply voltage to the selected bit line BL corresponding to the decoded column address, and to supply another voltage to other unselected bit lines BL.

[0211] In memory 100, control circuitry 126 is coupled to one or more of memory cells 117, weighted buffers 114, output circuitry 115, word line drivers 122, bit line drivers 124, or input buffers 128 to coordinate the operation of these circuits, drivers, and / or buffers in the overall operation of memory 100. For example, control circuitry 126 generates various control signals for controlling the operation of one or more of memory cells 117, weighted buffers 114, output circuitry 115, word line drivers 122, bit line drivers 124, and / or input buffers 128.

[0212] In memory 100, input buffer 128 is used to receive input data from external circuitry (e.g., a processor) outside of memory 100. The input data is received via one or more I / O circuits (not shown) of memory controller 120 and forwarded to memory array 112 via input buffer 128. Example input buffers include registers, memory cells, or other circuitry elements for data storage.

[0213] Compared to another method in which data moves back and forth between memory and processor to provide computation, memory 100 containing multiple 3D digital CIM DRAM bit cells is advantageous because using memory 100 can avoid this back-and-forth data movement, which is a bottleneck for performance and energy efficiency.

[0214] As described above, in one embodiment, each memory unit 117 includes a storage portion 117a and a processing portion 117b. Each storage portion 117a is used to store a segment or a bit of weighted data W_IN, and each processing portion 117b is used to perform CIM operations on the segment or bit of weighted data W_IN and a segment of received data D_IN.

[0215] Figure 2 This is a schematic diagram of a memory 200 according to one embodiment.

[0216] Memory 200 includes memory macros 202, 204, 206, and 208, and a memory controller 220. In one embodiment, one or more of memory macros 202, 204, 206, and 208 correspond to... Figure 1 The memory macro 110. In one embodiment, the memory controller 220 corresponds to... Figure 1 The memory controller 120.

[0217] Memory controller 220 is a common memory controller for memory macros 202, 204, 206, and 208. In another embodiment, at least one of memory macros 202, 204, 206, and 208 has its own memory controller. As an example... Figure 2 In memory, the number of memory macros in memory 200 is four.

[0218] In memory 200, memory macros 202, 204, 206, and 208 are sequentially coupled to each other, with the output data of the previous memory macro serving as the input data for the next. For example, input data D_IN2 is input to memory macro 202. Memory macro 202 is based on the input data D_IN2 and the weight data stored in memory macro 202 (combined with...). Figure 1 The described process performs one or more CIM operations and produces output data D_OUT2 as the result of the CIM operation. The output data D_OUT2 is supplied to memory macro 204 as input data D_IN4. Memory macro 204 performs one or more CIM operations based on the input data D_IN4 and weight data stored in memory macro 204, and produces output data D_OUT4 as the result of the CIM operation. The output data D_OUT4 is supplied as input data D_IN6 to memory macro 206. Memory macro 206 performs one or more CIM operations based on the input data D_IN6 and weight data stored in memory macro 206, and produces output data D_OUT6 as the result of the CIM operation. The output data D_OUT6 is supplied as input data D_IN8 to memory macro 208. The memory macro 208 performs one or more CIM operations based on the input data D_IN8 and the weight data stored in the memory macro 208, and produces output data D_OUT8 as the result of the CIM operation. In one embodiment, one or more of the input data D_IN2, D_IN4, D_IN6, and D_IN8 correspond to weights relative to... Figure 1 The described input data D_IN, and / or one or more of the output data D_OUT2, D_OUT4, D_OUT6, and D_OUT8, correspond to the input data D_IN. Figure 1 The described output data is D_OUT. In one embodiment, the configuration of memory macros 202, 204, 206, and 208 is implemented as a neural network or as part of a neural network.

[0219] Figure 3 This is a schematic diagram of a neural network 300 according to an embodiment.

[0220] Neural network 300 comprises layers A, B, C, D, and E, each containing multiple nodes (or neurons). Nodes in consecutive layers of neural network 300 are connected to each other via connection matrices or arrays. For example, nodes in layers A and B are connected via connections in matrix 212, nodes in layers B and C are connected via connections in matrix 214, nodes in layers C and D are connected via connections in matrix 216, and nodes in layers D and E are connected via connections in matrix 218. Layer A is the input layer for receiving input data 211. Input data 211 propagates from one layer to the next through the neural network 300 via corresponding connection matrices between layers. As data propagates through neural network 300, it undergoes one or more operations and is output as output data 219 from layer E, which is the output layer of neural network 300. The three layers B, C, and D between input layer A and output layer E are called hidden layers or intermediate layers. Figure 3 Three hidden layers are shown. In some embodiments, the neural network 300 has one, two, or more than three hidden layers or intermediate layers. Figure 3 The number of layers, the number of connection matrices, and the number of nodes in each layer are examples. In another embodiment, the neural network 300 does not contain hidden layers and has an input layer connected to the output layer via a connection matrix.

[0221] In one embodiment, matrices 212, 214, 216, and 218 are implemented accordingly by memory macros 202, 204, 206, and 208, input data 211 corresponds to input data D_IN2, and output data 219 corresponds to output data D_OUT8, and thus similar detailed descriptions are omitted. In one embodiment, in matrix 212, the connection between a node in layer A and another node in layer B has a corresponding weight. For example, the connection between node A1 and node B1 has a weight W(A1,B1) corresponding to a weight value stored in the memory array of memory macro 202. Memory macros 204, 206, and 208 are configured in a similar manner. When machine learning is performed using neural network 300, the weight data in one or more of memory macros 202, 204, 206, and 208 is updated, for example, by a processor and via memory controller 220. According to some embodiments, one or more advantages described herein can be achieved in a neural network 300 implemented wholly or partially by one or more memories, memory macros and / or memory devices.

[0222] Figure 4 This is a schematic diagram of an integrated circuit (IC) device 400 according to an embodiment.

[0223] In one example embodiment, the IC device 400 includes Figure 1 The memory 100. In one example embodiment, the IC device 400 includes... Figure 2 200 of the memory.

[0224] IC device 400 includes one or more processors 232 and one or more memory devices 234 coupled to the one or more processors 232 via one or more buses 236. In one embodiment, each of the one or more processors 232 is a hardware processor. In one embodiment, the one or more processors 232 can be used as... Figure 1 Memory controller 120 or Figure 2 One or more components in the memory controller 220. In one embodiment, a memory device 234 may be used as... Figure 1 One or more components in the memory macro 110, or Figure 2 One or more of the memory macros 202, 204, 206 or 208.

[0225] In one embodiment, the IC device 400 includes one or more additional circuitry, such as a cellular transceiver, a global positioning system (GPS) receiver, a network interface circuitry for one or more of Wi-Fi, USB, or Bluetooth, etc. Examples of processors 232 include a central processing unit (CPU), a multi-core CPU, a neural processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic devices, a multimedia processor, an image signal processor (ISP), etc. Examples of memory devices 234 include one or more memories, memory devices, and / or memory macros described herein. In one embodiment, each of the plurality of processors 232 is coupled to a corresponding memory device among the plurality of memory devices 234.

[0226] In one embodiment, one or more of the memory devices 234 are CIM memory devices, which include a plurality of 3D digital CIM DRAM bit cells described herein, and therefore, various operations can be performed in the memory devices. This reduces the computational workload of the corresponding one or more processors 232, reduces data transfer (e.g., on bus 236), reduces memory access time, and / or improves performance compared to a device or system where the arithmetic logic receives data from memory via a bus or network. In one embodiment, the IC device 400 is a system-on-a-chip (SOC).

[0227] Figure 5A This is a circuit diagram of a monolithic 3D digital CIM DRAM bit cell 500 according to one embodiment.

[0228] In one embodiment, bit unit 500 is included in the combination Figure 1 The memory unit 117 described may be this memory unit 117.

[0229] In one embodiment, the bit unit 500 is implemented as a monolithic 3D device having front-end devices formed in one or more front-end layers 512 on a first side of a substrate 510, and rear-end devices formed in a rear-end layer 514 on the first side of the substrate 510 above the one or more front-end layers 512. In some embodiments, the front-end devices and / or the rear-end devices are active devices including at least one transistor. The substrate 510 may be a wafer, a die, or other substrate.

[0230] In the in-bit cell 500, the back layer 514 contains memory circuitry with a 1T1C design (i.e., 1T1C circuitry). Memory structures other than 1T1C circuitry can be used.

[0231] In bit cell 500, storage node D is located in back layer 514, and storage node D is electrically connected to logic circuit LO containing one or more transistors in front layer 512. Figure 5A In the middle, bit cell 500 is implemented by 1T1C circuit. The access transistor T_a and storage capacitor C_s of 1T1C circuit are both located in the back layer 514 and are electrically connected from the storage node D in the back layer 514 (which is connected to the terminal of the storage capacitor C_s) to one or more logic circuits LO in the front layer 512.

[0232] One or more front-end layers 512 include transistors forming NOR gates (as an example of logic circuits LO), which have an electrical connection at a first input to a storage node D in the back-end layer 514. That is, the input to the NOR gate is a first signal representing a value stored in storage node D. The NOR gate receives an input signal IN at a second input that is logically combined with the first signal (representing a value, such as a logic 0 or 1 stored in storage node D), and the NOR gate operates to output an output signal OUT, which is false if either input is true. In another embodiment (… Figure 5A Not shown in the image; see also Figure 6D The logic circuit LO has three or more inputs, one of which is a first signal representing a value stored in storage node D. In other embodiments, the logic circuit LO is logic (which may be one or more circuit levels) used to perform operations such as AOI or OAI, or selection or multiplexing operations. In various cases, the logic circuit LO receives a first signal representing a value stored in storage node D as an input. In one embodiment, bit cell 500 constitutes a bit-by-bit multiplier.

[0233] In one embodiment, a voltage corresponding to the weight value to be stored in storage node D is written to bit cell 500. In one embodiment, a plurality of bit cells 500 are provided, and each bit cell 500 stores bits of a multi-bit weight value.

[0234] exist Figure 5A In this circuit, storage node D has three connections: a connection to the logic circuit LO, a connection to the access transistor T_a of the 1T1C circuit, and a connection to the storage capacitor C_s. In bit cell 500, the transistor is only present in one of the three connections; the transistor is the access transistor T_a. The first signal representing the value stored in storage node D is transmitted to the logic circuit LO without being actively controlled, gated, or switched. In other words, the connection from storage node D in the back-end layer 514 to the input of the logic circuit LO does not contain a transistor, and the logic circuit LO is directly connected to storage node D.

[0235] Examples of access transistors T_a include metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), finFETs, and planar MOS transistors with convex source / drain electrodes.

[0236] In bit cell 500, the word line (WL) is connected to the gate of the access transistor T_a, and the bit line (BL) is connected to the source / drain region (e.g., the source region) in the access transistor T_a.

[0237] The storage capacitor C_s has terminals connected to the storage node D. In one embodiment, the storage capacitor C_s is a discrete device, for example, having a first terminal and a second terminal separated by a charge storage dielectric (e.g., a dielectric layer such as a high-k material layer). In another embodiment, a capacitive structure other than a discrete capacitor is used. In one embodiment, the storage node D is part of or connected to the drain of the access transistor T_a.

[0238] In this document, access transistor T_a is considered to be activated in response to a voltage on word line WL sufficient to place access transistor T_a in a conductive state. In one embodiment, access transistor T_a is activated to write a value to or read a value from storage node D, while the connection between storage node D and the input of logic circuit LO on the first substrate remains connected, regardless of the voltage on word line WL or the state of access transistor T_a.

[0239] exist Figure 5A In this embodiment, storage node D is coupled to or formed as a terminal of storage capacitor C_s. In other embodiments, storage node D is a storage element such as SRAM, FERAM, RRAM, MRAM, PCRAM, STTRAM, FGMOS, spintronic element, etc., which remains connected to the input of logic circuit LO without being actively controlled, gated, or switched.

[0240] In one embodiment, the back-end layer 514 includes a plurality of bit cells 500 and is configured in an array (e.g., a regular rectangular grid pattern). The array of bit cells 500 may be referred to herein as a bit cell array. In embodiments of the bit cell array, two or more DRAM cells in a column share a single bit line BL.

[0241] In bit cell 500, storage node D is coupled to or formed as a terminal of storage capacitor C_s. Storage capacitor C_s has a first terminal connected to storage node D and a second terminal connected to board line PL. In one embodiment, the individual board lines PL of the plurality of bit cells 500 are electrically connected together. In one embodiment, board line PL is held to a reference voltage, such as ground (GND) or VSS, but in other embodiments another voltage, such as VDD, is used. In one embodiment, the reference voltage is a constant voltage. In another embodiment, the reference voltage is modulated or controlled to vary. In one embodiment, the storage element is FERAM, and the reference voltage is VDD, which is pulsed to a voltage other than VDD during write operations to the storage element.

[0242] exist Figure 5A In this embodiment, the access transistor T_a and the storage capacitor C_s are fabricated as BEOL devices in the back layer 514, and the logic circuit LO includes one or more transistors fabricated as FEOL devices in one or more front layers 512. Fabricating at least one of the access transistor T_a or the storage capacitor C_s in the back layer 514 reduces the overall area of ​​the bit cell. In one embodiment, the transistor implemented as a BEOL device, i.e., the transistor integrated into the metal layer of the back layer 514, is a thin-film transistor (TFT). In an exemplary embodiment, the transistor implemented as a BEOL device includes an oxide semiconductor material for the semiconductor layer (or channel), such as indium gallium zinc oxide (IGZO). Figure 5A Bit cell 500 contains an NMOS transistor as an access transistor T_a, but in other embodiments, the access transistor T_a is a PMOS transistor.

[0243] As follows Figure 9 In further detail, the output signal OUT of the logic circuit LO of bit unit 500 can be provided as the input of the adder tree.

[0244] exist Figure 5A In this embodiment, the access transistor T_a is contained in the back layer 514. In other embodiments, the access transistor T_a is contained in one or more front layers 512.

[0245] Figure 5B This is a cross-sectional view of an apparatus 505 comprising a monolithic 3D digital CIM DRAM bit cell according to an embodiment.

[0246] exist Figure 5B In this embodiment, the bit cell device 505 includes one or more active devices formed in the active region 518 of the semiconductor substrate 510. In some embodiments, the active device formed in the active region 518 includes one or more transistors, which in some instances are MOSFETs, PFETs and / or NFETs, CMOS transistors, FinFETs, planar MOS transistors with convex source / drain electrodes, BJTs, high-voltage transistors, high-frequency transistors, etc. The active device forms a portion of a logic circuit LO in one or more FEOL layers. In some embodiments, the active device forms a portion of one or more logic gates of a logic circuit such as NAND, NOR, AOI / OAI.

[0247] In the in-situ unit device 505, the BEOL layer above the substrate 510 includes metal layers M0 to Mn. The first metal layer M0 includes a conductor 522 connected to an active device in the active region 518 via a contact 520. The conductor 522 is connected to a conductor 526 in the overlying metal layers Mn-x via a through-hole 524.

[0248] The access transistor 530 of the 1T1C DRAM memory circuit is formed above the metal layer Mn-x. The access transistor 530 includes a semiconductor layer 532 and a gate 534. The semiconductor layer 532 is the channel layer of the access transistor 520 and has source / drain regions on the opposite side of the gate 534. In one embodiment, the semiconductor layer 532 comprises an oxide semiconductor material such as IGZO. The access transistor 530 includes a gate dielectric layer (not shown) between the semiconductor layer 530 and the gate 534. In one embodiment, the gate dielectric layer is formed of a metal oxide material. In one embodiment, the gate 534 is formed of a metal or other conductive material typically used for metal lines in the metal layers M0-Mn. In another embodiment, the gate 532 is formed of a material selectively used for the gate 534 and different from the metal used in the metal layers M0-Mn.

[0249] A storage capacitor 540 is formed in the BEOL layer above the access transistor 530. The storage capacitor 540 is connected to the access transistor 530 through a via 528 and a conductor 526. The storage capacitor 540 includes a first capacitor electrode 542 and a second capacitor electrode 544 facing the capacitor dielectric layer 546. In one embodiment, the first capacitor electrode 542 is formed in one of the metal layers M0 to Mn, and the second capacitor electrode 544 is formed as another conductive layer above the capacitor dielectric layer 546. The second capacitor electrode 542 is connected to the conductor 546 through the via 544. In one embodiment, the capacitor electrodes 542 and 544 are formed of a metal or other conductive material typically used for metal wires in the metal layers M0 to Mn. In another embodiment, the capacitor electrodes are formed of a material selectively used for the capacitor electrodes and different from the metal used in the metal layers M0 to Mn. In one embodiment, the capacitor dielectric layer 546 is formed of a material selectively used for the capacitor dielectric material and different from the material of the dielectric layer separating the metal layers M0 to Mn. In one embodiment, the capacitor dielectric layer 546 is a high-k material layer.

[0250] Figure 5C This is a flowchart of a method 5000 for manufacturing a single 3D digital CIM DRAM bit cell according to an embodiment.

[0251] Method 5000 includes operation 5012 of forming one or more active devices in one or more FEOL layers on a first side of a substrate. In some embodiments, the substrate is a wafer, a die, or other substrate. In some embodiments, the substrate is a single-crystal silicon substrate, a substrate having a silicon-on-insulator (SOI) structure, or another type of semiconductor substrate. In some embodiments, the active device includes one or more transistors, which in some instances are MOSFETs, PFETs and / or NFETs, CMOS transistors, finFETs, planar MOS transistors with convex source / drain terminals, BJTs, high-voltage transistors, high-frequency transistors, etc. The active device forms a portion of a logic circuit LO in one or more FEOL layers. In some embodiments, the active device in one or more FEOL layers forms a portion of one or more logic gates such as NAND, NOR, AOI / OAI, etc.

[0252] Method 5000 includes an operation 5014 of forming a BEOL layer on a first side of a substrate over one or more FEOL layers. Forming the BEOL layer includes forming one or more metal layers M0-Mn, forming an interlayer dielectric, and forming interconnect vias. The metal layers M0-Mn and the vias in the BEOL layer form wiring that interconnects active devices in the one or more FEOL layers to complete one or more logic gates (e.g., NAND, NOR, AOI / OAI, etc.) and connects access transistors T_a, storage capacitors C_s, and storage nodes D in the BEOL layer.

[0253] Operation 5014 includes operation 5016 of forming access transistor T_a in the BEOL layer and operation 5018 of forming storage capacitor C_s in the BEOL layer.

[0254] The operation 5016 of forming an access transistor T_a in the BEOL layer includes forming a semiconductor layer and forming a gate adjacent to the semiconductor layer. The semiconductor layer is formed to serve as a channel layer and has source / drain regions on the opposite side of the gate. In one embodiment, the semiconductor layer is an oxide semiconductor, such as IGZO. Forming the access transistor T_a in the BEOL layer further includes forming a gate dielectric layer between the semiconductor layer and the gate. In one embodiment, the gate dielectric layer is formed of a metal oxide material. In one embodiment, the gate is formed of a metal or other conductive material typically used for metal lines in the metal layers M0 to Mn. In another embodiment, the gate is formed of a material selectively used for the gate and different from the material of the metal lines. In one embodiment, the access transistor T_a is formed as a planar FET.

[0255] The operation 5018 of forming a storage capacitor C_s in the BEOL layer includes forming capacitor electrodes facing the capacitor dielectric layer. In one example, a first capacitor electrode is formed in one of the metal layers M0 to Mn, and a second capacitor electrode is formed in another adjacent metal in the metal layers M0 to Mn. In one embodiment, the capacitor electrode is formed of a metal or other conductive material typically used for metal wires in the metal layers M0 to Mn. In another embodiment, the capacitor electrode is formed of a material selectively used for the capacitor electrode and different from the material of the metal wire. In one embodiment, the capacitor dielectric layer is formed of a material selectively used for the capacitor dielectric material and different from the material of the interlayer dielectric layer of the BEOL layer.

[0256] In some embodiments, the access transistor T_a is formed in a lower layer of the BEOL layer, and the storage capacitor C_s is formed in a higher layer of the BEOL layer above the access transistor. In other embodiments, the storage capacitor C_s is formed in the common BEOL layer of the access transistor T_a, or below the access transistor T_a. In some embodiments, the access transistor T_a and / or the storage capacitor C_s are formed to vertically overlap with one or more logic gates in one or more FEOL layers, thereby reducing the die area occupied by the bit cells of the monolithic 3D digital CIM DRAM.

[0257] In method 5000, the access transistor T_a is described as being formed in one or more front-end layers 512. In other embodiments, the access transistor T_a is alternatively formed in a back-end layer 514.

[0258] Figure 6A This is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell 600 according to one embodiment.

[0259] In one embodiment, bit unit 600 is included in the combination Figure 1 The memory unit 117 described may be memory unit 117.

[0260] Bit cell 600 has a substrate stack, wherein a first substrate and a second substrate are combined by stacking, with one substrate stacked on top of the other substrate.

[0261] In one embodiment, bit cell 600 is a heterogeneous device, wherein the first and second substrates are different dies with different functions and / or are manufactured using different wafer node technologies (i.e., different process nodes).

[0262] For ease of reference, the first substrate may be referred to as the lower or bottom substrate, and the second substrate may be referred to as the upper or top substrate, but the terms “lower”, “bottom”, “upper” and “top” do not imply a specific orientation.

[0263] although Figure 6A The illustration shows certain elements contained in the first or lower substrate, but these elements may also be contained in the second or upper substrate. In other embodiments, elements shown as contained in the second or upper substrate are contained in the first or lower substrate.

[0264] The first substrate can be a wafer, a die, or other substrate. The second substrate can be a wafer, a die, or other substrate. The first substrate can be the same type as or different from the second substrate. If the second substrate can be a die and the first substrate can be a wafer, this structure can be called a chip-on-wafer (CoW) structure. If the second substrate can be a first wafer and the first substrate can be a second wafer, this structure can be called a wafer-on-wafer (WoW) structure. The first and second substrates can be combined in a face-to-face or face-to-back configuration.

[0265] In another embodiment, the first and second substrates include elements, such as active or passive elements, like transistors or capacitors, manufactured according to the same process node for each of the first and second substrates. In another embodiment, the first substrate includes elements, such as active or passive elements, like transistors or capacitors, manufactured according to a first process node, and the second substrate includes elements, such as active or passive elements, like transistors or capacitors, manufactured according to a second process node different from the first process node. Where the second process node differs from the first process node, the second process node may correspond to a different cost and / or PPA (power, performance, and area) for manufacturing the elements relative to the first process node. In a particular example, where the second process node differs from the first process node, the second process node provides a minimum transistor gate length different from the minimum transistor gate length of the first process node.

[0266] In some embodiments, the first and second substrates are the only substrates in the stack, that is, the stack of substrates has exactly two substrates, or in other embodiments, the first and second substrates are two of a stack of three or more substrates. Increasing the number of substrates in the stack increases the overall memory density.

[0267] The first and second substrates are assembled using appropriate 3D stacking techniques. In some embodiments, hybrid bonding or bumpless techniques such as SoIC-X, or microbump techniques such as SoIC-P, are used to assemble the first and second substrates. SoIC refers to System on Chip, which provides a stack of logical logic and logical memory chips, as well as heterogeneous integration of dies of different sizes, functions, and / or different wafer node technologies (i.e., different process nodes), all integrated into a single compact system chip.

[0268] In embodiments using hybrid bonding or bumpless technology, hybrid bonding is used to combine the first and second substrates, wherein two materials (e.g., metal-to-metal bonding, such as copper-to-copper bonding, and dielectric-to-dielectric bonding, of the first material) or more than two materials are bonded. Metal-to-metal bonding forms interconnects, wherein metal features (e.g., metal lines, metal pads, etc.) at the surface of the first substrate are bonded to metal features (e.g., metal lines, metal pads, etc.) at the surface of the second substrate. SoIC-X is a bumpless stacking technology using hybrid bonding that can be used for die-on-wafer or wafer-on-wafer stacking with a bond pitch of approximately 4.5 μm to approximately 9 μm.

[0269] In embodiments using microbump technology, microbump assemblies are used for the first and second substrates, wherein metal (e.g., solder, etc.) microbumps on the surface of one of the first or second substrates are bonded to metal features (e.g., metal lines, metal pads, etc.) on the surface of the other of the first or second substrates. Microbump technology forms interconnects comprising microbumps. SoIC-P is a microbump (μbump) stacking technology that can be used for μbump stacks with a pitch of approximately 18 μm to approximately 25 μm. In the case of stacking three or more substrates, the same stacking technology is used for all substrates, or a mixture of stacking technologies is used.

[0270] In the in-bit cell 600, the second substrate includes a memory circuit with a 1T1C design (i.e., a 1T1C circuit). Memory structures other than 1T1C circuits can be used.

[0271] In the bit cell 600, the storage node D is located on the second substrate, and the storage node D is electrically connected to the logic circuit LO on the first substrate. Figure 6A In this circuit, the bit cell 600 is implemented by a 1T1C circuit. The access transistor T_a and the storage capacitor C_s of the 1T1C circuit are both located on the second substrate, and the electrical connection extends from the storage node D on the second substrate (e.g., from the terminal of the storage capacitor) to the logic circuit LO on the first substrate. As described above, the electrical connection is or includes interconnects formed using hybrid bonding or bumpless technology, interconnects formed using microbump technology, etc.

[0272] In bit cell 600, the first substrate includes a NOR gate (as an example of logic circuit LO) having an electrical connection at its first input to a storage node D on the second substrate. That is, the input to the NOR gate is a first signal representing a value stored in storage node D. The NOR gate receives an input signal IN at its second input, which is logically combined with the first signal representing a value stored in storage node D (e.g., logic 0 or 1), and the NOR gate operates to output an output signal OUT, whereby the output signal OUT is false if either input is "true". In another embodiment (… Figure 6A Not shown in the image; see also Figure 6B The logic circuit LO has three or more inputs, one of which is a first signal representing a value stored in the storage node D. In other embodiments, the logic circuit LO is logic (which may be one or more circuit levels) used to perform operations such as AOI or OAI, or selection or multiplexing operations. In various cases, the logic circuit LO has a first signal representing a value stored in the storage node D as an input. In one embodiment, the bit unit 600 constitutes a bit-by-bit multiplier.

[0273] In one embodiment, a voltage corresponding to the weight value to be stored in storage node D is written to bit cell 600. In one embodiment, a plurality of bit cells 600 are provided, and each bit cell 600 stores bits of a multi-bit weight value.

[0274] exist Figure 6A In this circuit, storage node D has three connections: a connection to the logic circuit LO on the first substrate, a connection to the access transistor T_a of the 1T1C circuit, and a connection to the storage capacitor C_s. In bit cell 600, the transistor is only present in one of the three connections; this transistor is the access transistor T_a. A first signal representing the value stored in storage node D is transmitted to the logic circuit LO without being actively controlled, gated, or switched. In other words, the connection from storage node D on the second substrate to the input of the logic circuit LO on the first substrate does not contain a transistor, and the logic circuit LO is directly connected to storage node D.

[0275] Examples of access transistors T_a include metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), finFETs, and planar MOS transistors with convex source / drain electrodes.

[0276] In bit cell 600, the word line (WL) is connected to the gate of access transistor T_a, and the bit line (BL) is connected to the source / drain region (e.g., the source region) in access transistor T_a.

[0277] exist Figure 6A In this embodiment, the storage capacitor C_s has terminals connected to the storage node D. In one embodiment, the storage capacitor C_s is a discrete device, for example, having a first terminal and a second terminal separated by a charge storage dielectric (e.g., a dielectric layer). In another embodiment, a capacitive structure other than a discrete capacitor is used. In one embodiment, the storage node D is part of or connected to the drain of the access transistor T_a.

[0278] In this document, access transistor T_a is considered to be activated in response to a voltage on word line WL sufficient to place access transistor T_a in a conductive state. In one embodiment, access transistor T_a is activated to write a value to or read a value from storage node D, while the connection between storage node D and the input of logic circuit LO on the first substrate remains connected, regardless of the voltage on word line WL or the state of access transistor T_a.

[0279] In other embodiments, the storage node D is a storage element such as SRAM, FERAM, RRAM, MRAM, PCRAM, STTRAM, FGMOS, spintronic element, etc., which remains connected to the input of the logic circuit LO without being actively controlled, gated or switched.

[0280] In one embodiment, the second substrate includes a plurality of bit cells 600 and is arranged in an array (e.g., a regular rectangular grid pattern). The array of bit cells 600 may be referred to herein as a bit cell array. In embodiments of the bit cell array, two or more DRAM cells in a column share a single bit line BL.

[0281] In bit cell 600, storage node D has a connection to storage capacitor C_s. Storage capacitor C_s has a first terminal connected to storage node D and a second terminal connected to board line PL. In one embodiment, the individual board lines PL of the plurality of bit cells 600 are electrically connected together. In one embodiment, board line PL is held to a reference voltage, such as ground (GND) or VSS, but in other embodiments another voltage, such as VDD, is used. In one embodiment, the reference voltage is a constant voltage. In another embodiment, the reference voltage is modulated or controlled to vary. In one embodiment, the storage element is FERAM, and the reference voltage is VDD, which is pulsed to a voltage other than VDD during write operations to the storage element.

[0282] In one embodiment, the memory includes an array of bit cells 600, each bit cell 600 having a storage node D on a second substrate and an electrical connection (which may be or include hybrid bonding or bumpless interconnects, microbump interconnects, etc.), such that an array of electrical connections corresponding to the array of bit cells 600 (i.e., an array of hybrid bonding or bumpless interconnects, microbump interconnects, etc.) connects the first and second substrates. In one example embodiment, the ratio of bit cells to electrical connections to the first to second substrates in the array is 1:1. In another example embodiment, the ratio of bit cells to electrical connections to the first to second substrates is not 1:1. For example, the following discussion... Figure 7 The bit cell 700 contains a 2:1 (or higher) ratio of bit cells: first to second substrate electrical connection, that is, two or more bit cells share the electrical connection between substrates.

[0283] In one embodiment, bit cell 600 includes an access transistor T_a fabricated as a FEOL device on a second substrate, and logic circuit LO includes one or more transistors fabricated as FEOL devices on a first substrate. In one embodiment, access transistor T_a and storage capacitor C_s are fabricated as FEOL devices on a second substrate, and logic circuit LO includes one or more transistors fabricated as FEOL devices on a first substrate. In one embodiment, at least one of access transistor T_a or storage capacitor C_s is fabricated as a BEOL device on a second substrate (e.g., in a metal layer above the FEOL device on the second substrate, which reduces the overall area of ​​the second substrate), and logic circuit LO includes one or more transistors fabricated as FEOL devices on a first substrate. In an exemplary embodiment, the transistor implemented as a BEOL device, i.e., a transistor integrated into the metal layer of the BEOL structure, is a thin-film transistor (TFT). In an exemplary embodiment, the transistor implemented as a BEOL device includes an indium-gallium-zinc oxide (IGZO) channel.

[0284] As follows Figure 9 In further detail, the output signal OUT of the logic circuit LO of bit unit 600 can be provided as the input of the adder tree.

[0285] The various states of bit cell 600 described above are also combined in the following text. Figures 6B to 6E , Figure 7 and Figures 8A to 8B The description describes the state of the bit unit. Therefore, some details will not be repeated below to avoid confusing the description of other features.

[0286] Figure 6B This is a cross-sectional view of a device 605 comprising heterogeneous 3D digital CIM DRAM bit cells according to an embodiment.

[0287] The bit cell device 605 includes a substrate stack, wherein a first substrate 610 and a second substrate 620 are combined by stacking. For ease of reference, the first substrate 610 may be referred to as a lower or bottom substrate, and the second substrate 620 may be referred to as an upper or top substrate, but the terms “lower,” “bottom,” “upper,” and “top” do not imply a particular orientation.

[0288] The first substrate 610 includes an active region 618, in which logic circuitry (e.g., the logic circuitry LO described above) is formed. The second substrate 620 includes an active region 628, in which 1T1C DRAM memory circuitry is formed. The 1T1C circuitry includes access transistors (e.g., access transistor T_a described above) and storage capacitors (e.g., storage capacitor C_s described above).

[0289] exist Figure 6B In this configuration, a first substrate 610 and a second substrate 620 are arranged back-to-back, with the back side BS1 of the first substrate 610 facing the front side FS2 of the second substrate 620 and bonded to the front side FS2 of the second substrate 620 via hybrid bonding. The front side FS1 of the first substrate 610 includes connection bumps 656 (e.g., solder balls) for connecting to adjacent substrates (e.g., wafers, PCBs, etc.). Signal and / or power routing is performed to the back side BS1 of the first substrate 610 using through-silicon vias 658.

[0290] The hybrid bonding structure 650 includes a first dielectric layer 652 at the back side BS1 of the first substrate, which faces and bonds to a second dielectric layer 682 at the front side FS2 of the second substrate 620. In some embodiments, the first dielectric layer 652 and the second dielectric layer 652 comprise a silicon-containing dielectric, such as silicon oxide, silicon oxynitride, or silane oxide. The hybrid bonding structure 650 further includes a first interconnect element 654 within the first dielectric layer 652 and exposed on its surface, and a second interconnect element 684 within the second dielectric layer 682 and exposed on its surface. The first interconnect element 654 faces and bonds to the second interconnect element 684. In some embodiments, the first interconnect element 654 and the second interconnect element 684 are copper or contain copper, and are bonded together by copper-to-copper bonding. In some embodiments, the first interconnect element 654 and the second interconnect element 684 are connected to one or more conductive lines and vias within the BEOL layer of the first substrate 610 and the second substrate 620.

[0291] In one embodiment, the first substrate 610 and the second substrate 620 have different functions and / or are manufactured using different wafer node technologies (i.e., different process nodes). Where the second process node differs from the first process node, the second process node may correspond to different costs and / or PPAs (power, performance, and area) of the manufactured components relative to the first process node. In a particular example, where the second process node differs from the first process node, the second process node provides a minimum transistor gate length different from the minimum transistor gate length of the first process node. The first substrate 610 can be a wafer, a die, or other substrate. The second substrate 620 can be a wafer, a die, or other substrate. The first substrate 610 can be of the same type or a different type from the second substrate 620. The second substrate 620 can be a die, and the first substrate 610 can be a wafer; this structure can be referred to as a chip-on-wafer (CoW) structure. The second substrate 620 can be a first wafer, and the first substrate 610 can be a second wafer; this structure can be referred to as a wafer-on-wafer (WoW) structure. Figure 6B In this process, a hybrid bonding method is used to combine the first substrate 610 and the second substrate 620. However, any suitable stacking technique can be used to combine the first and second substrates.

[0292] exist Figure 6B In this embodiment, two substrates are arranged back-to-back. In other embodiments, two or more substrates are arranged face-to-face, back-to-back, or a combination of back-to-face, face-to-face, and back-to-back arrangements. In one embodiment, multiple substrates, each containing 1T1C circuitry, are stacked on the back side BS2 of the second substrate 620. Increasing the number of substrates containing 1T1C circuitry increases the overall memory density (see, for example...). Figure 7 ).

[0293] In one embodiment, at least some of the interconnects formed by the first interconnect element 654 and the second interconnect element 684 form an electrical connection between storage nodes (e.g., terminals of storage capacitors in an ITTIC circuit) on the second substrate 620 and logic circuits (e.g., logic circuit LO) on the first substrate 610. Figure 6B In this context, the second substrate 620 is described as containing a 1T1C circuit. However, memory structures other than the 1T1C circuit can be used.

[0294] although Figure 6B Some components are shown as being included in the first or lower substrate 610, but these components may alternatively be included in the second or upper substrate 620. In other embodiments, components shown as being included in the second or upper substrate 620 are alternatively included in the first or lower substrate 610.

[0295] Figure 6C This is a flowchart of a method 6000 for manufacturing a monolithic 3D digital CIM DRAM bit cell according to an embodiment.

[0296] Method 6000 includes an operation 6012 of forming one or more active devices for a logic circuit LO in an active region on the front side of a first substrate. In some embodiments, the active device includes one or more transistors, which in some instances are MOSFETs, PFETs and / or NFETs, CMOS transistors, finFETs, planar MOS transistors with convex source / drain terminals, BJTs, high-voltage transistors, high-frequency transistors, etc. The active device forms a portion of the logic circuit LO, and in some embodiments, the logic circuit LO is or includes logic gates such as NAND, NOR, AOI / OAI, etc. In some embodiments, operation 6012 further includes forming an adder tree on the first substrate. In some embodiments, the first substrate is a single-crystal silicon substrate, a substrate having a silicon-on-insulator (SOI) structure, or another type of semiconductor substrate.

[0297] Method 6000 also includes operation 6013 of forming a first dielectric layer and a first interconnect element on the back side of a first substrate. In some embodiments, the first dielectric layer comprises a silicon-containing dielectric, such as silicon oxide, silicon oxynitride, or silane oxide. In some embodiments, the first interconnect element is copper or contains copper. In some embodiments, at least some of the interconnect elements on the back side of the first substrate are connected to through-silicon vias (TSVs) formed extending from a BEOL layer on the front side of the first substrate to the back side of the first substrate. In some embodiments, operation 6013 further includes forming connection bumps (e.g., solder balls, etc.) on the front side of the first substrate for connection to adjacent substrates (e.g., wafers, interposers, PCBs, etc.).

[0298] Method 6000 also includes operation 6014 of forming a 1T1C circuit on the front side of the second substrate. Forming the 1T1C circuit includes forming an access transistor T_a, a storage capacitor C_s, and a storage node D in the active region. Operation 6014 includes forming a semiconductor layer, a gate dielectric layer, and a gate for the access transistor T_a. In one embodiment, the gate dielectric layer is formed of a metal oxide material, and the gate is formed of polysilicon, metal, or other conductive material. Operation 6014 includes forming capacitor electrodes facing the capacitor dielectric layer of the storage capacitor C_s. In one embodiment, the capacitor electrodes are formed of a metal or other conductive material. In one embodiment, the capacitor dielectric layer is formed of a material selectively used for the capacitor dielectric material (e.g., a high-k material). In some embodiments, operation 6014 further includes forming a column selector (see [link to documentation]) on the second substrate. Figure 6EThe selection logic (SL) in the middle. In some embodiments, the second substrate is a single-crystal silicon substrate, a substrate having a silicon-on-insulator (SOI) structure, or another type of semiconductor substrate.

[0299] Method 6000 also includes operation 6015 of forming a second dielectric layer and a second interconnect element on the front side of a second substrate above the 1T1C circuit. In some embodiments, the second dielectric layer comprises a silicon-containing dielectric, such as silicon oxide, silicon oxynitride, or silane oxide. In some embodiments, the second interconnect element is copper or contains copper.

[0300] Method 6000 also includes an operation 6016 of flipping the first substrate and an operation 6018 of stacking and bonding the first and second substrates, such that the first and second substrates are combined in a back-to-back configuration, in which the back side of the first substrate faces and is bonded to the front side of the second substrate. A hybrid bonding process is used to bond the first and second substrates, whereby a first dielectric layer on the back side of the first substrate is configured to face and bond to a second dielectric layer on the front side of the second substrate, and a first interconnect element is configured, for example, to face and bond to a second interconnect element via a copper-to-copper bonding.

[0301] In one embodiment, the first and second substrates are formed to have different functions and / or use different wafer node technologies (i.e., different process nodes). Where the second process node differs from the first process node, the second process node may correspond to a different cost and / or PPA (power, performance, and area) for the manufactured components relative to the first process node. In a particular example, where the second process node differs from the first process node, the second process node provides a minimum transistor gate length different from the minimum transistor gate length of the first process node. The first substrate can be a wafer, a die, or other substrate. The second substrate can be a wafer, a die, or other substrate. The first substrate can be the same type as or different from the second substrate. The second substrate can be a die, and the first substrate can be a wafer; this structure can be referred to as a chip-on-wafer (CoW) structure. The second substrate can be a first wafer, and the first substrate can be a second wafer; this structure can be referred to as a wafer-on-wafer (WoW) structure. In method 6000, hybrid bonding is used to combine the first and second substrates. However, any suitable stacking technique can be used to combine the first and second substrates. Furthermore, more than two dies can be combined. For example, multiple second substrates can be stacked on a first substrate to increase memory density. In one embodiment, multiple second substrates are stacked on a first substrate, and each of the second substrates is configured to include one or more tri-state buffers.

[0302] In method 6000, the first and second substrates are arranged back-to-back. In other embodiments, two or more substrates are arranged face-to-face, back-to-back, or a combination of back-to-face, face-to-face, and back-to-back arrangements. In one embodiment, multiple substrates, each containing 1T1C circuitry, are stacked on the back side of the second substrate. Increasing the number of substrates containing 1T1C circuitry increases the overall memory density (see, for example...). Figure 7 ).

[0303] In one embodiment, at least some of the interconnects formed by the first and second interconnect elements form electrical connections between storage nodes (e.g., terminals of storage capacitors in an ITIC circuit) on the second substrate and logic circuits (e.g., logic circuit LO) on the first substrate. In method 6000, the ITIC circuit is formed on the second substrate. However, memory structures other than the ITIC circuit can be used.

[0304] Although method 6000 describes certain elements as being formed on a first or lower substrate, these elements may alternatively be formed on a second or upper substrate. In other embodiments, elements described as being formed on a second or upper substrate are alternatively formed on a first or lower substrate.

[0305] Figure 6D This is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell 600' according to one embodiment.

[0306] In one embodiment, bit unit 600' is included in the combination Figure 1 The memory unit 117 described may be memory unit 117.

[0307] Except for the two 1T1C circuits on the second substrate and the logic circuit LO' on the first substrate having multiple corresponding inputs, bit cell 600' is basically the same as bit cell 600. In bit cell 600', each of the 1T1C circuits and... Figure 6A The 1T1C circuit is the same.

[0308] exist Figure 6D In this embodiment, bit cell 600' includes two ITC circuits on the second substrate. In other embodiments, bit cell 600' includes three or more ITC circuits on the second substrate. Furthermore, in... Figure 6A In this circuit, logic circuit LO' has three inputs (input signal IN and two signals from 1T1C circuit), and in some embodiments, logic circuit LO' has four or more inputs.

[0309] Figure 6E This is a circuit diagram of a heterogeneous 3D digital CIM DRAM bit cell 600 according to an embodiment.

[0310] In one embodiment, bit unit 600” is included in the combination Figure 1 The memory unit 117 described may be memory unit 117.

[0311] Except that the selection logic SL is inserted on the second substrate between the storage node D and the input of the logic circuit LO (on the first substrate), bit cell 600” is essentially the same as bit cell 600. The selection logic SL is used to switch between different groups of weights. The selection logic SL makes selections between rows. In one embodiment, compared to a device without selection logic SL, the selection logic SL reduces the frequency of memory accesses and results in lower power requirements and lower latency.

[0312] The selection logic SL in bit cell 600 contains NOR gates, which are logic or part of multiplexer operation. It should be understood that the selection logic SL can be or contains logic other than NOR gates, and can be selected from two or more bit cells.

[0313] In bit cell 600", the selection logic SL is included on the second substrate; that is, the second substrate includes the bit cell and the selection logic SL. However, in other embodiments, the selection logic SL is included on the first substrate. Figure 6E (Not shown in the image).

[0314] In one embodiment, the selection logic SL is formed as a FEOL device on a second substrate. In one embodiment, the selection logic SL is fabricated on the second substrate using a more mature process node than that used for fabricating logic circuits LO and / or other devices on a first substrate. Implementing the selection logic SL in a more mature node saves costs without reducing the performance of devices in which weight switching occurs infrequently and can tolerate lower speeds.

[0315] In one embodiment, three or more substrates are stacked. For example, the second substrate may be a plurality of second substrates, each second substrate including bit cells and selection logic SL, and each second substrate being coupled to logic circuitry LO on the first substrate. Increasing the number of second substrates in the stack increases the overall memory density.

[0316] Figure 7 This is a circuit diagram of a 3D digital CIM DRAM bit cell 700 according to an embodiment.

[0317] In one embodiment, bit unit 700 is included in the combination Figure 1 The memory unit 117 described may be memory unit 117.

[0318] Except for providing multiple second substrates (e.g., referred to as second, third... nth substrates) and inserting tri-state buffers (TSBs) between the storage node D and the logic input (on each of the multiple second substrates), bit cell 700 is essentially the same as bit cell 600.

[0319] In bit cell 700, the tri-state buffer TSB0...TSB n (On the second to nth substrates) shared signal lines. This configuration reduces the number of interconnects between substrates to save interconnect resources, for example, by reducing interconnect density.

[0320] In one embodiment, devices on multiple second substrates are fabricated using a more mature process node than that used for fabricating devices on a first substrate. Implementing the second substrates at a more mature node can save costs without reducing the performance of devices where weight switching occurs infrequently and where lower speeds are tolerable.

[0321] Figure 8A This is a circuit diagram of a 3D digital CIM DRAM bit cell 800 according to one embodiment.

[0322] In one embodiment, bit unit 800 is included in the combination Figure 1 The memory unit 117 described may be memory unit 117.

[0323] In bit cell 800, the second substrate includes a first capacitor C_s, and the first substrate includes an access transistor T_a. The first capacitor C_s and the access transistor T_a form a 1T1C circuit with a storage node D, which is tapped onto the first substrate to provide an input signal to a logic circuit LO on the first substrate. In contrast to bit cell 600, in bit cell 800, the second substrate does not include the access transistor T_a of the 1T1C circuit.

[0324] In the in-bit unit 800, the storage capacitor C_s of the 1T1C circuit is located on the second substrate, the access transistor T_a and the storage node D are located on the first substrate, and the electrical connection extends from the first terminal of the storage capacitor C_s to the storage node D. In some embodiments, the electrical connection is or includes hybrid bonding or bumpless interconnect, microbump interconnect, etc., as described above.

[0325] In the in-bit cell 800, the second substrate also includes a second capacitor C_d, which is implemented as a decoupling capacitor in the power connection to the logic circuit LO, thereby improving power integrity. Each of the first capacitor C_s and the second capacitor C_d is coupled to the first substrate through a corresponding electrical connection (e.g., a corresponding hybrid bonding or bumpless interconnect, microbump interconnect, etc.).

[0326] In one embodiment, the storage capacitor C_s and decoupling capacitor C_d are fabricated as FEOL devices on a second substrate, and the access transistor T_a and logic circuit LO on the first substrate include one or more transistors fabricated as FEOL devices. In another embodiment, the storage capacitor C_s and decoupling capacitor C_d are fabricated as BEOL devices on a second substrate (e.g., in a metal layer of the second substrate), and the access transistor T_a and logic circuit LO on the first substrate include one or more transistors fabricated as FEOL devices.

[0327] In one embodiment, bit cell 800 is a passive-to-active structure, wherein the second substrate includes passive devices (capacitors) and the first substrate includes active devices (e.g., transistors, etc.). In one embodiment, the second passive substrate contains no active devices at all. In one embodiment, the second passive substrate contains substantially no active devices. In an exemplary embodiment, the first active substrate includes all the active devices (e.g., transistors, etc.) of the bit cell.

[0328] Figure 8B This is a flowchart of a method 8000 for manufacturing a monolithic 3D digital CIM DRAM bit cell using active and passive substrates according to an embodiment.

[0329] Method 8000 includes operation 8002 of forming one or more active devices for a logic circuit LO in an active region on the front side of a first substrate. In some embodiments, the active device includes one or more transistors, which in some instances are MOSFETs, PFETs and / or NFETs, CMOS transistors, finFETs, planar MOS transistors with convex source / drain terminals, BJTs, high-voltage transistors, high-frequency transistors, etc. The active device forms a portion of the logic circuit LO, and in some embodiments, the logic circuit LO is or includes logic gates such as NAND, NOR, AOI / OAI, etc. In some embodiments, operation 8002 further includes forming an adder tree on the first substrate. In some embodiments, the first substrate is a single-crystal silicon substrate, a substrate having a silicon-on-insulator (SOI) structure, or another type of semiconductor substrate.

[0330] Operation 8002 further includes forming an access transistor T_a of a 1T1C circuit on the first substrate. Forming the access transistor T_a includes forming a gate dielectric layer and a gate on the first substrate above a semiconductor layer. In one embodiment, the gate dielectric layer is formed of a metal oxide material, and the gate is formed of polysilicon, metal, or other conductive material.

[0331] Method 8000 also includes operation 8003 of forming a first dielectric layer and a first interconnect element on the back side of a first substrate. In some embodiments, the first dielectric layer comprises a silicon-containing dielectric, such as silicon oxide, silicon oxynitride, or silane oxide. In some embodiments, the first interconnect element is copper or contains copper. In some embodiments, at least some of the interconnect elements on the back side of the first substrate are connected to through-silicon vias (TSVs) extending from a BEOL layer on the front side of the first substrate to the back side of the first substrate. In some embodiments, operation 8003 further includes forming connection bumps (e.g., solder balls, etc.) on the front side of the first substrate, also for connecting to adjacent substrates (e.g., wafers, interposers, PCBs, etc.).

[0332] Method 8000 also includes operation 8004 of forming a storage capacitor C_s with a 1T1C circuit on the front side of the second substrate. Forming the storage capacitor C_s includes forming capacitor electrodes with a capacitor dielectric layer facing the storage capacitor C_s. In one embodiment, the capacitor electrodes are formed of a metal or other conductive material. In one embodiment, the capacitor dielectric layer is formed of a material selectively used for the capacitor dielectric material (e.g., a high-k material). In some embodiments, the second substrate is a single-crystal silicon substrate, a substrate having a silicon-on-insulator (SOI) structure, or another type of semiconductor substrate. In some embodiments, the second substrate is a passive substrate without transistors and / or is formed of a material other than a semiconductor material. In some embodiments, in operation 8004, a decoupling capacitor C_d for a power line to a logic circuit LO on the first substrate is further formed on the second substrate.

[0333] Method 8000 also includes operation 8005 of forming a second dielectric layer and a second interconnect element on the front side of a second substrate. In some embodiments, the second dielectric layer comprises a silicon-containing dielectric, such as silicon oxide, silicon oxynitride, or silane oxide. In some embodiments, the second interconnect element is copper or contains copper.

[0334] Method 8000 also includes an operation 8006 of flipping the first substrate and an operation 8008 of stacking and bonding the first and second substrates, such that the first and second substrates are combined in a back-to-back configuration, wherein the back side of the first substrate faces the front side of the second substrate and is bonded to the front side of the second substrate. A hybrid bonding process is used to bond the first and second substrates, wherein a first dielectric layer on the back side of the first substrate is configured to face the second dielectric layer on the front side of the second substrate and is bonded to the second dielectric layer, and a first interconnect element is configured, for example, to face the second interconnect element and be bonded to the second interconnect element via a copper-to-copper bonding.

[0335] In one embodiment of method 8000, a first substrate is formed having active devices, and a second substrate is formed having only passive devices, such as storage capacitors and decoupling capacitors. In some embodiments, the first and second substrates are formed using different wafer node technologies (i.e., different process nodes). Where the second process node differs from the first process node, the second process node may correspond to a different cost and / or PPA (power, performance, and area) for the manufactured components relative to the first process node. The first substrate may be a wafer, a die, or other substrate. The second substrate may be a wafer, a die, or other substrate. The first substrate may be the same type as or different from the second substrate. The second substrate may be a die, and the first substrate may be a wafer; this structure may be referred to as a chip-on-wafer (CoW) structure. The second substrate may be a first wafer, and the first substrate may be a second wafer; this structure may be referred to as a wafer-on-wafer (WoW) structure. In method 8000, hybrid bonding is used to combine the first and second substrates. However, any suitable 3D stacking technology may be used to combine the first and second substrates. Furthermore, more than two dies can be combined. For example, multiple second substrates can be stacked on a first substrate to increase memory density. In one embodiment, multiple second substrates are stacked on a first substrate, and each of the second substrates is configured to include one or more tri-state buffers.

[0336] In method 8000, the first and second substrates are arranged back-to-back. In other embodiments, two or more substrates are arranged face-to-face, back-to-back, or a combination of back-to-face, face-to-face, and back-to-back arrangements.

[0337] In one embodiment, at least some of the interconnects formed by the first and second interconnect elements form an electrical connection between a storage capacitor C_s on the second substrate and an access transistor T_a on the first substrate, and at least some other interconnects formed by the first and second interconnect elements form an electrical connection between a decoupling capacitor C_d on the second substrate and a logic circuit LO on the first substrate.

[0338] Although method 8000 describes certain elements as being formed on a first or lower substrate, these elements may alternatively be formed on a second or upper substrate. In other embodiments, elements described as being formed on a second or upper substrate are alternatively formed on a first or lower substrate.

[0339] Figure 9 This is a schematic diagram of a memory macro 900 according to one embodiment.

[0340] The memory macro 900 includes one or more MAC arrays 905 (e.g., MAC arrays 905_1, 905_2, 905_3...905_n, where n is a positive integer). Each MAC array 905 includes one or more bit cell arrays 910, each bit cell array 910 having multiple bit cells, which in some embodiments are bit cells 500, 505, 600', 600", 605, 700 and / or 800.

[0341] Each MAC array 905 includes an adder tree 920. The adder tree 920 includes multiple adders configured in multiple stages. The adder tree 920 receives one or more outputs from the bit cell array 910 as one or more inputs (the outputs are represented as D[1], D[2]...D[i], where i is a positive integer). In some embodiments, the output is based on the signal ROW[N:0] provided to the NOR gates in the bit cell array 910 to select weight values. The adder tree 920 accumulates the result of the logic circuit outputs from the bit cell array 910. In some embodiments, the adder tree 920 accumulates the output signal OUT from the logic circuit LO of bit cells 500, 505, 600', 600”, 605, 700 and / or 800. In some embodiments, the adder tree 920 accumulates the result of an operation (e.g., a NOR operation) of the logic circuit LO of bit cells 500, 505, 600', 600”, 605, 700 and / or 800 as a partial summation result. In some embodiments, the adder tree 920 includes NOR gates to perform bit-by-bit multiplication on the outputs (D[1] to D[i]) of the bit cells in the bit cell array 910 and the input signal IN[M:0]. The adder tree 920 is coupled to a bit shifter and a final accumulator 930 (in Figure 9 (This is represented as "shift + summation"). In one embodiment, the shifter and accumulator 930 uses the two's complement of the partial summation result to process the signed input calculation. In some embodiments, the result of the operation (e.g., NOR operation) of the logic circuit LO of the adder tree 920 accumulating bit units 500, 505, 600', 600", 605, 700 and / or 800 is used as the partial summation result, the bit shifter compensates for the valid bit values ​​of the input, and the final MAC result is obtained as the output of the accumulator.

[0342] In one embodiment, the bit cell array 910 is combined Figure 1 The memory array 112 described herein includes an adder tree, a bit shifter, and an accumulator. Figure 1 The output circuit 115 of the memory macro 110 is described.

[0343] Figure 10 This is a flowchart of a method 1000 for operating a circuit according to an embodiment.

[0344] Method 1000 includes a first operation 1010 of writing to memory cells in a memory cell array.

[0345] In some embodiments, the memory cell is or includes bit cells 500, 505, 600', 600", 605, 700 and / or 800, and writing to the memory cell includes an operation 1012 of storing a first value in the storage node. In one example embodiment, the memory cell stores a value corresponding to 0 or 1 as the first value.

[0346] In one example embodiment, operation 1014 involves writing a first value to an access transistor of a storage node that includes a start bit cell to couple the storage node to a bit line. In one example embodiment, starting the access transistor includes applying a signal from a word line to the gate of the access transistor.

[0347] Method 1000 includes a second operation 1020 performing a computing-in-memory (CIM) operation on a first signal and a second signal representing a first value in a bit cell. The CIM operation in the bit cell is one of the CIM operations described above, such as mathematical operations, logical operations, combinations thereof, including NOR operations, AOI operations, OAI operations, MAC operations, and / or other operations on the first signal.

[0348] In one embodiment, the second operation 1020 includes an operation 1022 of providing a first signal representing a first value stored in the storage node of the bit cell to a logic element in the bit cell without activating the access transistor of the bit cell. In one embodiment, the logic element in the bit cell has an input directly coupled to the storage node of the bit cell, i.e., not controlled by the access transistor or another transistor. In one embodiment, the phrase "without activating the access transistor" means not changing the state of the signal applied to the gate of the access transistor. In one embodiment, the phrase "without activating the access transistor" means maintaining the access transistor in a non-conductive state, such that the storage node of the bit cell is electrically isolated from the bit line. In one embodiment, in operation 1022, the storage node is located on a second substrate of a substrate stack, and the logic element is located on a first substrate of a substrate stack.

[0349] In one example embodiment, the second operation also includes operation 1024 of providing a second signal to a logic element. The first and second signals are provided to the first and second inputs of the logic element, respectively.

[0350] In one example embodiment, the second operation 1020 includes an operation 1026 in which a logic element in the bit cell outputs an output signal, the output signal representing the output or result of a CIM operation performed on the first and second signals in the bit cell.

[0351] In some embodiments, a memory includes logic circuitry having a first input, a second input, and an output, and memory circuitry comprising: a transistor coupled to the logic circuitry, the transistor having a semiconductor layer including a source and a drain; and a storage node having a first connector, a second connector, and a third connector. The source or drain of the transistor is coupled to the first connector of the storage node. The logic circuitry includes one or more transistors in an active region of a substrate, the one or more transistors being front-end of line (FEOL) devices, and the semiconductor layer and storage node being located in a back-end of line (BEOL) layer above the substrate.

[0352] In some embodiments, a first input of the logic circuit is coupled to a second connection of the storage node via a conductor in the back-end process layer. In some embodiments, the memory circuit further includes a capacitor in the back-end process layer, a third connection of the storage node is coupled to a first terminal of the capacitor, and a second terminal of the capacitor is coupled to a reference voltage. In some embodiments, the back-end process layer includes metal layers, and at least one of the metal layers is located at a level between the semiconductor layer and the substrate. In some embodiments, the memory circuit includes the transistor, the storage node, and a capacitor, the back-end process layer includes metal layers, and at least one of the metal layers is located at a level between the capacitor and the substrate. In some embodiments, the memory circuit is a single-transistor, single-capacitor circuit. In some embodiments, the memory circuit does not contain a transistor in the active region. In some embodiments, the transistor is used to operate at a voltage higher than that of the logic circuit. In some embodiments, the memory includes memory circuits, each of which has a transistor, a capacitor, and a storage node in the back-end process layer, and the memory includes logic circuits corresponding to the memory circuits, each of which has a transistor in the active region. In some embodiments, the substrate includes an adder tree, and the output of the logic circuit is coupled to the input of the adder tree. In some embodiments, the logic circuit is configured to perform logical operations on a signal received at a second input and a value stored in a memory circuit and received at a first input. In some embodiments, the memory circuit is a first memory circuit, and the memory further includes a second memory circuit having transistors, capacitors, and storage nodes in a back-end process layer. The logic circuit further includes a third input, the first input of which is coupled to the storage node of the first memory circuit, and the third input of which is coupled to the storage node of the second memory circuit.

[0353] In some embodiments, a memory having a stacked substrate includes logic circuitry having a first input, a second input, and an output, and memory circuitry including: a transistor having a source and a drain; and a storage node having a first connector, a second connector, and a third connector. The source or drain of the transistor is coupled to the first connector of the storage node. The logic circuitry is located on a first substrate. The transistor and the storage node are located on a second substrate. The first and second substrates are coupled together in a stack.

[0354] In some embodiments, a memory having a stacked substrate includes: logic circuitry having a first input, a second input, and an output; and memory circuitry including a storage capacitor and a transistor. The transistor and logic circuitry are located on a first substrate, and the storage capacitor is located on a second substrate. The storage capacitor has first and second terminals. The transistor has a source and a drain, and the source or the drain is coupled to the first terminal of the storage capacitor via a conductor, the conductor including interconnects connecting the first and second substrates. The first input of the logic circuitry is coupled to the first terminal of the storage capacitor.

[0355] In some embodiments, a first input of the logic circuit is coupled to a first terminal of a storage capacitor via a conductor. In some embodiments, the memory includes a memory circuit, wherein transistors of the memory circuit are located on a first substrate and storage capacitors of the memory circuit are located on a second substrate, and each storage capacitor of the memory circuit is coupled to a corresponding transistor via a corresponding interconnect connecting the first substrate and the second substrate. In some embodiments, each storage capacitor of the memory circuit has a first terminal coupled to a corresponding logic circuit on the first substrate, and the memory further includes an adder tree, the output of the logic circuit being coupled to the input of the adder tree. In some embodiments, the interconnect coupling the source or drain of the transistor to the first terminal of the storage capacitor is a first interconnect, and the memory further includes a decoupling capacitor on the second substrate and a second interconnect connecting the first substrate and the second substrate, the terminal of the decoupling capacitor being coupled to a power supply terminal of the logic circuit via the second interconnect. In some embodiments, a second terminal of the storage capacitor is coupled to a reference voltage.

[0356] In some embodiments, a method of operating a memory having a first substrate and a second substrate includes: storing a first value in a memory circuit of the memory, wherein the memory circuit includes a storage node and a transistor on the second substrate, and the storage node has a first connector, a second connector and a third connector, the transistor has a source and a drain, and the source or the drain is coupled to the first connector of the storage node; providing a first signal representing the first value from the second connector of the storage node to a first input of a logic circuit on the first substrate via a conductor, the conductor including interconnects connecting the first and second substrates together in a stack; and performing a logic operation using the logic circuit, the output of the logic circuit corresponding to the result of a logic operation on a second signal received at a second input of the logic circuit and a first signal received at a first input of the logic circuit.

[0357] In some embodiments, a method of manufacturing memory includes: forming a logic circuit having a first input, a second input, and an output, the logic circuit including forming a first transistor in an active region of a substrate, the first transistor being a front-end of line (FEOL) device; and forming a plurality of back-end of line (BEOL) layers above the substrate, the formation of the plurality of back-end of line (BEOL) layers above the substrate including: forming a semiconductor layer of a second transistor in the BEOL layer, the semiconductor layer including a source and a drain; forming an electrical connection between the first input of the logic circuit and one of the source or drain; forming a storage node in the BEOL layer; and forming an electrical connection between the storage node and one of the source or drain.

[0358] In some embodiments, the step of forming a back-end process (BEOL) layer over a substrate further includes the steps of forming a capacitor in the back-end process layer and forming an electrical connection between a terminal of the capacitor and one of the source or drain.

[0359] In some embodiments, a memory includes: a logic circuit having a first input, a second input, and an output; a substrate having an active region, the active region including: one or more first transistors, the one or more first transistors being front-end process devices; a second transistor having a semiconductor layer including a source and a drain; a storage node electrically connected to one of the source and the drain; and a capacitor, the terminals of the capacitor being electrically connected to the other of the source and the drain, wherein the semiconductor layer and the storage node are located in a back-end process layer above the substrate.

[0360] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory, comprising: Comprising: a logic circuit having a first input, a second input, and an output; and a memory circuit including: a transistor coupled to the logic circuit, the transistor having a semiconductor layer including a source and a drain; and a storage node having a first connection, a second connection, and a third connection, wherein: the source or the drain of the transistor is coupled to the first connection of the storage node, the logic circuit includes one or more transistors in an active region of a substrate, the one or more transistors are front-end-of-line devices, and the semiconductor layer and the storage node are in back-end-of-line layers above the substrate.

2. The memory of claim 1, wherein, wherein: the memory circuit further includes a capacitor in the back-end-of-line layers, the third connection of the storage node is coupled to a first terminal of the capacitor, and a second terminal of the capacitor is coupled to a reference voltage.

3. The memory of claim 1, wherein, wherein: the back-end-of-line layers include metal layers, and at least one metal layer of the metal layers is at a level between the semiconductor layer and the substrate.

4. The memory of claim 1, wherein, wherein: the memory circuit includes the transistor, the storage node, and a capacitor, the back-end-of-line layers include metal layers, and at least one metal layer of the metal layers is at a level between the capacitor and the substrate.

5. The memory of claim 1, wherein, wherein: the memory includes a plurality of memory circuits, each of the plurality of memory circuits has a transistor, a capacitor, and a storage node in the back-end-of-line layers, and the memory includes a plurality of logic circuits corresponding to the plurality of memory circuits, each of the plurality of logic circuits has one or more transistors in the active region.

6. The memory of claim 1, wherein, wherein: the memory circuit is a first memory circuit, the memory further includes a second memory circuit, the second memory circuit has a transistor, a capacitor, and a storage node in the back-end-of-line layers, the logic circuit further includes a third input, the first input of the logic circuit is coupled to the storage node of the first memory circuit, and the third input of the logic circuit is coupled to the storage node of the second memory circuit.

7. A memory, comprising: Comprising: a logic circuit having a first input, a second input, and an output; and a memory circuit including a storage capacitor and a transistor, wherein: the transistor and the logic circuit are on a first substrate, and the storage capacitor is on a second substrate, the storage capacitor has a first terminal and a second terminal, the transistor has a source and a drain, and the source or the drain is coupled to the first terminal of the storage capacitor through a conductor, the conductor includes an interconnect connecting the first substrate and the second substrate, and the first input of the logic circuit is coupled to the first terminal of the storage capacitor. wherein:

8. The memory of claim 7, wherein, the memory includes a plurality of memory circuits, wherein transistors of the plurality of memory circuits are on the first substrate and storage capacitors of the plurality of memory circuits are on the second substrate, and each storage capacitor of the plurality of memory circuits is coupled to a corresponding transistor through a corresponding interconnect connecting the first substrate and the second substrate. ​ 9. The memory of claim 8, wherein, wherein each storage capacitor of the plurality of memory circuits has a first terminal coupled to a corresponding logic circuit on the first substrate, the memory further comprises an adder tree, outputs of the plurality of logic circuits are coupled to inputs of the adder tree.

10. A memory, comprising: comprising: a logic circuit having a first input, a second input, and an output; a substrate having an active region, the active region including: one or more first transistors, the one or more first transistors being a front-end-of-line device; a second transistor having a semiconductor layer including a source and a drain; a storage node electrically connected to the one of the source or the drain; and a capacitor having a terminal electrically connected to the other of the source or the drain, wherein the semiconductor layer and the storage node are in back-end-of-line layers above the substrate.

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