LED chip, high-voltage LED chip and light-emitting device

Abstract

The utility model provides an LED chip, a high-voltage LED chip and a light-emitting device. According to the technical scheme of the utility model, an epitaxial laminated layer comprises a first-type semiconductor layer, an active region and a second-type semiconductor layer which are sequentially stacked along a first direction. A local area of the epitaxial laminated layer is etched to the first type semiconductor layer to form a groove and a light-emitting table top; the transparent conductive layer is laminated on the light-emitting tabletop and is provided with a second hole for exposing part of the second type semiconductor layer; the first insulating layer is formed on the surface of one side, deviating from the epitaxial laminated layer, of the transparent conductive layer; the first electrode is stacked on a part of the surface of the groove and is arranged far away from the light-emitting tabletop; the second electrode extends to a part of the surface of the first insulating layer by being arranged in the second hole; and the second insulating layer is arranged on the surface of the epitaxial laminated layer, and at least parts of the surfaces of the first electrode and the second electrode are exposed.

Description

Technical Field

[0001] This utility model relates to the field of LED chips, and in particular to an LED chip, a high-voltage LED chip, and a light-emitting device. Background Technology

[0002] Light-emitting diodes (LEDs) have advantages such as high efficiency, long lifespan, small size, and low power consumption, and are widely used in indoor and outdoor white light lighting, screen displays, backlights, and other fields. The function of an LED chip is to convert electrical energy into light energy. Specifically, it includes an epitaxial wafer and N-type and P-type electrodes respectively disposed on the epitaxial wafer. The epitaxial wafer includes a P-type semiconductor layer, an N-type semiconductor layer, and an active layer located between the N-type and P-type semiconductor layers. When current flows through the LED chip, holes in the P-type semiconductor and electrons in the N-type semiconductor move towards the active layer and recombine there, causing the LED chip to emit light.

[0003] As the LED application market (especially display applications) continues to expand, LED packaging manufacturers are placing higher demands on the light extraction efficiency and reliability of LED chips to ensure the performance of LED products. Currently, the quantum efficiency of most LED chips is close to 99%, but their light extraction efficiency is generally low. The main factors include: 1. Due to the severe total internal reflection phenomenon inside the LED chip, only a small portion of the light source generated by the light-emitting layer can be extracted; 2. The current congestion effect leads to low luminous efficiency of the LED chip.

[0004] The main factors affecting the reliability of LED chips include: 1. The bottom contact area of ​​the P-pad region contains multiple functional dielectric layers, such as a current blocking layer (also known as a CB layer) and a transparent conductive layer (also known as an ITO layer). This structure increases the risk of soldering failure or cracking of the contact functional dielectric layers, thus affecting the reliability of the LED chip. 2. In actual operation, moisture penetration can cause micro-short circuits in LED chips under reverse pressure, ultimately leading to LED burnout and failure, affecting the reliability of LED chips in practical applications and limiting their application. Therefore, improving the light extraction efficiency and reliability of LED chips without affecting photoelectric performance has become an urgent technical challenge.

[0005] In view of this, the inventor has specifically designed an LED chip, a high-voltage LED chip, and a light-emitting device, which leads to this invention. Utility Model Content

[0006] The purpose of this invention is to provide an LED chip, a high-voltage LED chip, and a light-emitting device to solve the technical problems of low luminous efficiency and poor reliability of LED chips in the prior art.

[0007] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0008] An LED chip includes a substrate and a plurality of LED light-emitting units disposed on the surface of the substrate and isolated from each other by trenches, characterized in that the LED light-emitting units include:

[0009] An epitaxial stack is disposed on the surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along a first direction; and a local area of ​​the epitaxial stack is etched to the first type semiconductor layer to form a groove and a light-emitting mesa; wherein, the first direction is perpendicular to the substrate and points from the substrate to the epitaxial stack;

[0010] A transparent conductive layer, which is stacked on the light-emitting platform and has a second hole that exposes a portion of the second type semiconductor layer;

[0011] A first insulating layer is formed on the surface of the transparent conductive layer opposite to the epitaxial stack;

[0012] The first electrode is stacked on a portion of the surface of the groove and disposed away from the light-emitting platform;

[0013] The second electrode extends to a portion of the surface of the first insulating layer by being disposed in the second hole;

[0014] A second insulating layer is disposed on the surface of the epitaxial stack and exposes at least a portion of the surfaces of the first and second electrodes.

[0015] Preferably, the exposed portion of the first insulating layer forms a step in the transparent conductive layer, and the second electrode extends to the surface of the first insulating layer through the step.

[0016] Preferably, the projection of the second electrode onto the transparent conductive layer and the projection of the second electrode onto the first insulating layer have an area of ​​S. a If the regions partially overlap and the projected area of ​​the second electrode on the transparent conductive layer is S1, then 0 < S a ≤S1 / 2.

[0017] Preferably, the step is arranged around the edge of the second hole.

[0018] Preferably, a current blocking layer is provided on the bottom surface of the second hole.

[0019] Preferably, the current blocking layer and the transparent conductive layer form a spacer groove, and the second electrode is embedded in the spacer groove to form a contact with the second type of semiconductor layer.

[0020] Preferably, the projected area of ​​the current blocking layer on the transparent conductive layer is S2, and the bottom area of ​​the second hole is S3, then 0 < S2 ≤ S3 / 2.

[0021] Preferably, the first insulating layer and the current blocking layer are formed simultaneously by photolithography of the transparent dielectric layer.

[0022] Preferably, the transparent dielectric layer comprises one or more of silicon oxide, silicon nitride, aluminum oxide, and magnesium fluoride.

[0023] Preferably, a third insulating layer is further provided on the surface of the groove, and the third insulating layer has a first hole that exposes a portion of the first type semiconductor layer; then the first electrode is stacked on the surface of the third insulating layer by embedding into the first hole.

[0024] Preferably, the first insulating layer and the third insulating layer are formed simultaneously by photolithography of the transparent dielectric layer.

[0025] Preferably, the LED chip further includes a refractive index matching layer, which is disposed on the side of the second insulating layer facing away from the epitaxial stack and forms a gradient refractive index structure with the second insulating layer, further improving the light extraction efficiency; preferably, the refractive index of the refractive index matching layer is not less than the refractive index of the second insulating layer. Further, if the first insulating layer or the second insulating layer comprises a layered structure composed of one or more of SiO2 and MgF2, then the refractive index matching layer may comprise a layered structure composed of one or more of TiO2, Si3N4, and Al2O3. Preferably, the second insulating layer is a SiO2 layer and the refractive index matching layer is an Al2O3 layer. The excellent passivation properties of Al2O3 can effectively cover dangling bonds and defect states on the SiO2 surface, reducing nonradiative recombination of charge carriers on the surface. The reduction in nonradiative recombination directly improves the internal quantum efficiency (IQE), meaning more electrical energy is converted into light energy rather than heat.

[0026] Preferably, a reflective layer is further provided on the surface of the substrate facing away from the epitaxial stack. Further, the reflective layer comprises a distributed Bragg reflective layer composed of alternating layers of high-refractive-index material and low-refractive-index material; alternatively, the reflective layer may also be a metallic reflective layer.

[0027] Preferably, the first electrode includes a first electrode pad disposed at a first end of the LED chip, and the second hole is formed at a second end of the LED chip; the second electrode includes a second electrode pad and at least one electrode extension strip connected to the second electrode pad, wherein the second electrode pad extends to the surface of the first insulating layer by being disposed in the second hole, and the electrode extension strip extends from the second electrode pad toward the second end of the LED chip.

[0028] Furthermore, the first electrode may also include an electrode extension strip connected to the first electrode pad and extending toward the first end.

[0029] Preferably, at least a portion of the electrode extension strip of the second electrode forms contact with the transparent conductive layer.

[0030] Preferably, the electrode extension strip has forked fingers, which are then inserted into the first insulating layer through perforations to form contact with the transparent conductive layer. Alternatively, if the transparent conductive layer has perforations and the electrode extension strip has forked fingers, the forked fingers are formed in and held in the perforations of the transparent conductive layer.

[0031] Preferably, the second insulating layer covers the light-emitting platform and the groove in such a way that it is held on the exposed surface of the first type of semiconductor layer.

[0032] Preferably, the transparent conductive layer covers at least 80% of the area of ​​the light-emitting platform, excluding the second hole.

[0033] Preferably, the second electrode has a metal reflective layer.

[0034] Preferably, the bottom layer of the second electrode is the metal reflective layer.

[0035] Preferably, the metal reflective layer comprises one or more of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, and Au.

[0036] This utility model also provides a high-voltage LED chip, which electrically interconnects adjacent LED light-emitting units as described above through bridging electrodes; wherein, an insulating layer is provided in the trench, and the bridging electrodes connect two adjacent LED units by being stacked on the insulating layer.

[0037] This utility model also provides a light-emitting device, which includes a light-emitting diode, and the light-emitting diode adopts an LED chip as described in any of the above claims.

[0038] This utility model also provides another light-emitting device, characterized in that the light-emitting device includes a light-emitting diode, and the light-emitting diode adopts the high-voltage LED chip described above.

[0039] As can be seen from the above technical solution, the LED chip provided by this utility model is configured as follows: the epitaxial stack includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along a first direction; a local area of ​​the epitaxial stack is etched to the first type semiconductor layer to form a groove and a light-emitting mesa; a transparent conductive layer is stacked on the light-emitting mesa and has a second hole exposing a portion of the second type semiconductor layer; a first insulating layer is formed on the surface of the transparent conductive layer away from the epitaxial stack; a first electrode is stacked on a portion of the surface of the groove and disposed away from the light-emitting mesa; a second electrode extends to a portion of the surface of the first insulating layer by being disposed in the second hole; the second insulating layer is disposed on the surface of the epitaxial stack and exposes at least a portion of the surfaces of the first electrode and the second electrode. Based on the above configuration, the first insulating layer, the transparent conductive layer, the second insulating layer, and the second electrode form a composite region. This creates an ODR structure through the structural relationship between the transparent conductive layer, the first insulating layer, the second electrode, and the second insulating layer. Light can undergo total internal reflection in the composite region, allowing light from the composite region corresponding to the second electrode to be reflected and extracted from the upper surface of the LED chip, thereby effectively improving light extraction efficiency. Simultaneously, since the second insulating layer is disposed on the surface of the epitaxial stack and part of the surface of the first / second electrode, a first insulating layer and a second insulating layer with different extension directions can be formed at the edge of the second electrode to construct an angled connection structure. This effectively mitigates the diffusion of tensile stress generated by the LED chip under special environments (such as high temperature and high pressure), thereby reducing the risk of soldering failure or cracking of the functional dielectric layer (such as the transparent conductive layer and the insulating layer), which could affect the reliability of the LED chip. Furthermore, the dual protection of the first and second insulating layers enhances the LED chip's water and vapor resistance.

[0040] Secondly, by setting a step in the transparent conductive layer on the exposed portion of the first insulating layer, and extending the second electrode to the surface of the first insulating layer through the step, the electrode contact area can be increased through the step, thereby dispersing stress and reducing the risk of local failure.

[0041] Then, by setting the projection of the second electrode on the transparent conductive layer to have an area of ​​S with the projection of the second electrode on the first insulating layer. a If the regions partially overlap and the projected area of ​​the second electrode on the transparent conductive layer is S1, then 0 < S a≤S1 / 2. Thus, while ensuring the contact area between the second electrode and the transparent conductive layer to reduce contact resistance, the size of the composite region area is also ensured to improve the ODR reflection effect.

[0042] Next, by setting a current-blocking layer on the bottom surface of the second hole, the current-blocking layer forming a spacer groove with the transparent conductive layer, and the second electrode embedded in the spacer groove to form contact with the second type of semiconductor layer, the current accumulation phenomenon is improved and the lateral expansion of the current is promoted. At the same time, the structural relationship between the second electrode, the first insulating layer (dielectric layer), the spacer groove, the current-blocking layer (dielectric layer), and the transparent conductive layer (conductive layer) again forms an ODR structure, which is beneficial to the total reflection layer area below the electrode, further improving the reflection efficiency. Furthermore, the projected area of ​​the current-blocking layer on the transparent conductive layer is S2, and the bottom area of ​​the second hole is S3, then 0 < S2 ≤ S3 / 2. Thus, while ensuring the current blocking and total reflection effects, the contact area between the second electrode and the second type of semiconductor layer is ensured to improve the reliability of the electrode bonding wire.

[0043] Furthermore, by configuring the following: the first electrode includes a first electrode pad disposed at a first end of the LED chip, and the second hole is formed at a second end of the LED chip; the second electrode includes a second electrode pad and at least one electrode extension strip connected to the second electrode pad, wherein the second electrode pad extends to the surface of the first insulating layer by being disposed in the second hole, and the electrode extension strip extends from the second electrode pad toward the second end of the LED chip. This allows for better current guidance and expansion through the electrode extension strip, avoiding current congestion.

[0044] This utility model also provides a high-voltage LED chip, which electrically interconnects adjacent LED light-emitting units as described above through bridging electrodes; wherein, an insulating layer is provided in the trench, and the bridging electrodes connect two adjacent LED units by being stacked on the insulating layer; it has the beneficial effects of the aforementioned LED chip.

[0045] This utility model also provides a light-emitting device, which includes a light-emitting diode, wherein the light-emitting diode adopts an LED chip as described in any of the above claims; and it has the beneficial effects of the LED chip described above.

[0046] This utility model also provides another light-emitting device, which includes a light-emitting diode, wherein the light-emitting diode adopts the high-voltage LED chip as described above; it has the beneficial effects of the LED chip described above. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0048] Figure 1 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 1 of this utility model;

[0049] Figures 2 to 10 This is a schematic diagram of the structure corresponding to the steps of the LED chip manufacturing method provided in Embodiment 2 of this utility model;

[0050] Figure 11 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 3 of this utility model;

[0051] Figure 12 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 4 of this utility model;

[0052] Figure 13 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 5 of this utility model;

[0053] Figure 14 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 6 of this utility model;

[0054] Figure 15 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 7 of this utility model;

[0055] Figure 16 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 8 of this utility model;

[0056] Explanation of symbols in the diagram:

[0057] 1. Substrate;

[0058] 2. Type I semiconductor layer;

[0059] 3. Active region;

[0060] 4. Type II semiconductor layer;

[0061] 5. Transparent conductive layer; 5.1. Second hole;

[0062] 6. First insulating layer;

[0063] 7. Second electrode;

[0064] 8. First electrode;

[0065] 9. Second insulating layer;

[0066] 10. Groove;

[0067] 11. Illuminated tabletop;

[0068] 12. Third insulation layer; 12.1. First hole;

[0069] 13. Current blocking layer;

[0070] 14. Electrode extension strip;

[0071] 15. Refractive index matching layer;

[0072] 16. Reflective layer;

[0073] 17. Groove. Detailed Implementation

[0074] To make the content of this utility model clearer, the following description, in conjunction with the accompanying drawings, further illustrates the present utility model. This utility model is not limited to this specific embodiment. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without inventive effort are within the scope of protection of this utility model.

[0075] An LED chip includes a substrate and a plurality of LED light-emitting units disposed on the surface of the substrate and isolated from each other by trenches, wherein the LED light-emitting units include:

[0076] An epitaxial stack is disposed on the surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along a first direction; and a local area of ​​the epitaxial stack is etched to the first type semiconductor layer to form a groove and a light-emitting mesa; wherein, the first direction is perpendicular to the substrate and points from the substrate to the epitaxial stack;

[0077] A transparent conductive layer, which is stacked on the light-emitting platform and has a second hole that exposes a portion of the second type semiconductor layer;

[0078] A first insulating layer is formed on the surface of the transparent conductive layer opposite to the epitaxial stack;

[0079] The first electrode is stacked on a portion of the surface of the groove and disposed away from the light-emitting platform;

[0080] The second electrode extends to a portion of the surface of the first insulating layer by being disposed in the second hole;

[0081] A second insulating layer is disposed on the surface of the epitaxial stack, and at least exposes a portion of the surfaces of the first and second electrodes. Further, the second insulating layer covers the light-emitting platform and the groove, and exposes a portion of the surfaces of the first and second electrodes.

[0082] It should be noted that the type of substrate is not limited in the LED chip of this embodiment. For example, the substrate can be, but is not limited to, a sapphire substrate, a silicon substrate, etc. Furthermore, the types of the first type semiconductor layer, the active region, and the second type semiconductor layer in the epitaxial stack are also not limited in the LED chip of this embodiment. In the embodiments of this utility model, the first type semiconductor layer can be an N-type semiconductor layer, and correspondingly, the second type semiconductor layer can be a P-type semiconductor layer; for example, the first type semiconductor layer can be, but is not limited to, an N-type gallium nitride layer, and correspondingly, the second type semiconductor layer can be, but is not limited to, a P-type gallium nitride layer.

[0083] It should be noted that, in order to highlight the technical features of this application, only one epitaxial stacked unit is shown in the embodiment figure. In actual product applications, it may contain tens of thousands of epitaxial stacked units, depending on the application of the LED chip product. This application does not limit this.

[0084] Based on the above, in one embodiment of this application, the exposed portion of the first insulating layer forms a step in the transparent conductive layer, and the second electrode extends to the surface of the first insulating layer through the step.

[0085] Based on the above, in one embodiment of this application, the projection of the second electrode on the transparent conductive layer and the projection of the second electrode on the first insulating layer have an area of ​​S. a If the regions partially overlap and the projected area of ​​the second electrode on the transparent conductive layer is S1, then 0 < S a ≤S1 / 2.

[0086] Based on the above, in one embodiment of this application, the step is arranged around the edge of the second hole.

[0087] Based on the above, in one embodiment of this application, a current blocking layer is provided on the bottom surface of the second hole.

[0088] Based on the above, in one embodiment of this application, the current blocking layer and the transparent conductive layer form a spacer groove, and the second electrode is embedded in the spacer groove to form contact with the second type semiconductor layer.

[0089] Based on the above, in one embodiment of this application, the projected area of ​​the current blocking layer on the transparent conductive layer is S2, and the bottom area of ​​the second hole is S3, then 0 < S2 ≤ S3 / 2.

[0090] Based on the above, in one embodiment of this application, the first insulating layer and the current blocking layer are formed simultaneously by photolithography of the transparent dielectric layer.

[0091] Based on the above, in one embodiment of this application, the transparent dielectric layer includes one or more of silicon oxide, silicon nitride, aluminum oxide, and magnesium fluoride.

[0092] Based on the above, in one embodiment of this application, a third insulating layer is further provided on the surface of the groove, and the third insulating layer has a first hole that exposes a portion of the first type semiconductor layer; then the first electrode is stacked on the surface of the third insulating layer by embedding into the first hole.

[0093] Based on the above, in one embodiment of this application, the first insulating layer and the third insulating layer are formed simultaneously by photolithography of the transparent dielectric layer.

[0094] Based on the above, in one embodiment of this application, the LED chip further includes a refractive index matching layer, which is disposed on the side surface of the second insulating layer away from the epitaxial stack and forms a gradient refractive index structure with the second insulating layer to further improve the light extraction efficiency; preferably, the refractive index of the refractive index matching layer is not less than the refractive index of the second insulating layer.

[0095] Further, if the first insulating layer or the second insulating layer comprises a layered structure composed of one or more of SiO2 and MgF2, then the refractive index matching layer may comprise a layered structure composed of one or more of TiO2, Si3N4, and Al2O3. Preferably, the second insulating layer is a SiO2 layer and the refractive index matching layer is an Al2O3 layer. The excellent passivation properties of Al2O3 effectively cover dangling bonds and defect states on the SiO2 surface, reducing nonradiative recombination of charge carriers on the surface. The reduction in nonradiative recombination directly improves the internal quantum efficiency (IQE), meaning more electrical energy is converted into light energy rather than heat.

[0096] Based on the above, in one embodiment of this application, a reflective layer is further provided on the surface of the substrate facing away from the epitaxial stack. Further, the reflective layer includes a distributed Bragg reflective layer composed of alternating layers of high-refractive-index material and low-refractive-index material; alternatively, the reflective layer may also be a metallic reflective layer.

[0097] Based on the above, in one embodiment of this application, the first electrode includes a first electrode pad disposed at a first end of the LED chip, and the second hole is formed at a second end of the LED chip; the second electrode includes a second electrode pad and at least one electrode extension strip connected to the second electrode pad, wherein the second electrode pad extends to the surface of the first insulating layer by being disposed in the second hole, and the electrode extension strip extends from the second electrode pad toward the second end of the LED chip.

[0098] Furthermore, the first electrode may also include an electrode extension strip connected to the first electrode pad and extending toward the first end.

[0099] Based on the above, in one embodiment of this application, at least a portion of the electrode extension strip forms contact with the transparent conductive layer.

[0100] Based on the above, in one embodiment of this application, the electrode extension strip has forked fingers, and the forked fingers form contact with the transparent conductive layer by being embedded in the first insulating layer through perforations. Alternatively, the transparent conductive layer has perforations, and the electrode extension strip has forked fingers, then the forked fingers are formed in and held in the perforations of the transparent conductive layer.

[0101] Based on the above, in one embodiment of this application, the second insulating layer covers the light-emitting platform and the groove in such a way that it is held on the exposed surface of the first type of semiconductor layer.

[0102] Based on the above, in one embodiment of this application, the transparent conductive layer covers at least 80% of the area of ​​the light-emitting platform, excluding the second hole.

[0103] Based on the above, in one embodiment of this application, the second electrode has a metal reflective layer.

[0104] Based on the above, in one embodiment of this application, the bottom layer of the second electrode is the metal reflective layer.

[0105] Based on the above, in one embodiment of this application, the metal reflective layer includes one or more of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, and Au.

[0106] Based on the above, in one embodiment of this application, the transparent conductive layer includes a metal thin film or a metal oxide layer.

[0107] Based on the above, in one embodiment of this application, the metal thin film includes one or more of gold, silver, platinum, copper, aluminum, chromium, and palladium.

[0108] Based on the above, in one embodiment of this application, the metal oxide layer includes one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride.

[0109] As can be seen from the above technical solution, the LED chip provided by this utility model is configured as follows: the epitaxial stack includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along a first direction; a local area of ​​the epitaxial stack is etched to the first type semiconductor layer to form a groove and a light-emitting mesa; a transparent conductive layer is stacked on the light-emitting mesa and has a second hole exposing a portion of the second type semiconductor layer; a first insulating layer is formed on the surface of the transparent conductive layer away from the epitaxial stack; a first electrode is stacked on a portion of the surface of the groove and disposed away from the light-emitting mesa; a second electrode extends to a portion of the surface of the first insulating layer by being disposed in the second hole; the second insulating layer is disposed on the surface of the epitaxial stack and exposes at least a portion of the surfaces of the first electrode and the second electrode. Based on the above configuration, the first insulating layer, the transparent conductive layer, the second insulating layer, and the second electrode form a composite region. This creates an ODR structure through the structural relationship between the transparent conductive layer, the first insulating layer, the second electrode, and the second insulating layer. Light can undergo total internal reflection in this composite region, allowing light from the composite region corresponding to the second electrode to be reflected and extracted from the upper surface of the LED chip, thereby effectively improving light extraction efficiency. Simultaneously, based on the above configuration, the second insulating layer is disposed on the surface of the epitaxial stack and part of the surface of the first / second electrode. At the edge of the second electrode, the first and second insulating layers with different extension directions can be formed to construct an angled connection structure. This effectively mitigates the diffusion of tensile stress generated by the LED chip under special environments (such as high temperature and high pressure), thereby reducing the risk of soldering failure or cracking of the functional dielectric layers (such as the transparent conductive layer and insulating layer), which could affect the reliability of the LED chip. Furthermore, the dual protection of the first and second insulating layers enhances the LED chip's water vapor resistance.

[0110] Secondly, by setting a step in the transparent conductive layer on the exposed portion of the first insulating layer, and extending the second electrode to the surface of the first insulating layer through the step, the electrode contact area can be increased through the step, thereby dispersing stress and reducing the risk of local failure.

[0111] Then, by setting the projection of the second electrode on the transparent conductive layer to have an area of ​​S with the projection of the second electrode on the first insulating layer. a If the regions partially overlap and the projected area of ​​the second electrode on the transparent conductive layer is S1, then 0 < S a≤S1 / 2. Thus, while ensuring the contact area between the second electrode and the transparent conductive layer to reduce contact resistance, the size of the composite region area is also ensured to improve the ODR reflection effect.

[0112] Next, by setting a current-blocking layer on the bottom surface of the second hole, the current-blocking layer forming a spacer groove with the transparent conductive layer, and the second electrode embedded in the spacer groove to form contact with the second type of semiconductor layer, the current accumulation phenomenon is improved and the lateral expansion of the current is promoted. At the same time, the structural relationship between the second electrode, the first insulating layer (dielectric layer), the spacer groove, the current-blocking layer (dielectric layer), and the transparent conductive layer (conductive layer) again forms an ODR structure, which is beneficial to the total reflection layer area below the electrode, further improving the reflection efficiency. Furthermore, the projected area of ​​the current-blocking layer on the transparent conductive layer is S2, and the bottom area of ​​the second hole is S3, then 0 < S2 ≤ S3 / 2. Thus, while ensuring the current blocking and total reflection effects, the contact area between the second electrode and the second type of semiconductor layer is ensured to improve the reliability of the electrode bonding wire.

[0113] Furthermore, by configuring the following: the first electrode includes a first electrode pad disposed at a first end of the LED chip, and the second hole is formed at a second end of the LED chip; the second electrode includes a second electrode pad and at least one electrode extension strip connected to the second electrode pad, wherein the second electrode pad extends to the surface of the first insulating layer by being disposed in the second hole, and the electrode extension strip extends from the second electrode pad toward the second end of the LED chip. This allows for better current guidance and expansion through the electrode extension strip, avoiding current congestion. Example

[0114] An LED chip includes a substrate 1 and a plurality of LED light-emitting units disposed on the surface of the substrate 1 and isolated from each other by trenches, such as... Figure 1 As shown, the LED light-emitting unit includes:

[0115] An epitaxial stack is disposed on the surface of the substrate 1; the epitaxial stack includes a first type semiconductor layer 2, an active region 3, and a second type semiconductor layer 4 stacked sequentially along a first direction; and a local area of ​​the epitaxial stack is etched to the first type semiconductor layer 2 to form a groove 10 and a light-emitting mesa 11 (the illustration can be referred to the fabrication method corresponding to Embodiment 2). Figure 5 ); wherein, the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the epitaxial stack;

[0116] A transparent conductive layer 5 is stacked on the light-emitting platform 11 and has a second hole 5.1 that exposes a portion of the second type semiconductor layer 4;

[0117] A first insulating layer 6 is formed on the surface of the transparent conductive layer 5 facing away from the epitaxial stack;

[0118] The first electrode 8 is stacked on a portion of the surface of the groove 10 and disposed away from the light-emitting platform 11;

[0119] The second electrode 7 extends to a portion of the surface of the first insulating layer 6 by being disposed in the second hole 5.1;

[0120] A second insulating layer 9 is disposed on the surface of the epitaxial stack and exposes at least a portion of the surfaces of the first electrode 8 and the second electrode 7. Further, the second insulating layer 9 covers the light-emitting platform and the groove and exposes a portion of the surfaces of the first electrode 8 and the second electrode 7.

[0121] It should be noted that the type of substrate 1 is not limited in the LED chip of this embodiment. For example, substrate 1 can be, but is not limited to, sapphire substrate 1, silicon substrate 1, etc. Furthermore, the types of the epitaxially stacked first type semiconductor layer 2, active region 3, and second type semiconductor layer 4 are also not limited in the LED chip of this embodiment. In the embodiments of this utility model, the first type semiconductor layer 2 can be an N-type semiconductor layer, and correspondingly, the second type semiconductor layer 4 can be a P-type semiconductor layer; for example, the first type semiconductor layer 2 can be, but is not limited to, an N-type gallium nitride layer, and correspondingly, the second type semiconductor layer 4 can be, but is not limited to, a P-type gallium nitride layer.

[0122] It should be noted that, in order to highlight the technical features of this application, only one epitaxial stacked unit is shown in the figure in the embodiment of this application. In actual product applications, it may contain tens of thousands of epitaxial stacked units, depending on the application of the LED chip product. This application does not limit this.

[0123] Based on the above, in one embodiment of this application, the exposed portion of the transparent conductive layer 5 of the first insulating layer 6 forms a step, and the second electrode 7 extends to the surface of the first insulating layer 6 through the step.

[0124] Based on the above, in one embodiment of this application, the projection of the second electrode 7 on the transparent conductive layer 5 and the projection of the second electrode 7 on the first insulating layer 6 have an area of ​​S. a The overlapping area is partially defined, and the projected area of ​​the second electrode 7 on the transparent conductive layer 5 is S1, then 0 < S a ≤S1 / 2.

[0125] Based on the above, in one embodiment of this application, the step is arranged around the edge of the second hole 5.1.

[0126] Based on the above, in one embodiment of this application, the transparent conductive layer 5 covers at least 80% of the area of ​​the light-emitting mesa 11, excluding the second hole 5.1. Further, the edge of the transparent conductive layer 5 is located inside the edge of the second type semiconductor layer 4, with a distance d between them. This distance d is not greater than 2.5 μm, and preferably, in some embodiments, this distance d is not greater than 1.5 μm, for example, 1 μm. By reducing the distance from the edge of the transparent conductive layer 5 to the edge of the second type semiconductor layer 4, the area of ​​the transparent conductive layer 5 is increased, thereby increasing the area of ​​the light-emitting region and further improving the brightness of the light-emitting diode.

[0127] Based on the above, in one embodiment of this application, the second insulating layer 9 covers the light-emitting platform and the groove in such a way that it is held on the exposed surface of the first type semiconductor layer 2, and exposes a portion of the surface of the first electrode 8 and the second electrode 7.

[0128] Based on the above, in one embodiment of this application, the second electrode 7 has a metal reflective layer.

[0129] Based on the above, in one embodiment of this application, the bottom layer of the second electrode 7 is the metal reflective layer.

[0130] Based on the above, in one embodiment of this application, the metal reflective layer includes one or more of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, and Au.

[0131] Based on the above, in one embodiment of this application, the transparent conductive layer 5 includes a metal thin film or a metal oxide layer.

[0132] Based on the above, in one embodiment of this application, the metal thin film includes one or more of gold, silver, platinum, copper, aluminum, chromium, and palladium.

[0133] Based on the above, in one embodiment of this application, the metal oxide layer includes one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride.

[0134] Based on the above, in one embodiment of this application, the second insulating layer 9 includes, but is not limited to, one or more of silicon oxide and magnesium fluoride.

[0135] As can be seen from the above technical solution, the LED chip provided by this utility model is configured as follows: the epitaxial stack includes a first type semiconductor layer 2, an active region 3, and a second type semiconductor layer 4 stacked sequentially along a first direction; and a local area of ​​the epitaxial stack is etched to the first type semiconductor layer 2 to form a groove 10 and a light-emitting mesa 11; the transparent conductive layer 5 is stacked on the light-emitting mesa 11 and has a second hole 5.1 exposing a portion of the second type semiconductor layer 4; the first insulating layer 6 is formed on the side surface of the transparent conductive layer 5 away from the epitaxial stack; the first electrode 8 is stacked on a portion of the surface of the groove 10 and disposed away from the light-emitting mesa 11; the second electrode 7 extends to a portion of the surface of the first insulating layer 6 by being disposed in the second hole 5.1; the second insulating layer 9 is disposed on the surface of the epitaxial stack and exposes at least a portion of the surfaces of the first electrode 8 and the second electrode 7. Based on the above configuration, the first insulating layer 6, the transparent conductive layer 5, the second insulating layer 9, and the second electrode 7 form a composite region. This creates an ODR structure through the structural relationship between the transparent conductive layer 5, the first insulating layer 6, the second electrode 7, and the second insulating layer 9. Light can undergo total internal reflection in this composite region, allowing light from the composite region corresponding to the second electrode 7 to be reflected and extracted from the upper surface of the LED chip, thereby effectively improving light extraction efficiency. Simultaneously, based on the above configuration, the second insulating layer 9 is disposed on the surface of the epitaxial stack and part of the surface of the first electrode 8 / second electrode 7. At the edge of the second electrode 7, the first insulating layer 6 and the second insulating layer 9 with different extension directions can be formed to construct an angled connection structure. This effectively mitigates the diffusion of tensile stress generated by the LED chip under special environments (such as high temperature and high pressure), thereby reducing the risk of soldering failure or cracking of the functional dielectric layer (such as the transparent conductive layer 5 and the insulating layer), which could affect the reliability of the LED chip. Furthermore, the dual protection of the first insulating layer 6 and the second insulating layer 9 enhances the LED chip's water vapor resistance.

[0136] Secondly, by setting a step in the exposed portion of the transparent conductive layer 5 of the first insulating layer 6, and extending the second electrode 7 to the surface of the first insulating layer 6 through the step, the electrode contact area can be increased through the step, thereby dispersing stress and reducing the risk of local failure.

[0137] Then, by setting the projection of the second electrode 7 on the transparent conductive layer 5 and the projection of the second electrode 7 on the first insulating layer 6 to have an area of ​​S. a The overlapping area is partially defined, and the projected area of ​​the second electrode 7 on the transparent conductive layer 5 is S1, then 0 < S a≤S1 / 2. Thus, while ensuring the contact area between the second electrode 7 and the transparent conductive layer 5 to reduce the contact resistance, the size of the composite region area is ensured to improve the ODR reflection effect. Example

[0138] This utility model provides a method for preparing an LED chip, used to prepare the LED chip described in Example 1. The preparation method includes the following steps:

[0139] S01, such as Figure 2 As shown, a substrate 1 is provided;

[0140] It should be noted that the type of substrate 1 is not limited in the LED chip of this embodiment. For example, substrate 1 can be, but is not limited to, a sapphire substrate or a silicon substrate.

[0141] S02, such as Figure 3 As shown, an epitaxial stack is grown, the epitaxial stack comprising a first type semiconductor layer 2, an active region 3 and a second type semiconductor layer 4 stacked sequentially along a first direction; wherein, the first direction is perpendicular to the substrate 1 and extends from the substrate 1 toward the epitaxial stack;

[0142] It should be noted that in the embodiments of this utility model, the first type semiconductor layer 2 can be an N-type semiconductor layer, and correspondingly, the second type semiconductor layer 4 can be a P-type semiconductor layer; for example, the first type semiconductor layer 2 can be, but is not limited to, an N-type gallium nitride layer, and correspondingly, the second type semiconductor layer 4 can be, but is not limited to, a P-type gallium nitride layer.

[0143] S03, such as Figure 4 As shown, by deeply etching the epitaxial stack to expose the surface of the substrate 1, a plurality of epitaxial stack units that are independent of each other by trenches are formed.

[0144] In one embodiment of this application, the epitaxial stack is deeply etched to the surface of the exposed substrate 1 to form a plurality of epitaxial stack units arranged at intervals between each other by trenches; this includes: using an inductively coupled plasma (ICP) process, with etching gases including Cl2, Ar and O2. However, this application does not limit this, and the specific method depends on the circumstances.

[0145] It should be noted that, in order to highlight the technical features of this application, only one epitaxial stacked unit is shown in the figure in the embodiment of this application. In actual product applications, it may contain tens of thousands of epitaxial stacked units, depending on the application of the LED chip product. This application does not limit this.

[0146] S04, such as Figure 5 As shown, each of the epitaxial stacked units is etched to expose a portion of the first type semiconductor layer 2, thereby forming a groove 10 and a light-emitting mesa 11;

[0147] In one embodiment of this application, etching the epitaxial stack to form the groove 10 and the light-emitting mesa 11 includes: using an inductively coupled plasma (ICP) process, the etching gas including Cl2, Ar and O2, but this application does not limit this, and it depends on the specific situation.

[0148] In one embodiment of this application, the groove is disposed at the first end of the LED chip.

[0149] In one embodiment of this application, the exposed surface of the first type of semiconductor layer is disposed around the periphery of the light-emitting mesa 11.

[0150] S05, such as Figure 6 As shown, a transparent conductive layer 5 is fabricated on the light-emitting platform 11, wherein the transparent conductive layer 5 has a second hole 5.1 exposing a portion of the second type semiconductor layer 4;

[0151] Based on the above, in one embodiment of this application, the transparent conductive layer 5 covers at least 80% of the area of ​​the light-emitting mesa 11, excluding the second hole 5.1. Further, the edge of the transparent conductive layer 5 is located inside the edge of the second type semiconductor layer 4, with a distance d between them. This distance d is not greater than 2.5 μm, and preferably, in some embodiments, this distance d is not greater than 1.5 μm, for example, 1 μm. By reducing the distance from the edge of the transparent conductive layer 5 to the edge of the second type semiconductor layer 4, the area of ​​the transparent conductive layer 5 is increased, thereby increasing the area of ​​the light-emitting region and further improving the brightness of the light-emitting diode.

[0152] In one embodiment of this application, the transparent conductive layer 5 includes a metal thin film or a metal oxide layer.

[0153] Based on the above, in one embodiment of this application, the metal thin film includes one or more of gold, silver, platinum, copper, aluminum, chromium, and palladium.

[0154] Based on the above, in one embodiment of this application, the metal oxide layer includes one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride.

[0155] S06. Deposit a transparent dielectric layer, which covers the exposed surfaces of each of the epitaxial stack units; then, coat the surface of the transparent dielectric layer with photoresist, and through masking and etching processes, obtain a transparent dielectric layer located on the surface of the transparent conductive layer 5 to form a structure as shown in the image. Figure 7 The first insulating layer 6 is shown.

[0156] Based on the above, in one embodiment of this application, the transparent dielectric layer includes one or more materials such as silicon oxide, titanium oxide, silicon nitride, aluminum oxide, magnesium fluoride, spin-coated glass (SOG), and polymer.

[0157] Based on the above, in one embodiment of this application, the exposed portion of the first insulating layer 6 forms a step in the transparent conductive layer 5.

[0158] Based on the above, in one embodiment of this application, the step is arranged around the edge of the second hole 5.1.

[0159] S07, such as Figure 8 As shown, the first electrode 8 and the second electrode 7 are fabricated.

[0160] The first electrode 8 is stacked on a portion of the surface of the groove 10 and disposed away from the light-emitting platform 11;

[0161] The second electrode 7 extends to a portion of the surface of the first insulating layer 6 by being disposed in the second hole 5.1; further, the second electrode 7 extends to the surface of the first insulating layer 6 by the step.

[0162] Based on the above, in one embodiment of this application, the projection of the second electrode 7 on the transparent conductive layer 5 and the projection of the second electrode 7 on the first insulating layer 6 have an area of ​​S. a The overlapping area is partially defined, and the projected area of ​​the second electrode 7 on the transparent conductive layer 5 is S1, then 0 < S a ≤S1 / 2.

[0163] In this embodiment, the first electrode 8 and the second electrode 7 can be metal electrodes, that is, made of metal materials, such as at least one of nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten and molybdenum, or at least one alloy or stack of the above materials.

[0164] In one embodiment of this application, the second electrode 7 has a metal reflective layer.

[0165] Based on the above, in one embodiment of this application, the bottom layer of the second electrode 7 is the metal reflective layer. Further, the metal reflective layer includes one or more of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, and Au.

[0166] S08, such as Figure 9As shown, a second insulating layer 9 is fabricated on the surface of the epitaxial stack, exposing at least a portion of the surfaces of the first electrode 8 and the second electrode 7. Further, the second insulating layer 9 covers the light-emitting mesa 11 and the groove 10 in a manner held on the exposed surface of the first semiconductor layer 2, exposing a portion of the surfaces of the first electrode 8 and the second electrode 7.

[0167] Based on the above, in one embodiment of this application, the second insulating layer 9 includes, but is not limited to, one or more of silicon oxide and magnesium fluoride.

[0168] S09. Cut along the groove to obtain several such... Figure 10 The LED light-emitting unit shown. Example

[0169] Please see Figure 11 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 3 of this utility model. Compared to the LED chip in Embodiment 1, the main difference in this embodiment is that a third insulating layer 12 is further provided on the surface of the groove 10, and the third insulating layer 12 has a first hole 12.1 exposing a portion of the first type semiconductor layer 2; thus, the first electrode 8 is stacked on the surface of the third insulating layer 12 by embedding into the first hole 12.1, thereby further improving the stability of the first electrode 8.

[0170] It should be noted that, based on the above, in one embodiment of this application, the first insulating layer 6 and the third insulating layer can be formed simultaneously by photolithography of the transparent dielectric layer in step S06 of embodiment 2. Example

[0171] Please see Figure 12 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 4 of this utility model. Compared to the LED chip in Embodiment 1, the main difference in this embodiment is that a current blocking layer 13 is provided on the bottom surface of the second hole 5.1; furthermore, the current blocking layer 13 and the transparent conductive layer 5 form a spacer groove, and the second electrode 7 is embedded in the spacer groove to form contact with the second type semiconductor layer 4. This improves current concentration and promotes lateral current expansion, while also allowing the structural relationship between the second electrode 7, the first insulating layer 6 (dielectric layer), the spacer groove, the current blocking layer 13 (dielectric layer), and the transparent conductive layer 5 (conductive layer) to again form an ODR structure, which helps to increase the total reflection layer area below the second electrode 7 and further improves reflection efficiency.

[0172] Based on the above, in one embodiment of this application, the projected area of ​​the current blocking layer 13 on the transparent conductive layer 5 is S2, and the bottom area of ​​the second hole 5.1 is S3, then 0 < S2 ≤ S3 / 2. Thus, while ensuring current blocking and total internal reflection effects, the contact area between the second electrode 7 and the second type semiconductor layer 4 is ensured to improve the reliability of the electrode bonding wire. It should be noted that the specific area of ​​the current blocking layer 13 only needs to meet the above requirements, and this application will not elaborate further here. Similarly, the shape of the current blocking layer 13 can be trapezoidal, square, or rectangular, and this application will not elaborate further here.

[0173] It should be noted that, based on the above, in one embodiment of this application, the first insulating layer 6 and the current blocking layer 13 can be formed simultaneously by photolithography of the transparent dielectric layer in step S06 of embodiment 2. Example

[0174] Please see Figure 13 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 5 of this utility model. Compared to the LED chip in Embodiment 1, the main difference in this embodiment is that: the first electrode 8 includes a first electrode pad disposed at a first end of the LED chip, and the second hole 5.1 is formed at a second end of the LED chip; the second electrode 7 includes a second electrode pad and at least one electrode extension strip 14 connected to the second electrode pad, wherein the second electrode pad extends to the surface of the first insulating layer 6 by being disposed in the second hole 5.1, and the electrode extension strip 14 extends from the second electrode pad toward the second end of the LED chip; thus, current can be better guided and extended through the electrode extension strip 14, avoiding current congestion. It should be noted that the material, shape, and structure of the electrode extension strip 14 only need to meet the requirements for electrode extension and guidance, and will not be elaborated further in this application.

[0175] Furthermore, the first electrode 8 may also include an electrode extension strip connected to the first electrode pad and extending toward the first end, which will not be elaborated further in this application.

[0176] Based on the above, in one embodiment of this application, at least a portion of the electrode extension strip 14 forms contact with the transparent conductive layer 5.

[0177] Based on the above, in one embodiment of this application, the electrode extension strip 14 has interdigitated fingers, which then form contact with the transparent conductive layer 5 by being embedded in the first insulating layer 6 through perforations. Alternatively, the transparent conductive layer 5 has perforations, and the electrode extension strip 14 has interdigitated fingers, which are formed in and held in the perforations of the transparent conductive layer 5.

[0178] It should be emphasized that in other embodiments, it may be a combination of Embodiment 5 and Embodiment 4, which will not be elaborated further in this application. Example

[0179] Please see Figure 14 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 6 of this utility model. Compared to the LED chip in Embodiment 1 of this utility model, the main difference in the LED chip of Embodiment 6 is that the LED chip further includes a refractive index matching layer 15. The refractive index matching layer 15 is disposed on the surface of the second insulating layer 9 away from the epitaxial stack and forms a gradient refractive index structure with the second insulating layer 9, further improving light extraction efficiency. Preferably, the refractive index of the refractive index matching layer 15 is not less than the refractive index of the second insulating layer 9. Further, if the first insulating layer 6 or the second insulating layer 9 comprises a layered structure composed of one or more of SiO2 and MgF2, then the refractive index matching layer 15 may comprise a layered structure composed of one or more of TiO2, Si3N4, and Al2O3. Preferably, the second insulating layer 9 is a SiO2 layer, and the refractive index matching layer 15 is an Al2O3 layer. Through the excellent passivation properties of Al2O3, dangling bonds and defect states on the SiO2 surface can be effectively covered, reducing non-radiative recombination of charge carriers on the surface. The reduction in nonradiative recombination directly improves the internal quantum efficiency (IQE), meaning that more electrical energy is converted into light energy rather than heat. Example

[0180] Please see Figure 15 This is a cross-sectional structural diagram of the LED chip provided in Embodiment 7 of this utility model. Compared to the LED chip in Embodiment 1, the main difference in this embodiment lies in the fact that a reflective layer 16 is further provided on the surface of the substrate 1 facing away from the epitaxial stack. Further, the reflective layer 16 comprises a distributed Bragg reflective layer composed of alternating layers of high-refractive-index material and low-refractive-index material. Alternatively, the reflective layer can also be a metallic reflective layer. The material only needs to meet the requirements of a distributed Bragg reflective layer / metallic reflective layer, which will not be elaborated upon further in this application. Example

[0181] Please see Figure 16This is a cross-sectional structural diagram of the LED chip provided in Embodiment 8 of the present invention. Compared with the LED chip of Embodiment 1 of the present invention, the main difference of the LED chip in Embodiment 7 is that the exposed surface of the first type semiconductor layer is only disposed in the groove and is not disposed around the periphery of the light-emitting platform 11. Therefore, the second insulating layer 9 does not completely cover the epitaxial stack at this time.

[0182] Based on the above embodiments, in practical applications, any combination of two or more of the above embodiments may also be used, depending on the technical requirements of the specific product. This application does not limit this.

[0183] It should also be noted that the LED chips provided in the above embodiments are also applicable to high-voltage LED chips, which electrically interconnect adjacent LED light-emitting units as described above through bridging electrodes; wherein, an insulating layer is further provided in the trench, and the bridging electrodes connect two adjacent LED units by being stacked on the insulating layer. Its specific structure, performance, and advantages can be referred to the foregoing content, and will not be elaborated further here.

[0184] In addition, this utility model also provides a light-emitting device, which includes a light-emitting diode. The light-emitting diode adopts an LED chip or a high-voltage LED chip as provided in the above embodiments. Its specific performance and advantages can be referred to the foregoing content, and will not be elaborated in detail here.

[0185] The device provided in this embodiment of the present invention has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can all be referred to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0186] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0187] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0188] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, comprising a substrate and a plurality of LED light-emitting units disposed on the surface of the substrate and isolated from each other by trenches, characterized in that, The LED light-emitting unit includes: An epitaxial stack is disposed on the surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active region, and a second type semiconductor layer stacked sequentially along a first direction; and a local area of ​​the epitaxial stack is etched to the first type semiconductor layer to form a groove and a light-emitting mesa; wherein, the first direction is perpendicular to the substrate and points from the substrate to the epitaxial stack; A transparent conductive layer, which is stacked on the light-emitting platform and has a second hole that exposes a portion of the second type semiconductor layer; A first insulating layer is formed on the surface of the transparent conductive layer opposite to the epitaxial stack; The first electrode is stacked on a portion of the surface of the groove and disposed away from the light-emitting platform; The second electrode extends to a portion of the surface of the first insulating layer by being disposed in the second hole; A second insulating layer is disposed on the surface of the epitaxial stack and exposes at least a portion of the surfaces of the first and second electrodes.

2. The LED chip according to claim 1, characterized in that, The exposed portion of the first insulating layer forms a step in the transparent conductive layer, and the second electrode extends to the surface of the first insulating layer through the step.

3. The LED chip according to claim 1, characterized in that, The projection of the second electrode onto the transparent conductive layer and the projection of the second electrode onto the first insulating layer have an area of ​​S. a If the regions partially overlap and the projected area of ​​the second electrode on the transparent conductive layer is S1, then 0 < S a ≤S1 / 2.

4. The LED chip according to claim 2, characterized in that, The steps are arranged around the edge of the second hole.

5. The LED chip according to claim 1, characterized in that, A current blocking layer is provided on the bottom surface of the second hole.

6. The LED chip according to claim 5, characterized in that, The current blocking layer forms a spacer groove with the transparent conductive layer, and the second electrode is embedded in the spacer groove to form a contact with the second type of semiconductor layer.

7. The LED chip according to claim 6, characterized in that, The projected area of ​​the current blocking layer on the transparent conductive layer is S2, and the bottom area of ​​the second hole is S3, then 0 < S2 ≤ S3 / 2.

8. The LED chip according to claim 7, characterized in that, The first insulating layer and the current blocking layer are formed simultaneously by photolithography on the transparent dielectric layer.

9. The LED chip according to claim 8, characterized in that, The transparent dielectric layer includes one of silicon oxide, silicon nitride, aluminum oxide, and magnesium fluoride.

10. The LED chip according to claim 1, characterized in that, A third insulating layer is also provided on the surface of the groove, and the third insulating layer has a first hole that exposes a portion of the first type semiconductor layer; then the first electrode is stacked on the surface of the third insulating layer by embedding into the first hole.

11. The LED chip according to claim 10, characterized in that, The first insulating layer and the third insulating layer are formed simultaneously by photolithography on the transparent dielectric layer.

12. The LED chip according to claim 1, characterized in that, The LED chip further includes a refractive index matching layer, which is disposed on the side surface of the second insulating layer away from the epitaxial stack and forms a gradient refractive index structure with the second insulating layer, and the refractive index of the refractive index matching layer is not less than the refractive index of the second insulating layer.

13. The LED chip according to claim 1, characterized in that, A reflective layer is also provided on one side surface of the substrate opposite to the epitaxial stack.

14. The LED chip according to claim 1, characterized in that, The first electrode includes a first electrode pad disposed at a first end of the LED chip, and the second hole is formed at a second end of the LED chip; the second electrode includes a second electrode pad and at least one electrode extension strip connected to the second electrode pad, wherein the second electrode pad extends to the surface of the first insulating layer by being disposed in the second hole, and the electrode extension strip extends from the second electrode pad toward the second end of the LED chip.

15. The LED chip according to claim 14, characterized in that, At least a portion of the electrode extension strip is in contact with the transparent conductive layer.

16. The LED chip according to claim 15, characterized in that, The electrode extension strip has forked fingers, which then form contact with the transparent conductive layer by being embedded in the first insulating layer through perforations.

17. The LED chip according to claim 1, characterized in that, The second insulating layer covers the light-emitting platform and the groove in such a way that it is held on the exposed surface of the first type of semiconductor layer.

18. A high-voltage LED chip, characterized in that, The high-voltage LED chip electrically interconnects adjacent LED light-emitting units according to any one of claims 1 to 17 through a bridging electrode; wherein, an insulating layer is further provided in the trench, and the bridging electrode connects two adjacent LED units by being stacked on the insulating layer.

19. A light-emitting device, characterized in that, The light-emitting device includes a light-emitting diode, which is an LED chip as described in any one of claims 1 to 17.

20. A light-emitting device, characterized in that, The light-emitting device includes a light-emitting diode, which employs the high-voltage LED chip as described in claim 18.

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