Display panel and display device

Abstract

The utility model provides a display panel and a display device. Abnormalities caused by a reliability test are improved. The display panel comprises a substrate, a plurality of sub-pixels located in a display area, a plurality of data lines located in the display area and a first frame area, a first contact pad group, a second contact pad group and a first organic film layer which are located in a first signal access area, and a first inorganic film layer located on the side, away from the substrate, of the first organic film layer. The second contact pad group is located on one side of the first contact pad group away from the display area. The first contact pad group and the second contact pad group are configured to be bound with the driving chip. The orthographic projection of the first organic film layer on the substrate is located between the orthographic projections of the first contact pad group and the second contact pad group on the substrate. The first inorganic film layer is provided with at least one of at least one first inorganic groove at least partially located between the first contact pad group and the first organic film layer and at least one second inorganic groove at least partially located between the second contact pad group and the first organic film layer in the first frame area.

Description

Technical Field

[0001] This utility model relates to, but is not limited to, the field of display technology, and particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Utility Model Content

[0003] The following is an overview of the subject matter of this utility model in detail. This overview is not intended to limit the scope of the claims.

[0004] To improve the display abnormalities caused by high temperature and high humidity environments during reliability testing, this utility model provides a display panel and a display device.

[0005] On one hand, this utility model provides a display panel, including: a substrate, a plurality of sub-pixels, a plurality of data lines, a first contact pad group, a second contact pad group, a first organic film layer, and a first inorganic film layer. The substrate includes a display area and a first border area located on one side of the display area, the first border area including at least one first signal access area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and the first border area, and the plurality of sub-pixels and the plurality of data lines are connected. The first contact pad group and the second contact pad group are located in the first signal access area, the second contact pad group being located on the side of the first contact pad group away from the display area. The first contact pad group includes a plurality of first contact pads connected to the plurality of data lines, and the second contact pad group includes a plurality of second contact pads. The plurality of first contact pads and the plurality of second contact pads are configured to be bonded to a driver chip. A first organic film layer is located in the first signal access area. The orthographic projection of the first organic film layer onto the substrate does not overlap with the orthographic projections of the first contact pad group and the second contact pad group onto the substrate, and is located between the orthographic projections of the first contact pad group and the second contact pad group onto the substrate in a direction away from the display area. A first inorganic film layer is located on the side of the first organic film layer away from the substrate. The first inorganic film layer has at least one of the following in the first frame area: at least one first inorganic groove and at least one second inorganic groove. At least a portion of the at least one first inorganic groove is located between the orthographic projections of the first contact pad group and the first organic film layer onto the substrate. At least a portion of the at least one second inorganic groove is located between the orthographic projections of the second contact pad group and the first organic film layer onto the substrate.

[0006] In some exemplary embodiments, the orthographic projection of the first inorganic film layer onto the substrate overlaps the orthographic projection of the first organic film layer onto the substrate.

[0007] In some exemplary embodiments, the display panel further includes: a test unit located in the first signal access area, the test unit being located between the first contact pad group and the second contact pad group in a direction away from the display area; the orthographic projection of the test unit on the substrate at least partially overlaps with the orthographic projection of the first organic film layer on the substrate.

[0008] In some exemplary embodiments, the test unit includes: a plurality of test pins and a plurality of test circuits, wherein the plurality of test pins are located on the side of the plurality of test circuits away from the first contact pad group; the orthographic projection of the first organic film layer on the substrate at least partially overlaps with the orthographic projection of the plurality of test pins and the plurality of test circuits on the substrate.

[0009] In some exemplary embodiments, the first organic film layer includes: a first organic bump and a second organic bump; the first organic bump and the second organic bump are disposed in the same layer, and the first organic bump and the second organic bump are disposed along the arrangement direction of the plurality of test circuits; the orthographic projection of the first organic bump and the second organic bump on the substrate at least partially overlaps with the orthographic projection of the plurality of test circuits on the substrate; along the direction away from the display area, the first organic bump and the second organic bump are both adjacent to the first inorganic groove.

[0010] In some exemplary embodiments, the first organic film layer further includes: a third organic bump and a fourth organic bump, wherein the third organic bump is disposed in the same layer as the first organic bump, and the fourth organic bump is located on the side of the third organic bump away from the substrate; the orthographic projections of the third organic bump and the fourth organic bump on the substrate at least partially overlap with the orthographic projections of the plurality of test pins on the substrate; and along the direction away from the display area, both the third organic bump and the fourth organic bump are adjacent to the second inorganic groove.

[0011] In some exemplary embodiments, the test pin includes: a first pin layer and a second pin layer stacked sequentially, the first pin layer being located on the side of the second pin layer closer to the substrate; the second pin layer contacting the first pin layer through a via formed by the third organic bump, and the fourth organic bump being located on the side of the second pin layer away from the substrate.

[0012] In some exemplary embodiments, the at least one first inorganic tank and the at least one second inorganic tank are an integral structure.

[0013] In some exemplary embodiments, the orthographic projection of the at least one first inorganic groove and the at least one second inorganic groove onto the substrate surrounds the orthographic projection of the first organic film layer onto the substrate.

[0014] In some exemplary embodiments, the orthographic projection of the first inorganic groove on the substrate covers the orthographic projection of the first contact pad assembly on the substrate, and the orthographic projection of the second inorganic groove on the substrate covers the orthographic projection of the second contact pad assembly on the substrate.

[0015] In some exemplary embodiments, the first inorganic film layer has a plurality of first inorganic grooves and a plurality of second inorganic grooves in the first border region; along the direction away from the display area, the minimum distance between adjacent first inorganic grooves is the same, and the minimum distance between adjacent second inorganic grooves is the same.

[0016] In some exemplary embodiments, the orthographic projection of the at least one first inorganic groove on the substrate surrounds the orthographic projection of the first contact pad group on the substrate; the orthographic projection of the at least one second inorganic groove on the substrate surrounds the orthographic projection of the second contact pad group on the substrate.

[0017] In some exemplary embodiments, the first border area further includes: a second signal access area located on the side of the at least one first signal access area away from the display area; the display panel further includes: a third contact pad group located in the second signal access area, the third contact pad group including a plurality of third contact pads, a portion of the plurality of third contact pads being connected to the plurality of second contact pads via a plurality of internal bonding lines; the orthographic projection of the at least one second inorganic groove on the substrate surrounds the orthographic projection of the second contact pad group, the third contact pad group, and the plurality of internal bonding lines on the substrate; or, the orthographic projection of the at least one second inorganic groove on the substrate covers the orthographic projection of the second contact pad group, the third contact pad group, and the plurality of internal bonding lines on the substrate.

[0018] In some exemplary embodiments, the minimum distance between the first inorganic groove and the first contact pad group along the direction away from the display area is different from the minimum distance between the first inorganic groove and the first organic film layer.

[0019] In some exemplary embodiments, the minimum distance between the second inorganic groove and the second contact pad group along the direction away from the display area is different from the minimum distance between the second inorganic groove and the first organic film layer.

[0020] In some exemplary embodiments, the substrate further includes: a second border region located on the remaining side of the display area; the first inorganic film layer having at least one third inorganic groove extending along the edge of the display panel in the second border region, the third inorganic groove being close to the edge of the display panel.

[0021] In some exemplary embodiments, the substrate further includes: an opening region and a third border region at least partially surrounding the opening region, the display region at least partially surrounding the third border region; the first inorganic film layer is provided with at least one fourth inorganic groove surrounding the opening region in the third border region.

[0022] In some exemplary embodiments, the display panel further includes: a first touch conductive layer and a second touch conductive layer; the first touch conductive layer is located on the side of the plurality of sub-pixels away from the substrate, and the second touch conductive layer is located on the side of the first touch conductive layer away from the substrate; the first inorganic film layer includes at least one of the following: a touch interlayer insulating layer located between the first touch conductive layer and the second touch conductive layer; and a touch buffer layer located on the side of the first touch conductive layer near the substrate.

[0023] In some exemplary embodiments, the first contact pad includes a first sub-pad, a second sub-pad, a third sub-pad, and a fourth sub-pad stacked sequentially; the second contact pad includes a fifth sub-pad, a sixth sub-pad, a seventh sub-pad, and an eighth sub-pad stacked sequentially; the fourth sub-pad contacts the third sub-pad through a through-hole in the first inorganic film layer, and the eighth sub-pad contacts the seventh sub-pad through a through-hole in the first inorganic film layer.

[0024] On the other hand, the present invention provides a display device, including the display panel as described above.

[0025] The display panel provided by this utility model, by setting a first inorganic groove that separates the first contact pad group and the first organic film layer or a second inorganic groove that separates the second contact pad group and the first organic film layer in the first signal access area, can block the peeling of the first inorganic film layer after the bonding process of the driver chip by using the inorganic groove, which can effectively avoid the extension of the water and oxygen propagation path, thereby improving the display abnormality caused by the high temperature and high humidity environment during the reliability test and ensuring the quality of the display panel.

[0026] Other features and advantages of this invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description

[0027] The accompanying drawings are provided to further understand the technical solution of this utility model and constitute a part of the specification. They are used together with the embodiments of this utility model to explain the technical solution of this utility model, and do not constitute a limitation on the technical solution of this utility model.

[0028] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present invention;

[0029] Figure 2 This is a partial cross-sectional schematic diagram of the display area of ​​the display panel of at least one embodiment of the present invention;

[0030] Figure 3This is a partial structural diagram of the first border region of at least one embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram illustrating the bonding process between a display panel and a driver chip.

[0032] Figure 5 This is a plan view of the first signal access area according to at least one embodiment of the present invention;

[0033] Figure 6 for Figure 5 A partial cross-sectional view along the QQ' direction;

[0034] Figure 7 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention;

[0035] Figure 8 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention;

[0036] Figure 9 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention;

[0037] Figure 10 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention;

[0038] Figure 11 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention;

[0039] Figure 12 This is a partial planar schematic diagram of the first border region of at least one embodiment of the present invention;

[0040] Figure 13 This is another partial planar schematic diagram of the first signal access area according to at least one embodiment of the present invention;

[0041] Figure 14 This is a partial planar schematic diagram of the first border region of at least one embodiment of the present invention;

[0042] Figure 15 for Figure 1 A partial cross-sectional view along the RR' direction;

[0043] Figure 16 This is another schematic diagram of the display panel of at least one embodiment of the present invention;

[0044] Figure 17 for Figure 16 A partial cross-sectional view along the PP' direction;

[0045] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present invention. Detailed Implementation

[0046] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings. The embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this utility model. Therefore, this utility model should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this utility model can be arbitrarily combined with each other.

[0047] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, one aspect of the invention is not necessarily limited to these dimensions, and the shape and size of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of the invention is not limited to the shapes or values ​​shown in the drawings.

[0048] The ordinal numbers "first," "second," and "third" used in this specification are provided to avoid confusion among the constituent elements, not to limit the quantity. In this utility model, "multiple" refers to two or more items.

[0049] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this utility model. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as needed.

[0050] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or a joint; they can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the meaning of these terms in this utility model according to the context. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0051] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0052] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0053] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0054] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0055] In this specification, "approximately" and "about" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this utility model, "same" includes cases where the numerical values ​​differ by less than 10%, such as cases where the numerical values ​​differ by less than 5%.

[0056] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0057] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are at approximately the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B. The "shape of A" in this invention refers to the shape of the orthographic projection of A onto the substrate.

[0058] Figure 1 This is a schematic diagram of a display panel according to at least one embodiment of the present invention. In some examples, such as... Figure 1 As shown, the display panel can be a closed polygon including linear edges. The display panel can include: a display area AA and a border area BB surrounding the display area AA. The border area BB can include: a first border area B1 located on one side of the display area AA along a first direction D1, and a second border area located on the remaining sides of the display area AA. For example, the first border area B1 can also be referred to as the bottom border area of ​​the display panel. The second border area can include: an upper border area B4 located in the display area AA away from the first border area B1 along the first direction D1, and a left border area B2 and a right border area B3 located on both sides of the display area AA along a second direction D2. The first border area B1 can be connected to the left border area B2 and the right border area B3, and the upper border area B4 can be connected to the left border area B2 and the right border area B3. The first border area B1, the left border area B2, the right border area B3, and the upper border area B4, when connected, can surround the display area AA.

[0059] In some examples, such as Figure 1As shown, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array. These sub-pixels PX can be configured to display moving or still images. The display area AA can also be referred to as the active area. In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circular or elliptical. In some examples, the display panel can be a flexible panel, and therefore the display panel can be deformable, such as rolled, bent, folded, or rolled up.

[0060] In some examples, such as Figure 1 As shown, the display area AA may include: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals or test data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and light emission control signals, or may include scan signals, reset control signals, and light emission control signals.

[0061] In some examples, the first direction D1 can be the extension direction of the data line DL within the display area AA (e.g., column direction); the second direction D2 can be the extension direction of the grid line GL within the display area AA (e.g., row direction). The first direction D1 and the second direction D2 can be parallel to the plane of the base and intersect each other, for example, they can be perpendicular to each other.

[0062] In some examples, a pixel unit of the display area AA may include multiple sub-pixels. For instance, a pixel unit may include four sub-pixels, which may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and two third sub-pixels emitting a third color light (e.g., green light). In other examples, a pixel unit may include three sub-pixels, which may be a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light.

[0063] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0064] In some examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be either P-type or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the manufacturing process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0065] In some examples, the shape of the light-emitting element of a sub-pixel can be rectangular, rhomboid, circular, semi-circular, elliptical, pentagonal, or hexagonal. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited to this. In other examples, when a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement.

[0066] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0067] Figure 2 This is a partial cross-sectional schematic diagram of the display area of ​​the display panel of at least one embodiment of the present invention. Figure 2This example illustrates the structure of a sub-pixel in the display area. In this example, multiple transistors in the pixel circuit are of the same type; for example, all transistors in the pixel circuit can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS) or all can be oxide (OPS) thin-film transistors (OSTs). In other examples, the multiple transistors in the pixel circuit can be both LTPS and OPS. Furthermore, this example illustrates a display panel integrating a mutual capacitance touch structure to form an FMLOC structure.

[0068] In some examples, such as Figure 2 As shown, in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a substrate 100, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the substrate 100. The circuit structure layer 12 may include at least pixel circuits for multiple sub-pixels, and each sub-pixel's pixel circuit may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least light-emitting elements for multiple sub-pixels.

[0069] Figure 2The illustration uses an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 12 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 100. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first and second gate metal layers; an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer 104 and a first planarization layer 105 may be disposed between the first and second source / drain metal layers; and a second planarization layer 106 may be disposed on the side of the second source / drain metal layer away from the substrate 100. The first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 may be inorganic insulating layers, while the first planarization layer 105 and the second planarization layer 106 may be organic insulating layers. However, this embodiment is not limited in this respect. In other examples, a buffer layer may be disposed on the side of the semiconductor layer near the substrate. This buffer layer prevents harmful substances from the substrate from penetrating the interior of the display panel and increases the adhesion of the film layers in the display panel to the substrate. In still other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer near the substrate. This bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistors of the pixel circuitry to prevent external light from affecting the performance of the thin-film transistors. In still other examples, a passivation layer may be omitted between the first and second source / drain metal layers, and only a first planarization layer may be disposed between the first and second source / drain metal layers.

[0070] In some examples, such as Figure 2As shown, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 104 and the first planarization layer 105. In this example, the first transition electrode 231 can be used to achieve the electrical connection between the pixel circuit and the light-emitting element.

[0071] In some examples, the gate line GL of the display area may be located in the first gate metal layer, the data line DL of the display area may be located in the second source-drain metal layer, and the high-potential power line of the display area may be located in the second source-drain metal layer. This embodiment is not limited in this respect.

[0072] In some examples, such as Figure 2As shown, the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on a second planarization layer 106 and electrically connected to a first transition electrode 231 through a third pixel via formed in the second planarization layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the second planarization layer 106, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133. An isolation pillar layer can also be set on the side of the pixel definition layer 134 away from the substrate 100. The isolation pillar layer can include multiple isolation pillars (PS).

[0073] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0074] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0075] In some examples, such as Figure 2 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first encapsulation layer 141 and the third encapsulation layer 143. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have penetrated the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0076] In some examples, such as Figure 2As shown, the touch structure layer 15 may include: a touch buffer layer (TBL) 151, a first touch conductive layer (TMA) 155, a touch interlayer insulating layer (TLD) 152, a second touch conductive layer (TMB) 156, and a touch protective layer 153, arranged sequentially. For example, the first touch conductive layer 155 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions; the plurality of first touch electrodes, the plurality of second touch electrodes, and the plurality of first connecting portions may be formed by the same patterning process, and the first touch electrodes and the first connecting portions may be an integral structure interconnected with each other. The second touch conductive layer 156 may include a plurality of second connecting portions; the second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer 152. In other examples, the first touch conductive layer 155 may include a plurality of second connecting portions; the second touch conductive layer 156 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. This embodiment does not limit this.

[0077] In some examples, the first touch electrode can be a drive (Tx) electrode and the second touch electrode can be a sensing (Rx) electrode. Alternatively, the first touch electrode can be a sensing (Rx) electrode and the second touch electrode can be a drive (Tx) electrode.

[0078] In some examples, the touch buffer layer 151 and the inter-touch insulating layer 152 can be inorganic insulating layers. For example, the touch buffer layer 151 and the inter-touch insulating layer 152 can be any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The touch protective layer 153 can be an organic insulating layer. The first touch conductive layer 155 and the second touch conductive layer 156 can be made of any one or more of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti, ITO / Ag / ITO, etc.

[0079] In some examples, such as Figure 1As shown, the first border region B1 may include: a first sub-region B11, a bent region B12, and a second sub-region B13 arranged sequentially along the side away from the display region AA in the first direction D1. The first sub-region B11 may be connected to the left border region B2, the right border region B3, and the display region AA. The bent region B12 may be connected between the first sub-region B11 and the second sub-region B13. The bent region B12 may be configured to bend the second sub-region B13 to the back of the display region AA.

[0080] Figure 3 This is a partial structural diagram of the first border region according to at least one embodiment of the present invention. In some examples, such as... Figure 1 and Figure 3 As shown, the second sub-region B13 may include: a first signal access region B131 and a second signal access region B132. The first signal access region B131 may be located on the side of the second signal access region B132 near the bending region B12. The maximum length of the first signal access region B131 along the second direction D2 may be less than the maximum length of the second signal access region B132 along the second direction D2.

[0081] In some examples, the first signal access area B131 may be provided with a first contact pad group 31, a second contact pad group 32, and a test unit 35 located between the first contact pad group 31 and the second contact pad group 32 along a first direction D1. The first contact pad group 31 may be located on the side of the second contact pad group 32 near the bending area B12. The first contact pad group 31 may include a plurality of first contact pads 311. The plurality of first contact pads 311 in the first contact pad group 31 may be arranged in at least two rows along the first direction D1, and each row may include a plurality of first contact pads 311 arranged sequentially along a second direction D2. Some of the plurality of first contact pads 311 may be connected to a plurality of data lines DL extending to the first border area B1. For example, in the second sub-area B13, the plurality of data lines DL may be alternately arranged in the first gate metal layer and the second gate metal layer. The second contact pad group 32 may include a plurality of second contact pads 321. The plurality of second contact pads 321 in the second contact pad group 32 may be arranged sequentially along the second direction D2, for example, arranged in a row. The first contact pad group 31 and the second contact pad group 32 within the first signal access area B131 can be configured to bond to a driver chip (IC). The first signal access area B131 can also be referred to as a driver chip setting area. In other examples, the second sub-area B13 may include a plurality of first signal access areas B131 arranged sequentially along the second direction D2, each first signal access area B131 being configured to bond to a driver chip.

[0082] In some examples, test unit 35 can be used for array testing (AT). Test unit 35 can be configured to provide test data signals and test control signals (such as start signals, clock signals, and voltage signals provided to the gate drive circuit) during the array testing phase. Array testing is mainly used to inspect the pixel units of the display panel and provide feedback signals such as the type, quantity, and location of defects, thereby monitoring the manufacturing process of the display panel to continuously improve the manufacturing process and achieve the goal of increasing product yield. For example, test unit 35 may include multiple test pins and multiple test circuits, with the multiple test pins connected to the multiple test circuits. During the array testing phase, test equipment can be connected to the multiple test pins to perform comprehensive functional testing of the display panel through test unit 35, including brightness, color accuracy, and response time.

[0083] In some examples, the second signal access area B132 may be provided with a third contact pad group 33. The third contact pad group 33 may include a plurality of third contact pads 331, which may be arranged sequentially along the second direction D2, for example, in a row. The third contact pad group 33 may be configured to bond to an external flexible printed circuit board (FPC). A plurality of second contact pads 321 in the first signal access area B131 may be connected to a portion of the third contact pads 331 in the second signal access area B132 via multiple inner lead-bonding lines (ILB).

[0084] In some examples, such as Figure 3 As shown, the first border region B1 may also be provided with at least one first power line (e.g., including first power lines VDD1 and VDD2) and at least one second power line (e.g., including second power lines VSS1, VSS2, and VSS3). The first power lines VDD1 and VDD2 may be located on either side of the second power line VSS3 along the second direction D2. The second power line VSS1 may be located on the side of the first power line VDD1 away from the second power line VSS3, and the second power line VSS2 may be located on the side of the first power line VDD2 away from the second power line VSS3. The second power lines VSS1, VSS2, and VSS3 may be interconnected in the first sub-region B11.

[0085] In some examples, such as Figure 3As shown, the first border area B1 may also be provided with multiple display control lines 411 and 412, and multiple touch control lines 413 and 414. The multiple display control lines 411 and 412 can be configured to provide initial signals to the pixel circuit, and can also be configured to provide start signals, clock signals, and voltage signals to the gate drive circuit, etc.; the multiple touch control lines 413 and 414 can be configured to transmit touch signals. The multiple display control lines 411 can extend from the first border area B1 to the left border area B2, and the multiple display control lines 412 can extend from the first border area B1 to the right border area B3; the multiple touch control lines 413 can extend from the first border area B1 to the left border area B2, and the multiple touch control lines 414 can extend from the first border area B1 to the right border area B3. The multiple touch control lines 413 and 414 can be located on the side of the multiple display control lines 411 and 414 away from the substrate.

[0086] With the continuous development of display technology, the requirements for display panel performance are becoming increasingly stringent. Display malfunction is one of the most common defects in display panels, manifesting as abnormal display after the LEDs are turned on, usually due to abnormal circuit signal transmission. The driver chip bonded to the first signal access area is a crucial component controlling the display panel's performance; therefore, the bonding quality of the driver chip is paramount for normal display. Furthermore, determining the quality of a display panel requires reliability testing, high-temperature and high-humidity operation, or storage testing. In other words, such tests involve placing the display panel in a high-temperature and high-humidity environment with and without power on, and then observing for display malfunctions after a certain period of time. If no defects are found after the display panel has been stored or operated under reliable conditions for a certain period, it indicates that the display panel is of acceptable quality and can be used in the next stage.

[0087] Figure 4 This is a schematic diagram illustrating the bonding process between a display panel and a driver chip. In some examples, such as... Figure 4As shown, the driver chip 70 may include a plurality of first pads 701 and a plurality of second pads 702. The plurality of first pads 701 can be connected to a plurality of first contact pads 311 in the first signal access area of ​​the display panel 10 via anisotropic conductive adhesive (ACF), and the plurality of second pads 702 can be connected to a plurality of second contact pads 321 in the first signal access area of ​​the display panel 10 via anisotropic conductive adhesive (ACF). During the bonding process of the driver chip, the metal conductive particles in the ACF break after pressing, enabling a conductive connection between the driver chip 70 and the display panel 10 along a direction perpendicular to the substrate. The first contact pads 311 can be pressed and connected to the first pads 701 of the driver chip 70 to transmit signals, and the second contact pads 321 can be pressed and connected to the second pads 702 of the driver chip 70 to transmit signals. A test unit 35 located between the plurality of first contact pads 311 and the plurality of second contact pads 321 is used for array testing before the driver chip 70 is bonded. Test unit 35 may be covered by organic bumps 360 (e.g., formed by partial stacking of the first and second planarization layers) to protect the traces located on the source / drain metal layers. Test unit 35 is not connected to driver chip 70. The first signal access area may be covered by a touch inorganic film layer 370 (e.g., including a stacked touch buffer layer and an interlayer insulation layer) in addition to the exposed contact pads.

[0088] During the process of bonding the driver chip 70 to the first signal access area of ​​the display panel, the first contact pad group 31 and the second contact pad group 32 on both sides of the test unit 35 will be subjected to a large downward force (e.g., about 200N). Due to the influence of the soft ufilm layer, after the area where the first contact pad group 31 and the second contact pad group 32 are located is subjected to pressure, the organic bump 360 in the middle area between the first contact pad group 31 and the second contact pad group 32 is extremely easy to lift up and contact the driver chip 70, and then the touch inorganic film layer 370 will crack near the organic bump 360. Subsequently, under high temperature and high humidity reliability conditions, the touch inorganic film layer 370 will gradually peel off, and the peeling will spread to the area where the first contact pad group 31 and the second contact pad group 32 are located, thereby creating a water and oxygen intrusion path (for example, water and oxygen can intrude through the exposed metal layer of the touch inorganic film layer 370), causing the metal traces to oxidize and corrode and become unconductive, resulting in the failure of the display panel.

[0089] This embodiment provides a display panel, including: a substrate, a plurality of sub-pixels disposed on the substrate, a plurality of data lines, a first contact pad group, a second contact pad group, a first organic film layer, and a first inorganic film layer. The substrate includes a display area and a first border area located on one side of the display area, the first border area including at least one first signal access area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and the first border area, and the plurality of sub-pixels and the plurality of data lines are connected. The first contact pad group, the second contact pad group, and the first organic film layer are located in the first signal access area. The second contact pad group is located on the side of the first contact pad group away from the display area. The first contact pad group includes a plurality of first contact pads, which are connected to the plurality of data lines. The second contact pad group includes a plurality of second contact pads, and the plurality of first and second contact pads are configured to be bonded to a driver chip. The orthographic projection of the first organic film layer onto the substrate does not overlap with the orthographic projections of the first and second contact pad groups onto the substrate, and is located between the orthographic projections of the first and second contact pad groups onto the substrate in a direction away from the display area. The first inorganic film layer is located on the side of the first organic film layer away from the substrate. The first inorganic film layer has at least one of the following in the first border region: at least one first inorganic groove and at least one second inorganic groove. At least a portion of the at least one first inorganic groove, when projected onto the substrate, lies between the first contact pad group and the first organic film layer when projected onto the substrate; at least a portion of the at least one second inorganic groove, when projected onto the substrate, lies between the second contact pad group and the first organic film layer when projected onto the substrate.

[0090] In some examples, the first inorganic film layer may have a first inorganic groove in the first border region, with a portion of the first inorganic groove located between the first contact pad group and the first organic film layer; or, all of the first inorganic grooves may be located between the first contact pad group and the first organic film layer. Alternatively, the first inorganic film layer may have multiple first inorganic grooves in the first border region, with all of the multiple first inorganic grooves located between the first contact pad group and the first organic film layer; or, at least one of the multiple first inorganic grooves may have a portion located between the first contact pad group and the first organic film layer.

[0091] In some examples, the first inorganic film layer may have a second inorganic groove in the first border region, with a portion of the second inorganic groove located between the second contact pad group and the first organic film layer; or, all of the second inorganic grooves may be located between the second contact pad group and the first organic film layer. Alternatively, the first inorganic film layer may have multiple second inorganic grooves in the first border region, with all of the multiple second inorganic grooves located between the second contact pad group and the first organic film layer; or, at least one of the multiple second inorganic grooves may have a portion located between the second contact pad group and the first organic film layer.

[0092] In some examples, the first inorganic film layer may have a first inorganic groove and a second inorganic groove in the first border region, or it may have a first inorganic groove and multiple second inorganic grooves, or it may have multiple first inorganic grooves and a second inorganic groove, or it may have multiple first inorganic grooves and multiple second inorganic grooves.

[0093] The display panel provided in this embodiment, by setting a first inorganic groove that separates the first contact pad group and the first organic film layer or a second inorganic groove that separates the second contact pad group and the first organic film layer in the first signal access area, can block the peeling of the first inorganic film layer after the bonding process of the driver chip by using the inorganic groove. This can effectively avoid the extension of the water and oxygen propagation path, thereby improving the display abnormality caused by the high temperature and high humidity environment during the reliability test and ensuring the quality of the display panel.

[0094] In some exemplary embodiments, at least one first inorganic trench and at least one second inorganic trench can be an integral structure. In some examples, the orthographic projection of the integral structure of the at least one first inorganic trench and the at least one second inorganic trench onto the substrate can surround the orthographic projection of the first organic film layer onto the substrate. This example, by setting the first and second inorganic trenches as an integral structure, allows the peeling of the first inorganic film layer in the first signal access area after the driver chip bonding process to stop at the inorganic trench location, thereby blocking the water and oxygen propagation path and ensuring the quality of the display panel.

[0095] In some exemplary embodiments, the orthographic projection of at least one first inorganic groove onto the substrate may surround the orthographic projection of the first contact pad group onto the substrate; the orthographic projection of at least one second inorganic groove onto the substrate may surround the orthographic projection of the second contact pad group onto the substrate. This example, by setting the first inorganic groove to surround the first contact pad group and the second inorganic groove to surround the second contact pad group, ensures that the peeling of the first inorganic film layer in the first signal access area after the driver chip bonding process stops at the inorganic groove location, thereby blocking the water and oxygen propagation path and ensuring the quality of the display panel.

[0096] The following examples illustrate the solution of this embodiment.

[0097] Figure 5 This is a plan view of the first signal access area according to at least one embodiment of the present invention. Figure 6 for Figure 5 A partial cross-sectional view along the QQ' direction. Figure 5 The diagram illustrates a portion of the structure of the first signal access area. In some examples, such as... Figure 5As shown, the first signal access area B131 may be provided with a first contact pad group 31, a second contact pad group 32, and a test unit 35. The first contact pad group 31, the test unit 35, and the second contact pad group 32 may be arranged sequentially along the direction away from the display area in the first direction D1. The test unit 35 may include multiple test pins 351 and multiple test circuits (such as... Figure 6 The test circuit 352 shown is illustrated. Multiple test circuits can be located on one side of multiple test pins 351 near the first contact pad group 31. The multiple test pins 351 can be arranged in at least one row along the second direction D2. This embodiment is not limited in this respect.

[0098] In some examples, such as Figure 6 As shown, the substrate 100 may include: a first flexible material layer 1001, a first barrier layer 1002, a second flexible material layer 1003, and a second barrier layer 1004 stacked together. The materials of the first flexible material layer 1001 and the second flexible material layer 1003 may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first barrier layer 1002 and the second barrier layer 1004 may be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0099] In some examples, such as Figure 5 As shown, the first contact pad group 31 may include a plurality of first contact pads 311 and a plurality of invalid contact pads 312, wherein the plurality of invalid contact pads 312 may be located in the middle of the plurality of first contact pads 311 along the second direction D2. The plurality of first contact pads 311 and the plurality of invalid contact pads 312 may be arranged in three rows, for example, and each row may include a plurality of first contact pads 311 and a plurality of invalid contact pads 312 arranged along the second direction D2.

[0100] In some examples, such as Figure 5 As shown, a first alignment mark 601 and a second alignment mark 602 can be provided on both sides of the first contact pad group 31 along the second direction D2. A third alignment mark 603 and a fourth alignment mark 604 can be provided on both sides of the second contact pad group 32 along the second direction D2. The first alignment marks 601 to the fourth alignment marks 604 can be electrode blocks located in the source and drain metal layers. The first alignment marks 601 and the third alignment marks 603 can be aligned along the first direction D1, for example, and the second alignment marks 602 and the fourth alignment marks 604 can be aligned along the first direction D1, for example. The first alignment marks 601, the second alignment marks 602, the third alignment marks 603, and the fourth alignment marks 604 can be configured to play an alignment role during the bonding process of the driver chip, which can help ensure the bonding effect of the driver chip.

[0101] In some examples, such as Figure 5 and Figure 6 As shown, the first organic film layer 61 disposed within the first signal access region B131 may include multiple organic bumps, such as a first organic bump 611, a second organic bump 612, a third organic bump 613, and a fourth organic bump 614. The orthographic projection of the first inorganic film layer 51 in the first signal access region B131 onto the substrate can cover the orthographic projection of the first organic film layer 61 onto the substrate. The first organic bump 611, the second organic bump 612, and the third organic bump 613 can be disposed in the same layer, for example, in the same layer as the first planarization layer of the display region; the fourth organic bump 614 can be located on the side of the third organic bump 613 away from the substrate, for example, in the same layer as the second planarization layer of the display region. For example, the second planarization layer and the fourth organic bump can be fabricated using a halftone mask process, where the second planarization layer corresponds to the non-transmissive area in the halftone mask process, and the fourth organic bump corresponds to the semi-transmissive area in the halftone mask process, such that the thickness of the fourth organic bump can be less than the thickness of the second planarization layer of the display region.

[0102] In some examples, such as Figure 5 and Figure 6 As shown, the first organic bump 611 and the second organic bump 612 can be arranged along the arrangement direction of the multiple test circuits, for example, they can be arranged sequentially along the second direction D2. The orthogonal projection of the first organic bump 611 and the second organic bump 612 onto the substrate can at least partially overlap with the orthogonal projection of the multiple test circuits 352 of the test unit 35 onto the substrate. The test circuit 352 can include multiple transistors. The orthogonal projection of the first organic bump 611 and the second organic bump 612 onto the substrate can cover the traces and electrodes of the multiple test circuits 352 located in the first source / drain metal layer.

[0103] In some examples, such as Figure 5 and Figure 6 As shown, the test pin 351 may include a first pin layer 3511 and a second pin layer 3512 stacked sequentially. The first pin layer 3511 may be located on the side of the second pin layer 3512 closer to the substrate 100. The second pin layer 3512 may contact the first pin layer 3511 through a via formed by the third organic bump 613. The orthogonal projection of the fourth organic bump 614 onto the substrate may cover the orthogonal projection of the second pin layer 3512 onto the substrate. For example, the first pin layer 3511 may be disposed on the same layer as the first source / drain metal layer of the display area, and the second pin layer 3512 may be disposed on the same layer as the second source / drain metal layer of the display area.

[0104] In some examples, such as Figure 5 and Figure 6As shown, the orthographic projections of the third organic bump 613 and the fourth organic bump 614 onto the substrate may at least partially overlap with the orthographic projections of the plurality of test pins 351 of the test unit 35 onto the substrate. For example, the orthographic projection of the fourth organic bump 614 onto the substrate may cover the orthographic projections of the plurality of test pins 351 onto the substrate.

[0105] In some examples, such as Figure 6 As shown, the first contact pad 311 may include a first sub-pad 3111, a second sub-pad 3112, a third sub-pad 3113, and a fourth sub-pad 3114 stacked sequentially. The second sub-pad 3111 can be connected to the first sub-pad 3111 through a via formed in the composite inorganic insulating layer (e.g., including a stacked second gate insulating layer 102 and an interlayer insulating layer 103). The third sub-pad 3113 can be in direct contact with the second sub-pad 3112. The fourth sub-pad 3114 can be in contact with the third sub-pad 3113 through a via formed in the first inorganic film layer 51. For example, the first sub-pad 3111 can be disposed in the same layer as the first gate metal layer of the display area, the second sub-pad 3112 can be disposed in the same layer as the first source / drain metal layer of the display area, the third sub-pad 3113 can be disposed in the same layer as the second source / drain metal layer of the display area, and the fourth sub-pad 3114 can be disposed in the same layer as the second touch conductive layer of the display area.

[0106] In some examples, such as Figure 6 As shown, the second contact pad 321 may include a fifth sub-pad 3211, a sixth sub-pad 3212, a seventh sub-pad 3213, and an eighth sub-pad 3214 stacked sequentially. The sixth sub-pad 3212 can be connected to the fifth sub-pad 3211 through a via formed in the composite inorganic insulating layer (e.g., including a stacked second gate insulating layer 102 and an interlayer insulating layer 103). The seventh sub-pad 3213 can be in direct contact with the sixth sub-pad 3212. The eighth sub-pad 3214 can be in contact with the seventh sub-pad 3213 through a via formed in the first inorganic film layer 51. For example, the fifth sub-pad 3211 can be disposed in the same layer as the first gate metal layer of the display area, the sixth sub-pad 3212 can be disposed in the same layer as the first source / drain metal layer of the display area, the seventh sub-pad 3213 can be disposed in the same layer as the second source / drain metal layer of the display area, and the eighth sub-pad 3214 can be disposed in the same layer as the second touch conductive layer of the display area.

[0107] In some examples, the first inorganic film layer 51 in the first border region may include a stacked touch buffer layer and an inter-touch insulating layer. In other examples, the first inorganic film layer 51 may include only the inter-touch insulating layer or the touch buffer layer.

[0108] In some examples, such as Figure 5 and Figure 6As shown, the first inorganic film layer 51 may have a first inorganic groove 511 and a second inorganic groove 512 in the first signal access area B131. The first inorganic groove 511 and the second inorganic groove 512 may expose the surface of the composite inorganic insulating layer. At least a portion of the first inorganic groove 511 may be located between the first contact pad group 31 and the first organic film layer 61, and at least a portion of the second inorganic groove 512 may be located between the second contact pad group 32 and the first organic film layer 61. For example, the first inorganic groove 511 may include a first portion 5111 extending along the second direction D2, and a second portion 5112 and a third portion 5113 extending along the first direction D1, with the second portion 5112 and the third portion 5113 respectively connecting to the two ends of the first portion 5111; the second inorganic groove 512 may include a fourth portion 5121 extending along the second direction D2, and a fifth portion 5122 and a sixth portion 5123 extending along the first direction D1, with the fifth portion 5122 and the sixth portion 5123 respectively connecting to the two ends of the fourth portion 5121. The first portion 5111 of the first inorganic groove 511 may be located between the first organic film layer 61 and the first contact pad group 31, and the fourth portion 5121 of the second inorganic groove 512 may be located between the first organic film layer 61 and the second contact pad group 32. The orthographic projection of the first portion 5111 of the first inorganic groove 511 and the fourth portion 5121 of the second inorganic groove 512 onto the substrate may be a straight line segment extending along the second direction D2.

[0109] In some examples, the widths of the first portion 5111, the second portion 5112, and the third portion 5113 of the first inorganic groove 511 may be approximately the same; the widths of the fourth portion 5121, the fifth portion 5122, and the sixth portion 5123 of the second inorganic groove 512 may also be approximately the same. The widths of the first portion 5111 and the fourth portion 5121 of the first inorganic groove 511 may also be approximately the same. In this example, the width of the inorganic groove refers to its length in a plane parallel to the substrate, along a direction perpendicular to the extension of the inorganic groove.

[0110] In some examples, the minimum distance between the first portion 5111 of the first inorganic tank 511 and the first contact pad group 31 can be the same as the minimum distance between the first portion 5111 of the first inorganic tank 511 and the first organic film layer 61. Similarly, the minimum distance between the fourth portion 5121 of the second inorganic tank 512 and the second contact pad group 32 can be the same as the minimum distance between the fourth portion 5121 of the second inorganic tank 512 and the first organic film layer 61.

[0111] In some examples, the first inorganic trench 511 and the second inorganic trench 512 can be an integral structure. For example, the second portion 5112 of the first inorganic trench 511 and the fifth portion 5122 of the second inorganic trench 512 can be connected, and the third portion 5113 of the first inorganic trench 511 and the sixth portion 5123 of the second inorganic trench 512 can be connected. The orthographic projection of the integral structure of the second portion 5112 of the first inorganic trench 511 and the fifth portion 5122 of the second inorganic trench 512 onto the substrate can be a straight line segment extending along the first direction D1, and the orthographic projection of the integral structure of the third portion 5113 of the first inorganic trench 511 and the sixth portion 5123 of the second inorganic trench 512 onto the substrate can be a straight line segment extending along the first direction D1. The orthographic projection of the integral structure of the first inorganic trench 511 and the second inorganic trench 512 onto the substrate can be approximately rectangular and can surround the orthographic projection of the first organic film layer 61 and the test unit 35 onto the substrate.

[0112] In some examples, along a direction away from the display area, the first organic bump 611 and the second organic bump 612 are both adjacent to the first portion 5111 of the first inorganic groove 511; the third organic bump 613 and the fourth organic bump 614 are both adjacent to the fourth portion 5121 of the second inorganic groove 512. For example, the minimum distance along the first direction D1 between the first organic bump 611 and the first portion 5111 of the first inorganic groove 511 can be less than the minimum distance along the first direction D1 between the first organic bump 611 and the third organic bump 613. The minimum distance along the first direction D1 between the third organic bump 613 and the fourth portion 5121 of the second inorganic groove 512 can also be less than the minimum distance along the first direction D1 between the first organic bump 611 and the third organic bump 613.

[0113] In this example, by setting up a first inorganic slot and a second inorganic slot to surround the first organic film layer and the test unit in the first signal access area, the peeling of the first inorganic film layer caused by the contact between the first organic film layer and the driver chip during the bonding process of the driver chip can stop at the location of the first inorganic slot and the second inorganic slot. This can block the water and oxygen propagation path caused by the peeling of the first inorganic film layer, and can ensure the signal transmission of the first contact pad group and the second contact pad group. This can improve the display abnormality caused by the high temperature and high humidity environment during the reliability test and ensure the quality of the display panel.

[0114] Figure 7 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention. In some examples, such as... Figure 7As shown, the first inorganic film layer 51 may have two first inorganic grooves 511a and 511b and two second inorganic grooves 512a and 512b in the first signal access area B131. The first inorganic grooves 511a and 512a may be an integral structure; the first inorganic grooves 511b and 512b may also be an integral structure. The integral structure of the first inorganic grooves 511b and 512b may surround the periphery of the integral structure of the first inorganic grooves 511a and 512a; the orthographic projection of the integral structure of the first inorganic grooves 511a and 512a onto the substrate may surround the orthographic projection of the first organic film layer 61 and the test unit 35 onto the substrate.

[0115] In some examples, such as Figure 7 As shown, the minimum distance between the first inorganic grooves 511a and 511b can be equal to the minimum distance between the second inorganic grooves 512a and 512b. The minimum distance between the first inorganic groove 511a and the first organic film layer 61 can be equal to the minimum distance between the first inorganic groove 511b and the first contact pad group 31. The minimum distance between the second inorganic groove 512a and the first organic film layer 61 can be equal to the minimum distance between the second inorganic groove 512b and the second contact pad group 32.

[0116] In this example, by setting two sets of first and second inorganic slots to surround the first organic film layer and the test unit within the first signal access area, the peeling of the first inorganic film layer caused by contact between the first organic film layer and the driver chip during the driver chip bonding process can stop at the location of the first and second inorganic slots. This blocks the water and oxygen propagation path caused by the peeling of the first inorganic film layer, ensuring signal transmission between the first and second contact pad groups. This, in turn, improves display anomalies caused by the high temperature and humidity environment during reliability testing, ensuring the quality of the display panel. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0117] Figure 8 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention. In some examples, such as... Figure 8As shown, the first inorganic film layer 51 may have two first inorganic grooves 511a and 511b and two second inorganic grooves 512a and 512b in the first signal access area B131. The first inorganic grooves 511a and 512a may be an integral structure. The first inorganic groove 511b may be located on the side of the first inorganic groove 511a closer to the first contact pad 31, and the second inorganic groove 512b may be located on the side of the second inorganic groove 512a closer to the second contact pad 32. The orthographic projection of the first inorganic grooves 511b and 512b onto the substrate may be a straight line segment extending along the second direction D2. The orthographic projection of the integral structure of the first inorganic grooves 511a and 512a onto the substrate may surround the orthographic projection of the first organic film layer 61 and the test unit 35 onto the substrate. In other examples, the first inorganic groove 511b may be located on the side of the first inorganic groove 511a away from the first contact pad 31, or the second inorganic groove 512b may be located on the side of the second inorganic groove 512a away from the second contact pad 32.

[0118] In this example, by setting a first inorganic groove and a second inorganic groove to surround the first organic film layer and the test unit within the first signal access area, and by using a first inorganic groove and a second inorganic groove that separate the first organic film layer and the first contact pad group along the first direction D1, the peeling of the first inorganic film layer caused by the contact between the first organic film layer and the driver chip during the driver chip bonding process can stop at the location of the first inorganic groove and the second inorganic groove. This can block the water and oxygen propagation path caused by the peeling of the first inorganic film layer, ensuring the signal transmission of the first contact pad group and the second contact pad group, thereby improving the display abnormalities caused by the high temperature and high humidity environment during the reliability test and ensuring the quality of the display panel. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0119] Figure 9 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention. In some examples, such as... Figure 9As shown, the first inorganic film layer 51 may have three first inorganic grooves 511a, 511b and 511c, and three second inorganic grooves 512a, 512b and 512c in the first signal access region B131. The first inorganic grooves 511a and 512a may be an integral structure; the first inorganic grooves 511b and 512b may be an integral structure; and the first inorganic grooves 511c and 512c may be an integral structure. The integrated structure of the first inorganic tank 511c and the second inorganic tank 512c can surround the periphery of the integrated structure of the first inorganic tank 511b and the second inorganic tank 512b; the integrated structure of the first inorganic tank 511b and the second inorganic tank 512b can surround the periphery of the integrated structure of the first inorganic tank 511a and the second inorganic tank 512a; the orthographic projection of the integrated structure of the first inorganic tank 511a and the second inorganic tank 512a on the substrate can surround the orthographic projection of the first organic film layer 61 and the test unit 35 on the substrate.

[0120] In some examples, such as Figure 9 As shown, the minimum distance between adjacent first inorganic tanks can be the same, and the minimum distance between adjacent second inorganic tanks can be the same. For example, the minimum distance between first inorganic tanks 511a and 511b can be equal to the minimum distance between first inorganic tanks 511b and 511c; the minimum distance between second inorganic tanks 512a and 512b can be equal to the minimum distance between second inorganic tanks 512b and 512c. The minimum distance between first inorganic tank 511a and first organic film layer 61 can be equal to the minimum distance between first inorganic tank 511c and first contact pad group 31. The minimum distance between second inorganic tank 512a and first organic film layer 61 can be equal to the minimum distance between second inorganic tank 512c and second contact pad group 32.

[0121] In this example, by setting three sets of first inorganic slots and second inorganic slots to surround the first organic film layer and the test unit within the first signal access area, the peeling of the first inorganic film layer caused by contact between the first organic film layer and the driver chip during the driver chip bonding process can stop at the location of the first inorganic slots and second inorganic slots. This blocks the water and oxygen propagation path caused by the peeling of the first inorganic film layer, ensuring signal transmission between the first contact pad group and the second contact pad group. This improves display anomalies caused by the high temperature and high humidity environment during reliability testing, thus guaranteeing the quality of the display panel. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0122] Figure 10 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention. In some examples, such as... Figure 10As shown, the first inorganic film layer 51 may have a first inorganic groove 511 and a second inorganic groove 512 in the first signal access area B131. The first inorganic groove 511 and the second inorganic groove 512 may be an integral structure, and the orthographic projection of the integral structure of the first inorganic groove 511 and the second inorganic groove 512 onto the substrate may surround the orthographic projection of the first organic film layer 61 and the test unit 35 onto the substrate. The minimum distance L1 between the first inorganic groove 511 and the first contact pad group 31 may be different from the minimum distance L3 between the first inorganic groove 511 and the first organic film layer 61; for example, the minimum distance L1 between the first inorganic groove 511 and the first contact pad group 31 may be less than the minimum distance L3 between the first inorganic groove 511 and the first organic film layer 61. The minimum distance L2 between the second inorganic groove 512 and the second contact pad group 32 may be different from the minimum distance L4 between the second inorganic groove 512 and the first organic film layer 61; for example, the minimum distance L2 between the second inorganic groove 512 and the second contact pad group 32 may be less than the minimum distance L4 between the second inorganic groove 512 and the first organic film layer 61. However, this embodiment is not limited in this respect. In other examples, L1 may be equal to L3, and L2 may be different from L4; or, L1 may be different from L3, and L2 may be equal to L4; or, L1 may be greater than L3, and L2 may be greater than L4.

[0123] In this example, by setting up a first inorganic slot and a second inorganic slot to surround the first organic film layer and the test unit within the first signal access area, and by adjusting the minimum distance difference between the first inorganic slot and the first contact pad group and the first organic film layer, as well as adjusting the minimum distance difference between the second inorganic slot and the second contact pad group and the first organic film layer, the stress at the edge of the inorganic slot can be improved, and the water and oxygen propagation path caused by the peeling of the first inorganic film layer can be blocked. This improves the display abnormalities caused by the high temperature and high humidity environment during the reliability test, ensuring the quality of the display panel. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0124] Figure 11 This is another planar schematic diagram of the first signal access area according to at least one embodiment of the present invention. In some examples, such as... Figure 11As shown, the first inorganic film layer 51 may have a first inorganic groove 511 and a second inorganic groove 512 in the first signal access area B131. The orthographic projection of the first inorganic groove 511 onto the substrate may surround the orthographic projection of the first contact pad group 31 onto the substrate, and the orthographic projection of the second inorganic groove 512 onto the substrate may surround the orthographic projection of the second contact pad group 512 onto the substrate. The orthographic projections of the first inorganic groove 511 and the second inorganic groove 512 onto the substrate may be approximately rectangular annular. The first inorganic groove 511 may separate the first organic film layer 61 and the first contact pad group 31 along the first direction D1, and the second inorganic groove 512 may separate the first organic film layer 61 and the second contact pad group 32 along the first direction D1.

[0125] In this example, a first inorganic groove surrounds the first contact pad group to separate the first contact pad group and the first organic film layer, and a second inorganic groove surrounds the second contact pad group to separate the second contact pad group and the second organic film layer. This ensures that during the bonding process of the driver chip, the peeling of the first inorganic film layer caused by contact between the first organic film layer and the driver chip stops at the locations of the first and second inorganic grooves. This blocks the water and oxygen propagation path caused by the peeling of the first inorganic film layer, thereby improving display anomalies caused by the high temperature and high humidity environment during reliability testing and ensuring the quality of the display panel. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0126] Figure 12 This is a partial planar schematic diagram of the first border region according to at least one embodiment of the present invention. In some examples, such as... Figure 12 As shown, the first inorganic film layer 51 may have a second inorganic groove 512 in the first border region. The orthographic projection of the second inorganic groove 512 onto the substrate may surround the second contact pad group 32, multiple internal bonding lines 34, and the third contact pad group 33 located in the second signal access region B132. The third contact pad group 33 may include multiple third contact pads 331, some of which may be connected to multiple second contact pads 321 within the second contact pad group 32 via the multiple internal bonding lines 34. The second inorganic groove 512 may separate the first organic film layer and the second contact pad group 32 within the first signal access region B131 along a first direction D1. The first border region may also include a second organic film layer 62 located between the first signal access region B131 and the second signal access region B132, the orthographic projection of the second organic film layer 62 onto the substrate may overlap with the orthographic projection portion of the multiple internal bonding lines 34 onto the substrate. The orthographic projection of the second inorganic groove 512 onto the substrate does not overlap with the orthographic projection of the second organic film layer 62 onto the substrate. For example, the second inorganic groove 512 can surround the second organic film layer 62. The second organic film layer 62 can be disposed in the same layer as the fourth organic bump of the first organic film layer.

[0127] This example, by surrounding the second and third contact pad groups with a second inorganic groove, can block the water and oxygen propagation path caused by the peeling of the first inorganic film layer, thereby improving display anomalies caused by the high temperature and humidity environment during reliability testing and ensuring the quality of the display panel. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0128] Figure 13 This is another partial planar schematic diagram of the first signal access area according to at least one embodiment of the present invention. In some examples, such as... Figure 13 As shown, the first inorganic film layer 51 may have a first inorganic groove 511 and a second inorganic groove 512 in the first signal access area. The orthographic projection of the first inorganic groove 511 onto the substrate may cover the orthographic projection of the first contact pad group 31 onto the substrate, and the orthographic projection of the second inorganic groove 512 onto the substrate may cover the orthographic projection of the second contact pad group 32 onto the substrate. The orthographic projections of the first inorganic groove 511 and the second inorganic groove 512 onto the substrate may not overlap with the orthographic projections of the first organic film layer 61 and the test unit 35 onto the substrate.

[0129] This example avoids peeling of the first inorganic film layer during the bonding process of the driver chip by removing the first inorganic film layer in the area where the first contact pad group and the second contact pad group are located. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0130] Figure 14 This is a partial planar schematic diagram of the first border region according to at least one embodiment of the present invention. In some examples, such as... Figure 14 As shown, the first inorganic film layer 51 may have a second inorganic groove 512 in the first frame region. The orthographic projection of the second inorganic groove 512 onto the substrate may cover the orthographic projections of the second contact pad group 32, the multiple internal bonding lines 34, and the third contact pad group 33 located in the second signal access region B132 onto the substrate. The orthographic projection of the second inorganic groove 512 onto the substrate may not overlap with the orthographic projections of the first organic film layer 61 and the test unit 35 onto the substrate.

[0131] This example avoids peeling of the first inorganic film layer during the bonding process of the driver chip by removing the first inorganic film layer in the areas where the second and third contact pad groups are located. Further descriptions of the display panel in this example can be found in the foregoing embodiments and will not be repeated here.

[0132] Figure 15 for Figure 1 A partial cross-sectional view along the RR' direction. In some examples, such as... Figure 1 and Figure 15As shown, the first inorganic film layer 51 has at least one third inorganic groove (e.g., including third inorganic grooves 513a and 513b) extending along the edge of the display panel in the second bezel region of the display panel. The third inorganic groove 513a may be located on the side of the third inorganic groove 513b closer to the display area. The third inorganic grooves 513a and 513b may extend along the edge of the display panel in the left bezel region, the top bezel region, and the right bezel region. The third inorganic grooves 513a and 513b may expose the surface of the third encapsulation layer 143 of the encapsulation structure layer. This example, by providing at least one third inorganic groove near the module cutting channel in the second bezel region, can prevent the first inorganic film layer from peeling off due to excessive stress during display panel cutting. Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0133] Figure 16 This is another schematic diagram of a display panel according to at least one embodiment of the present invention. Figure 17 for Figure 16 A partial cross-sectional view along the PP' direction. In some examples, such as... Figure 16 and Figure 17 As shown, the display panel may include: a display area AA, an opening area CC, a third border area DD surrounding the opening area CC, a first border area B1 located on one side of the display area AA along the first direction D1, and a second border area located on the remaining sides of the display area AA. The display area AA may surround the third border area DD. The opening area CC may correspond to the position of a light sensor such as a camera or an infrared sensor. A first inorganic film layer (e.g., including a touch interlayer insulating layer 152) is provided with a fourth inorganic groove (e.g., including fourth inorganic grooves 514a, 514b, and 514c) surrounding the opening area CC in the third border area DD.

[0134] In some examples, the first trace 651 located in the second touch conductive layer can be connected to the second trace 652 located in the first touch conductive layer via fourth inorganic trenches 514a, 514b, and 514c. The second trace 652 can be connected to the third trace 653 located in the second source / drain metal layer. A first planarization layer 105 and an inorganic insulating layer 200 (e.g., including a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer) can be disposed on the side of the third trace 653 near the substrate 100. The orthographic projection of the fourth inorganic trenches 514a, 514b, and 514c onto the substrate can be annular.

[0135] This example, by providing at least one fourth inorganic groove in the third border area, can prevent the first inorganic film layer from peeling off due to excessive stress. Further descriptions of the display panel in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0136] Figure 18This is a schematic diagram of a display device according to at least one embodiment of the present invention. In some examples, such as... Figure 18 As shown, the display device 91 may include a display panel 910. The display panel 910 may be an OLED display panel. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0137] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0138] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A display panel, characterized in that, include: The substrate includes a display area and a first border area located on one side of the display area, the first border area including at least one first signal access area; Multiple sub-pixels are located in the display area; Multiple data lines are located in the display area and the first border area, and the multiple sub-pixels are connected to the multiple data lines; A first contact pad group and a second contact pad group are located in the first signal access area. The second contact pad group is located on the side of the first contact pad group away from the display area. The first contact pad group includes a plurality of first contact pads, which are connected to the plurality of data lines. The second contact pad group includes a plurality of second contact pads. The plurality of first contact pads and the plurality of second contact pads are configured to be bonded to a driver chip. A first organic film layer is located in the first signal access area. The orthographic projection of the first organic film layer on the substrate does not overlap with the orthographic projections of the first contact pad group and the second contact pad group on the substrate, and is located between the orthographic projections of the first contact pad group and the second contact pad group on the substrate in a direction away from the display area. A first inorganic film layer is located on the side of the first organic film layer away from the substrate, and the first inorganic film layer has at least one of the following in the first border region: at least one first inorganic groove and at least one second inorganic groove. At least a portion of the first inorganic groove is located between the first contact pad group and the first organic film layer in the orthographic projection of the substrate. At least a portion of the at least one second inorganic groove is located between the second contact pad assembly and the first organic film layer in the orthographic projection of the substrate.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the first inorganic film layer onto the substrate covers the orthographic projection of the first organic film layer onto the substrate.

3. The display panel according to claim 1, characterized in that, The display panel further includes: a test unit located in the first signal access area, the test unit being located between the first contact pad group and the second contact pad group in a direction away from the display area; the orthographic projection of the test unit on the substrate at least partially overlaps with the orthographic projection of the first organic film layer on the substrate.

4. The display panel according to claim 3, characterized in that, The test unit includes: multiple test pins and multiple test circuits, wherein the multiple test pins are located on the side of the multiple test circuits away from the first contact pad group; The orthographic projection of the first organic film layer on the substrate at least partially overlaps with the orthographic projections of the plurality of test pins and the plurality of test circuits on the substrate.

5. The display panel according to claim 4, characterized in that, The first organic film layer includes: a first organic bump and a second organic bump; the first organic bump and the second organic bump are disposed in the same layer, and the first organic bump and the second organic bump are disposed along the arrangement direction of the plurality of test circuits; the orthographic projection of the first organic bump and the second organic bump on the substrate at least partially overlaps with the orthographic projection of the plurality of test circuits on the substrate; along the direction away from the display area, the first organic bump and the second organic bump are both adjacent to the first inorganic groove.

6. The display panel according to claim 5, characterized in that, The first organic film layer further includes: a third organic bump and a fourth organic bump, wherein the third organic bump is disposed in the same layer as the first organic bump, and the fourth organic bump is located on the side of the third organic bump away from the substrate; the orthographic projections of the third organic bump and the fourth organic bump on the substrate at least partially overlap with the orthographic projections of the plurality of test pins on the substrate; along the direction away from the display area, both the third organic bump and the fourth organic bump are adjacent to the second inorganic groove.

7. The display panel according to claim 6, characterized in that, The test pins include: a first pin layer and a second pin layer stacked sequentially, the first pin layer being located on the side of the second pin layer closer to the substrate; the second pin layer being in contact with the first pin layer through a via formed by the third organic bump, and the fourth organic bump being located on the side of the second pin layer away from the substrate.

8. The display panel according to claim 1, characterized in that, The at least one first inorganic tank and the at least one second inorganic tank are an integral structure.

9. The display panel according to claim 8, characterized in that, The orthographic projection of the integral structure of the at least one first inorganic groove and the at least one second inorganic groove on the substrate surrounds the orthographic projection of the first organic film layer on the substrate.

10. The display panel according to claim 1, characterized in that, The orthographic projection of the first inorganic groove on the substrate covers the orthographic projection of the first contact pad assembly on the substrate, and the orthographic projection of the second inorganic groove on the substrate covers the orthographic projection of the second contact pad assembly on the substrate.

11. The display panel according to claim 1, characterized in that, The first inorganic film layer has a plurality of first inorganic grooves and a plurality of second inorganic grooves in the first frame area; along the direction away from the display area, the minimum distance between adjacent first inorganic grooves is the same, and the minimum distance between adjacent second inorganic grooves is the same.

12. The display panel according to claim 1, characterized in that, The orthographic projection of the at least one first inorganic groove on the substrate surrounds the orthographic projection of the first contact pad assembly on the substrate; The orthographic projection of the at least one second inorganic groove on the substrate surrounds the orthographic projection of the second contact pad assembly on the substrate.

13. The display panel according to claim 1, characterized in that, The first border area further includes: a second signal access area located on the side of the at least one first signal access area away from the display area; The display panel further includes: a third contact pad group located in the second signal access area, the third contact pad group including a plurality of third contact pads, a portion of the plurality of third contact pads being connected to the plurality of second contact pads through a plurality of internal binding lines; The orthographic projection of the at least one second inorganic groove on the substrate surrounds the orthographic projections of the second contact pad group, the third contact pad group, and the plurality of internal bonding lines on the substrate; or, the orthographic projection of the at least one second inorganic groove on the substrate covers the orthographic projections of the second contact pad group, the third contact pad group, and the plurality of internal bonding lines on the substrate.

14. The display panel according to claim 1, characterized in that, Along the direction away from the display area, the minimum distance between the first inorganic groove and the first contact pad group is different from the minimum distance between the first inorganic groove and the first organic film layer.

15. The display panel according to claim 1, characterized in that, Along the direction away from the display area, the minimum distance between the second inorganic groove and the second contact pad group is different from the minimum distance between the second inorganic groove and the first organic film layer.

16. The display panel according to claim 1, characterized in that, The substrate further includes: a second border region located on the remaining sides of the display area; The first inorganic film layer has at least one third inorganic groove extending along the edge of the display panel in the second frame region, the third inorganic groove being close to the edge of the display panel.

17. The display panel according to claim 1, characterized in that, The substrate further includes: an opening area and a third border area that at least partially surrounds the opening area, the display area that at least partially surrounds the third border area; the first inorganic film layer has at least one fourth inorganic groove surrounding the opening area in the third border area.

18. The display panel according to claim 1, characterized in that, The display panel further includes: a first touch conductive layer and a second touch conductive layer; the first touch conductive layer is located on the side of the plurality of sub-pixels away from the substrate, and the second touch conductive layer is located on the side of the first touch conductive layer away from the substrate; The first inorganic film layer includes at least one of the following: a touch interlayer insulating layer located between the first touch conductive layer and the second touch conductive layer; a touch buffer layer located on the side of the first touch conductive layer near the substrate.

19. The display panel according to claim 1, characterized in that, The first contact pad includes a first sub-pad, a second sub-pad, a third sub-pad, and a fourth sub-pad stacked sequentially; the second contact pad includes a fifth sub-pad, a sixth sub-pad, a seventh sub-pad, and an eighth sub-pad stacked sequentially; the fourth sub-pad contacts the third sub-pad through a through-hole in the first inorganic film layer, and the eighth sub-pad contacts the seventh sub-pad through a through-hole in the first inorganic film layer.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

Images