Pixel sensor and pixel sensor array

Abstract

The utility model provides a pixel sensor and a pixel sensor array. A plurality of vertically aligned layers including a plurality of diffusive structures at photodiodes higher than the pixel sensors. The diffusive structure of each layer disperses incident light via refraction to provide a greater amount of dispersion of incident light than the diffusive structure of a single layer. For example, a top layer of the diffusing structure may disperse incident light via refraction, and a bottom layer of the diffusing structure may further disperse incident light dispersed from the top layer of the diffusing structure before the incident light enters a photodiode of the pixel sensor. This increases the length of the path of propagation of the photons of the incident light, thereby increasing the likelihood that the photons are absorbed in the photodiode. Accordingly, the plurality of vertically arranged layers of the diffusion structure may further increase quantum efficiency (QE) of the pixel sensor.

Description

Technical Field

[0001] This disclosure relates to pixel sensors and pixel sensor arrays with diffuse structures. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors use light-sensitive CMOS circuitry to convert light energy (e.g., photons) into electrical energy. The light-sensitive CMOS circuitry may include photodiodes formed in a silicon substrate. When a photodiode is exposed to light, a charge (called photocurrent) is generated within it. The photodiode may be coupled to a switching transistor, which samples the charge in the photodiode. Color can be determined by placing a filter over the light-sensitive CMOS circuitry. Utility Model Content

[0003] Some embodiments of this disclosure provide a pixel sensor comprising: a photodiode, a first plurality of diffuse structures, and a second plurality of diffuse structures. The photodiode is located in a substrate. The first plurality of diffuse structures extend into a portion of the substrate above the photodiode. The second plurality of diffuse structures extend above the first plurality of diffuse structures. The second plurality of diffuse structures extend into a dielectric layer above the substrate.

[0004] Some embodiments of this disclosure provide a pixel sensor array comprising: a pixel sensor, a first plurality of diffuse structures, a deep trench isolation (DTI) structure, a second plurality of diffuse structures, and a grid structure. The pixel sensor includes a photodiode within a substrate. The first plurality of diffuse structures extend into a portion of the substrate above the photodiode. The deep trench isolation (DTI) structures extend into the substrate and laterally surround at least a portion of the first plurality of diffuse structures and the photodiode. The second plurality of diffuse structures extend above the first plurality of diffuse structures. The second plurality of diffuse structures extend into a dielectric layer above the substrate. The grid structure extends above the deep trench isolation structure and laterally surrounds the second plurality of diffuse structures.

[0005] Some embodiments of this disclosure provide a pixel sensor comprising: a photodiode, a first plurality of diffuse structures, a second plurality of diffuse structures, and a third plurality of diffuse structures. The photodiode is located in a substrate. The first plurality of diffuse structures extend into a portion of the substrate above the photodiode. The second plurality of diffuse structures extend into a dielectric layer above the substrate above the first plurality of diffuse structures. The third plurality of diffuse structures extend into another dielectric layer above the dielectric layer above the dielectric layer. Attached Figure Description

[0006] Several aspects of this disclosure can be described in detail below and in conjunction with the appended... Figure 1 For best understanding, please read carefully. Note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be increased or decreased arbitrarily for clarity of discussion.

[0007] Figure 1 This is a schematic diagram of an embodiment of the pixel sensor described herein;

[0008] Figures 2A to 2C This is a schematic diagram of an embodiment of the image sensor device described herein;

[0009] Figures 3A to 3G These are schematic diagrams of multiple embodiments of a plurality of pixel sensors, which may be included in a pixel sensor array of an image sensor device described herein;

[0010] Figures 4A to 4I These are schematic diagrams of multiple embodiments of a plurality of pixel sensors, which may be included in a pixel sensor array of an image sensor device described herein;

[0011] Figures 5A to 5G These are schematic diagrams of multiple embodiments of a plurality of pixel sensors, which may be included in a pixel sensor array of an image sensor device described herein;

[0012] Figures 6A to 6E This is a schematic diagram of an example embodiment of forming the circuit die (or a portion thereof) described herein;

[0013] Figures 7A to 7F This is a schematic diagram of an example embodiment of forming a sensor die (or a portion thereof) as described herein;

[0014] Figure 8A and Figure 8B This is a schematic diagram illustrating an example embodiment of an image sensor device (or a portion thereof) described herein;

[0015] Figures 9A to 9I This is a schematic diagram of an example embodiment of a pixel sensor array that forms a sensor die (or a portion thereof) as described herein;

[0016] Figures 10A to 10E The figure is a schematic diagram of an example embodiment of a pixel sensor array forming a sensor die (or a portion thereof) as described herein;

[0017] Figures 11A to 11E This is a schematic diagram of an example embodiment of a pixel sensor array that forms a sensor die (or a portion thereof) as described herein;

[0018] Figures 12A to 12C This is a schematic diagram of an example embodiment of a pixel sensor array that forms a sensor die (or a portion thereof) as described herein;

[0019] Figure 13 This is a flowchart of an embodiment process associated with forming the pixel sensor array described herein.

[0020] [Symbol Explanation]

[0021] 100: Pixel sensor

[0022] 102: Power supply voltage

[0023] 104: Electrical grounding

[0024] 106: Sensing Area

[0025] 108: Control Circuit Area

[0026] 110: Photocurrent

[0027] 112: Photodiode

[0028] 114: Transfer Gate

[0029] 116: Transmission Voltage

[0030] 118: Reset Gate

[0031] 120: Reset voltage

[0032] 122: Floating diffusion node

[0033] 124: Source Follower Gate

[0034] 126: Column Select Gate

[0035] 128: Select Voltage

[0036] 130: Output

[0037] 200: Example

[0038] 202: Circuit Wafer

[0039] 204: Sensor Wafer

[0040] 206: Circuit chip

[0041] 208: Sensor chip

[0042] 210: Image sensor device

[0043] 212: Device Layer

[0044] 214: Interconnection Layer

[0045] 216: Device Layer

[0046] 218: Interconnection Layer

[0047] 220: Joint interface

[0048] 222: Pixel sensor array

[0049] 224: Deep trench isolation structure

[0050] 226: Black Level Correction Area

[0051] 228: Joint Pad Area

[0052] 230: Sealing ring area

[0053] 232:Substrate

[0054] 234: Dielectric layer

[0055] 236: Integrated circuit device

[0056] 238: Dielectric layer

[0057] 240: Bonding layer

[0058] 242: Interconnection Structure

[0059] 244: Joint structure

[0060] 246:Substrate

[0061] 248: Dielectric layer

[0062] 250: Shallow trench isolation structure

[0063] 252: Dielectric layer

[0064] 254: Dielectric Pad

[0065] 256: Dielectric layer

[0066] 258: Bonding layer

[0067] 260: Interconnection Structure

[0068] 262: Joint structure

[0069] 264: Buffer layer

[0070] 266: Diffuse Structure

[0071] 268: Passivation layer

[0072] 270: Metal Grid Structure

[0073] 272: Diffuse Structure

[0074] 274: Metal Grid Structure

[0075] 276: Color Filter Area

[0076] 278: Diffuse Structure

[0077] 280: Microlens

[0078] 282: Metal layer

[0079] 284: Dielectric layer

[0080] 286: Dielectric layer

[0081] 288: Dielectric layer

[0082] 290: Dielectric layer

[0083] 292: Joint pad structure

[0084] 294: Joint pad opening

[0085] 300: Example

[0086] 302: concave part

[0087] 304: Partial

[0088] 306: concave part

[0089] 308: Part

[0090] 310: Example

[0091] 312: concave part

[0092] 314: Part

[0093] 316: Example

[0094] 318: Example

[0095] 400: Example

[0096] 402: Example

[0097] 404: Example

[0098] 406: Example

[0099] 408: Example

[0100] 410: Example

[0101] 412: Example

[0102] 414: Example

[0103] 416: Example

[0104] 500: Example

[0105] 502: Example

[0106] 504: Example

[0107] 506: Example

[0108] 600: Example Implementation

[0109] 700: Example Implementation

[0110] 800: Example Implementation

[0111] 900: Example Implementation

[0112] 902: concave part

[0113] 904: Neutral free radical

[0114] 906: Ions

[0115] 908: Materials

[0116] 1000: Example Implementation

[0117] 1002: Protective gasket

[0118] 1100: Example Implementation

[0119] 1200: Example Implementation

[0120] 1300: Process

[0121] 1310: Square

[0122] 1320: Square

[0123] 1330: Square

[0124] 1340: Square

[0125] 1350: Square

[0126] D1: Dimensions

[0127] D2: Dimensions

[0128] D3: Dimensions

[0129] D4: Dimensions

[0130] D5: Size

[0131] D6: Size

[0132] PR: Photoresist layer

[0133] BARC: Bottom Anti-reflective Coating

[0134] x: direction

[0135] y: direction

[0136] z: Direction Detailed Implementation

[0137] The following disclosure provides numerous different implementations or embodiments for carrying out various features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and not limiting. For example, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplification and clarity, and the repetition itself does not imply a relationship between the various implementations and / or configurations discussed.

[0138] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” and similar terms may be used herein. In addition to the directions depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0139] In some cases, a pixel sensor may include multiple diffuse structures (also known as high absorption (HA) structures) between a photodiode and a microlens. These diffuse structures may include multiple portions of a dielectric layer extending into multiple recesses in the substrate of the pixel sensor. Incident light propagating from the microlens toward the photodiode is refracted at the interface between the dielectric layer and the substrate, causing the incident light to travel a less straight path toward the photodiode. Therefore, the diffuse structure distributes the incident light throughout the photodiode and increases the length of the path traveled by photons, thereby increasing the likelihood of photons being absorbed in the photodiode. Accordingly, multiple vertically aligned layers of multiple diffuse structures can increase the quantum efficiency (QE) of the pixel sensor.

[0140] However, the size and / or shape of the diffuse structure may not be optimal for multiple wavelengths of incident light, resulting in poor performance over a wide wavelength range. Therefore, while a diffuse structure can increase the quantum efficiency of a pixel sensor for some wavelengths of incident light, the pixel sensor may suffer from low quantum efficiency performance for other wavelengths.

[0141] In some embodiments described herein, multiple vertically arranged layers comprising diffuse structures are located above the photodiode of the pixel sensor. Each layer's diffuse structure disperses incident light via refraction to provide a greater amount of dispersion of incident light than a single-layer diffuse structure. For example, the top diffuse structure may disperse incident light via refraction, and the bottom diffuse structures may further disperse the dispersed incident light from the top layer before the incident light enters the photodiode of the pixel sensor. This ensures that the incident light diffuses outward across the photodiode and increases the path length of the photons, thereby increasing the likelihood that these photons will be absorbed in the photodiode. Therefore, multiple vertically arranged layers of diffuse structures can further increase the quantum efficiency of the pixel sensor. Furthermore, the size and / or shape of each layer's diffuse structure can be designed to disperse incident light of a specific wavelength, thereby dispersing a wider range of incident light wavelengths to further enhance quantum efficiency.

[0142] Figure 1 This is a schematic diagram of an embodiment of the pixel sensor 100 described herein. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from the front side of a sensor die), a back-side pixel sensor (e.g., a pixel sensor configured to receive photons of light from the back side of a sensor die), and / or another type of pixel sensor. The pixel sensor 100 may be electrically connected to a power supply voltage (V). dd 102 and electrical grounding 104.

[0143] Pixel sensor 100 includes a sensing region 106 configured to sense and / or accumulate incident light (e.g., light directed toward pixel sensor 100). Pixel sensor 100 also includes a control circuitry region 108. Control circuitry region 108 is electrically connected to sensing region 106 and configured to receive photocurrent 110 generated by sensing region 106. Furthermore, control circuitry region 108 is configured to transfer photocurrent 110 from sensing region 106 to downstream circuitry, such as an amplifier or analog-to-digital (AD) converter, or other examples.

[0144] Sensing region 106 includes a photodiode 112. The photodiode 112 absorbs and accumulates multiple photons of incident light and generates a photocurrent 110 based on the absorbed photons. The magnitude of the photocurrent 110 is based on the amount of light collected in the photodiode 112. Therefore, the accumulation of photons in the photodiode 112 results in the accumulation of charge, which represents the intensity or brightness of the incident light (e.g., a larger amount of charge corresponds to a larger intensity or brightness, while a smaller amount of charge corresponds to a lower intensity or brightness).

[0145] Photodiode 112 is electrically connected to the source of a transfer gate 114 in control circuit region 108. The transfer gate 114 is configured to control the transmission of photocurrent 110 from photodiode 112. Photocurrent 110 is supplied from the source to the drain of the transfer gate 114 based on selectively switching the gate of the transfer gate 114. Selective switching of the gate of the transfer gate 114 can be achieved by applying a transfer voltage (V) to the transfer gate 114. tx 116. In some embodiments, the transmission voltage 116 applied to the transmission gate 114 causes a conductive path to be formed between the source and drain of the transmission gate 114, allowing the photocurrent 110 to flow from the source to the drain along the conductive path. In some embodiments, removing the transmission voltage 116 from the transmission gate 114 (or the transmission voltage 116 not existing) causes the conductive path to be removed, preventing the photocurrent 110 from flowing from the source to the drain.

[0146] The control circuit region 108 also includes a reset gate 118. The reset gate 118 is electrically connected to the power supply voltage 102. The reset gate 118 can be controlled via a reset voltage (V). rst120. Transfer gate 114 and reset gate 118 may be electrically coupled to floating diffusion node 122. Before the transfer gate 114 is activated to transfer photocurrent 110 from photodiode 112 to floating diffusion node 122, a reset voltage 120 may be applied to reset gate 118 to pull the drain of transfer gate 114 to a high voltage (e.g., supply voltage 102) to “reset” floating diffusion node 122 (e.g., by draining any remaining charge in floating diffusion node 122).

[0147] Photocurrent 110 can be used to apply a floating diffusion voltage (V fd The photocurrent 110 is directed to the source follower gate 124 of the control circuit region 108. This allows the photocurrent 110 to be observed without removing or releasing it from the floating diffusion node 122. The reset gate 118 can alternatively be used to remove or release the photocurrent 110 from the floating diffusion node 122.

[0148] The source follower gate 124 functions as a high-impedance amplifier for the pixel sensor 100. The source follower gate 124 provides voltage-to-current conversion for the floating diffusion voltage. The output of the source follower gate 124 is electrically connected to the column select gate 126, which is configured to control the flow of photocurrent 110 to external circuitry. The column select gate 126 is controlled by selectively applying a selection voltage (V0). di The gate of column select gate 128 is connected to the gate of column select gate 126. This allows photocurrent 110 to flow to the output 130 of pixel sensor 100.

[0149] As mentioned above, it provides Figure 1 As one embodiment, other embodiments may differ from those described above. Figure 1 The content described.

[0150] Figures 2A to 2C This is a schematic diagram of embodiment 200 of the image sensor device described herein. (As shown in...) Figure 2A As shown, image sensor devices can be formed via bonding circuit wafer 202 and sensor wafer 204. For example, bonding tools can be used to perform bonding operations to bond circuit wafer 202 and sensor wafer 204 using metal-to-metal bonding, dielectric-to-dielectric bonding, and / or another bonding technique. In the bonding operation, a plurality of circuit dies 206 on circuit wafer 202 are bonded to a plurality of associated sensor dies 208 on sensor wafer 204 to form a plurality of image sensor devices 210. These image sensor devices 210 are then diced and packaged. Further processing steps may be performed to form the image sensor devices 210.

[0151] Each image sensor device 210 includes a circuit die 206 and a sensor die 208. The circuit die 206 and the sensor die 208 may be stacked or arranged vertically in the image sensor device 210. The sensor die 208 includes a pixel sensor array, which includes a plurality of pixel sensors 100 or a plurality of portions of a plurality of pixel sensors 100. Specifically, the pixel sensor array includes at least the sensing region 106 of the pixel sensor 100 (and a photodiode 112). Accordingly, the sensor die 208 is primarily configured to sense photons of incident light and convert these photons into a photocurrent 110.

[0152] Circuit die 206 includes circuitry configured to measure, manipulate, and / or otherwise utilize the photocurrent 110. Furthermore, circuit die 206 includes a plurality of transistors of at least a subset of the control circuitry region 108 of the pixel sensor 100. For example, circuit die 206 may include a column select gate 126 of the pixel sensor 100, a source follower gate 124 of the pixel sensor, and / or combinations thereof. This provides increased area for the photodiode 112 on the sensor die 208, allowing the size of the photodiode 112 to be increased to improve the overall performance of the pixel sensor's sensitivity and / or photosensitivity, and / or to allow the size of the pixel sensor 100 to be reduced while maintaining the same size for the photodiode 112.

[0153] As in Figure 2A As further shown, circuit die 206 may include device layer 212 and interconnect layer 214. Device layer 212 may include multiple devices (e.g., multiple transistors) of circuit die 206, and interconnect layer 214 may include multiple interconnects that enable the provision of signals and / or power to and / or from the multiple devices in device layer 212. Sensor die 208 may also include device layer 216 and interconnect layer 218. Device layer 216 may include multiple portions of pixel sensor 100, including photodiode 112, transmission gate 114, and floating diffusion node 122, or other examples. Interconnect layer 218 may include multiple interconnects that enable the provision of signals and / or power to and / or from device layer 216.

[0154] The circuit die 206 and the sensor die 208 may be bonded at a bonding interface 220, which may be included between interconnect layers 214 and 218, and / or may be included in a portion of interconnect layers 214 and / or 218. The bonding interface 220 may include bonding pads, bonding vias, bonding dielectric layers, and / or other bonding structures.

[0155] Figure 2BThis is a top view of an embodiment of the pixel sensor array 222 included on the sensor die 208. The pixel sensor array 222 may be included on the sensor die 208 of the image sensor device 210. (As shown in...) Figure 2B As shown, the pixel sensor array 222 may include a plurality of pixel sensors 100 (or a plurality of portions of a plurality of pixel sensors 100). For example, the pixel sensor array 222 may include a plurality of photodiodes 112 of the plurality of pixel sensors 100. Figure 2B As further shown, the pixel sensors 100 can be arranged in a grid. In some embodiments, the pixel sensors 100 are square (as in...). Figure 2B (As shown in the embodiments). In some embodiments, the pixel sensor 100 includes other shapes, such as rectangles, circles, octagons, rhombuses, and / or other shapes.

[0156] In some embodiments, the size (e.g., width or diameter) of pixel sensor 100 is about 1 micrometer. In some embodiments, the size (e.g., width or diameter) of pixel sensor 100 is less than about 1 micrometer. For example, the width of one or more pixel sensors 100 may be included in the range of about 0.6 micrometers to about 0.7 micrometers. In these embodiments, pixel sensor 100 may be referred to as a sub-micron pixel sensor. Sub-micron pixel sensors can reduce the pixel sensor spacing (e.g., the distance between adjacent pixels) in pixel sensor array 222, which can increase the pixel sensor density in pixel sensor array 222 (which can improve the performance of pixel sensor array 222). However, other values ​​for the range of sizes of pixel sensor 100 are also within the scope of this disclosure.

[0157] Each pixel sensor 100 may be configured to sense a specific wavelength range of incident light associated with a specific color component of the incident light. For example, pixel sensor 100 may be configured to sense a wavelength range associated with the red component of the incident light, and thus may be referred to as a red pixel sensor. As another embodiment, pixel sensor 100 may be configured to sense a wavelength range associated with the blue component of the incident light, and thus may be referred to as a blue pixel sensor. As another embodiment, pixel sensor 100 may be configured to sense a wavelength range associated with the green component of the incident light, and thus may be referred to as a green pixel sensor. In some embodiments, a plurality of pixel sensors 100 are configured to sense a wavelength range associated with the near-infrared (NIR) component of the incident light, and thus may be referred to as near-infrared pixel sensors. Near-infrared pixel sensors may be included in pixel sensor array 222 to improve the low-light performance of image sensor device 210 and / or enable image sensor device 210 to achieve night vision functionality.

[0158] As in Figure 2B As further shown, the plurality of pixel sensors 100 can be electrically and optically isolated via a deep trench isolation (DTI) structure 224 included in the pixel sensor array 222. The deep trench isolation structure 224 may include a plurality of interconnected and intersecting trenches in a substrate, these trenches being filled with one or more types of materials, such as dielectric materials, metallic materials, and / or another type of material. A plurality of trenches of the deep trench isolation structure 224 may be included around a plurality of perimeters of the plurality of pixel sensors 100, such that the deep trench isolation structure 224 forms an isolation grid surrounding the photodiodes 112 of the pixel sensors 100, as shown in Figure 2B As shown in the image.

[0159] Figure 2C A cross-sectional view of the image sensor device 210 is shown. (As shown in...) Figure 2C As shown, the circuit die 206 and the sensor die 208 can be joined at the bonding interface 220, such that the circuit die 206 and the sensor die 208 are stacked or vertically arranged in the z-direction in the image sensor device 210. For example, in Figure 2C As further shown, the image sensor device 210 includes a pixel sensor array 222 (e.g., including pixel sensor 100), a black level correction (BLC) region 226 adjacent to (e.g., horizontally adjacent) the pixel sensor array 222, a bonding pad region 228 adjacent to (e.g., horizontally adjacent) the black level correction region 226, and a sealing ring region 230 adjacent to (e.g., horizontally adjacent) the bonding pad region 228, etc.

[0160] As in Figure 2C As further shown, the image sensor device 210 includes multiple layers, such as device layer 212 and interconnect layer 214 of circuit die 206, and device layer 216 and interconnect layer 218 of sensor die 208. Device layer 212 of circuit die 206 includes a substrate 232 and a dielectric layer 234 above the substrate 232. The substrate 232 may include silicon (Si) (e.g., a silicon substrate), a silicon-containing material, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon-on-insulator (SOI), or another type of semiconductor material. The substrate 232 may include a semiconductor layer, such as a silicon layer. The dielectric layer 234 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, or other examples.

[0161] Multiple integrated circuit devices 236 may be included in and / or on the substrate 232 of the device layer 212. The integrated circuit devices 236 may include one or more application-specific integrated circuit (ASIC) devices, one or more system-on-a-chip (SOC) devices, one or more transistors, and / or one or more other components configured to measure the magnitude of the photocurrent 110 generated by the pixel sensor 100 to determine the light intensity of the incident light, and / or generate images, and / or videos (e.g., digital images, digital videos).

[0162] The interconnect layer 214 of the circuit die 206 may include a dielectric layer 238, a bonding layer 240, a plurality of interconnect structures 242 in the dielectric layer 238, and a plurality of bonding structures 244 in the bonding layer 240. The dielectric layer 238 may include one or more interlayer dielectric (ILD) layers, one or more intermetallic dielectric (IMD) layers, and / or one or more etch stop layers (ESLs), or other examples. The dielectric layer 238 and the bonding layer 240 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, or other examples.

[0163] Multiple interconnect structures 242 may each include wires, trenches, vias, interconnects, metallization layers, and / or other types of conductive structures that electrically connect the integrated circuit device 236 to one or more other regions of the circuit die 206 and / or one or more regions of the sensor die 208, or other examples. Bond structures 244 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 242 and bonding structures 244 may each include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), or other embodiments of conductive materials.

[0164] The device layer 216 of the sensor die 208 includes a substrate 246 and a dielectric layer 248 below the substrate 246. The substrate 246 may include silicon (Si) (e.g., a silicon substrate), a silicon layer, or another type of semiconductor layer, a silicon-containing material, a III-V compound semiconductor material such as gallium arsenide (GaAs), a semiconductor-on-insulator (SOI), or another type of semiconductor material. The dielectric layer 248 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Six N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, or other examples.

[0165] The substrate 246 of the sensor die 208 includes a plurality of photodiodes 112 of a plurality of pixel sensors 100. Each of the plurality of photodiodes 112 may include one or more doped regions of the substrate 246. The substrate 246 may be doped with various types of ions to form a pn junction or PIN junction corresponding to a photodiode 112 (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, the substrate 246 may be doped with n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 112 and doped with p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 112. The photodiode 112 may be configured to absorb a plurality of photons of incident light. Due to the photoelectric effect, the absorption of the plurality of photons causes the photodiode 112 to accumulate charge (photocurrent 110). Here, photons bombard the photodiode 112, which leads to the emission of a plurality of electrons from the photodiode 112. The emission of multiple electrons leads to the formation of electron-hole pairs, in which electrons migrate toward the cathode of photodiode 112, while holes migrate toward the anode, which generates photocurrent 110.

[0166] These photodiodes 112 may be electrically and / or optically isolated from each other via one or more isolation structures in the substrate 246. A shallow trench isolation (STI) structure 250 extends from the bottom side of the substrate 246 (referred to as the front side of the substrate 246) into the substrate 246, and a deep trench isolation structure 224 extends above the shallow trench isolation structure 250 from the top side of the substrate 246 (referred to as the back side of the substrate 246) into the substrate 246. A combination of the plurality of shallow trench isolation structures 250 and the plurality of deep trench isolation structures 224 in the substrate 246 laterally surrounds the plurality of pixel sensors 100 in the substrate 246 and provides electrical and / or optical isolation for these pixel sensors 100 in the substrate 246.

[0167] The deep trench isolation structure 224 may include an elongated structure comprising a dielectric layer 252 and a dielectric pad 254 between the dielectric layer 252 and the substrate 246. The dielectric pad 254 may be a conformal pad included on the sidewalls and bottom surface of the deep trench isolation structure 224 and conforming to the contours of the sidewalls and bottom surface. The dielectric pad may be included as an antireflective coating (ARC) to passivate the substrate 246 near the deep trench isolation structure 224 and / or further promote electrical and / or optical isolation of the pixel sensor 100. The shallow trench isolation structure 250 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y ), and / or silicon oxynitride (SiON), or other examples. The dielectric layer 252 of the deep trench isolation structure 224 may include silicon oxide (SiO2), x For example, SiO2), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), another low-k dielectric material having a dielectric constant of about 3.9 or less, and / or another dielectric material. In some embodiments, the dielectric pad 254 may include a high-k dielectric material, such as silicon nitride (SiO2), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), another low-k dielectric material having a dielectric constant of about 3.9 or less, and / or another dielectric material. x N y For example, Si3N4), hafnium oxide (HfO) x For example, HfO2), aluminum oxide (Al) x O y (e.g., Al3O4), and / or another high-k dielectric material having a dielectric constant greater than about 3.9.

[0168] A deep trench isolation structure 224 is included in the back side of the substrate 246. A plurality of transfer gates 114 for a plurality of pixel sensors 100 are included on the front side of the substrate 246, and a dielectric layer 248 is included above these transfer gates 114. The transfer gates 114 are electrically connected to the interconnect layer 218, which allows an input (e.g., a gate voltage) to be provided to the transfer gates 114 to control the flow of photocurrent 110 from the photodiode 112 to the floating diffusion node 122 (not shown) of the pixel sensor 100.

[0169] Interconnect layer 218 may include dielectric layer 256, bonding layer 258, a plurality of interconnect structures 260 in dielectric layer 256, and a plurality of bonding structures 262 in bonding layer 258. In other embodiments, dielectric layer 256 may include one or more interlayer dielectric layers, one or more intermetallic dielectric layers, and / or one or more etch stop layers, or other examples. Dielectric layer 256 and bonding layer 258 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, or other examples.

[0170] Multiple interconnect structures 260 may each include wires, trenches, vias, interconnects, metallization layers, and / or other types of conductive structures that electrically connect the transmission gate 114 to one or more other regions of the sensor die 208 and / or one or more regions of the circuit die 206, or other examples. Bond structures 262 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 260 and bonding structures 262 may each include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), or other embodiments of conductive materials.

[0171] At the bonding interface 220, bonding layers 240 and 258 may be bonded together (e.g., dielectric to dielectric bonding), and bonding structures 244 and 262 may be bonded together (e.g., metal to metal bonding). Signal and / or power may be provided between circuit die 206 and sensor die 208 via bonding structures 244 and 262.

[0172] On a top side (e.g., back side) above the substrate 246, a buffer layer 264 may be included above the deep trench isolation structure 224 and above the photodiode 112. The buffer layer 264 may comprise an oxide material, such as silicon oxide (SiO2). x Additionally and / or alternatively, silicon nitride (SiN) x ), silicon carbide (SiC) xA dielectric material, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON), or another dielectric material, is used for buffer layer 264. In some embodiments, buffer layer 264 is integrated with dielectric layer 252 of deep trench isolation structure 224. In some embodiments, buffer layer 264 is separated from dielectric layer 252 of deep trench isolation structure 224. In some embodiments, the thickness of buffer layer 264 is included in the range of about 1,000 to about 2,000 angstroms. However, other values ​​used in this range are also within the scope of this disclosure.

[0173] As in Figure 2C As further shown, a diffuser structure 266 may be included at the photodiode 112 above the pixel sensor 100. The diffuser structure 266 is included to diffuse or scatter photons of incident light into the substrate 246 (e.g., via refraction), causing these photons to travel a longer path to the photodiode 112. The longer path traveled by the photons provides more opportunities for these photons to be absorbed in the photodiode 112, thereby increasing the probability of these photons being absorbed. This increases the quantum efficiency of the pixel sensor 100.

[0174] In a top view of the pixel sensor array 222, the diffuse structure 266 may be located within the perimeter of the deep trench isolation structure 224. In a cross-sectional view of the pixel sensor array 222, the diffuse structure 266 may be located between opposing segments of the deep trench isolation structure 224 on opposing sides of the photodiode 112. Each of the plurality of diffuse structures 266 includes a portion or region of the dielectric material of the buffer layer 264, which is included in a plurality of recesses in the back side of the substrate 246 above the photodiode 112. Thus, the diffuse structure 266 extends into the back side of the substrate 246, similar to the deep trench isolation structure 224. However, the depth of the diffuse structure 266 in the substrate 246 is shallower than that of the deep trench isolation structure 224. In some embodiments, the dielectric pad 254 of the deep trench isolation structure 224 is also included in a plurality of recesses (including a plurality of diffuse structures 266) such that the dielectric pad 254 is between a plurality of portions or regions of the dielectric material between the substrate 246 and the diffuse structure 266.

[0175] Because the recesses in the substrate 246 have inclined sidewalls, the bottom surfaces of the multiple diffuse structures 266 can have an approximately V-shaped cross-sectional profile. Alternatively, the bottom surfaces of the diffuse structures 266 can have circular or approximately U-shaped sidewalls. The angles of the sidewalls forming the recesses of the diffuse structures 266, combined with the different refractive indices of the materials of the substrate 246 and the dielectric material of the diffuse structures 266, cause the path of photons entering the substrate 246 to be modified by refraction at the interface between the multiple diffuse structures 266 and the substrate 246.

[0176] The passivation layer 268 may be included above and / or on top of the buffer layer 264. The passivation layer 268 may include one or more dielectric materials and may have the same or similar material composition as the buffer layer 264, or the passivation layer 268 and the buffer layer 264 may include different dielectric materials and / or different material compositions. In some embodiments, the thickness of the passivation layer 268 is greater than the thickness of the buffer layer 264. For example, the thickness of the passivation layer 268 may be about 3 to about 6 times the thickness of the buffer layer 264. However, other values ​​used in this range are also within the scope of this disclosure. In some embodiments, the thickness of the passivation layer is included in the range of about 5000 angstroms to about 7000 angstroms. However, other values ​​used in this range are also within the scope of this disclosure.

[0177] The metal grid structure 270 may be included on the buffer layer 264 and embedded in the passivation layer 268. Multiple segments of the metal grid structure 270 may be located above the deep trench isolation structure 224 and may form the perimeter of multiple photodiodes 112 surrounding the multiple pixel sensors 100. Multiple openings in the metal grid structure 270 may be included above the photodiodes 112 to allow incident light to pass through the metal grid structure 270 and reach the multiple photodiodes 112. The metal grid structure 270 may be formed of a metallic material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof, or other examples.

[0178] Another layer of the diffuser structure 272 may be included above the photodiode 112 of the pixel sensor 100. Including the diffuser structure 272 further diffuses or scatters photons of the incident light within the substrate 246, such that (in conjunction with the diffuser structure 266) photons travel a longer path to reach the plurality of photodiodes 112, further increasing the quantum efficiency of the pixel sensor 100. In a top view of the pixel sensor array 222, the diffuser structure 272 may be located within the perimeter of the metal grid structure 270, and in a cross-sectional view of the pixel sensor array 222, it may be located between opposing segments of the metal grid structure 270 on opposing sides of the photodiode 112. The diffuser structure 272 is included above the diffuser structure 266, such that the diffuser structure 266 and the diffuser structure 272 are vertically aligned above the photodiode 112 (e.g., in the z-direction). Each of the multiple diffuse structures 272 includes a portion or region of the dielectric material of the passivation layer 268, which is included in a plurality of recesses in the top surface of the buffer layer 264.

[0179] Because the multiple recesses in the buffer layer 264 have multiple angled sidewalls, the bottom surface of the diffuse structure 272 can have an approximately V-shaped cross-sectional profile. Alternatively, the bottom surface of the diffuse structure 272 can have circular or approximately U-shaped sidewalls. The angle of the sidewalls forming the recesses of the diffuse structure 272, combined with the different refractive indices of the materials of the buffer layer 264 and the dielectric material of the diffuse structure 272, causes the path of photons entering the substrate 246 to be modified by refraction at the interface between the diffuse structure 272 and the buffer layer 264.

[0180] Another metal grid structure 274 may be included on the passivation layer 268. Multiple segments of the metal grid structure 270 may be located above the metal grid structure 270 and may form the perimeter of the photodiode 112 surrounding the pixel sensor 100. Multiple openings in the metal grid structure 274 may be included above the photodiode 112 to allow incident light to pass through the metal grid structure 274 to reach the photodiode 112. The metal grid structure 274 may be formed of a metallic material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof, or other examples.

[0181] In some embodiments, the metal grid structure 274 is omitted, and only the metal grid structure 270 is included in the pixel sensor array 222. In some embodiments, the metal grid structure 270 is omitted, and only the metal grid structure 274 is included in the pixel sensor array 222. In some embodiments, both the metal grid structure 270 and the metal grid structure 274 are omitted from the pixel sensor array 222.

[0182] Multiple color filter regions 276 of the multiple pixel sensors 100 are included in multiple openings in the metal grid structure 274. The color filter regions 276 may be included above the photodiode 112 of the pixel sensors 100. Each color filter region 276 may be configured to filter incident light to allow incident light of a specific wavelength to pass through the photodiode 112. For example, the color filter region 276 may filter incident light to allow red light to pass through the color filter region 276 to reach the associated photodiode 112. As another embodiment, the color filter region 276 may filter incident light to allow green light to pass through the color filter region 276 to reach the associated photodiode 112. As another embodiment, the color filter region 276 may filter incident light to allow blue light to pass through the color filter region 276 to reach the associated photodiode 112. In some embodiments, the color filter region 276 may be non-discriminative or unfiltered, which may define a white pixel sensor. The non-discriminative or unfiltered color filter region 276 may include a material that allows light of all wavelengths to enter the associated photodiode 112 (e.g., to determine overall brightness to increase the photosensitivity for an image sensor). In some embodiments, the color filter region 276 may be a near-infrared bandpass color filter region 276, which may define a near-infrared pixel sensor. The near-infrared bandpass color filter region 276 may include a material that allows incident light in this portion of the near-infrared wavelength range to pass through the associated photodiode 112 while blocking visible light from passing through.

[0183] Another layer of the diffuser structure 278 may be included above the photodiode 112 of the pixel sensor 100. Including the diffuser structure 278 further diffuses or scatters photons of incident light into the substrate 246, such that (in conjunction with diffuser structures 266 and / or 272) photons travel a longer path to reach the photodiode 112, further increasing the quantum efficiency of the pixel sensor 100. In a top view of the pixel sensor array 222, multiple diffuser structures 278 may be located within the perimeter of the metal grid structure 274, and in a cross-sectional view of the pixel sensor array 222, between opposing segments of the metal grid structure 274 on opposing sides of the photodiode 112. The diffuser structure 278 is included above the diffuser structures 266 and / or 272, such that the diffuser structures 266, 272, and / or 278 are vertically aligned (e.g., in the z-direction) above the photodiode 112. Each of the multiple diffuse structures 278 includes a portion or region of the dielectric material of the color filter region 276, which is included in a plurality of recesses in the top surface of the passivation layer 268.

[0184] Because the recesses in the passivation layer 268 have multiple angled sidewalls, the bottom surface of the diffuse structure 278 can have an approximately V-shaped cross-sectional profile. Alternatively, the bottom surface of the diffuse structure 278 can have circular or approximately U-shaped sidewalls. The angle of the sidewalls forming the recesses of the diffuse structure 278, combined with the different refractive indices of the materials of the passivation layer 268 and the dielectric material of the diffuse structure 278, causes the path of photons entering the substrate 246 to be modified by refraction at the interface between the diffuse structure 278 and the passivation layer 268.

[0185] As described herein in conjunction with various embodiments, for example, in conjunction with Figures 3A to 3G , Figures 4A to 4F and / or Figures 5A to 5G In various embodiments, the pixel sensor 100 may include two or more layers of diffuse structures to improve the quantum efficiency of the pixel sensor 100. For example, the pixel sensor 100 may include layers of diffuse structure 266 and diffuse structure 272, and the layer of diffuse structure 278 may be omitted. In another embodiment, the pixel sensor 100 may include layers of diffuse structure 266 and diffuse structure 278, and the layer of diffuse structure 272 may be omitted. In yet another embodiment, the pixel sensor 100 may include layers of diffuse structure 272 and diffuse structure 278, and the layer of diffuse structure 266 may be omitted. In yet another embodiment, the pixel sensor 100 may include layers of diffuse structure 266, diffuse structure 272, and diffuse structure 278. The various arrangements of the diffuse structure layers described herein enable the flexible placement of multiple diffuse structures in multiple layers to achieve high quantum efficiency for specific combinations of incident light wavelengths, specific sizes of pixel sensors 100, and / or the fabrication flexibility of pixel sensors 100.

[0186] Multiple microlenses 280 may be included above and / or over multiple color filter regions 276. The multiple microlenses 280 may include corresponding microlenses for each of the multiple pixel sensors 100. Microlenses may be formed to focus incident light toward the photodiode 112 of the associated pixel sensor 100.

[0187] As in Figure 2CAs further shown, a metal layer 282 may be included above the substrate 246 in the black level correction region 226 of the substrate 246. The metal layer 282 serves as a light-blocking layer to prevent incident light from entering the portion of the substrate 246 within the black level correction region 226. Therefore, the portion of the substrate 246 within the black level correction region 226 is a sensing region that remains “dark,” allowing dark current measurements to be performed within the black level correction region 226. Dark current measurements can be performed to measure the amount of charge (dark current) generated in the substrate 246 by sources other than incident light (e.g., heat energy from the substrate 246), making the dark current measurement usable for black level correction (or black level calibration) of the pixel sensor array 222.

[0188] As in Figure 2C As further shown, the bonding pad region 228 may include multiple dielectric layers 284, 286, 288, and / or 290 that electrically insulate the bonding pad structure 292. The bonding pad structure 292 is electrically coupled and / or physically coupled to one or more interconnect structures 260 in the interconnect layer 218 of the sensor die 208. The bonding pad opening 294 is included above the bonding pad structure 292 to enable the formation of external electrical connections to the bonding pad structure 292.

[0189] Multiple dielectric layers 284, 286, 288 and / or 290 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y The bonding pad structure 292 may include metallic materials such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum copper (AlCu)), and / or combinations thereof, or other examples.

[0190] The sealing ring region 230 includes a plurality of stacked interconnect structures 242 in the interconnect layer 214 and a plurality of stacked interconnect structures 260 in the interconnect layer 218 to seal the plurality of structures and layers of the image sensor device 210, prevent moisture and other contaminants from entering, and provide structural rigidity to the image sensor device 210.

[0191] As mentioned above, it provides Figures 2A to 2C These are just some of the embodiments. Other embodiments may relate to... Figures 2A to 2C The content described is different.

[0192] Figures 3A to 3GThis is a schematic diagram of an embodiment of pixel sensor 100, which includes a plurality of pixel sensors 100 in the pixel sensor array 222 of the image sensor device 210 described herein. (As shown in...) Figure 3A As shown, embodiment 300 of pixel sensor 100 includes a photodiode 112 in a substrate 246 of sensor die 208. A color filter region 276 and a microlens 280 of pixel sensor 100 are included above the photodiode 112. A deep trench isolation structure 224 is included in the substrate 246 and laterally surrounds the photodiode 112 in the substrate 246.

[0193] As in Figure 3A As further shown, multiple layers comprising multiple diffuse structures are included above the photodiode 112. A diffuse structure 266 is included between the substrate 246 and the buffer layer 264. Diffuse structures 266 are included between multiple segments of the deep trench isolation structure 224. In a top view of the pixel sensor 100, the multiple diffuse structures 266 are included within the inner periphery of this portion of the deep trench isolation structure 224 surrounding the photodiode 112. Each diffuse structure 266 is included in a recess 302 extending into the substrate 246. The multiple recesses 302 are filled with multiple portions 304 of the dielectric material of the buffer layer 264 to form the multiple diffuse structures 266. Thus, the diffuse structures 266 extend into the back surface of the substrate 246.

[0194] The refractive index of the dielectric material (or material composition) of the diffuse structure 266 may be less than the refractive index of the material of the substrate 246. The smaller refractive index of the dielectric material of the diffuse structure 266 reduces the likelihood of incident light being reflected from the interface between the diffuse structure 266 and the substrate 246, and increases the likelihood of incident light being refracted into the substrate 246. In some embodiments, the material of the substrate 246 has a refractive index of approximately 4, and the dielectric material of the diffuse structure 266 has a refractive index less than 4. In some embodiments, the dielectric material of the diffuse structure 266 has a refractive index in the range of approximately 1.5 to approximately 2.7. However, other values ​​and ranges of the refractive index of the dielectric material of the diffuse structure 266 are within the scope of this disclosure. Additionally and / or alternatively, the refractive index of the dielectric material of the diffuse structure 266 may be greater than the refractive index of the material of the substrate 246.

[0195] In some embodiments, the dielectric material of the diffuse structure 266 includes silicon nitride (Si). x N y Such as Si3N4), silicon-rich silicon nitride materials (which can improve the refractive index of silicon nitride materials), silicon oxynitride materials (SiON), and silicon oxide materials (SiO). xFor example, SiO or SiO2), nitrogen-rich silicon oxide materials (which can increase the refractive index of silicon oxide materials), silicon-rich silicon oxide materials (which can increase the refractive index of silicon oxide materials), oxygen-rich polycrystalline silicon materials (which can decrease the refractive index of polycrystalline silicon materials), magnesium oxide materials (MgO) x For example, MgO), alumina materials (Al) x O y For example, Al2O3), ytterbium oxide materials (Yb x O y For example, Yb2O3), zinc oxide materials (ZnO) x For example, ZnO), tantalum oxide materials (Ta x O y For example, Ta2O5), zirconium oxide materials (ZrO2). x For example, ZrO2), hafnium oxide materials (HfO) x For example, HfO2), tellurium oxide materials (TeO) x Examples of dopant materials include, for instance, TeO2, or other examples. In some embodiments, the dielectric material of the diffuse structure 266 comprises silicon oxide material doped with one or more types of dopants. Examples of such dopants include boron (B), phosphorus (P), barium (Ba), lanthanum (La), and / or lead (Pb), or other examples.

[0196] As in Figure 3A As further shown, a diffuse structure 272 is included between the buffer layer 264 and the passivation layer 268. Multiple diffuse structures 272 are included between multiple segments of the metal grid structure 270. In a top view of the pixel sensor 100, a diffuse structure 272 is included within the inner periphery of a portion of the metal grid structure 270 surrounding the photodiode 112. Each diffuse structure 272 is included in a recess 306 extending into the substrate 246. Multiple recesses 306 are filled with multiple portions 308 of the dielectric material of the passivation layer 268 to form the diffuse structure 272.

[0197] The refractive index of the dielectric material (or material composition) of the diffuse structure 272 may be less than the refractive index of the material of the buffer layer 264. The smaller refractive index of the dielectric material of the diffuse structure 272 reduces the likelihood of incident light being reflected by the interface between the diffuse structure 272 and the buffer layer 264, and increases the likelihood of incident light being refracted into the substrate 246. In some embodiments, the dielectric material of the diffuse structure 272 has a refractive index ranging from about 1.4 to about 2. However, other values ​​and ranges of the refractive index of the dielectric material of the diffuse structure 272 are within the scope of this disclosure. Additionally and / or alternatively, the refractive index of the dielectric material of the diffuse structure 272 may be greater than the refractive index of the material of the buffer layer 264.

[0198] In some embodiments, the dielectric material of the diffuse structure 272 includes an oxygen-rich silicon nitride material (which can reduce the refractive index of the silicon nitride material), a silicon oxynitride material (SiON), or a silicon oxide material (SiO). x Examples include SiO or SiO2), nitrogen-rich silicon oxide materials (which can increase the refractive index of silicon oxide materials), silicon-rich silicon oxide materials (which can increase the refractive index of silicon oxide materials), oxygen-rich silicon oxide materials (which can decrease the refractive index of silicon oxide materials), and magnesium oxide materials (MgO). x For example, MgO), alumina materials (Al) x O y For example, Al2O3), and / or ytterbium oxide materials (Yb x O y Examples include, for instance, Yb₂O₃, or other examples. In some embodiments, the dielectric material of the diffuse structure 272 comprises silicon oxide material doped with one or more types of dopants. Examples of such dopants include boron (B), phosphorus (P), barium (Ba), lanthanum (La), and / or lead (Pb), or other examples.

[0199] As in Figure 3A As further shown, the pixel sensor 100 may include a greater number of diffuse structures 266 than the number of diffuse structures 272. The larger number of diffuse structures 266 may be due to the larger cross-sectional width of these diffuse structures 266 (in...). Figure 3A The dimension D1 is smaller than the cross-sectional width of multiple diffuse structures 272 (in Figure 3A (This is denoted as size D2). This can result in the sidewalls of the diffuse structure 272 being more horizontal than the sidewalls of the diffuse structure 266 (e.g., having a larger angle between the sidewalls of the diffuse structure 272). The greater horizontality of the sidewalls of the diffuse structure 272 results in less lateral scattering of incident light at the level of the diffuse structure 272 in the pixel sensor 100 than at the level of the diffuse structure 266. Therefore, as the incident light approaches the photodiode 112, the incident light gradually becomes more laterally diffused. At the level of the diffuse structure 272 in the pixel sensor 100, the less horizontal scattering of the incident light reduces the amount of incident light that is guided away from the photodiode 112. However, size D1 may alternatively be larger than size D2, and the number of multiple diffuse structures 272 may alternatively be greater than the number of multiple diffuse structures 266.

[0200] The depth or vertical (z-direction) thickness of the diffuse structure 266 (in Figure 3A The depth or vertical (z-direction) thickness of the diffuse structure 272 is represented as dimension D3. Figure 3AThe dimensions (D4) can be approximately the same. For example, the vertical thickness of diffuse structure 266 and the vertical thickness of diffuse structure 272 can each be included in the range of about 0.3 micrometers to about 0.4 micrometers. However, other values ​​used in this range are also within the scope of this disclosure. In some embodiments, the vertical thickness of diffuse structure 266 is greater than the vertical thickness of diffuse structure 272. In some embodiments, the vertical thickness of diffuse structure 272 is greater than the vertical thickness of diffuse structure 266.

[0201] Figure 3B A cross-sectional view and a top view of the diffuse structure 266 in embodiment 300 of pixel sensor 100 are shown. (As in...) Figure 3B As shown, each of the diffuse structures 266 may have a V-shaped cross-sectional profile. Each of the diffuse structures 266 may have an approximately inverted pyramidal three-dimensional shape. In a top view, multiple diffuse structures 266 are arranged in a grid (e.g., a 4×4 grid). In some embodiments, the grid of the diffuse structures 266 is aligned with the deep trench isolation structure 224 such that multiple segments of the deep trench isolation structure 224 extend along the four sides of this grid of the multiple diffuse structures 266, for example, in a material where the substrate 246 has… <100> In the embodiment of grain orientation. In other embodiments, for example, where the material of substrate 246 has <110> In those grain-oriented embodiments, the grid of the plurality of diffuse structures 266 can be rotated relative to the deep trench isolation structure 224 such that a plurality of segments of the deep trench isolation structure 224 extending along the corners of the grid of the diffuse structure 266 are aligned with the deep trench isolation structure 224.

[0202] Figure 3C Cross-sectional and top views of multiple diffuse structures 272 in embodiment 300 of pixel sensor 100 are shown. (As in...) Figure 3C As shown, the multiple diffuse structures 272 may each have a V-shaped cross-sectional profile. Unlike diffuse structure 266, diffuse structure 272 may each have an approximately inverted conical three-dimensional shape. The conical shape of diffuse structure 272 may be generated by recesses 306 formed in a dielectric layer (e.g., buffer layer 264), while the pyramidal shape of diffuse structure 266 may be generated by recesses 302 formed in a silicon layer (e.g., substrate 246). In a top view, the diffuse structures 272 are arranged in a grid (e.g., a 3×3 grid).

[0203] Figure 3D An embodiment 310 of a pixel sensor 100 is shown, which is related to... Figure 3A The pixel sensor 100 is similar to embodiment 300, except that embodiment 310 of pixel sensor 100 includes a layer of diffuse structure 278 instead of a layer of diffuse structure 272.

[0204] A diffuse structure 278 is included above the diffuse structure 266 and extends within the passivation layer 268. The diffuse structure 278 is included between multiple segments of the metal grid structure 274. In a top view of the pixel sensor 100, multiple diffuse structures 278 are included within the inner periphery of this portion of the metal grid structure 274 surrounding the color filter region 276 of the pixel sensor 100. Each diffuse structure 278 is included within a recess 312 extending into the passivation layer 268. The multiple recesses 312 are filled with multiple portions 314 of the dielectric material of the color filter region 276 to form multiple diffuse structures 278.

[0205] The refractive index of the dielectric material (or material composition) of the diffuse structure 278 may be smaller than that of the material of the passivation layer 268. The smaller refractive index of the dielectric material of the diffuse structure 278 reduces the likelihood of incident light being reflected from the interface between the diffuse structure 278 and the passivation layer 268, and increases the likelihood of incident light being refracted into the substrate 246.

[0206] As in Figure 3D As further shown, the pixel sensor 100 may include a greater number of diffuse structures 266 than the number of diffuse structures 278. The larger number of diffuse structures 266 may be due to the larger cross-sectional width of the diffuse structures 266 (in...). Figure 3D The dimension D1 is smaller than the cross-sectional width (dimension D5) of the diffuse structure 278. This may result in the sidewalls of the diffuse structure 278 being more horizontal than the sidewalls of the diffuse structure 266 (e.g., a larger angle between the multiple sidewalls of the diffuse structure 278). In the pixel sensor 100, the greater horizontality of the sidewalls of the diffuse structure 278 results in less lateral scattering of incident light at the level of the diffuse structure 278 compared to the level of the diffuse structure 266. Therefore, as the incident light approaches the photodiode 112, the lateral diffusion of the incident light gradually increases. The less horizontal scattering of incident light at the level of the diffuse structure 278 in the pixel sensor 100 reduces the amount of incident light lost that is guided away from the photodiode 112. However, dimension D1 may alternatively be larger than dimension D5, and the number of multiple diffuse structures 278 may alternatively be greater than the number of multiple diffuse structures 266.

[0207] The depth or vertical (z-direction) thickness (dimension D3) of diffuse structure 266 and the depth or vertical (z-direction) thickness (in) of diffuse structure 278 Figure 3DThe dimensions (D6) can be approximately the same value. For example, the vertical thickness of the diffuse structure 266 and the vertical thickness of the diffuse structure 278 can each be included in the range of about 0.3 micrometers to about 0.4 micrometers. However, other values ​​used in this range are also within the scope of this disclosure. In some embodiments, the vertical thickness of the diffuse structure 266 is greater than the vertical thickness of the diffuse structure 278. In some embodiments, the vertical thickness of the diffuse structure 278 is greater than the vertical thickness of the diffuse structure 266.

[0208] Figure 3E Cross-sectional and top views of multiple diffuse structures 278 in embodiment 310 of pixel sensor 100 are shown. (As in...) Figure 3E As shown, each of the diffuse structures 278 may have a V-shaped cross-sectional profile. Unlike the plurality of diffuse structures 266, each of the diffuse structures 278 may have an approximately inverted conical three-dimensional shape. The conical shape of the diffuse structure 278 may be generated by a recess 312 formed in a dielectric layer (e.g., passivation layer 268), while the pyramidal shape of the diffuse structure 266 may be generated by a recess 302 formed in a silicon layer (e.g., substrate 246). In a top view, the plurality of diffuse structures 278 are arranged in a grid (e.g., a 2×2 grid).

[0209] Figure 3F Embodiment 316 of the pixel sensor 100 is shown, which is consistent with... Figure 3A The pixel sensor 100 is similar to embodiment 300, except that embodiment 316 of pixel sensor 100 includes layers of multiple diffuse structures 266, multiple diffuse structures 272, and multiple diffuse structures 278. Diffuse structures 272 are included above diffuse structures 266, and diffuse structures 278 are included above diffuse structures 272. Therefore, the multiple diffuse structures 266, 272, and 278 are arranged perpendicularly in the z-direction in pixel sensor 100. This provides three levels of diffusion or scattering of incident light. The cross-sectional width (dimension D5) of diffuse structure 278 may be greater than the cross-sectional width (dimension D2) of diffuse structure 272, such that the number of multiple diffuse structures 272 is greater than the number of multiple diffuse structures 278. Alternatively, the number of multiple diffuse structures 278 may be greater than the number of multiple diffuse structures 272, and / or the cross-sectional width (dimension D5) of diffuse structure 278 may be less than the cross-sectional width (dimension D2) of diffuse structure 272.

[0210] Figure 3G Embodiment 318 of pixel sensor 100 is shown, which is related to... Figure 3FThe pixel sensor 100 in embodiment 316 is similar, except that the diffuse structure 266 is omitted in the pixel sensor 100 of embodiment 318. A diffuse structure 278 is included above the diffuse structure 272. Therefore, a plurality of diffuse structures 272 and a plurality of diffuse structures 278 are arranged vertically in the z-direction in the pixel sensor 100.

[0211] As mentioned above, it provides Figures 3A to 3G These are just some examples. Other embodiments may differ from those described above. Figures 3A to 3G The content described. For example, pixel sensor 100 may include multiple diffuse structures in more than three layers arranged vertically.

[0212] Figures 4A to 4I This is a schematic diagram of an embodiment of pixel sensor 100, which may include a plurality of pixel sensors 100 in the pixel sensor array 222 of the image sensor device 210 described herein. Figures 4A to 4I In the embodiment of the pixel sensor 100 shown, the buffer layer 264 and / or the passivation layer 268 include material composition gradients such that a refractive index gradient (e.g., a vertical gradient in the z-direction) occurs in the buffer layer 264 and / or in the passivation layer 268. The refractive index gradients in the buffer layer 264 and / or the passivation layer 268 facilitate the bending of incident light between the microlens 280 and the substrate 246. In this way, incident light can be directed onto a more vertically oriented path between the multiple layers of the plurality of diffuse structures in the pixel sensor 100.

[0213] As in Figure 4A As shown, embodiment 400 of pixel sensor 100 and Figure 3A The pixel sensor 100 is similar to embodiment 300, except that a refractive index gradient is included in the buffer layer 264. In some embodiments, the refractive index in the buffer layer 264 increases from the top to the bottom of the buffer layer 264. In some embodiments, the refractive index in the buffer layer 264 decreases from the top to the bottom of the buffer layer 264. In some embodiments, the refractive index in the buffer layer 264 increases from the top towards the center and decreases from the center to the bottom of the buffer layer 264. In some embodiments, the refractive index in the buffer layer 264 decreases from the top towards the center and increases from the center to the bottom of the buffer layer 264.

[0214] In some embodiments, the refractive index gradient in the buffer layer 264 can be achieved by doping the dielectric material with a specific doping distribution. For example, the buffer layer 264 may be doped with one or more types of dopants such that the dopant concentration increases from the top to the bottom of the buffer layer 264. As another embodiment, the buffer layer 264 may be doped with one or more types of dopants such that the dopant concentration decreases from the top to the bottom of the buffer layer 264. As yet another embodiment, the buffer layer 264 may be doped with one or more types of dopants such that the dopant concentration of a first dopant increases from the top to the bottom of the buffer layer 264, and the dopant concentration of a second dopant decreases from the top to the bottom of the buffer layer 264.

[0215] In some embodiments, the refractive index gradient in the buffer layer 264 can be achieved by forming an oxygen concentration gradient in the dielectric material. For example, the oxygen concentration can increase from the top to the bottom of the buffer layer 264. As another embodiment, the oxygen concentration can decrease from the top to the bottom of the buffer layer 264.

[0216] In some embodiments, the refractive index gradient in the buffer layer 264 can be achieved by forming a nitrogen concentration gradient in the dielectric material. For example, the nitrogen concentration can increase from the top to the bottom of the buffer layer 264. As another embodiment, the nitrogen concentration can decrease from the top to the bottom of the buffer layer 264.

[0217] In some embodiments, the refractive index gradient in the buffer layer 264 can be achieved by forming a silicon concentration gradient in the dielectric material. For example, the silicon concentration can increase from the top to the bottom of the buffer layer 264. As another embodiment, the silicon concentration can decrease from the top to the bottom of the buffer layer 264.

[0218] Figure 4B An embodiment 402 of the pixel sensor 100 is shown. Embodiment 402 of the pixel sensor 100 is similar to... Figure 3B Embodiment 310 of the pixel sensor 100, except that embodiment 402 of the pixel sensor 100 includes a... Figure 4A The refractive index gradient in the buffer layer 264 included in embodiment 400 of the pixel sensor 100.

[0219] Figure 4C An embodiment 404 of the pixel sensor 100 is shown. Embodiment 404 of the pixel sensor 100 is similar to... Figure 3F Embodiment 316 of the pixel sensor 100, except that embodiment 404 of the pixel sensor 100 includes a... Figure 4A The refractive index gradient in the buffer layer 264 included in embodiment 400 of the pixel sensor 100.

[0220] Figure 4DEmbodiment 406 of pixel sensor 100 is shown, pixel sensor 100 and in Figure 3A The pixel sensor 100 is similar to embodiment 300, except for the refractive index gradient included in the passivation layer 268. In some embodiments, the refractive index in the passivation layer 268 increases from the top of the passivation layer 268 to the bottom of the passivation layer 268. In some embodiments, the refractive index in the passivation layer 268 decreases from the top of the passivation layer 268 to the bottom of the passivation layer 268. In some embodiments, the refractive index in the passivation layer 268 increases from the top of the passivation layer 268 towards the center and decreases from the center of the passivation layer 268 towards the bottom of the passivation layer 268. In some embodiments, the refractive index in the passivation layer 268 decreases from the top of the passivation layer 268 towards the center and increases from the center of the passivation layer 268 towards the bottom of the passivation layer 268.

[0221] In some embodiments, a refractive index gradient in the passivation layer 268 can be achieved by doping the dielectric material with a specific doping distribution. For example, the passivation layer 268 may be doped with one or more types of dopants such that the dopant concentration increases from the top to the bottom of the passivation layer 268. As another embodiment, the passivation layer 268 may be doped with one or more types of dopants such that the dopant concentration of a first dopant increases from the top to the bottom of the passivation layer 268, and the dopant concentration of a second dopant decreases from the top to the bottom of the passivation layer 268. As yet another embodiment, the passivation layer 268 may be doped with one or more types of dopants such that the dopant concentration of a first dopant increases from the top to the bottom of the passivation layer 268, and the dopant concentration of a second dopant decreases from the top to the bottom of the passivation layer 268.

[0222] In some embodiments, the refractive index gradient in the passivation layer 268 can be achieved by forming an oxygen concentration gradient in the dielectric material. For example, the oxygen concentration can increase from the top to the bottom of the passivation layer 268. As another embodiment, the oxygen concentration can decrease from the top to the bottom of the passivation layer 268.

[0223] In some embodiments, the refractive index gradient in the passivation layer 268 can be achieved by forming a nitrogen concentration gradient in the dielectric material. For example, the nitrogen concentration can increase from the top to the bottom of the passivation layer 268. As another embodiment, the nitrogen concentration can decrease from the top to the bottom of the passivation layer 268.

[0224] In some embodiments, the refractive index gradient in the passivation layer 268 can be achieved by forming a silicon concentration gradient in the dielectric material. For example, the silicon concentration can increase from the top to the bottom of the passivation layer 268. As another embodiment, the silicon concentration can decrease from the top to the bottom of the passivation layer 268.

[0225] Figure 4E An embodiment 408 of the pixel sensor 100 is shown. Embodiment 408 of the pixel sensor 100 is similar to... Figure 3B Embodiment 310 of the pixel sensor 100, except that embodiment 408 of the pixel sensor 100 includes a... Figure 4D The refractive index gradient in the passivation layer 268 included in embodiment 406 of the pixel sensor 100.

[0226] Figure 4F An embodiment 410 of the pixel sensor 100 is shown. Embodiment 410 of the pixel sensor 100 is similar to... Figure 3F Embodiment 316 of the pixel sensor 100, except that embodiment 410 of the pixel sensor 100 includes a... Figure 4D The refractive index gradient in the passivation layer 268 included in embodiment 406 of the pixel sensor 100.

[0227] Figure 4G An embodiment 412 of the pixel sensor 100 is shown. Embodiment 412 of the pixel sensor 100 is similar to... Figure 3A Embodiment 300 of the pixel sensor 100, except that embodiment 412 of the pixel sensor 100 includes a... Figure 4A The refractive index gradient in the buffer layer 264 and in the pixel sensor 100 included in embodiment 400 Figure 4D The combination of refractive index gradients in the passivation layer 268 included in embodiment 406 of the pixel sensor 100.

[0228] Figure 4H Embodiment 414 of the pixel sensor 100 is shown. Embodiment 414 of the pixel sensor 100 is similar to that in... Figure 3B Embodiment 310 of the pixel sensor 100, except that embodiment 414 of the pixel sensor 100 includes a... Figure 4A The refractive index gradient in the buffer layer 264 and in the pixel sensor 100 included in embodiment 400 Figure 4D The combination of refractive index gradients in the passivation layer 268 included in embodiment 406 of the pixel sensor 100.

[0229] Figure 4I An embodiment 416 of the pixel sensor 100 is shown. Embodiment 416 of the pixel sensor 100 is similar to... Figure 3F Embodiment 316 of the pixel sensor 100, except that embodiment 416 of the pixel sensor 100 includes a... Figure 4A The refractive index gradient in the buffer layer 264 and in the pixel sensor 100 included in embodiment 400 Figure 4D The combination of refractive index gradients in the passivation layer 268 included in embodiment 406 of the pixel sensor 100.

[0230] As mentioned above, it provides Figures 4A to 4I These are just some examples. Other embodiments may differ from those described above. Figures 4A to 4I The content described.

[0231] Figures 5A to 5G This is a schematic diagram of an embodiment of pixel sensor 100, which may include a plurality of pixel sensors 100 in the pixel sensor array 222 of the image sensor device 210 described herein. Figures 5A to 5G In the embodiment of the pixel sensor 100 shown, one or more layers of the plurality of diffuse structures 266, 272, and / or 278 include diffuse structures having a circular or approximately U-shaped cross-sectional profile and an approximately hemispherical three-dimensional shape. The hemispherical three-dimensional shape of the diffuse structure may be formed due to the use of semiconductor processing techniques different from those used to form diffuse structures with approximately pyramidal or approximately conical three-dimensional shapes. Combined with Figures 9A to 9I Embodiments of techniques for forming diffuse structures with approximate pyramidal or conical three-dimensional shapes are described. Figures 10A to 10E An embodiment technique for forming a diffuse structure with an approximately hemispherical three-dimensional shape is described.

[0232] As in Figure 5A As shown, embodiment 500 of pixel sensor 100 is similar to... Figure 3A The pixel sensor 100 is similar to embodiment 300, except that the diffuse structure 272 has a circular or approximately U-shaped cross-sectional profile (in this case, multiple diffuse structures 272 may each have an approximately hemispherical three-dimensional shape). As in Figure 5B As shown in the top view of the diffuse structure 272, the multiple diffuse structures 272 may have an approximately circular top view shape and be arranged in a grid (e.g., a 3×3 grid).

[0233] As in Figure 5C As shown, embodiment 502 of pixel sensor 100 is similar to... Figure 3D The pixel sensor 100 is similar to embodiment 310, except that the diffuse structure 278 has a circular or approximately U-shaped cross-sectional profile (in this case, multiple diffuse structures 278 may each have an approximately hemispherical three-dimensional shape). As in Figure 5D As shown in the top view of the diffuse structure 278, the multiple diffuse structures 278 may have an approximately circular top view shape and be arranged in a grid (e.g., a 2×2 grid).

[0234] As in Figure 5E As shown, embodiment 504 of pixel sensor 100 is similar to... Figure 3FThe pixel sensor 100 is similar to embodiment 316, except that the plurality of diffuse structures 272 and the plurality of diffuse structures 278 each have a circular or approximately U-shaped cross-sectional profile (in this case, the plurality of diffuse structures 272 and the plurality of diffuse structures 278 may each have an approximately hemispherical three-dimensional shape).

[0235] As in Figure 5F As shown, embodiment 506 of pixel sensor 100 is similar to... Figure 3F The pixel sensor 100 is similar to embodiment 316, except that the plurality of diffuse structures 266, 272, and 278 each have a circular or approximately U-shaped cross-sectional profile (in this case, the plurality of diffuse structures 266, 272, and 278 may each have an approximately hemispherical three-dimensional shape). As in Figure 5G As shown in the top view of the diffuse structure 278, the diffuse structure 266 may have an approximately circular top view shape and be arranged in a grid (e.g., a 4×4 grid).

[0236] As mentioned above, it provides Figures 5A to 5G These are just some examples. Other embodiments may differ from those described above. Figures 5A to 5G The content described.

[0237] Figures 6A to 6E This is a schematic diagram of an exemplary embodiment 600 that forms the circuit die 206 (or a portion thereof) described herein. In some embodiments, combined with Figures 6A to 6E The one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0238] Go to Figure 6A The substrate 232 provides the device layer 212 of the circuit die 206. The substrate 232 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, which may be provided as a semiconductor on insulator (SOI) wafer and / or another type of semiconductor workpiece.

[0239] As in Figure 6BAs shown, one or more integrated circuit devices 236 may be formed in and / or on substrate 232. One or more semiconductor processing tools may be used to form one or more portions of the multiple integrated circuit devices 236. For example, deposition tools may be used to perform various deposition operations to deposit multiple layers of the integrated circuit devices 236, and / or deposit photoresist layers for etching multiple portions of substrate 232 and / or the deposited multiple layers. As another embodiment, an exposure tool may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another embodiment, a developing tool may be used to develop the pattern in the photoresist layer. As another embodiment, an etching tool may be used to etch multiple portions of substrate 232 and / or the deposited multiple layers to form multiple integrated circuit devices 236. As another embodiment, a planarization tool may be used to planarize multiple portions of the multiple integrated circuit devices 236. As another embodiment, a plating tool may be used to deposit multiple metal structures and / or multiple layers of the multiple integrated circuit devices 236.

[0240] As in Figure 6B As further shown, dielectric layer 234 may be deposited above and / or on substrate 232, and above and / or on integrated circuit device 236. Dielectric layer 234 may be deposited using deposition tools, employing physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, or another type of deposition technique. In some embodiments, after depositing dielectric layer 234, planarization tools may be used to planarize dielectric layer 234.

[0241] As in Figure 6C As shown, a first portion of the interconnect layer 214 of the circuit die 206 is formed above the device layer 212. To form the first portion of the interconnect layer 214, a deposition tool can be used to deposit a dielectric layer 238 (which may include one or more interlayer dielectric layers, one or more intermetallic dielectric layers, one or more etch stop layers, and / or one or more dielectric layers of another type), using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or another deposition technique. In some embodiments, after depositing the dielectric layer 238, a planarization tool can be used to planarize the dielectric layer 238.

[0242] Deposition tools, exposure tools, developing tools, etching tools, planarization tools, plating tools, and / or other semiconductor processing tools can be used to perform various operations to form a plurality of interconnect structures 242 in a first portion of interconnect layer 214. Deposition tools and / or plating tools can be used to deposit the interconnect structures 242 using physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating, and / or other deposition techniques. In some embodiments, after depositing the interconnect structures 242, a planarization tool can be used to planarize the interconnect structures 242.

[0243] In some embodiments, a first portion of interconnect layer 214 is constructed in a plurality of via layers (V layers) and metallization layers (M layers) in the z-direction. For example, a first portion of dielectric layer 238 may be formed, in which a plurality of recesses may be formed, and in these recesses a plurality of first interconnect structures 242 (e.g., V0 via layers, M0 metallization layers). A second portion of dielectric layer 238 may be formed, in which a plurality of recesses may be formed, and in these recesses a plurality of second interconnect structures 242 (e.g., V1 via layers, M1 metallization layers). The remaining via layers and / or metallization layers forming the first portion of interconnect layer 214 may be constructed in a similar manner.

[0244] As in Figure 6D and Figure 6E As shown, a second portion of interconnect layer 214 may be formed, and the second portion of interconnect layer 214 may include bonding layer 240 and bonding structure 244. As in Figure 6D As shown, the bonding layer 240 may be formed above and / or on the dielectric layer 238, and above and / or on the topmost interconnect structure 242. The bonding layer 240 may be deposited using deposition tools, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or other deposition techniques. In some embodiments, after depositing the bonding layer 240, a planarization tool may be used to planarize the bonding layer 240.

[0245] As in Figure 6EAs shown, bonding structures 244 may be formed in bonding layer 240. For example, deposition tools, exposure tools, and developing tools may be used to form a patterned mask layer on bonding layer 240. Etching tools may be used to etch bonding layer 240 (e.g., using wet etching techniques, dry etching techniques) to form a plurality of recesses in bonding layer 240. Deposition tools and / or plating tools may be used to deposit bonding structures 244 in these recesses, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another deposition technique. In some embodiments, after bonding structure 244 is deposited, a planarization tool may perform a planarization operation to planarize bonding structure 244.

[0246] As mentioned above, it provides Figures 6A to 6E As one embodiment, other embodiments may differ from those described above. Figures 6A to 6E The content described.

[0247] Figures 7A to 7F This is a schematic diagram of an example embodiment 700 forming the sensor die 208 (or a portion thereof) described herein. In some embodiments, combined with Figures 7A to 7F The one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0248] Go to Figure 7A The substrate 246 provides the device layer 216 for the sensor die 208. The substrate 246 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, which may be provided as an SOI wafer and / or another type of semiconductor workpiece.

[0249] As in Figure 7B As shown, a plurality of photodiodes 112 of a plurality of pixel sensors 100 of a pixel sensor array 222 of sensor die 208 can be formed from the front side of substrate 246 within substrate 246. In some embodiments, ions can be implanted into substrate 246 using an ion implantation tool to form a PN junction between a P-doped region and an N-doped region of substrate 246, or a PIN junction between a P-doped region of substrate 246, an N-doped region of substrate 246, and an intrinsic (e.g., undoped) semiconductor region for photodiode 112.

[0250] As in Figure 7BAs further shown, a plurality of shallow trench isolation structures 250 may be formed within the substrate 246 (e.g., from the front side of the substrate 246) such that these shallow trench isolation structures 250 are located between a plurality of photodiodes 112. In some embodiments, the shallow trench isolation structures 250 are formed after the photodiodes 112 are formed. In some embodiments, the shallow trench isolation structures 250 are formed before the photodiodes 112 are formed. Deposition tools, exposure tools, and development tools can be used to form a patterned mask layer on the substrate 246. Etching tools can be used to etch from the front side of the substrate 246 into the substrate 246 (e.g., using wet etching techniques, dry etching techniques) to form a plurality of recesses within the front side of the substrate 246. Deposition tools can be used to deposit the plurality of shallow trench isolation structures 250 in these recesses using chemical vapor deposition, physical vapor deposition, atomic layer deposition, oxidation techniques, and / or another deposition technique. In some implementations, after the shallow trench isolation structure 250 is deposited, a planarization tool can perform a planarization operation to planarize the shallow trench isolation structure 250.

[0251] As in Figure 7C As shown, a plurality of transmission gates 114 of the pixel sensor 100 may be formed above and / or on the front surface of the substrate 246. Forming the transmission gates 114 may include depositing a gate dielectric on the front surface of the substrate 246, depositing a gate electrode on the gate dielectric layer, and / or forming sidewall spacers on the sidewalls of the gate electrode, or other examples.

[0252] As in Figure 7C As further shown, a dielectric layer 248 may be formed above and / or on the front side of the substrate 246, and above and / or on the transmission gate 114. The dielectric layer 248 may be deposited using deposition tools, employing chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another deposition technique. In some embodiments, after depositing the dielectric layer 248, a planarization tool may perform a planarization operation to planarize the dielectric layer 248.

[0253] As in Figure 7D As shown, a first portion of the interconnect layer 218 of the sensor die 208 is formed above the device layer 216. To form the first portion of the interconnect layer 218, a deposition tool can be used to deposit a dielectric layer 256 (which may include one or more interlayer dielectric layers, one or more intermetallic dielectric layers, one or more etch stop layers, and / or one or more dielectric layers of another type), using physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or another deposition technique. In some embodiments, after depositing the dielectric layer 256, a planarization tool can be used to planarize the dielectric layer 256.

[0254] Various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, plating tools, and / or other semiconductor processing tools to form a plurality of interconnect structures 260 in a first portion of interconnect layer 218. The interconnect structures 260 can be deposited using deposition tools and / or plating tools, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating, and / or other deposition techniques. In some embodiments, planarization tools can be used to planarize the interconnect structures 260 after deposition.

[0255] In some embodiments, a first portion of interconnect layer 218 is constructed in the z-direction within a plurality of via layers (V layers) and metallization layers (M layers). For example, a first portion of dielectric layer 256 may be formed, in which a plurality of recesses may be formed, and in these recesses a plurality of first interconnect structures 260 (e.g., V0 via layers, M0 metallization layers). A second portion of dielectric layer 256 may be formed, in which a plurality of recesses may be formed, and in these recesses a plurality of second interconnect structures 260 (e.g., V1 via layers, M1 metallization layers). The remaining via layers and / or metallization layers forming the first portion of interconnect layer 218 may be constructed in a similar manner.

[0256] As in Figure 7E and Figure 7F As shown, a second portion of interconnect layer 218 may be formed, and the second portion of interconnect layer 218 may include bonding layer 258 and bonding structure 262. (As shown in...) Figure 7E As shown, the bonding layer 258 may be formed above and / or on the dielectric layer 256, and above and / or on the topmost interconnect structure 260. The bonding layer 258 may be deposited using deposition tools, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or other deposition techniques. In some embodiments, after the bonding layer 258 is deposited, a planarization tool may be used to planarize the bonding layer 258.

[0257] As in Figure 7FAs shown, bonding structure 262 may be formed in bonding layer 258. For example, deposition tools, exposure tools, and developing tools may be used to form a patterned mask layer on bonding layer 258. Etching tools may be used to etch bonding layer 258 (e.g., using wet etching techniques, dry etching techniques) to form a plurality of recesses in bonding layer 258. Deposition tools and / or plating tools may be used to deposit bonding structure 262 in the recesses, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another deposition technique. In some embodiments, after bonding structure 262 is deposited, a planarization tool may perform a planarization operation to planarize bonding structure 262.

[0258] As mentioned above, it provides Figures 7A to 7F As one embodiment, other embodiments may differ from those described above. Figures 7A to 7F The content described.

[0259] Figure 8A and Figure 8B This is a schematic diagram of an example embodiment 800 that forms the image sensor device 210 (or a portion thereof) described herein. In some embodiments, combined with Figure 8A and Figure 8B The one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0260] As in Figure 8A and Figure 8B As shown, a bonding operation is performed to bond circuit die 206 and sensor die 208 to form image sensor device 210. Circuit die 206 and sensor die 208 may be bonded at bonding interface 220, which may include bonding layer 240 and bonding layer 258 (belonging to circuit die 206 and sensor die 208, respectively), and bonding structure 244 and bonding structure 262 (belonging to circuit die 206 and sensor die 208, respectively). A bonding tool may be used to form a dielectric-to-dielectric bond between bonding layer 240 and bonding layer 258 at bonding interface 220, and a metal-to-metal bond between bonding structure 244 and bonding structure 262 at bonding interface 220.

[0261] As in Figure 8BAs shown, after bonding, the circuit die 206 and the sensor die 208 are stacked or vertically arranged in the z-direction in the image sensor device 210. The interconnect layer 214 of the circuit die 206 and the interconnect layer 218 of the sensor die 208 face each other in the image sensor device 210, and the device layer 212 of the circuit die 206 and the device layer 216 of the sensor die 208 face away from each other.

[0262] As mentioned above, it provides Figure 8A and Figure 8B As one embodiment, other embodiments may differ from those described above. Figure 8A and Figure 8B The content described.

[0263] Figures 9A to 9I This is a schematic diagram of an exemplary embodiment 900 of a pixel sensor array 222 forming the sensor die 208 (or a portion thereof) described herein. Specifically, the exemplary embodiment 900 may include embodiments of a pixel sensor 100 forming the pixel sensor array 222, comprising multiple diffuse structures across multiple layers, including multiple diffuse structures 266 and multiple diffuse structures 272. In some embodiments, combined with... Figures 9A to 9I The one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0264] As in Figure 9A As shown, during execution in Figures 7C to 7F , Figure 8A and / or Figure 8B After the multiple operations described in the document, it can be performed in Figures 9A to 9I The operations described herein are performed as part of the back-side process of sensor die 208. As in Figure 9B As shown, multiple recesses 302 for multiple diffuse structures 266 of the pixel sensor 100 may be formed in the back side of the substrate 246. These recesses 302 may extend into the back side of the substrate 246 above the photodiode 112.

[0265] In some embodiments, the pattern in the photoresist layer is used to etch the substrate 246 to form a plurality of recesses 302. In these embodiments, a deposition tool can be used to form the photoresist layer on the substrate 246. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool can be used to etch into the substrate 246 based on the pattern to form a plurality of recesses 302. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer can be used as an alternative technique for pattern-based etching of the substrate 246.

[0266] As in Figure 9C As shown, a plurality of recesses 902 may be formed around the photodiode 112 in the substrate 246, forming a deep trench isolation structure 224. In some embodiments, the plurality of recesses 902 are formed after the plurality of recesses 302 are formed. In some embodiments, the plurality of recesses 902 are formed before the plurality of recesses 302 are formed.

[0267] In some embodiments, the pattern in the photoresist layer is used to etch the substrate 246 to form a plurality of recesses 902. In these embodiments, a deposition tool can be used to form the photoresist layer on the back side of the substrate 246. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove multiple portions of the photoresist layer to expose the pattern. An etching tool can be used to etch into the substrate 246 based on the pattern to form a plurality of recesses 902. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove multiple remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the substrate 246.

[0268] As in Figure 9D As shown, the dielectric pads 254 of the deep trench isolation structure 224 are conformally deposited on the sidewalls and bottom surfaces of the plurality of recesses 902. Deposition tools can be used to deposit the dielectric pads 254 using conformal deposition techniques, such as atomic layer deposition. Additionally and / or alternatively, another deposition technique, such as chemical vapor deposition, can be used. The dielectric pads 254 may extend continuously over the back side of the substrate 246 such that the dielectric pads 254 are deposited within the plurality of recesses 302.

[0269] As in Figure 9E As shown, dielectric material is deposited in a plurality of recesses 302 and a plurality of recesses 902 to form a plurality of diffuse structures 266 in the recesses 302, a dielectric layer 252 forming a plurality of deep trench isolation structures 224 in the recesses 902, and a buffer layer 264 formed above the deep trench isolation structures 224 and the diffuse structures 266. Dielectric material may be deposited on the dielectric pad 254. Deposition tools may be used to deposit the dielectric layer 252, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or another deposition technique. In some embodiments, a planarization operation, such as chemical mechanical planarization (CMP), is performed using a planarization tool to planarize the buffer layer 264.

[0270] As in Figure 9F As shown, a metal grid structure 270 may be formed above and / or on a buffer layer 264. A deposition tool may be used to deposit a metal layer on the buffer layer 264, employing chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another suitable deposition technique. The metal layer may be patterned using photolithography and etched to form the metal grid structure 270.

[0271] As in Figure 9G As shown, multiple recesses 306 for multiple diffuse structures 272 of the pixel sensor 100 may be formed within a buffer layer 264. In some embodiments, a pattern in the photoresist layer is used to etch the buffer layer 264 to form the multiple recesses 306. In some embodiments, a metal grid structure 270 is used as a self-aligned pattern to form the multiple recesses 306 in the buffer layer 264.

[0272] As in Figure 9G As shown, a combination of sputtering etching and chemical etching can be used to form a plurality of recesses 306, such that these recesses 306 have an approximately V-shaped cross-sectional profile and an approximately conical three-dimensional shape. Neutral free radicals 904 can be used to chemically etch the buffer layer 264, and ions 906 can be used to bombard the buffer layer 264 to sputter-etch the buffer layer 264, resulting in the removal of material 908 from the buffer layer 264. In some embodiments, the low bias power of the ions 906 can be used to achieve a specific directionality for sputtering etching to achieve the approximately V-shaped cross-sectional profile and approximately conical three-dimensional shape for the plurality of recesses 306.

[0273] As in Figure 9HAs shown, dielectric material is deposited over and / or on a buffer layer 264 and in a plurality of recesses 306 to form a passivation layer 268 on the buffer layer 264 and a plurality of diffuse structures 272 in the plurality of recesses 306. Deposition tools can be used to deposit the dielectric material, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or other deposition techniques. In some embodiments, after depositing the passivation layer 268, a planarization tool is used to planarize the passivation layer 268.

[0274] As in Figure 9I As further shown, a metal grid structure 274 may be formed above and / or on the passivation layer 268. A deposition tool may be used to deposit a metal layer on the passivation layer 268, employing chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another suitable deposition technique. The metal layer may be patterned using photolithography and etched to form the metal grid structure 274. A color filter region 276 may be formed in the metal grid structure 274, and a microlens 280 may be formed on the color filter region 276.

[0275] As mentioned above, it provides Figures 9A to 9I As one embodiment, other embodiments may differ from those described above. Figures 9A to 9I The content described.

[0276] Figures 10A to 10E This is a schematic diagram of an exemplary embodiment 1000 of a pixel sensor array 222 forming the sensor die 208 (or a portion thereof) described herein. Specifically, the exemplary embodiment 1000 may include embodiments of the pixel sensor 100 forming the pixel sensor array 222, comprising a plurality of diffuse structures in multiple layers, including a plurality of diffuse structures 266 and a plurality of diffuse structures 272. In some embodiments, combined with... Figures 10A to 10E The one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0277] As in Figure 10A As shown, it can be combined. Figures 9A to 9F Similar processing operations, as shown and described, are used to form a deep trench isolation structure 224, a buffer layer 264, multiple diffuse structures 266, and a metal grid structure 270.

[0278] As in Figure 10BAs shown, multiple recesses 306 for multiple diffuse structures 272 of the pixel sensor 100 can be formed in the buffer layer 264. In some embodiments, a pattern in the photoresist layer is used to etch the buffer layer 264 to form the recesses 306. In some embodiments, the buffer layer 264 is etched to form the multiple recesses 306, using a metal grid structure 270 as a self-aligned pattern.

[0279] As in Figure 10B As shown, it can be used with Figure 9G The described techniques employ various etching methods to form multiple recesses 306, such that these recesses have an approximately U-shaped cross-sectional profile and an approximately semi-circular three-dimensional shape. Specifically, cyclic reactive ion etching (sometimes referred to as BOSCH etching) can be used to achieve the approximately U-shaped cross-sectional profile and approximately semi-circular three-dimensional shape for the multiple recesses 306.

[0280] Figure 10C An embodiment process sequence for etching buffer layer 264 to form a plurality of recesses 306 having an approximately U-shaped cross-sectional profile and an approximately semi-circular three-dimensional shape is shown. Figure 10C In the diagram, BARC is the bottom anti-reflective coating, and PR is the photoresist. For example, in... Figure 10C As shown, one cycle of the cyclic reactive ion etching process may include etching the recess 306 to a first depth in the buffer layer 264. A protective liner 1002 may be formed on the sidewalls and bottom surface of the recess 306. A portion of the protective liner 1002 on the bottom surface of the recess 306 may be removed by etching, leaving the protective liner 1002 on the sidewalls of the recess 306. By further etching into the buffer layer 264, the depth of the recess 306 may subsequently increase from the first depth to a second depth, while the protective liner 1002 protects the sidewalls of the recess 306 from lateral etching. Additional multiple cycles may be performed to achieve specific depths for these recesses 306. In some embodiments, a similar technique may be used to etch the substrate 246 to form a plurality of recesses 302, such that the diffuse structure 266 has an approximately U-shaped cross-sectional profile and an approximately semi-circular three-dimensional shape.

[0281] As in Figure 10D As shown, dielectric material is deposited above and / or on buffer layer 264 and in multiple recesses 306 to form a passivation layer 268 on buffer layer 264 and multiple diffuse structures 272 in multiple recesses 306. Deposition tools can be used to deposit the dielectric material, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or other deposition techniques. In some embodiments, after depositing passivation layer 268, a planarization tool is used to planarize passivation layer 268.

[0282] As in Figure 10E As further shown, a metal grid structure 274 may be formed above and / or on the passivation layer 268. A deposition tool may be used to deposit a metal layer on the passivation layer 268, employing chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another suitable deposition technique. The metal layer may be patterned using photolithography and etched to form the metal grid structure 274. A color filter region 276 may be formed in the metal grid structure 274, and a microlens 280 may be formed on the color filter region 276.

[0283] As mentioned above, it provides Figures 10A to 10E As one embodiment, other embodiments may be related to... Figures 10A to 10E The content described is different.

[0284] Figures 11A to 11E This is a schematic diagram of an exemplary embodiment 1100 of a pixel sensor array 222 forming the sensor die 208 (or a portion thereof) described herein. Specifically, the exemplary embodiment 1100 may include embodiments of the pixel sensor 100 forming the pixel sensor array 222, comprising multiple diffuse structures across multiple layers, including multiple diffuse structures 266 and multiple diffuse structures 278. In some embodiments, combined with... Figures 11A to 11E The one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0285] As in Figure 11A As shown, executable combination Figures 9A to 9F Similar processing operations, as shown and described, are used to form a deep trench isolation structure 224, a buffer layer 264, multiple diffuse structures 266, and a metal grid structure 270.

[0286] As in Figure 11B As shown, a passivation layer 268 is formed above and / or on a buffer layer 264. The passivation layer 268 can be deposited using deposition tools, employing physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, or other deposition techniques. In some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, is performed using a planarization tool to planarize the passivation layer 268.

[0287] As in Figure 11CAs shown, a metal grid structure 274 may be formed above and / or on the passivation layer 268. A deposition tool may be used to deposit a metal layer on the passivation layer 268, employing chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another suitable deposition technique. The metal layer may be patterned using photolithography and etched to form the metal grid structure 274.

[0288] As in Figure 11D As shown, a plurality of recesses 312 for a plurality of diffuse structures 278 for a pixel sensor 100 are formed in the passivation layer 268. In some embodiments, a pattern in the photoresist layer can be used to etch the passivation layer 268 to form the plurality of recesses 312. In some embodiments, the passivation layer 268 is etched to form the recesses 312 using a metal grid structure 274 as a self-aligned pattern.

[0289] In some implementations, etching techniques (e.g., combined with...) can be used. Figure 9G The described combination of sputtering etching and chemical etching forms a plurality of recesses 312, giving these recesses an approximately V-shaped cross-sectional profile and an approximately conical three-dimensional shape. In some embodiments, etching techniques, such as those combined with... Figure 10C The described cyclic reactive ion technique is used to form a plurality of recesses 312, such that these recesses 312 have an approximately U-shaped cross-sectional profile and an approximately semi-circular three-dimensional shape.

[0290] As in Figure 11E As shown, a color filter region 276 may be formed in a metal grid structure 274, such that the dielectric material of the color filter region 276 fills a plurality of recesses 312 to form a plurality of diffuse structures 278. A microlens 280 may be formed on the color filter region 276.

[0291] As mentioned above, it provides Figures 11A to 11E As one embodiment, other embodiments may be related to... Figures 11A to 11E The content described is different.

[0292] Figures 12A to 12C This is a schematic diagram of an exemplary embodiment 1200 of a pixel sensor array 222 forming the sensor die 208 (or a portion thereof) described herein. Specifically, the exemplary embodiment 1200 may include embodiments of the pixel sensor 100 forming the pixel sensor array 222, comprising a plurality of diffuse structures, including a plurality of diffuse structures 266, a plurality of diffuse structures 272, and a plurality of diffuse structures 278. In some embodiments, combined with... Figures 12A to 12CThe one or more semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, plating tools, ion implantation tools, and / or wafer / die transfer tools, or other examples.

[0293] As in Figure 12A As shown, executable combination Figures 9A to 9F Similar processing operations, as shown and described, are used to form a deep trench isolation structure 224, a buffer layer 264, multiple diffuse structures 266, and a metal grid structure 270. (As in...) Figure 12A As further shown, a plurality of recesses 306 for the plurality of diffuse structures 272 are formed in the buffer layer 264. In some embodiments, etching techniques (e.g., combined with...) can be used. Figure 9G The described combination of sputtering etching and chemical etching is used to form a plurality of recesses 306, such that these recesses 306 have an approximately V-shaped cross-sectional profile and an approximately conical three-dimensional shape. In some embodiments, etching techniques (e.g., combined with...) can be used. Figure 10C The described cyclic reactive ion technology is used to form multiple recesses 306, such that these recesses 306 have an approximately U-shaped cross-sectional profile and an approximately semi-circular three-dimensional shape.

[0294] As in Figure 12B As shown, a passivation layer 268 is formed above and / or on a buffer layer 264, such that the passivation layer 268 fills a plurality of recesses 306 to form a plurality of diffuse structures 266. The passivation layer 268 can be deposited using deposition tools, employing physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, or other deposition techniques. In some embodiments, a planarization operation, such as a chemical mechanical planarization operation, is performed using a planarization tool to planarize the passivation layer 268.

[0295] As in Figure 12B As further shown, a metal grid structure 274 may be formed above and / or on the passivation layer 268. A deposition tool may be used to deposit a metal layer on the passivation layer 268, employing chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or another suitable deposition technique. The metal layer may be patterned using photolithography and etched to form the metal grid structure 274.

[0296] Multiple recesses 312 for multiple diffuse structures 278 of the pixel sensor 100 are formed in the passivation layer 268. In some embodiments, a pattern in the photoresist layer is used to etch the passivation layer 268 to form the multiple recesses 312. In some embodiments, the passivation layer 268 is etched to form the multiple recesses 312, using a metal grid structure 274 as a self-aligned pattern.

[0297] In some implementations, etching techniques (e.g., combined with...) can be used. Figure 9G The described combination of sputtering etching and chemical etching is used to form a plurality of recesses 312, such that these recesses 312 have an approximately V-shaped cross-sectional profile and an approximately conical three-dimensional shape. In some embodiments, etching techniques (e.g., combined with...) can be used. Figure 10C The described cyclic reactive ion technique is used to form a plurality of recesses 312, such that these recesses 312 have an approximately U-shaped cross-sectional profile and an approximately semi-circular three-dimensional shape.

[0298] As in Figure 12C As shown, a color filter region 276 may be formed in a metal grid structure 274, such that the dielectric material of the color filter region 276 fills a plurality of recesses 312 to form a plurality of diffuse structures 278. A microlens 280 may be formed on the color filter region 276.

[0299] As mentioned above, it provides Figures 12A to 12C As one embodiment, other embodiments may be related to... Figures 12A to 12C The content described is different.

[0300] Figure 13 This is a flowchart of an embodiment of process 1300 associated with forming the pixel sensor array described herein. In some embodiments, one or more semiconductor processing tools are used to perform the process. Figure 13 One or more process blocks, the semiconductor processing tools being such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or another type of semiconductor processing tool.

[0301] As in Figure 13 As shown, process 1300 may include a photodiode (block 1310) forming a pixel sensor in a substrate of the pixel sensor array. For example, one or more semiconductor processing tools may be used to form a photodiode 112 of the pixel sensor 100 in a substrate 246 of the pixel sensor array 222, as described herein.

[0302] As in Figure 13 As further shown, process 1300 may include forming a first plurality of recesses (block 1320) in a substrate above the photodiode. For example, as described herein, one or more semiconductor processing tools may be used to form the first plurality of recesses 302 in a substrate 246 above the photodiode 112.

[0303] As in Figure 13As further shown, process 1300 may include forming a first dielectric layer above the substrate, such that a plurality of first dielectric regions of the first dielectric layer fill into a plurality of first recesses to form a plurality of diffuse structures in the plurality of recesses (block 1330). For example, one or more semiconductor processing tools may be used to form a first dielectric layer (e.g., buffer layer 264) above the substrate 246, such that a plurality of first dielectric regions (e.g., a plurality of portions 304) of the first dielectric layer fill into a plurality of first recesses 302 to form a plurality of diffuse structures 266 in the plurality of recesses 302, as described herein.

[0304] As in Figure 13 As further shown, process 1300 may include forming a second plurality of recesses (block 1340) in a first dielectric layer above the first plurality of diffuse structures. For example, as described herein, one or more semiconductor processing tools may be used to form the second plurality of recesses 306 in the first dielectric layer above the first plurality of diffuse structures 266. Alternatively, as described herein, one or more semiconductor processing tools may be used to form the second plurality of recesses 312 in another dielectric layer above the first dielectric layer.

[0305] As in Figure 13 As further shown, process 1300 may include forming a second dielectric layer above the first dielectric layer, such that a plurality of second dielectric regions of the second dielectric layer fill into a second plurality of recesses to form a second plurality of diffuse structures in the second plurality of recesses (block 1350). For example, one or more semiconductor processing tools may be used to form a second dielectric layer (e.g., passivation layer 268) above the first dielectric layer, such that a plurality of second dielectric regions (e.g., portions 308) of the second dielectric layer fill into a second plurality of recesses 306 to form a second plurality of diffuse structures 272 in the second plurality of recesses 306, as described herein.

[0306] Process 1300 may include additional implementations, such as any single implementation or any combination of multiple implementations described below, and / or in combination with one or more other processes described elsewhere herein. Alternatively, a color filter region 276 may be formed above the second dielectric layer using one or more semiconductor processing tools, such that multiple second dielectric regions (e.g., multiple portions 314) of the color filter region 276 fill into a second plurality of recesses 312 to form a second plurality of diffuse structures 278 in the second plurality of recesses 312, as described herein.

[0307] Process 1300 may include additional implementations, such as any single implementation or any combination of multiple implementations described below, and / or in combination with one or more other processes described elsewhere herein.

[0308] In a first embodiment, process 1300 includes forming a third plurality of recesses 312 in a second dielectric layer above the second plurality of diffuse structures 272, and forming a color filter region 276 of the pixel sensor 100 above the second dielectric layer, such that a plurality of third dielectric regions (e.g., a plurality of portions 314) of the color filter region 276 fill the third plurality of recesses 312 to form a third plurality of diffuse structures 278 in the third plurality of recesses 312.

[0309] In the second embodiment, either alone or in combination with the first embodiment, each of the first plurality of recesses 302 has an approximately pyramidal shape, and each of the second plurality of recesses 306 or 312 has an approximately conical shape.

[0310] In the third embodiment, forming the second plurality of recesses 306 or 312, alone or in combination with one or more of the first and second embodiments, includes performing a combination of chemical etching and sputtering etching to form the second plurality of recesses 306 or 312.

[0311] In the fourth embodiment, forming the second plurality of recesses 306 or 312, alone or in combination with one or more of the first to third embodiments, includes forming the second plurality of recesses 306 or 312 to a first depth in the first dielectric layer, forming a protective pad 1002 in the second plurality of recesses 306 or 312, and etching through the bottom portion of the protective pad 1002 and into the first dielectric layer to increase the second plurality of recesses 306 or 312 from the first depth to a second depth in the first dielectric layer, wherein the protective pad 1002 protects the sidewalls of the second plurality of recesses 306 or 312 from being etched.

[0312] although Figure 13 The diagram illustrates an embodiment of process 1300, but in some embodiments, process 1300 includes components that are more complex than those shown in the diagram. Figure 13 The diagram shows more blocks, fewer blocks, different blocks, or blocks arranged differently. Additionally or alternatively, two or more blocks of process 1300 can be executed in parallel.

[0313] In this manner, the pixel sensor comprises multiple vertically arranged layers of diffuse structures above the photodiode. Each diffuse structure disperses incident light via refraction to provide a greater dispersion of incident light than a single-layer diffuse structure. For example, before the incident light enters the photodiode of the pixel sensor, the top layer of the multiple diffuse structures can disperse the incident light via refraction, and the bottom layer of the multiple diffuse structures can further disperse the dispersed incident light from the top layer. This ensures that the incident light is dispersed throughout the photodiode and increases the path length of photons, thereby increasing the likelihood of photons being absorbed in the photodiode. Therefore, the multiple vertically arranged layers of diffuse structures can further increase the quantum efficiency of the pixel sensor. Furthermore, the size and / or shape of each diffuse structure layer can be designed to disperse specific wavelengths of incident light, thereby dispersing a wider range of incident light wavelengths to further enhance quantum efficiency.

[0314] As described in more detail above, some embodiments described herein provide a pixel sensor. The pixel sensor includes a photodiode in a substrate. The pixel sensor includes a first plurality of diffuse structures extending into a portion of the substrate above the photodiode. The pixel sensor includes a second plurality of diffuse structures extending into a dielectric layer above the substrate above the first plurality of diffuse structures.

[0315] In some implementations, in a pixel sensor, a first number of diffuse structures in the first plurality of diffuse structures and a second number of diffuse structures in the second plurality of diffuse structures are different numbers of diffuse structures.

[0316] In some implementations, in the pixel sensor, the first material composition of the first plurality of diffuse structures and the second material composition of the second plurality of diffuse structures are different material compositions.

[0317] In some implementations, in the pixel sensor, the first refractive index of the material composition of the first plurality of diffuse structures and the second refractive index of the material composition of the second plurality of diffuse structures are different refractive indices.

[0318] In some implementations, in the pixel sensor, the first vertical thickness of the diffuse structure of the first plurality of diffuse structures and the second vertical thickness of the diffuse structure of the second plurality of diffuse structures are different vertical thicknesses.

[0319] In some implementations, in the pixel sensor, the first lateral width of the diffuse structure of the first plurality of diffuse structures and the second lateral width of the diffuse structure of the second plurality of diffuse structures are different lateral widths.

[0320] In some embodiments, the pixel sensor further includes a third plurality of diffuse structures, higher than the second plurality of diffuse structures. The third plurality of diffuse structures extend into another dielectric layer higher than the dielectric layer.

[0321] As described in more detail above, some embodiments described herein provide pixel sensor arrays. The pixel sensor array includes pixel sensors, which include photodiodes within a substrate. The pixel sensor array includes a first plurality of diffuse structures extending into a portion of the substrate above the photodiodes. The pixel sensor array includes a deep trench isolation structure extending into the substrate and laterally surrounding at least a portion of the first plurality of diffuse structures and the photodiodes. The pixel sensor array includes a second plurality of diffuse structures extending into a dielectric layer above the first plurality of diffuse structures. The pixel sensor array includes a grid structure extending into the deep trench isolation structure and laterally surrounding the second plurality of diffuse structures.

[0322] In some implementations, in the pixel sensor array, the first plurality of diffuse structures have an approximately V-shaped cross-sectional profile; and the second plurality of diffuse structures have an approximately U-shaped cross-sectional profile.

[0323] In some implementations, in a pixel sensor array, the refractive index of the dielectric layer is different at the bottom of the dielectric layer than at the top of the dielectric layer.

[0324] In some implementations, the pixel sensor array further includes another dielectric layer above the first dielectric layer, wherein the refractive index of the first dielectric layer is greater than the refractive index of the second dielectric layer.

[0325] In some implementations, in a pixel sensor array, the refractive index of the other dielectric layer is greater at the bottom of the other dielectric layer than at the top of the other dielectric layer.

[0326] In some embodiments, the pixel sensor array further includes a third plurality of diffuse structures above the second plurality of diffuse structures, wherein the third plurality of diffuse structures extend into another dielectric layer above the dielectric layer.

[0327] In some implementations, in the pixel sensor array, a first number of diffuse structures in the second plurality of diffuse structures is greater than a second number of diffuse structures in the third plurality of diffuse structures.

[0328] In some implementations, in the pixel sensor array, a third number of diffuse structures in the first plurality of diffuse structures are larger than the first number of diffuse structures in the second plurality of diffuse structures.

[0329] As described in more detail above, some embodiments described herein provide a method. This method includes forming a photodiode of a pixel sensor in a substrate of a pixel sensor array. This method includes forming a first plurality of recesses within the substrate above the photodiode. This method includes forming a first dielectric layer above the substrate, such that a plurality of first dielectric regions of the first dielectric layer fill the first plurality of recesses to form a first plurality of diffuse structures in the first plurality of recesses. This method includes forming a second plurality of recesses in the first dielectric layer above the first plurality of diffuse structures. This method includes forming a second dielectric layer above the first dielectric layer, such that a plurality of second dielectric regions of the second dielectric layer fill the second plurality of recesses to form a second plurality of diffuse structures in the second plurality of recesses.

[0330] In some embodiments, the method of forming a pixel sensor further includes: forming a third plurality of recesses in the second dielectric layer above the second plurality of diffuse structures; and forming a color filter region of the pixel sensor above the second dielectric layer, such that a plurality of third dielectric regions of the color filter region fill the third plurality of recesses to form a third plurality of diffuse structures in the third plurality of recesses.

[0331] In some embodiments, in the method of forming a pixel sensor, the first plurality of recesses each have an approximate pyramid shape; and wherein the second plurality of recesses each have an approximate cone shape.

[0332] In some embodiments, forming the second plurality of recesses in the method of forming a pixel sensor includes performing a combination of chemical etching and sputtering etching to form the second plurality of recesses.

[0333] In some embodiments, in the method of forming a pixel sensor, forming the second plurality of recesses includes: forming the second plurality of recesses to a first depth in the first dielectric layer; forming a protective pad in the second plurality of recesses; and etching through a bottom portion of the protective pad into the first dielectric layer to increase the second plurality of recesses in the first dielectric layer from the first depth to a second depth, wherein the protective pad protects a plurality of sidewalls of the second plurality of recesses from being etched.

[0334] Some embodiments of this disclosure provide a pixel sensor comprising: a photodiode, a first plurality of diffuse structures, a second plurality of diffuse structures, and a third plurality of diffuse structures. The photodiode is located in a substrate. The first plurality of diffuse structures extend into a portion of the substrate above the photodiode. The second plurality of diffuse structures extend into a dielectric layer above the substrate above the first plurality of diffuse structures. The third plurality of diffuse structures extend into another dielectric layer above the dielectric layer above the dielectric layer.

[0335] The terms “about” and “substantially” can indicate that a given quantity varies within ±5% of that value (e.g., 1%, 2%, 3%, 4%, 5% of that value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “about” and “substantially” can refer to a percentage of the given quantity.

[0336] The foregoing outlines several features of various embodiments, enabling those skilled in the art to better understand the multiple variations of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for the design or modification of other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A pixel sensor, characterized in that, Include: A photodiode is embedded in a substrate. The first plurality of diffuse structures extend into a portion of the substrate above the photodiode; and The second plurality of diffuse structures are higher than the first plurality of diffuse structures. The second plurality of diffuse structures extend into a dielectric layer above the substrate.

2. The pixel sensor as claimed in claim 1, characterized in that, The first number of diffuse structures in the first plurality of diffuse structures and the second number of diffuse structures in the second plurality of diffuse structures are different numbers of diffuse structures.

3. The pixel sensor as described in claim 1, characterized in that, The first vertical thickness of the first plurality of diffuse structures and the second vertical thickness of the second plurality of diffuse structures are different vertical thicknesses.

4. The pixel sensor as claimed in claim 1, characterized in that, The first lateral width of the diffuse structure of the first plurality of diffuse structures and the second lateral width of the diffuse structure of the second plurality of diffuse structures are different lateral widths.

5. A pixel sensor array, characterized in that, Include: A pixel sensor, comprising a photodiode in a substrate; The first plurality of diffuse structures extend into a portion of the substrate above the photodiode. A deep trench isolation structure extends into the substrate and laterally surrounds at least a portion of the first plurality of diffuse structures and the photodiode; The second plurality of diffuse structures are higher than the first plurality of diffuse structures. The second plurality of diffuse structures extend into a dielectric layer above the substrate; and A grid structure, above the deep trench isolation structure and laterally surrounding the second plurality of diffuse structures.

6. The pixel sensor array as described in claim 5, characterized in that, The first plurality of diffuse structures have an approximately V-shaped cross-sectional profile; and The second plurality of diffuse structures have an approximately U-shaped cross-sectional profile.

7. The pixel sensor array as described in claim 5, characterized in that, Also includes: The third set of multiple diffuse structures is superior to the second set of multiple diffuse structures. The third plurality of diffuse structures extend into another dielectric layer above the dielectric layer.

8. The pixel sensor array as claimed in claim 7, characterized in that, The first number of diffuse structures in the second plurality of diffuse structures is greater than the second number of diffuse structures in the third plurality of diffuse structures.

9. The pixel sensor array as claimed in claim 8, characterized in that, The third number of diffuse structures in the first plurality of diffuse structures is greater than the first number of diffuse structures in the second plurality of diffuse structures.

10. A pixel sensor, characterized in that, Include: A photodiode is embedded in a substrate. The first plurality of diffuse structures extend into a portion of the substrate above the photodiode; A second plurality of diffuse structures are higher than the first plurality of diffuse structures, wherein the second plurality of diffuse structures extend into a dielectric layer above the substrate; as well as A third plurality of diffuse structures are above the second plurality of diffuse structures, wherein the third plurality of diffuse structures extend into another dielectric layer above the dielectric layer.

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